linux/drivers/scsi/aic7xxx/aic79xx.h
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   1/*
   2 * Core definitions and data structures shareable across OS platforms.
   3 *
   4 * Copyright (c) 1994-2002 Justin T. Gibbs.
   5 * Copyright (c) 2000-2002 Adaptec Inc.
   6 * All rights reserved.
   7 *
   8 * Redistribution and use in source and binary forms, with or without
   9 * modification, are permitted provided that the following conditions
  10 * are met:
  11 * 1. Redistributions of source code must retain the above copyright
  12 *    notice, this list of conditions, and the following disclaimer,
  13 *    without modification.
  14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  15 *    substantially similar to the "NO WARRANTY" disclaimer below
  16 *    ("Disclaimer") and any redistribution must be conditioned upon
  17 *    including a substantially similar Disclaimer requirement for further
  18 *    binary redistribution.
  19 * 3. Neither the names of the above-listed copyright holders nor the names
  20 *    of any contributors may be used to endorse or promote products derived
  21 *    from this software without specific prior written permission.
  22 *
  23 * Alternatively, this software may be distributed under the terms of the
  24 * GNU General Public License ("GPL") version 2 as published by the Free
  25 * Software Foundation.
  26 *
  27 * NO WARRANTY
  28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  38 * POSSIBILITY OF SUCH DAMAGES.
  39 *
  40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.h#109 $
  41 *
  42 * $FreeBSD$
  43 */
  44
  45#ifndef _AIC79XX_H_
  46#define _AIC79XX_H_
  47
  48/* Register Definitions */
  49#include "aic79xx_reg.h"
  50
  51/************************* Forward Declarations *******************************/
  52struct ahd_platform_data;
  53struct scb_platform_data;
  54
  55/****************************** Useful Macros *********************************/
  56#ifndef TRUE
  57#define TRUE 1
  58#endif
  59#ifndef FALSE
  60#define FALSE 0
  61#endif
  62
  63#define ALL_CHANNELS '\0'
  64#define ALL_TARGETS_MASK 0xFFFF
  65#define INITIATOR_WILDCARD      (~0)
  66#define SCB_LIST_NULL           0xFF00
  67#define SCB_LIST_NULL_LE        (ahd_htole16(SCB_LIST_NULL))
  68#define QOUTFIFO_ENTRY_VALID 0x80
  69#define SCBID_IS_NULL(scbid) (((scbid) & 0xFF00 ) == SCB_LIST_NULL)
  70
  71#define SCSIID_TARGET(ahd, scsiid)      \
  72        (((scsiid) & TID) >> TID_SHIFT)
  73#define SCSIID_OUR_ID(scsiid)           \
  74        ((scsiid) & OID)
  75#define SCSIID_CHANNEL(ahd, scsiid) ('A')
  76#define SCB_IS_SCSIBUS_B(ahd, scb) (0)
  77#define SCB_GET_OUR_ID(scb) \
  78        SCSIID_OUR_ID((scb)->hscb->scsiid)
  79#define SCB_GET_TARGET(ahd, scb) \
  80        SCSIID_TARGET((ahd), (scb)->hscb->scsiid)
  81#define SCB_GET_CHANNEL(ahd, scb) \
  82        SCSIID_CHANNEL(ahd, (scb)->hscb->scsiid)
  83#define SCB_GET_LUN(scb) \
  84        ((scb)->hscb->lun)
  85#define SCB_GET_TARGET_OFFSET(ahd, scb) \
  86        SCB_GET_TARGET(ahd, scb)
  87#define SCB_GET_TARGET_MASK(ahd, scb) \
  88        (0x01 << (SCB_GET_TARGET_OFFSET(ahd, scb)))
  89#ifdef AHD_DEBUG
  90#define SCB_IS_SILENT(scb)                                      \
  91        ((ahd_debug & AHD_SHOW_MASKED_ERRORS) == 0              \
  92      && (((scb)->flags & SCB_SILENT) != 0))
  93#else
  94#define SCB_IS_SILENT(scb)                                      \
  95        (((scb)->flags & SCB_SILENT) != 0)
  96#endif
  97/*
  98 * TCLs have the following format: TTTTLLLLLLLL
  99 */
 100#define TCL_TARGET_OFFSET(tcl) \
 101        ((((tcl) >> 4) & TID) >> 4)
 102#define TCL_LUN(tcl) \
 103        (tcl & (AHD_NUM_LUNS - 1))
 104#define BUILD_TCL(scsiid, lun) \
 105        ((lun) | (((scsiid) & TID) << 4))
 106#define BUILD_TCL_RAW(target, channel, lun) \
 107        ((lun) | ((target) << 8))
 108
 109#define SCB_GET_TAG(scb) \
 110        ahd_le16toh(scb->hscb->tag)
 111
 112#ifndef AHD_TARGET_MODE
 113#undef  AHD_TMODE_ENABLE
 114#define AHD_TMODE_ENABLE 0
 115#endif
 116
 117#define AHD_BUILD_COL_IDX(target, lun)                          \
 118        (((lun) << 4) | target)
 119
 120#define AHD_GET_SCB_COL_IDX(ahd, scb)                           \
 121        ((SCB_GET_LUN(scb) << 4) | SCB_GET_TARGET(ahd, scb))
 122
 123#define AHD_SET_SCB_COL_IDX(scb, col_idx)                               \
 124do {                                                                    \
 125        (scb)->hscb->scsiid = ((col_idx) << TID_SHIFT) & TID;           \
 126        (scb)->hscb->lun = ((col_idx) >> 4) & (AHD_NUM_LUNS_NONPKT-1);  \
 127} while (0)
 128
 129#define AHD_COPY_SCB_COL_IDX(dst, src)                          \
 130do {                                                            \
 131        dst->hscb->scsiid = src->hscb->scsiid;                  \
 132        dst->hscb->lun = src->hscb->lun;                        \
 133} while (0)
 134
 135#define AHD_NEVER_COL_IDX 0xFFFF
 136
 137/**************************** Driver Constants ********************************/
 138/*
 139 * The maximum number of supported targets.
 140 */
 141#define AHD_NUM_TARGETS 16
 142
 143/*
 144 * The maximum number of supported luns.
 145 * The identify message only supports 64 luns in non-packetized transfers.
 146 * You can have 2^64 luns when information unit transfers are enabled,
 147 * but until we see a need to support that many, we support 256.
 148 */
 149#define AHD_NUM_LUNS_NONPKT 64
 150#define AHD_NUM_LUNS 256
 151
 152/*
 153 * The maximum transfer per S/G segment.
 154 */
 155#define AHD_MAXTRANSFER_SIZE     0x00ffffff     /* limited by 24bit counter */
 156
 157/*
 158 * The maximum amount of SCB storage in hardware on a controller.
 159 * This value represents an upper bound.  Due to software design,
 160 * we may not be able to use this number.
 161 */
 162#define AHD_SCB_MAX     512
 163
 164/*
 165 * The maximum number of concurrent transactions supported per driver instance.
 166 * Sequencer Control Blocks (SCBs) store per-transaction information.
 167 */
 168#define AHD_MAX_QUEUE   AHD_SCB_MAX
 169
 170/*
 171 * Define the size of our QIN and QOUT FIFOs.  They must be a power of 2
 172 * in size and accommodate as many transactions as can be queued concurrently.
 173 */
 174#define AHD_QIN_SIZE    AHD_MAX_QUEUE
 175#define AHD_QOUT_SIZE   AHD_MAX_QUEUE
 176
 177#define AHD_QIN_WRAP(x) ((x) & (AHD_QIN_SIZE-1))
 178/*
 179 * The maximum amount of SCB storage we allocate in host memory.
 180 */
 181#define AHD_SCB_MAX_ALLOC AHD_MAX_QUEUE
 182
 183/*
 184 * Ring Buffer of incoming target commands.
 185 * We allocate 256 to simplify the logic in the sequencer
 186 * by using the natural wrap point of an 8bit counter.
 187 */
 188#define AHD_TMODE_CMDS  256
 189
 190/* Reset line assertion time in us */
 191#define AHD_BUSRESET_DELAY      25
 192
 193/******************* Chip Characteristics/Operating Settings  *****************/
 194/*
 195 * Chip Type
 196 * The chip order is from least sophisticated to most sophisticated.
 197 */
 198typedef enum {
 199        AHD_NONE        = 0x0000,
 200        AHD_CHIPID_MASK = 0x00FF,
 201        AHD_AIC7901     = 0x0001,
 202        AHD_AIC7902     = 0x0002,
 203        AHD_AIC7901A    = 0x0003,
 204        AHD_PCI         = 0x0100,       /* Bus type PCI */
 205        AHD_PCIX        = 0x0200,       /* Bus type PCIX */
 206        AHD_BUS_MASK    = 0x0F00
 207} ahd_chip;
 208
 209/*
 210 * Features available in each chip type.
 211 */
 212typedef enum {
 213        AHD_FENONE              = 0x00000,
 214        AHD_WIDE                = 0x00001,/* Wide Channel */
 215        AHD_AIC79XXB_SLOWCRC    = 0x00002,/* SLOWCRC bit should be set */
 216        AHD_MULTI_FUNC          = 0x00100,/* Multi-Function/Channel Device */
 217        AHD_TARGETMODE          = 0x01000,/* Has tested target mode support */
 218        AHD_MULTIROLE           = 0x02000,/* Space for two roles at a time */
 219        AHD_RTI                 = 0x04000,/* Retained Training Support */
 220        AHD_NEW_IOCELL_OPTS     = 0x08000,/* More Signal knobs in the IOCELL */
 221        AHD_NEW_DFCNTRL_OPTS    = 0x10000,/* SCSIENWRDIS bit */
 222        AHD_FAST_CDB_DELIVERY   = 0x20000,/* CDB acks released to Output Sync */
 223        AHD_REMOVABLE           = 0x00000,/* Hot-Swap supported - None so far*/
 224        AHD_AIC7901_FE          = AHD_FENONE,
 225        AHD_AIC7901A_FE         = AHD_FENONE,
 226        AHD_AIC7902_FE          = AHD_MULTI_FUNC
 227} ahd_feature;
 228
 229/*
 230 * Bugs in the silicon that we work around in software.
 231 */
 232typedef enum {
 233        AHD_BUGNONE             = 0x0000,
 234        /*
 235         * Rev A hardware fails to update LAST/CURR/NEXTSCB
 236         * correctly in certain packetized selection cases.
 237         */
 238        AHD_SENT_SCB_UPDATE_BUG = 0x0001,
 239        /* The wrong SCB is accessed to check the abort pending bit. */
 240        AHD_ABORT_LQI_BUG       = 0x0002,
 241        /* Packetized bitbucket crosses packet boundaries. */
 242        AHD_PKT_BITBUCKET_BUG   = 0x0004,
 243        /* The selection timer runs twice as long as its setting. */
 244        AHD_LONG_SETIMO_BUG     = 0x0008,
 245        /* The Non-LQ CRC error status is delayed until phase change. */
 246        AHD_NLQICRC_DELAYED_BUG = 0x0010,
 247        /* The chip must be reset for all outgoing bus resets.  */
 248        AHD_SCSIRST_BUG         = 0x0020,
 249        /* Some PCIX fields must be saved and restored across chip reset. */
 250        AHD_PCIX_CHIPRST_BUG    = 0x0040,
 251        /* MMAPIO is not functional in PCI-X mode.  */
 252        AHD_PCIX_MMAPIO_BUG     = 0x0080,
 253        /* Reads to SCBRAM fail to reset the discard timer. */
 254        AHD_PCIX_SCBRAM_RD_BUG  = 0x0100,
 255        /* Bug workarounds that can be disabled on non-PCIX busses. */
 256        AHD_PCIX_BUG_MASK       = AHD_PCIX_CHIPRST_BUG
 257                                | AHD_PCIX_MMAPIO_BUG
 258                                | AHD_PCIX_SCBRAM_RD_BUG,
 259        /*
 260         * LQOSTOP0 status set even for forced selections with ATN
 261         * to perform non-packetized message delivery.
 262         */
 263        AHD_LQO_ATNO_BUG        = 0x0200,
 264        /* FIFO auto-flush does not always trigger.  */
 265        AHD_AUTOFLUSH_BUG       = 0x0400,
 266        /* The CLRLQO registers are not self-clearing. */
 267        AHD_CLRLQO_AUTOCLR_BUG  = 0x0800,
 268        /* The PACKETIZED status bit refers to the previous connection. */
 269        AHD_PKTIZED_STATUS_BUG  = 0x1000,
 270        /* "Short Luns" are not placed into outgoing LQ packets correctly. */
 271        AHD_PKT_LUN_BUG         = 0x2000,
 272        /*
 273         * Only the FIFO allocated to the non-packetized connection may
 274         * be in use during a non-packetzied connection.
 275         */
 276        AHD_NONPACKFIFO_BUG     = 0x4000,
 277        /*
 278         * Writing to a DFF SCBPTR register may fail if concurent with
 279         * a hardware write to the other DFF SCBPTR register.  This is
 280         * not currently a concern in our sequencer since all chips with
 281         * this bug have the AHD_NONPACKFIFO_BUG and all writes of concern
 282         * occur in non-packetized connections.
 283         */
 284        AHD_MDFF_WSCBPTR_BUG    = 0x8000,
 285        /* SGHADDR updates are slow. */
 286        AHD_REG_SLOW_SETTLE_BUG = 0x10000,
 287        /*
 288         * Changing the MODE_PTR coincident with an interrupt that
 289         * switches to a different mode will cause the interrupt to
 290         * be in the mode written outside of interrupt context.
 291         */
 292        AHD_SET_MODE_BUG        = 0x20000,
 293        /* Non-packetized busfree revision does not work. */
 294        AHD_BUSFREEREV_BUG      = 0x40000,
 295        /*
 296         * Paced transfers are indicated with a non-standard PPR
 297         * option bit in the neg table, 160MHz is indicated by
 298         * sync factor 0x7, and the offset if off by a factor of 2.
 299         */
 300        AHD_PACED_NEGTABLE_BUG  = 0x80000,
 301        /* LQOOVERRUN false positives. */
 302        AHD_LQOOVERRUN_BUG      = 0x100000,
 303        /*
 304         * Controller write to INTSTAT will lose to a host
 305         * write to CLRINT.
 306         */
 307        AHD_INTCOLLISION_BUG    = 0x200000,
 308        /*
 309         * The GEM318 violates the SCSI spec by not waiting
 310         * the mandated bus settle delay between phase changes
 311         * in some situations.  Some aic79xx chip revs. are more
 312         * strict in this regard and will treat REQ assertions
 313         * that fall within the bus settle delay window as
 314         * glitches.  This flag tells the firmware to tolerate
 315         * early REQ assertions.
 316         */
 317        AHD_EARLY_REQ_BUG       = 0x400000,
 318        /*
 319         * The LED does not stay on long enough in packetized modes.
 320         */
 321        AHD_FAINT_LED_BUG       = 0x800000
 322} ahd_bug;
 323
 324/*
 325 * Configuration specific settings.
 326 * The driver determines these settings by probing the
 327 * chip/controller's configuration.
 328 */
 329typedef enum {
 330        AHD_FNONE             = 0x00000,
 331        AHD_BOOT_CHANNEL      = 0x00001,/* We were set as the boot channel. */
 332        AHD_USEDEFAULTS       = 0x00004,/*
 333                                         * For cards without an seeprom
 334                                         * or a BIOS to initialize the chip's
 335                                         * SRAM, we use the default target
 336                                         * settings.
 337                                         */
 338        AHD_SEQUENCER_DEBUG   = 0x00008,
 339        AHD_RESET_BUS_A       = 0x00010,
 340        AHD_EXTENDED_TRANS_A  = 0x00020,
 341        AHD_TERM_ENB_A        = 0x00040,
 342        AHD_SPCHK_ENB_A       = 0x00080,
 343        AHD_STPWLEVEL_A       = 0x00100,
 344        AHD_INITIATORROLE     = 0x00200,/*
 345                                         * Allow initiator operations on
 346                                         * this controller.
 347                                         */
 348        AHD_TARGETROLE        = 0x00400,/*
 349                                         * Allow target operations on this
 350                                         * controller.
 351                                         */
 352        AHD_RESOURCE_SHORTAGE = 0x00800,
 353        AHD_TQINFIFO_BLOCKED  = 0x01000,/* Blocked waiting for ATIOs */
 354        AHD_INT50_SPEEDFLEX   = 0x02000,/*
 355                                         * Internal 50pin connector
 356                                         * sits behind an aic3860
 357                                         */
 358        AHD_BIOS_ENABLED      = 0x04000,
 359        AHD_ALL_INTERRUPTS    = 0x08000,
 360        AHD_39BIT_ADDRESSING  = 0x10000,/* Use 39 bit addressing scheme. */
 361        AHD_64BIT_ADDRESSING  = 0x20000,/* Use 64 bit addressing scheme. */
 362        AHD_CURRENT_SENSING   = 0x40000,
 363        AHD_SCB_CONFIG_USED   = 0x80000,/* No SEEPROM but SCB had info. */
 364        AHD_HP_BOARD          = 0x100000,
 365        AHD_BUS_RESET_ACTIVE  = 0x200000,
 366        AHD_UPDATE_PEND_CMDS  = 0x400000,
 367        AHD_RUNNING_QOUTFIFO  = 0x800000,
 368        AHD_HAD_FIRST_SEL     = 0x1000000
 369} ahd_flag;
 370
 371/************************* Hardware  SCB Definition ***************************/
 372
 373/*
 374 * The driver keeps up to MAX_SCB scb structures per card in memory.  The SCB
 375 * consists of a "hardware SCB" mirroring the fields available on the card
 376 * and additional information the kernel stores for each transaction.
 377 *
 378 * To minimize space utilization, a portion of the hardware scb stores
 379 * different data during different portions of a SCSI transaction.
 380 * As initialized by the host driver for the initiator role, this area
 381 * contains the SCSI cdb (or a pointer to the  cdb) to be executed.  After
 382 * the cdb has been presented to the target, this area serves to store
 383 * residual transfer information and the SCSI status byte.
 384 * For the target role, the contents of this area do not change, but
 385 * still serve a different purpose than for the initiator role.  See
 386 * struct target_data for details.
 387 */
 388
 389/*
 390 * Status information embedded in the shared poriton of
 391 * an SCB after passing the cdb to the target.  The kernel
 392 * driver will only read this data for transactions that
 393 * complete abnormally.
 394 */
 395struct initiator_status {
 396        uint32_t residual_datacnt;      /* Residual in the current S/G seg */
 397        uint32_t residual_sgptr;        /* The next S/G for this transfer */
 398        uint8_t  scsi_status;           /* Standard SCSI status byte */
 399};
 400
 401struct target_status {
 402        uint32_t residual_datacnt;      /* Residual in the current S/G seg */
 403        uint32_t residual_sgptr;        /* The next S/G for this transfer */
 404        uint8_t  scsi_status;           /* SCSI status to give to initiator */
 405        uint8_t  target_phases;         /* Bitmap of phases to execute */
 406        uint8_t  data_phase;            /* Data-In or Data-Out */
 407        uint8_t  initiator_tag;         /* Initiator's transaction tag */
 408};
 409
 410/*
 411 * Initiator mode SCB shared data area.
 412 * If the embedded CDB is 12 bytes or less, we embed
 413 * the sense buffer address in the SCB.  This allows
 414 * us to retrieve sense information without interrupting
 415 * the host in packetized mode.
 416 */
 417typedef uint32_t sense_addr_t;
 418#define MAX_CDB_LEN 16
 419#define MAX_CDB_LEN_WITH_SENSE_ADDR (MAX_CDB_LEN - sizeof(sense_addr_t))
 420union initiator_data {
 421        struct {
 422                uint64_t cdbptr;
 423                uint8_t  cdblen;
 424        } cdb_from_host;
 425        uint8_t  cdb[MAX_CDB_LEN];
 426        struct {
 427                uint8_t  cdb[MAX_CDB_LEN_WITH_SENSE_ADDR];
 428                sense_addr_t sense_addr;
 429        } cdb_plus_saddr;
 430};
 431
 432/*
 433 * Target mode version of the shared data SCB segment.
 434 */
 435struct target_data {
 436        uint32_t spare[2];      
 437        uint8_t  scsi_status;           /* SCSI status to give to initiator */
 438        uint8_t  target_phases;         /* Bitmap of phases to execute */
 439        uint8_t  data_phase;            /* Data-In or Data-Out */
 440        uint8_t  initiator_tag;         /* Initiator's transaction tag */
 441};
 442
 443struct hardware_scb {
 444/*0*/   union {
 445                union   initiator_data idata;
 446                struct  target_data tdata;
 447                struct  initiator_status istatus;
 448                struct  target_status tstatus;
 449        } shared_data;
 450/*
 451 * A word about residuals.
 452 * The scb is presented to the sequencer with the dataptr and datacnt
 453 * fields initialized to the contents of the first S/G element to
 454 * transfer.  The sgptr field is initialized to the bus address for
 455 * the S/G element that follows the first in the in core S/G array
 456 * or'ed with the SG_FULL_RESID flag.  Sgptr may point to an invalid
 457 * S/G entry for this transfer (single S/G element transfer with the
 458 * first elements address and length preloaded in the dataptr/datacnt
 459 * fields).  If no transfer is to occur, sgptr is set to SG_LIST_NULL.
 460 * The SG_FULL_RESID flag ensures that the residual will be correctly
 461 * noted even if no data transfers occur.  Once the data phase is entered,
 462 * the residual sgptr and datacnt are loaded from the sgptr and the
 463 * datacnt fields.  After each S/G element's dataptr and length are
 464 * loaded into the hardware, the residual sgptr is advanced.  After
 465 * each S/G element is expired, its datacnt field is checked to see
 466 * if the LAST_SEG flag is set.  If so, SG_LIST_NULL is set in the
 467 * residual sg ptr and the transfer is considered complete.  If the
 468 * sequencer determines that there is a residual in the tranfer, or
 469 * there is non-zero status, it will set the SG_STATUS_VALID flag in
 470 * sgptr and dma the scb back into host memory.  To sumarize:
 471 *
 472 * Sequencer:
 473 *      o A residual has occurred if SG_FULL_RESID is set in sgptr,
 474 *        or residual_sgptr does not have SG_LIST_NULL set.
 475 *
 476 *      o We are transferring the last segment if residual_datacnt has
 477 *        the SG_LAST_SEG flag set.
 478 *
 479 * Host:
 480 *      o A residual can only have occurred if a completed scb has the
 481 *        SG_STATUS_VALID flag set.  Inspection of the SCSI status field,
 482 *        the residual_datacnt, and the residual_sgptr field will tell
 483 *        for sure.
 484 *
 485 *      o residual_sgptr and sgptr refer to the "next" sg entry
 486 *        and so may point beyond the last valid sg entry for the
 487 *        transfer.
 488 */ 
 489#define SG_PTR_MASK     0xFFFFFFF8
 490/*16*/  uint16_t tag;           /* Reused by Sequencer. */
 491/*18*/  uint8_t  control;       /* See SCB_CONTROL in aic79xx.reg for details */
 492/*19*/  uint8_t  scsiid;        /*
 493                                 * Selection out Id
 494                                 * Our Id (bits 0-3) Their ID (bits 4-7)
 495                                 */
 496/*20*/  uint8_t  lun;
 497/*21*/  uint8_t  task_attribute;
 498/*22*/  uint8_t  cdb_len;
 499/*23*/  uint8_t  task_management;
 500/*24*/  uint64_t dataptr;
 501/*32*/  uint32_t datacnt;       /* Byte 3 is spare. */
 502/*36*/  uint32_t sgptr;
 503/*40*/  uint32_t hscb_busaddr;
 504/*44*/  uint32_t next_hscb_busaddr;
 505/********** Long lun field only downloaded for full 8 byte lun support ********/
 506/*48*/  uint8_t  pkt_long_lun[8];
 507/******* Fields below are not Downloaded (Sequencer may use for scratch) ******/
 508/*56*/  uint8_t  spare[8];
 509};
 510
 511/************************ Kernel SCB Definitions ******************************/
 512/*
 513 * Some fields of the SCB are OS dependent.  Here we collect the
 514 * definitions for elements that all OS platforms need to include
 515 * in there SCB definition.
 516 */
 517
 518/*
 519 * Definition of a scatter/gather element as transferred to the controller.
 520 * The aic7xxx chips only support a 24bit length.  We use the top byte of
 521 * the length to store additional address bits and a flag to indicate
 522 * that a given segment terminates the transfer.  This gives us an
 523 * addressable range of 512GB on machines with 64bit PCI or with chips
 524 * that can support dual address cycles on 32bit PCI busses.
 525 */
 526struct ahd_dma_seg {
 527        uint32_t        addr;
 528        uint32_t        len;
 529#define AHD_DMA_LAST_SEG        0x80000000
 530#define AHD_SG_HIGH_ADDR_MASK   0x7F000000
 531#define AHD_SG_LEN_MASK         0x00FFFFFF
 532};
 533
 534struct ahd_dma64_seg {
 535        uint64_t        addr;
 536        uint32_t        len;
 537        uint32_t        pad;
 538};
 539
 540struct map_node {
 541        bus_dmamap_t             dmamap;
 542        dma_addr_t               physaddr;
 543        uint8_t                 *vaddr;
 544        SLIST_ENTRY(map_node)    links;
 545};
 546
 547/*
 548 * The current state of this SCB.
 549 */
 550typedef enum {
 551        SCB_FLAG_NONE           = 0x00000,
 552        SCB_TRANSMISSION_ERROR  = 0x00001,/*
 553                                           * We detected a parity or CRC
 554                                           * error that has effected the
 555                                           * payload of the command.  This
 556                                           * flag is checked when normal
 557                                           * status is returned to catch
 558                                           * the case of a target not
 559                                           * responding to our attempt
 560                                           * to report the error.
 561                                           */
 562        SCB_OTHERTCL_TIMEOUT    = 0x00002,/*
 563                                           * Another device was active
 564                                           * during the first timeout for
 565                                           * this SCB so we gave ourselves
 566                                           * an additional timeout period
 567                                           * in case it was hogging the
 568                                           * bus.
 569                                           */
 570        SCB_DEVICE_RESET        = 0x00004,
 571        SCB_SENSE               = 0x00008,
 572        SCB_CDB32_PTR           = 0x00010,
 573        SCB_RECOVERY_SCB        = 0x00020,
 574        SCB_AUTO_NEGOTIATE      = 0x00040,/* Negotiate to achieve goal. */
 575        SCB_NEGOTIATE           = 0x00080,/* Negotiation forced for command. */
 576        SCB_ABORT               = 0x00100,
 577        SCB_ACTIVE              = 0x00200,
 578        SCB_TARGET_IMMEDIATE    = 0x00400,
 579        SCB_PACKETIZED          = 0x00800,
 580        SCB_EXPECT_PPR_BUSFREE  = 0x01000,
 581        SCB_PKT_SENSE           = 0x02000,
 582        SCB_EXTERNAL_RESET      = 0x04000,/* Device was reset externally */
 583        SCB_ON_COL_LIST         = 0x08000,
 584        SCB_SILENT              = 0x10000 /*
 585                                           * Be quiet about transmission type
 586                                           * errors.  They are expected and we
 587                                           * don't want to upset the user.  This
 588                                           * flag is typically used during DV.
 589                                           */
 590} scb_flag;
 591
 592struct scb {
 593        struct  hardware_scb     *hscb;
 594        union {
 595                SLIST_ENTRY(scb)  sle;
 596                LIST_ENTRY(scb)   le;
 597                TAILQ_ENTRY(scb)  tqe;
 598        } links;
 599        union {
 600                SLIST_ENTRY(scb)  sle;
 601                LIST_ENTRY(scb)   le;
 602                TAILQ_ENTRY(scb)  tqe;
 603        } links2;
 604#define pending_links links2.le
 605#define collision_links links2.le
 606        struct scb               *col_scb;
 607        ahd_io_ctx_t              io_ctx;
 608        struct ahd_softc         *ahd_softc;
 609        scb_flag                  flags;
 610#ifndef __linux__
 611        bus_dmamap_t              dmamap;
 612#endif
 613        struct scb_platform_data *platform_data;
 614        struct map_node          *hscb_map;
 615        struct map_node          *sg_map;
 616        struct map_node          *sense_map;
 617        void                     *sg_list;
 618        uint8_t                  *sense_data;
 619        dma_addr_t                sg_list_busaddr;
 620        dma_addr_t                sense_busaddr;
 621        u_int                     sg_count;/* How full ahd_dma_seg is */
 622#define AHD_MAX_LQ_CRC_ERRORS 5
 623        u_int                     crc_retry_count;
 624};
 625
 626TAILQ_HEAD(scb_tailq, scb);
 627LIST_HEAD(scb_list, scb);
 628
 629struct scb_data {
 630        /*
 631         * TAILQ of lists of free SCBs grouped by device
 632         * collision domains.
 633         */
 634        struct scb_tailq free_scbs;
 635
 636        /*
 637         * Per-device lists of SCBs whose tag ID would collide
 638         * with an already active tag on the device.
 639         */
 640        struct scb_list free_scb_lists[AHD_NUM_TARGETS * AHD_NUM_LUNS_NONPKT];
 641
 642        /*
 643         * SCBs that will not collide with any active device.
 644         */
 645        struct scb_list any_dev_free_scb_list;
 646
 647        /*
 648         * Mapping from tag to SCB.
 649         */
 650        struct  scb *scbindex[AHD_SCB_MAX];
 651
 652        /*
 653         * "Bus" addresses of our data structures.
 654         */
 655        bus_dma_tag_t    hscb_dmat;     /* dmat for our hardware SCB array */
 656        bus_dma_tag_t    sg_dmat;       /* dmat for our sg segments */
 657        bus_dma_tag_t    sense_dmat;    /* dmat for our sense buffers */
 658        SLIST_HEAD(, map_node) hscb_maps;
 659        SLIST_HEAD(, map_node) sg_maps;
 660        SLIST_HEAD(, map_node) sense_maps;
 661        int              scbs_left;     /* unallocated scbs in head map_node */
 662        int              sgs_left;      /* unallocated sgs in head map_node */
 663        int              sense_left;    /* unallocated sense in head map_node */
 664        uint16_t         numscbs;
 665        uint16_t         maxhscbs;      /* Number of SCBs on the card */
 666        uint8_t          init_level;    /*
 667                                         * How far we've initialized
 668                                         * this structure.
 669                                         */
 670};
 671
 672/************************ Target Mode Definitions *****************************/
 673
 674/*
 675 * Connection descriptor for select-in requests in target mode.
 676 */
 677struct target_cmd {
 678        uint8_t scsiid;         /* Our ID and the initiator's ID */
 679        uint8_t identify;       /* Identify message */
 680        uint8_t bytes[22];      /* 
 681                                 * Bytes contains any additional message
 682                                 * bytes terminated by 0xFF.  The remainder
 683                                 * is the cdb to execute.
 684                                 */
 685        uint8_t cmd_valid;      /*
 686                                 * When a command is complete, the firmware
 687                                 * will set cmd_valid to all bits set.
 688                                 * After the host has seen the command,
 689                                 * the bits are cleared.  This allows us
 690                                 * to just peek at host memory to determine
 691                                 * if more work is complete. cmd_valid is on
 692                                 * an 8 byte boundary to simplify setting
 693                                 * it on aic7880 hardware which only has
 694                                 * limited direct access to the DMA FIFO.
 695                                 */
 696        uint8_t pad[7];
 697};
 698
 699/*
 700 * Number of events we can buffer up if we run out
 701 * of immediate notify ccbs.
 702 */
 703#define AHD_TMODE_EVENT_BUFFER_SIZE 8
 704struct ahd_tmode_event {
 705        uint8_t initiator_id;
 706        uint8_t event_type;     /* MSG type or EVENT_TYPE_BUS_RESET */
 707#define EVENT_TYPE_BUS_RESET 0xFF
 708        uint8_t event_arg;
 709};
 710
 711/*
 712 * Per enabled lun target mode state.
 713 * As this state is directly influenced by the host OS'es target mode
 714 * environment, we let the OS module define it.  Forward declare the
 715 * structure here so we can store arrays of them, etc. in OS neutral
 716 * data structures.
 717 */
 718#ifdef AHD_TARGET_MODE 
 719struct ahd_tmode_lstate {
 720        struct cam_path *path;
 721        struct ccb_hdr_slist accept_tios;
 722        struct ccb_hdr_slist immed_notifies;
 723        struct ahd_tmode_event event_buffer[AHD_TMODE_EVENT_BUFFER_SIZE];
 724        uint8_t event_r_idx;
 725        uint8_t event_w_idx;
 726};
 727#else
 728struct ahd_tmode_lstate;
 729#endif
 730
 731/******************** Transfer Negotiation Datastructures *********************/
 732#define AHD_TRANS_CUR           0x01    /* Modify current neogtiation status */
 733#define AHD_TRANS_ACTIVE        0x03    /* Assume this target is on the bus */
 734#define AHD_TRANS_GOAL          0x04    /* Modify negotiation goal */
 735#define AHD_TRANS_USER          0x08    /* Modify user negotiation settings */
 736#define AHD_PERIOD_10MHz        0x19
 737
 738#define AHD_WIDTH_UNKNOWN       0xFF
 739#define AHD_PERIOD_UNKNOWN      0xFF
 740#define AHD_OFFSET_UNKNOWN      0xFF
 741#define AHD_PPR_OPTS_UNKNOWN    0xFF
 742
 743/*
 744 * Transfer Negotiation Information.
 745 */
 746struct ahd_transinfo {
 747        uint8_t protocol_version;       /* SCSI Revision level */
 748        uint8_t transport_version;      /* SPI Revision level */
 749        uint8_t width;                  /* Bus width */
 750        uint8_t period;                 /* Sync rate factor */
 751        uint8_t offset;                 /* Sync offset */
 752        uint8_t ppr_options;            /* Parallel Protocol Request options */
 753};
 754
 755/*
 756 * Per-initiator current, goal and user transfer negotiation information. */
 757struct ahd_initiator_tinfo {
 758        struct ahd_transinfo curr;
 759        struct ahd_transinfo goal;
 760        struct ahd_transinfo user;
 761};
 762
 763/*
 764 * Per enabled target ID state.
 765 * Pointers to lun target state as well as sync/wide negotiation information
 766 * for each initiator<->target mapping.  For the initiator role we pretend
 767 * that we are the target and the targets are the initiators since the
 768 * negotiation is the same regardless of role.
 769 */
 770struct ahd_tmode_tstate {
 771        struct ahd_tmode_lstate*        enabled_luns[AHD_NUM_LUNS];
 772        struct ahd_initiator_tinfo      transinfo[AHD_NUM_TARGETS];
 773
 774        /*
 775         * Per initiator state bitmasks.
 776         */
 777        uint16_t         auto_negotiate;/* Auto Negotiation Required */
 778        uint16_t         discenable;    /* Disconnection allowed  */
 779        uint16_t         tagenable;     /* Tagged Queuing allowed */
 780};
 781
 782/*
 783 * Points of interest along the negotiated transfer scale.
 784 */
 785#define AHD_SYNCRATE_160        0x8
 786#define AHD_SYNCRATE_PACED      0x8
 787#define AHD_SYNCRATE_DT         0x9
 788#define AHD_SYNCRATE_ULTRA2     0xa
 789#define AHD_SYNCRATE_ULTRA      0xc
 790#define AHD_SYNCRATE_FAST       0x19
 791#define AHD_SYNCRATE_MIN_DT     AHD_SYNCRATE_FAST
 792#define AHD_SYNCRATE_SYNC       0x32
 793#define AHD_SYNCRATE_MIN        0x60
 794#define AHD_SYNCRATE_ASYNC      0xFF
 795#define AHD_SYNCRATE_MAX        AHD_SYNCRATE_160
 796
 797/* Safe and valid period for async negotiations. */
 798#define AHD_ASYNC_XFER_PERIOD   0x44
 799
 800/*
 801 * In RevA, the synctable uses a 120MHz rate for the period
 802 * factor 8 and 160MHz for the period factor 7.  The 120MHz
 803 * rate never made it into the official SCSI spec, so we must
 804 * compensate when setting the negotiation table for Rev A
 805 * parts.
 806 */
 807#define AHD_SYNCRATE_REVA_120   0x8
 808#define AHD_SYNCRATE_REVA_160   0x7
 809
 810/***************************** Lookup Tables **********************************/
 811/*
 812 * Phase -> name and message out response
 813 * to parity errors in each phase table. 
 814 */
 815struct ahd_phase_table_entry {
 816        uint8_t phase;
 817        uint8_t mesg_out; /* Message response to parity errors */
 818        const char *phasemsg;
 819};
 820
 821/************************** Serial EEPROM Format ******************************/
 822
 823struct seeprom_config {
 824/*
 825 * Per SCSI ID Configuration Flags
 826 */
 827        uint16_t device_flags[16];      /* words 0-15 */
 828#define         CFXFER          0x003F  /* synchronous transfer rate */
 829#define                 CFXFER_ASYNC    0x3F
 830#define         CFQAS           0x0040  /* Negotiate QAS */
 831#define         CFPACKETIZED    0x0080  /* Negotiate Packetized Transfers */
 832#define         CFSTART         0x0100  /* send start unit SCSI command */
 833#define         CFINCBIOS       0x0200  /* include in BIOS scan */
 834#define         CFDISC          0x0400  /* enable disconnection */
 835#define         CFMULTILUNDEV   0x0800  /* Probe multiple luns in BIOS scan */
 836#define         CFWIDEB         0x1000  /* wide bus device */
 837#define         CFHOSTMANAGED   0x8000  /* Managed by a RAID controller */
 838
 839/*
 840 * BIOS Control Bits
 841 */
 842        uint16_t bios_control;          /* word 16 */
 843#define         CFSUPREM        0x0001  /* support all removeable drives */
 844#define         CFSUPREMB       0x0002  /* support removeable boot drives */
 845#define         CFBIOSSTATE     0x000C  /* BIOS Action State */
 846#define             CFBS_DISABLED       0x00
 847#define             CFBS_ENABLED        0x04
 848#define             CFBS_DISABLED_SCAN  0x08
 849#define         CFENABLEDV      0x0010  /* Perform Domain Validation */
 850#define         CFCTRL_A        0x0020  /* BIOS displays Ctrl-A message */      
 851#define         CFSPARITY       0x0040  /* SCSI parity */
 852#define         CFEXTEND        0x0080  /* extended translation enabled */
 853#define         CFBOOTCD        0x0100  /* Support Bootable CD-ROM */
 854#define         CFMSG_LEVEL     0x0600  /* BIOS Message Level */
 855#define                 CFMSG_VERBOSE   0x0000
 856#define                 CFMSG_SILENT    0x0200
 857#define                 CFMSG_DIAG      0x0400
 858#define         CFRESETB        0x0800  /* reset SCSI bus at boot */
 859/*              UNUSED          0xf000  */
 860
 861/*
 862 * Host Adapter Control Bits
 863 */
 864        uint16_t adapter_control;       /* word 17 */   
 865#define         CFAUTOTERM      0x0001  /* Perform Auto termination */
 866#define         CFSTERM         0x0002  /* SCSI low byte termination */
 867#define         CFWSTERM        0x0004  /* SCSI high byte termination */
 868#define         CFSEAUTOTERM    0x0008  /* Ultra2 Perform secondary Auto Term*/
 869#define         CFSELOWTERM     0x0010  /* Ultra2 secondary low term */
 870#define         CFSEHIGHTERM    0x0020  /* Ultra2 secondary high term */
 871#define         CFSTPWLEVEL     0x0040  /* Termination level control */
 872#define         CFBIOSAUTOTERM  0x0080  /* Perform Auto termination */
 873#define         CFTERM_MENU     0x0100  /* BIOS displays termination menu */    
 874#define         CFCLUSTERENB    0x8000  /* Cluster Enable */
 875
 876/*
 877 * Bus Release Time, Host Adapter ID
 878 */
 879        uint16_t brtime_id;             /* word 18 */
 880#define         CFSCSIID        0x000f  /* host adapter SCSI ID */
 881/*              UNUSED          0x00f0  */
 882#define         CFBRTIME        0xff00  /* bus release time/PCI Latency Time */
 883
 884/*
 885 * Maximum targets
 886 */
 887        uint16_t max_targets;           /* word 19 */   
 888#define         CFMAXTARG       0x00ff  /* maximum targets */
 889#define         CFBOOTLUN       0x0f00  /* Lun to boot from */
 890#define         CFBOOTID        0xf000  /* Target to boot from */
 891        uint16_t res_1[10];             /* words 20-29 */
 892        uint16_t signature;             /* BIOS Signature */
 893#define         CFSIGNATURE     0x400
 894        uint16_t checksum;              /* word 31 */
 895};
 896
 897/*
 898 * Vital Product Data used during POST and by the BIOS.
 899 */
 900struct vpd_config {
 901        uint8_t  bios_flags;
 902#define         VPDMASTERBIOS   0x0001
 903#define         VPDBOOTHOST     0x0002
 904        uint8_t  reserved_1[21];
 905        uint8_t  resource_type;
 906        uint8_t  resource_len[2];
 907        uint8_t  resource_data[8];
 908        uint8_t  vpd_tag;
 909        uint16_t vpd_len;
 910        uint8_t  vpd_keyword[2];
 911        uint8_t  length;
 912        uint8_t  revision;
 913        uint8_t  device_flags;
 914        uint8_t  termnation_menus[2];
 915        uint8_t  fifo_threshold;
 916        uint8_t  end_tag;
 917        uint8_t  vpd_checksum;
 918        uint16_t default_target_flags;
 919        uint16_t default_bios_flags;
 920        uint16_t default_ctrl_flags;
 921        uint8_t  default_irq;
 922        uint8_t  pci_lattime;
 923        uint8_t  max_target;
 924        uint8_t  boot_lun;
 925        uint16_t signature;
 926        uint8_t  reserved_2;
 927        uint8_t  checksum;
 928        uint8_t  reserved_3[4];
 929};
 930
 931/****************************** Flexport Logic ********************************/
 932#define FLXADDR_TERMCTL                 0x0
 933#define         FLX_TERMCTL_ENSECHIGH   0x8
 934#define         FLX_TERMCTL_ENSECLOW    0x4
 935#define         FLX_TERMCTL_ENPRIHIGH   0x2
 936#define         FLX_TERMCTL_ENPRILOW    0x1
 937#define FLXADDR_ROMSTAT_CURSENSECTL     0x1
 938#define         FLX_ROMSTAT_SEECFG      0xF0
 939#define         FLX_ROMSTAT_EECFG       0x0F
 940#define         FLX_ROMSTAT_SEE_93C66   0x00
 941#define         FLX_ROMSTAT_SEE_NONE    0xF0
 942#define         FLX_ROMSTAT_EE_512x8    0x0
 943#define         FLX_ROMSTAT_EE_1MBx8    0x1
 944#define         FLX_ROMSTAT_EE_2MBx8    0x2
 945#define         FLX_ROMSTAT_EE_4MBx8    0x3
 946#define         FLX_ROMSTAT_EE_16MBx8   0x4
 947#define                 CURSENSE_ENB    0x1
 948#define FLXADDR_FLEXSTAT                0x2
 949#define         FLX_FSTAT_BUSY          0x1
 950#define FLXADDR_CURRENT_STAT            0x4
 951#define         FLX_CSTAT_SEC_HIGH      0xC0
 952#define         FLX_CSTAT_SEC_LOW       0x30
 953#define         FLX_CSTAT_PRI_HIGH      0x0C
 954#define         FLX_CSTAT_PRI_LOW       0x03
 955#define         FLX_CSTAT_MASK          0x03
 956#define         FLX_CSTAT_SHIFT         2
 957#define         FLX_CSTAT_OKAY          0x0
 958#define         FLX_CSTAT_OVER          0x1
 959#define         FLX_CSTAT_UNDER         0x2
 960#define         FLX_CSTAT_INVALID       0x3
 961
 962int             ahd_read_seeprom(struct ahd_softc *ahd, uint16_t *buf,
 963                                 u_int start_addr, u_int count, int bstream);
 964
 965int             ahd_write_seeprom(struct ahd_softc *ahd, uint16_t *buf,
 966                                  u_int start_addr, u_int count);
 967int             ahd_verify_cksum(struct seeprom_config *sc);
 968int             ahd_acquire_seeprom(struct ahd_softc *ahd);
 969void            ahd_release_seeprom(struct ahd_softc *ahd);
 970
 971/****************************  Message Buffer *********************************/
 972typedef enum {
 973        MSG_FLAG_NONE                   = 0x00,
 974        MSG_FLAG_EXPECT_PPR_BUSFREE     = 0x01,
 975        MSG_FLAG_IU_REQ_CHANGED         = 0x02,
 976        MSG_FLAG_EXPECT_IDE_BUSFREE     = 0x04,
 977        MSG_FLAG_EXPECT_QASREJ_BUSFREE  = 0x08,
 978        MSG_FLAG_PACKETIZED             = 0x10
 979} ahd_msg_flags;
 980
 981typedef enum {
 982        MSG_TYPE_NONE                   = 0x00,
 983        MSG_TYPE_INITIATOR_MSGOUT       = 0x01,
 984        MSG_TYPE_INITIATOR_MSGIN        = 0x02,
 985        MSG_TYPE_TARGET_MSGOUT          = 0x03,
 986        MSG_TYPE_TARGET_MSGIN           = 0x04
 987} ahd_msg_type;
 988
 989typedef enum {
 990        MSGLOOP_IN_PROG,
 991        MSGLOOP_MSGCOMPLETE,
 992        MSGLOOP_TERMINATED
 993} msg_loop_stat;
 994
 995/*********************** Software Configuration Structure *********************/
 996struct ahd_suspend_channel_state {
 997        uint8_t scsiseq;
 998        uint8_t sxfrctl0;
 999        uint8_t sxfrctl1;
1000        uint8_t simode0;
1001        uint8_t simode1;
1002        uint8_t seltimer;
1003        uint8_t seqctl;
1004};
1005
1006struct ahd_suspend_pci_state {
1007        uint32_t  devconfig;
1008        uint8_t   command;
1009        uint8_t   csize_lattime;
1010};
1011
1012struct ahd_suspend_state {
1013        struct  ahd_suspend_channel_state channel[2];
1014        struct  ahd_suspend_pci_state pci_state;
1015        uint8_t optionmode;
1016        uint8_t dscommand0;
1017        uint8_t dspcistatus;
1018        /* hsmailbox */
1019        uint8_t crccontrol1;
1020        uint8_t scbbaddr;
1021        /* Host and sequencer SCB counts */
1022        uint8_t dff_thrsh;
1023        uint8_t *scratch_ram;
1024        uint8_t *btt;
1025};
1026
1027typedef void (*ahd_bus_intr_t)(struct ahd_softc *);
1028
1029typedef enum {
1030        AHD_MODE_DFF0,
1031        AHD_MODE_DFF1,
1032        AHD_MODE_CCHAN,
1033        AHD_MODE_SCSI,
1034        AHD_MODE_CFG,
1035        AHD_MODE_UNKNOWN
1036} ahd_mode;
1037
1038#define AHD_MK_MSK(x) (0x01 << (x))
1039#define AHD_MODE_DFF0_MSK       AHD_MK_MSK(AHD_MODE_DFF0)
1040#define AHD_MODE_DFF1_MSK       AHD_MK_MSK(AHD_MODE_DFF1)
1041#define AHD_MODE_CCHAN_MSK      AHD_MK_MSK(AHD_MODE_CCHAN)
1042#define AHD_MODE_SCSI_MSK       AHD_MK_MSK(AHD_MODE_SCSI)
1043#define AHD_MODE_CFG_MSK        AHD_MK_MSK(AHD_MODE_CFG)
1044#define AHD_MODE_UNKNOWN_MSK    AHD_MK_MSK(AHD_MODE_UNKNOWN)
1045#define AHD_MODE_ANY_MSK (~0)
1046
1047typedef uint8_t ahd_mode_state;
1048
1049typedef void ahd_callback_t (void *);
1050
1051struct ahd_completion
1052{
1053        uint16_t        tag;
1054        uint8_t         sg_status;
1055        uint8_t         valid_tag;
1056};
1057
1058struct ahd_softc {
1059        bus_space_tag_t           tags[2];
1060        bus_space_handle_t        bshs[2];
1061#ifndef __linux__
1062        bus_dma_tag_t             buffer_dmat;   /* dmat for buffer I/O */
1063#endif
1064        struct scb_data           scb_data;
1065
1066        struct hardware_scb      *next_queued_hscb;
1067        struct map_node          *next_queued_hscb_map;
1068
1069        /*
1070         * SCBs that have been sent to the controller
1071         */
1072        LIST_HEAD(, scb)          pending_scbs;
1073
1074        /*
1075         * Current register window mode information.
1076         */
1077        ahd_mode                  dst_mode;
1078        ahd_mode                  src_mode;
1079
1080        /*
1081         * Saved register window mode information
1082         * used for restore on next unpause.
1083         */
1084        ahd_mode                  saved_dst_mode;
1085        ahd_mode                  saved_src_mode;
1086
1087        /*
1088         * Platform specific data.
1089         */
1090        struct ahd_platform_data *platform_data;
1091
1092        /*
1093         * Platform specific device information.
1094         */
1095        ahd_dev_softc_t           dev_softc;
1096
1097        /*
1098         * Bus specific device information.
1099         */
1100        ahd_bus_intr_t            bus_intr;
1101
1102        /*
1103         * Target mode related state kept on a per enabled lun basis.
1104         * Targets that are not enabled will have null entries.
1105         * As an initiator, we keep one target entry for our initiator
1106         * ID to store our sync/wide transfer settings.
1107         */
1108        struct ahd_tmode_tstate  *enabled_targets[AHD_NUM_TARGETS];
1109
1110        /*
1111         * The black hole device responsible for handling requests for
1112         * disabled luns on enabled targets.
1113         */
1114        struct ahd_tmode_lstate  *black_hole;
1115
1116        /*
1117         * Device instance currently on the bus awaiting a continue TIO
1118         * for a command that was not given the disconnect priveledge.
1119         */
1120        struct ahd_tmode_lstate  *pending_device;
1121
1122        /*
1123         * Timer handles for timer driven callbacks.
1124         */
1125        ahd_timer_t               reset_timer;
1126        ahd_timer_t               stat_timer;
1127
1128        /*
1129         * Statistics.
1130         */
1131#define AHD_STAT_UPDATE_US      250000 /* 250ms */
1132#define AHD_STAT_BUCKETS        4
1133        u_int                     cmdcmplt_bucket;
1134        uint32_t                  cmdcmplt_counts[AHD_STAT_BUCKETS];
1135        uint32_t                  cmdcmplt_total;
1136
1137        /*
1138         * Card characteristics
1139         */
1140        ahd_chip                  chip;
1141        ahd_feature               features;
1142        ahd_bug                   bugs;
1143        ahd_flag                  flags;
1144        struct seeprom_config    *seep_config;
1145
1146        /* Command Queues */
1147        struct ahd_completion     *qoutfifo;
1148        uint16_t                  qoutfifonext;
1149        uint16_t                  qoutfifonext_valid_tag;
1150        uint16_t                  qinfifonext;
1151        uint16_t                  qinfifo[AHD_SCB_MAX];
1152
1153        /*
1154         * Our qfreeze count.  The sequencer compares
1155         * this value with its own counter to determine
1156         * whether to allow selections to occur.
1157         */
1158        uint16_t                  qfreeze_cnt;
1159
1160        /* Values to store in the SEQCTL register for pause and unpause */
1161        uint8_t                   unpause;
1162        uint8_t                   pause;
1163
1164        /* Critical Section Data */
1165        struct cs                *critical_sections;
1166        u_int                     num_critical_sections;
1167
1168        /* Buffer for handling packetized bitbucket. */
1169        uint8_t                  *overrun_buf;
1170
1171        /* Links for chaining softcs */
1172        TAILQ_ENTRY(ahd_softc)    links;
1173
1174        /* Channel Names ('A', 'B', etc.) */
1175        char                      channel;
1176
1177        /* Initiator Bus ID */
1178        uint8_t                   our_id;
1179
1180        /*
1181         * Target incoming command FIFO.
1182         */
1183        struct target_cmd        *targetcmds;
1184        uint8_t                   tqinfifonext;
1185
1186        /*
1187         * Cached verson of the hs_mailbox so we can avoid
1188         * pausing the sequencer during mailbox updates.
1189         */
1190        uint8_t                   hs_mailbox;
1191
1192        /*
1193         * Incoming and outgoing message handling.
1194         */
1195        uint8_t                   send_msg_perror;
1196        ahd_msg_flags             msg_flags;
1197        ahd_msg_type              msg_type;
1198        uint8_t                   msgout_buf[12];/* Message we are sending */
1199        uint8_t                   msgin_buf[12];/* Message we are receiving */
1200        u_int                     msgout_len;   /* Length of message to send */
1201        u_int                     msgout_index; /* Current index in msgout */
1202        u_int                     msgin_index;  /* Current index in msgin */
1203
1204        /*
1205         * Mapping information for data structures shared
1206         * between the sequencer and kernel.
1207         */
1208        bus_dma_tag_t             parent_dmat;
1209        bus_dma_tag_t             shared_data_dmat;
1210        struct map_node           shared_data_map;
1211
1212        /* Information saved through suspend/resume cycles */
1213        struct ahd_suspend_state  suspend_state;
1214
1215        /* Number of enabled target mode device on this card */
1216        u_int                     enabled_luns;
1217
1218        /* Initialization level of this data structure */
1219        u_int                     init_level;
1220
1221        /* PCI cacheline size. */
1222        u_int                     pci_cachesize;
1223
1224        /* IO Cell Parameters */
1225        uint8_t                   iocell_opts[AHD_NUM_PER_DEV_ANNEXCOLS];
1226
1227        u_int                     stack_size;
1228        uint16_t                 *saved_stack;
1229
1230        /* Per-Unit descriptive information */
1231        const char               *description;
1232        const char               *bus_description;
1233        char                     *name;
1234        int                       unit;
1235
1236        /* Selection Timer settings */
1237        int                       seltime;
1238
1239        /*
1240         * Interrupt coalescing settings.
1241         */
1242#define AHD_INT_COALESCING_TIMER_DEFAULT                250 /*us*/
1243#define AHD_INT_COALESCING_MAXCMDS_DEFAULT              10
1244#define AHD_INT_COALESCING_MAXCMDS_MAX                  127
1245#define AHD_INT_COALESCING_MINCMDS_DEFAULT              5
1246#define AHD_INT_COALESCING_MINCMDS_MAX                  127
1247#define AHD_INT_COALESCING_THRESHOLD_DEFAULT            2000
1248#define AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT       1000
1249        u_int                     int_coalescing_timer;
1250        u_int                     int_coalescing_maxcmds;
1251        u_int                     int_coalescing_mincmds;
1252        u_int                     int_coalescing_threshold;
1253        u_int                     int_coalescing_stop_threshold;
1254
1255        uint16_t                  user_discenable;/* Disconnection allowed  */
1256        uint16_t                  user_tagenable;/* Tagged Queuing allowed */
1257};
1258
1259/*************************** IO Cell Configuration ****************************/
1260#define AHD_PRECOMP_SLEW_INDEX                                          \
1261    (AHD_ANNEXCOL_PRECOMP_SLEW - AHD_ANNEXCOL_PER_DEV0)
1262
1263#define AHD_AMPLITUDE_INDEX                                             \
1264    (AHD_ANNEXCOL_AMPLITUDE - AHD_ANNEXCOL_PER_DEV0)
1265
1266#define AHD_SET_SLEWRATE(ahd, new_slew)                                 \
1267do {                                                                    \
1268    (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_SLEWRATE_MASK;   \
1269    (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |=                       \
1270        (((new_slew) << AHD_SLEWRATE_SHIFT) & AHD_SLEWRATE_MASK);       \
1271} while (0)
1272
1273#define AHD_SET_PRECOMP(ahd, new_pcomp)                                 \
1274do {                                                                    \
1275    (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] &= ~AHD_PRECOMP_MASK;    \
1276    (ahd)->iocell_opts[AHD_PRECOMP_SLEW_INDEX] |=                       \
1277        (((new_pcomp) << AHD_PRECOMP_SHIFT) & AHD_PRECOMP_MASK);        \
1278} while (0)
1279
1280#define AHD_SET_AMPLITUDE(ahd, new_amp)                                 \
1281do {                                                                    \
1282    (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] &= ~AHD_AMPLITUDE_MASK;     \
1283    (ahd)->iocell_opts[AHD_AMPLITUDE_INDEX] |=                          \
1284        (((new_amp) << AHD_AMPLITUDE_SHIFT) & AHD_AMPLITUDE_MASK);      \
1285} while (0)
1286
1287/************************ Active Device Information ***************************/
1288typedef enum {
1289        ROLE_UNKNOWN,
1290        ROLE_INITIATOR,
1291        ROLE_TARGET
1292} role_t;
1293
1294struct ahd_devinfo {
1295        int      our_scsiid;
1296        int      target_offset;
1297        uint16_t target_mask;
1298        u_int    target;
1299        u_int    lun;
1300        char     channel;
1301        role_t   role;          /*
1302                                 * Only guaranteed to be correct if not
1303                                 * in the busfree state.
1304                                 */
1305};
1306
1307/****************************** PCI Structures ********************************/
1308#define AHD_PCI_IOADDR0 PCIR_BAR(0)     /* I/O BAR*/
1309#define AHD_PCI_MEMADDR PCIR_BAR(1)     /* Memory BAR */
1310#define AHD_PCI_IOADDR1 PCIR_BAR(3)     /* Second I/O BAR */
1311
1312typedef int (ahd_device_setup_t)(struct ahd_softc *);
1313
1314struct ahd_pci_identity {
1315        uint64_t                 full_id;
1316        uint64_t                 id_mask;
1317        const char              *name;
1318        ahd_device_setup_t      *setup;
1319};
1320
1321/***************************** VL/EISA Declarations ***************************/
1322struct aic7770_identity {
1323        uint32_t                 full_id;
1324        uint32_t                 id_mask;
1325        const char              *name;
1326        ahd_device_setup_t      *setup;
1327};
1328extern struct aic7770_identity aic7770_ident_table [];
1329extern const int ahd_num_aic7770_devs;
1330
1331#define AHD_EISA_SLOT_OFFSET    0xc00
1332#define AHD_EISA_IOSIZE         0x100
1333
1334/*************************** Function Declarations ****************************/
1335/******************************************************************************/
1336
1337/***************************** PCI Front End *********************************/
1338const struct    ahd_pci_identity *ahd_find_pci_device(ahd_dev_softc_t);
1339int                       ahd_pci_config(struct ahd_softc *,
1340                                         const struct ahd_pci_identity *);
1341int     ahd_pci_test_register_access(struct ahd_softc *);
1342#ifdef CONFIG_PM
1343void    ahd_pci_suspend(struct ahd_softc *);
1344void    ahd_pci_resume(struct ahd_softc *);
1345#endif
1346
1347/************************** SCB and SCB queue management **********************/
1348void            ahd_qinfifo_requeue_tail(struct ahd_softc *ahd,
1349                                         struct scb *scb);
1350
1351/****************************** Initialization ********************************/
1352struct ahd_softc        *ahd_alloc(void *platform_arg, char *name);
1353int                      ahd_softc_init(struct ahd_softc *);
1354void                     ahd_controller_info(struct ahd_softc *ahd, char *buf);
1355int                      ahd_init(struct ahd_softc *ahd);
1356#ifdef CONFIG_PM
1357int                      ahd_suspend(struct ahd_softc *ahd);
1358void                     ahd_resume(struct ahd_softc *ahd);
1359#endif
1360int                      ahd_default_config(struct ahd_softc *ahd);
1361int                      ahd_parse_vpddata(struct ahd_softc *ahd,
1362                                           struct vpd_config *vpd);
1363int                      ahd_parse_cfgdata(struct ahd_softc *ahd,
1364                                           struct seeprom_config *sc);
1365void                     ahd_intr_enable(struct ahd_softc *ahd, int enable);
1366void                     ahd_pause_and_flushwork(struct ahd_softc *ahd);
1367void                     ahd_set_unit(struct ahd_softc *, int);
1368void                     ahd_set_name(struct ahd_softc *, char *);
1369struct scb              *ahd_get_scb(struct ahd_softc *ahd, u_int col_idx);
1370void                     ahd_free_scb(struct ahd_softc *ahd, struct scb *scb);
1371void                     ahd_free(struct ahd_softc *ahd);
1372int                      ahd_reset(struct ahd_softc *ahd, int reinit);
1373int                      ahd_write_flexport(struct ahd_softc *ahd,
1374                                            u_int addr, u_int value);
1375int                      ahd_read_flexport(struct ahd_softc *ahd, u_int addr,
1376                                           uint8_t *value);
1377
1378/***************************** Error Recovery *********************************/
1379typedef enum {
1380        SEARCH_COMPLETE,
1381        SEARCH_COUNT,
1382        SEARCH_REMOVE,
1383        SEARCH_PRINT
1384} ahd_search_action;
1385int                     ahd_search_qinfifo(struct ahd_softc *ahd, int target,
1386                                           char channel, int lun, u_int tag,
1387                                           role_t role, uint32_t status,
1388                                           ahd_search_action action);
1389int                     ahd_search_disc_list(struct ahd_softc *ahd, int target,
1390                                             char channel, int lun, u_int tag,
1391                                             int stop_on_first, int remove,
1392                                             int save_state);
1393int                     ahd_reset_channel(struct ahd_softc *ahd, char channel,
1394                                          int initiate_reset);
1395/*************************** Utility Functions ********************************/
1396void                    ahd_compile_devinfo(struct ahd_devinfo *devinfo,
1397                                            u_int our_id, u_int target,
1398                                            u_int lun, char channel,
1399                                            role_t role);
1400/************************** Transfer Negotiation ******************************/
1401void                    ahd_find_syncrate(struct ahd_softc *ahd, u_int *period,
1402                                          u_int *ppr_options, u_int maxsync);
1403/*
1404 * Negotiation types.  These are used to qualify if we should renegotiate
1405 * even if our goal and current transport parameters are identical.
1406 */
1407typedef enum {
1408        AHD_NEG_TO_GOAL,        /* Renegotiate only if goal and curr differ. */
1409        AHD_NEG_IF_NON_ASYNC,   /* Renegotiate so long as goal is non-async. */
1410        AHD_NEG_ALWAYS          /* Renegotiat even if goal is async. */
1411} ahd_neg_type;
1412int                     ahd_update_neg_request(struct ahd_softc*,
1413                                               struct ahd_devinfo*,
1414                                               struct ahd_tmode_tstate*,
1415                                               struct ahd_initiator_tinfo*,
1416                                               ahd_neg_type);
1417void                    ahd_set_width(struct ahd_softc *ahd,
1418                                      struct ahd_devinfo *devinfo,
1419                                      u_int width, u_int type, int paused);
1420void                    ahd_set_syncrate(struct ahd_softc *ahd,
1421                                         struct ahd_devinfo *devinfo,
1422                                         u_int period, u_int offset,
1423                                         u_int ppr_options,
1424                                         u_int type, int paused);
1425typedef enum {
1426        AHD_QUEUE_NONE,
1427        AHD_QUEUE_BASIC,
1428        AHD_QUEUE_TAGGED
1429} ahd_queue_alg;
1430
1431/**************************** Target Mode *************************************/
1432#ifdef AHD_TARGET_MODE
1433void            ahd_send_lstate_events(struct ahd_softc *,
1434                                       struct ahd_tmode_lstate *);
1435void            ahd_handle_en_lun(struct ahd_softc *ahd,
1436                                  struct cam_sim *sim, union ccb *ccb);
1437cam_status      ahd_find_tmode_devs(struct ahd_softc *ahd,
1438                                    struct cam_sim *sim, union ccb *ccb,
1439                                    struct ahd_tmode_tstate **tstate,
1440                                    struct ahd_tmode_lstate **lstate,
1441                                    int notfound_failure);
1442#ifndef AHD_TMODE_ENABLE
1443#define AHD_TMODE_ENABLE 0
1444#endif
1445#endif
1446/******************************* Debug ***************************************/
1447#ifdef AHD_DEBUG
1448extern uint32_t ahd_debug;
1449#define AHD_SHOW_MISC           0x00001
1450#define AHD_SHOW_SENSE          0x00002
1451#define AHD_SHOW_RECOVERY       0x00004
1452#define AHD_DUMP_SEEPROM        0x00008
1453#define AHD_SHOW_TERMCTL        0x00010
1454#define AHD_SHOW_MEMORY         0x00020
1455#define AHD_SHOW_MESSAGES       0x00040
1456#define AHD_SHOW_MODEPTR        0x00080
1457#define AHD_SHOW_SELTO          0x00100
1458#define AHD_SHOW_FIFOS          0x00200
1459#define AHD_SHOW_QFULL          0x00400
1460#define AHD_SHOW_DV             0x00800
1461#define AHD_SHOW_MASKED_ERRORS  0x01000
1462#define AHD_SHOW_QUEUE          0x02000
1463#define AHD_SHOW_TQIN           0x04000
1464#define AHD_SHOW_SG             0x08000
1465#define AHD_SHOW_INT_COALESCING 0x10000
1466#define AHD_DEBUG_SEQUENCER     0x20000
1467#endif
1468void                    ahd_print_devinfo(struct ahd_softc *ahd,
1469                                          struct ahd_devinfo *devinfo);
1470void                    ahd_dump_card_state(struct ahd_softc *ahd);
1471int                     ahd_print_register(const ahd_reg_parse_entry_t *table,
1472                                           u_int num_entries,
1473                                           const char *name,
1474                                           u_int address,
1475                                           u_int value,
1476                                           u_int *cur_column,
1477                                           u_int wrap_point);
1478#endif /* _AIC79XX_H_ */
1479