1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#ifndef __BFA_DEFS_H__
19#define __BFA_DEFS_H__
20
21#include "bfa_fc.h"
22#include "bfad_drv.h"
23
24#define BFA_MFG_SERIALNUM_SIZE 11
25#define STRSZ(_n) (((_n) + 4) & ~3)
26
27
28
29
30enum {
31 BFA_MFG_TYPE_CB_MAX = 825,
32 BFA_MFG_TYPE_FC8P2 = 825,
33 BFA_MFG_TYPE_FC8P1 = 815,
34 BFA_MFG_TYPE_FC4P2 = 425,
35 BFA_MFG_TYPE_FC4P1 = 415,
36 BFA_MFG_TYPE_CNA10P2 = 1020,
37 BFA_MFG_TYPE_CNA10P1 = 1010,
38 BFA_MFG_TYPE_JAYHAWK = 804,
39 BFA_MFG_TYPE_WANCHESE = 1007,
40 BFA_MFG_TYPE_ASTRA = 807,
41 BFA_MFG_TYPE_LIGHTNING_P0 = 902,
42 BFA_MFG_TYPE_LIGHTNING = 1741,
43 BFA_MFG_TYPE_PROWLER_F = 1560,
44 BFA_MFG_TYPE_PROWLER_N = 1410,
45 BFA_MFG_TYPE_PROWLER_C = 1710,
46 BFA_MFG_TYPE_PROWLER_D = 1860,
47 BFA_MFG_TYPE_CHINOOK = 1867,
48 BFA_MFG_TYPE_CHINOOK2 = 1869,
49 BFA_MFG_TYPE_INVALID = 0,
50};
51
52#pragma pack(1)
53
54
55
56
57#define bfa_mfg_is_mezz(type) (( \
58 (type) == BFA_MFG_TYPE_JAYHAWK || \
59 (type) == BFA_MFG_TYPE_WANCHESE || \
60 (type) == BFA_MFG_TYPE_ASTRA || \
61 (type) == BFA_MFG_TYPE_LIGHTNING_P0 || \
62 (type) == BFA_MFG_TYPE_LIGHTNING || \
63 (type) == BFA_MFG_TYPE_CHINOOK || \
64 (type) == BFA_MFG_TYPE_CHINOOK2))
65
66
67
68
69#define bfa_mfg_is_old_wwn_mac_model(type) (( \
70 (type) == BFA_MFG_TYPE_FC8P2 || \
71 (type) == BFA_MFG_TYPE_FC8P1 || \
72 (type) == BFA_MFG_TYPE_FC4P2 || \
73 (type) == BFA_MFG_TYPE_FC4P1 || \
74 (type) == BFA_MFG_TYPE_CNA10P2 || \
75 (type) == BFA_MFG_TYPE_CNA10P1 || \
76 (type) == BFA_MFG_TYPE_JAYHAWK || \
77 (type) == BFA_MFG_TYPE_WANCHESE))
78
79#define bfa_mfg_increment_wwn_mac(m, i) \
80do { \
81 u32 t = ((u32)(m)[0] << 16) | ((u32)(m)[1] << 8) | \
82 (u32)(m)[2]; \
83 t += (i); \
84 (m)[0] = (t >> 16) & 0xFF; \
85 (m)[1] = (t >> 8) & 0xFF; \
86 (m)[2] = t & 0xFF; \
87} while (0)
88
89
90
91
92#define BFA_MFG_VPD_LEN 512
93
94
95
96
97enum {
98 BFA_MFG_VPD_UNKNOWN = 0,
99 BFA_MFG_VPD_IBM = 1,
100 BFA_MFG_VPD_HP = 2,
101 BFA_MFG_VPD_DELL = 3,
102 BFA_MFG_VPD_PCI_IBM = 0x08,
103 BFA_MFG_VPD_PCI_HP = 0x10,
104 BFA_MFG_VPD_PCI_DELL = 0x20,
105 BFA_MFG_VPD_PCI_BRCD = 0xf8,
106};
107
108
109
110
111struct bfa_mfg_vpd_s {
112 u8 version;
113 u8 vpd_sig[3];
114 u8 chksum;
115 u8 vendor;
116 u8 len;
117 u8 rsv;
118 u8 data[BFA_MFG_VPD_LEN];
119};
120
121#pragma pack()
122
123
124
125
126enum bfa_status {
127 BFA_STATUS_OK = 0,
128 BFA_STATUS_FAILED = 1,
129 BFA_STATUS_EINVAL = 2,
130
131 BFA_STATUS_ENOMEM = 3,
132 BFA_STATUS_ETIMER = 5,
133
134 BFA_STATUS_EPROTOCOL = 6,
135 BFA_STATUS_SFP_UNSUPP = 10,
136 BFA_STATUS_UNKNOWN_VFID = 11,
137 BFA_STATUS_DATACORRUPTED = 12,
138 BFA_STATUS_DEVBUSY = 13,
139 BFA_STATUS_HDMA_FAILED = 16,
140 BFA_STATUS_FLASH_BAD_LEN = 17,
141 BFA_STATUS_UNKNOWN_LWWN = 18,
142 BFA_STATUS_UNKNOWN_RWWN = 19,
143 BFA_STATUS_VPORT_EXISTS = 21,
144 BFA_STATUS_VPORT_MAX = 22,
145 BFA_STATUS_UNSUPP_SPEED = 23,
146 BFA_STATUS_INVLD_DFSZ = 24,
147 BFA_STATUS_CMD_NOTSUPP = 26,
148 BFA_STATUS_FABRIC_RJT = 29,
149 BFA_STATUS_UNKNOWN_VWWN = 30,
150 BFA_STATUS_PORT_OFFLINE = 34,
151 BFA_STATUS_VPORT_WWN_BP = 46,
152 BFA_STATUS_PORT_NOT_DISABLED = 47,
153 BFA_STATUS_NO_FCPIM_NEXUS = 52,
154 BFA_STATUS_IOC_FAILURE = 56,
155
156 BFA_STATUS_INVALID_WWN = 57,
157 BFA_STATUS_ADAPTER_ENABLED = 60,
158 BFA_STATUS_IOC_NON_OP = 61,
159 BFA_STATUS_VERSION_FAIL = 70,
160 BFA_STATUS_DIAG_BUSY = 71,
161 BFA_STATUS_BEACON_ON = 72,
162 BFA_STATUS_ENOFSAVE = 78,
163 BFA_STATUS_IOC_DISABLED = 82,
164 BFA_STATUS_ERROR_TRL_ENABLED = 87,
165 BFA_STATUS_ERROR_QOS_ENABLED = 88,
166 BFA_STATUS_NO_SFP_DEV = 89,
167 BFA_STATUS_MEMTEST_FAILED = 90,
168 BFA_STATUS_LEDTEST_OP = 109,
169 BFA_STATUS_INVALID_MAC = 134,
170 BFA_STATUS_CMD_NOTSUPP_CNA = 146,
171 BFA_STATUS_PBC = 154,
172
173 BFA_STATUS_BAD_FWCFG = 156,
174 BFA_STATUS_INVALID_VENDOR = 158,
175 BFA_STATUS_SFP_NOT_READY = 159,
176 BFA_STATUS_TRUNK_ENABLED = 164,
177
178 BFA_STATUS_TRUNK_DISABLED = 165,
179
180 BFA_STATUS_IOPROFILE_OFF = 175,
181 BFA_STATUS_PHY_NOT_PRESENT = 183,
182 BFA_STATUS_FEATURE_NOT_SUPPORTED = 192,
183 BFA_STATUS_ENTRY_EXISTS = 193,
184 BFA_STATUS_ENTRY_NOT_EXISTS = 194,
185 BFA_STATUS_NO_CHANGE = 195,
186 BFA_STATUS_FAA_ENABLED = 197,
187 BFA_STATUS_FAA_DISABLED = 198,
188 BFA_STATUS_FAA_ACQUIRED = 199,
189 BFA_STATUS_FAA_ACQ_ADDR = 200,
190 BFA_STATUS_BBCR_FC_ONLY = 201,
191
192 BFA_STATUS_ERROR_TRUNK_ENABLED = 203,
193 BFA_STATUS_MAX_ENTRY_REACHED = 212,
194 BFA_STATUS_TOPOLOGY_LOOP = 230,
195 BFA_STATUS_LOOP_UNSUPP_MEZZ = 231,
196
197 BFA_STATUS_INVALID_BW = 233,
198 BFA_STATUS_QOS_BW_INVALID = 234,
199
200 BFA_STATUS_DPORT_ENABLED = 235,
201 BFA_STATUS_DPORT_DISABLED = 236,
202 BFA_STATUS_CMD_NOTSUPP_MEZZ = 239,
203 BFA_STATUS_FRU_NOT_PRESENT = 240,
204 BFA_STATUS_DPORT_NO_SFP = 243,
205
206
207 BFA_STATUS_DPORT_ERR = 245,
208 BFA_STATUS_DPORT_ENOSYS = 254,
209 BFA_STATUS_DPORT_CANT_PERF = 255,
210
211 BFA_STATUS_DPORT_LOGICALERR = 256,
212 BFA_STATUS_DPORT_SWBUSY = 257,
213 BFA_STATUS_ERR_BBCR_SPEED_UNSUPPORT = 258,
214
215 BFA_STATUS_ERROR_BBCR_ENABLED = 259,
216
217 BFA_STATUS_INVALID_BBSCN = 260,
218
219 BFA_STATUS_DDPORT_ERR = 261,
220
221
222 BFA_STATUS_DPORT_SFPWRAP_ERR = 262,
223
224 BFA_STATUS_BBCR_CFG_NO_CHANGE = 265,
225
226 BFA_STATUS_DPORT_SW_NOTREADY = 268,
227
228
229 BFA_STATUS_DPORT_INV_SFP = 271,
230 BFA_STATUS_DPORT_CMD_NOTSUPP = 273,
231
232 BFA_STATUS_MAX_VAL
233};
234#define bfa_status_t enum bfa_status
235
236enum bfa_eproto_status {
237 BFA_EPROTO_BAD_ACCEPT = 0,
238 BFA_EPROTO_UNKNOWN_RSP = 1
239};
240#define bfa_eproto_status_t enum bfa_eproto_status
241
242enum bfa_boolean {
243 BFA_FALSE = 0,
244 BFA_TRUE = 1
245};
246#define bfa_boolean_t enum bfa_boolean
247
248#define BFA_STRING_32 32
249#define BFA_VERSION_LEN 64
250
251
252
253
254
255
256
257
258enum {
259 BFA_ADAPTER_SERIAL_NUM_LEN = STRSZ(BFA_MFG_SERIALNUM_SIZE),
260
261
262
263 BFA_ADAPTER_MODEL_NAME_LEN = 16,
264 BFA_ADAPTER_MODEL_DESCR_LEN = 128,
265 BFA_ADAPTER_MFG_NAME_LEN = 8,
266 BFA_ADAPTER_SYM_NAME_LEN = 64,
267 BFA_ADAPTER_OS_TYPE_LEN = 64,
268 BFA_ADAPTER_UUID_LEN = 16,
269};
270
271struct bfa_adapter_attr_s {
272 char manufacturer[BFA_ADAPTER_MFG_NAME_LEN];
273 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
274 u32 card_type;
275 char model[BFA_ADAPTER_MODEL_NAME_LEN];
276 char model_descr[BFA_ADAPTER_MODEL_DESCR_LEN];
277 wwn_t pwwn;
278 char node_symname[FC_SYMNAME_MAX];
279 char hw_ver[BFA_VERSION_LEN];
280 char fw_ver[BFA_VERSION_LEN];
281 char optrom_ver[BFA_VERSION_LEN];
282 char os_type[BFA_ADAPTER_OS_TYPE_LEN];
283 struct bfa_mfg_vpd_s vpd;
284 struct mac_s mac;
285
286 u8 nports;
287 u8 max_speed;
288 u8 prototype;
289 char asic_rev;
290
291 u8 pcie_gen;
292 u8 pcie_lanes_orig;
293 u8 pcie_lanes;
294 u8 cna_capable;
295
296 u8 is_mezz;
297 u8 trunk_capable;
298 u8 mfg_day;
299 u8 mfg_month;
300 u16 mfg_year;
301 u16 rsvd;
302 u8 uuid[BFA_ADAPTER_UUID_LEN];
303};
304
305
306
307
308
309enum {
310 BFA_IOC_DRIVER_LEN = 16,
311 BFA_IOC_CHIP_REV_LEN = 8,
312};
313
314
315
316
317struct bfa_ioc_driver_attr_s {
318 char driver[BFA_IOC_DRIVER_LEN];
319 char driver_ver[BFA_VERSION_LEN];
320 char fw_ver[BFA_VERSION_LEN];
321 char bios_ver[BFA_VERSION_LEN];
322 char efi_ver[BFA_VERSION_LEN];
323 char ob_ver[BFA_VERSION_LEN];
324};
325
326
327
328
329struct bfa_ioc_pci_attr_s {
330 u16 vendor_id;
331 u16 device_id;
332 u16 ssid;
333 u16 ssvid;
334 u32 pcifn;
335 u32 rsvd;
336 char chip_rev[BFA_IOC_CHIP_REV_LEN];
337};
338
339
340
341
342enum bfa_ioc_state {
343 BFA_IOC_UNINIT = 1,
344 BFA_IOC_RESET = 2,
345 BFA_IOC_SEMWAIT = 3,
346 BFA_IOC_HWINIT = 4,
347 BFA_IOC_GETATTR = 5,
348 BFA_IOC_OPERATIONAL = 6,
349 BFA_IOC_INITFAIL = 7,
350 BFA_IOC_FAIL = 8,
351 BFA_IOC_DISABLING = 9,
352 BFA_IOC_DISABLED = 10,
353 BFA_IOC_FWMISMATCH = 11,
354 BFA_IOC_ENABLING = 12,
355 BFA_IOC_HWFAIL = 13,
356 BFA_IOC_ACQ_ADDR = 14,
357};
358
359
360
361
362struct bfa_fw_ioc_stats_s {
363 u32 enable_reqs;
364 u32 disable_reqs;
365 u32 get_attr_reqs;
366 u32 dbg_sync;
367 u32 dbg_dump;
368 u32 unknown_reqs;
369};
370
371
372
373
374struct bfa_ioc_drv_stats_s {
375 u32 ioc_isrs;
376 u32 ioc_enables;
377 u32 ioc_disables;
378 u32 ioc_hbfails;
379 u32 ioc_boots;
380 u32 stats_tmos;
381 u32 hb_count;
382 u32 disable_reqs;
383 u32 enable_reqs;
384 u32 disable_replies;
385 u32 enable_replies;
386 u32 rsvd;
387};
388
389
390
391
392struct bfa_ioc_stats_s {
393 struct bfa_ioc_drv_stats_s drv_stats;
394 struct bfa_fw_ioc_stats_s fw_stats;
395};
396
397enum bfa_ioc_type_e {
398 BFA_IOC_TYPE_FC = 1,
399 BFA_IOC_TYPE_FCoE = 2,
400 BFA_IOC_TYPE_LL = 3,
401};
402
403
404
405
406struct bfa_ioc_attr_s {
407 enum bfa_ioc_type_e ioc_type;
408 enum bfa_ioc_state state;
409 struct bfa_adapter_attr_s adapter_attr;
410 struct bfa_ioc_driver_attr_s driver_attr;
411 struct bfa_ioc_pci_attr_s pci_attr;
412 u8 port_id;
413 u8 port_mode;
414 u8 cap_bm;
415 u8 port_mode_cfg;
416 u8 def_fn;
417 u8 rsvd[3];
418};
419
420
421
422
423enum bfa_aen_category {
424 BFA_AEN_CAT_ADAPTER = 1,
425 BFA_AEN_CAT_PORT = 2,
426 BFA_AEN_CAT_LPORT = 3,
427 BFA_AEN_CAT_RPORT = 4,
428 BFA_AEN_CAT_ITNIM = 5,
429 BFA_AEN_CAT_AUDIT = 8,
430 BFA_AEN_CAT_IOC = 9,
431};
432
433
434enum bfa_adapter_aen_event {
435 BFA_ADAPTER_AEN_ADD = 1,
436 BFA_ADAPTER_AEN_REMOVE = 2,
437};
438
439struct bfa_adapter_aen_data_s {
440 char serial_num[BFA_ADAPTER_SERIAL_NUM_LEN];
441 u32 nports;
442 wwn_t pwwn;
443};
444
445
446enum bfa_port_aen_event {
447 BFA_PORT_AEN_ONLINE = 1,
448 BFA_PORT_AEN_OFFLINE = 2,
449 BFA_PORT_AEN_RLIR = 3,
450 BFA_PORT_AEN_SFP_INSERT = 4,
451 BFA_PORT_AEN_SFP_REMOVE = 5,
452 BFA_PORT_AEN_SFP_POM = 6,
453 BFA_PORT_AEN_ENABLE = 7,
454 BFA_PORT_AEN_DISABLE = 8,
455 BFA_PORT_AEN_AUTH_ON = 9,
456 BFA_PORT_AEN_AUTH_OFF = 10,
457 BFA_PORT_AEN_DISCONNECT = 11,
458 BFA_PORT_AEN_QOS_NEG = 12,
459 BFA_PORT_AEN_FABRIC_NAME_CHANGE = 13,
460 BFA_PORT_AEN_SFP_ACCESS_ERROR = 14,
461 BFA_PORT_AEN_SFP_UNSUPPORT = 15,
462};
463
464enum bfa_port_aen_sfp_pom {
465 BFA_PORT_AEN_SFP_POM_GREEN = 1,
466 BFA_PORT_AEN_SFP_POM_AMBER = 2,
467 BFA_PORT_AEN_SFP_POM_RED = 3,
468 BFA_PORT_AEN_SFP_POM_MAX = BFA_PORT_AEN_SFP_POM_RED
469};
470
471struct bfa_port_aen_data_s {
472 wwn_t pwwn;
473 wwn_t fwwn;
474 u32 phy_port_num;
475 u16 ioc_type;
476 u16 level;
477 mac_t mac;
478 u16 rsvd;
479};
480
481
482enum bfa_lport_aen_event {
483 BFA_LPORT_AEN_NEW = 1,
484 BFA_LPORT_AEN_DELETE = 2,
485 BFA_LPORT_AEN_ONLINE = 3,
486 BFA_LPORT_AEN_OFFLINE = 4,
487 BFA_LPORT_AEN_DISCONNECT = 5,
488 BFA_LPORT_AEN_NEW_PROP = 6,
489 BFA_LPORT_AEN_DELETE_PROP = 7,
490 BFA_LPORT_AEN_NEW_STANDARD = 8,
491 BFA_LPORT_AEN_DELETE_STANDARD = 9,
492 BFA_LPORT_AEN_NPIV_DUP_WWN = 10,
493 BFA_LPORT_AEN_NPIV_FABRIC_MAX = 11,
494 BFA_LPORT_AEN_NPIV_UNKNOWN = 12,
495};
496
497struct bfa_lport_aen_data_s {
498 u16 vf_id;
499 u16 roles;
500 u32 rsvd;
501 wwn_t ppwwn;
502 wwn_t lpwwn;
503};
504
505
506enum bfa_itnim_aen_event {
507 BFA_ITNIM_AEN_ONLINE = 1,
508 BFA_ITNIM_AEN_OFFLINE = 2,
509 BFA_ITNIM_AEN_DISCONNECT = 3,
510};
511
512struct bfa_itnim_aen_data_s {
513 u16 vf_id;
514 u16 rsvd[3];
515 wwn_t ppwwn;
516 wwn_t lpwwn;
517 wwn_t rpwwn;
518};
519
520
521enum bfa_audit_aen_event {
522 BFA_AUDIT_AEN_AUTH_ENABLE = 1,
523 BFA_AUDIT_AEN_AUTH_DISABLE = 2,
524 BFA_AUDIT_AEN_FLASH_ERASE = 3,
525 BFA_AUDIT_AEN_FLASH_UPDATE = 4,
526};
527
528struct bfa_audit_aen_data_s {
529 wwn_t pwwn;
530 int partition_inst;
531 int partition_type;
532};
533
534
535enum bfa_ioc_aen_event {
536 BFA_IOC_AEN_HBGOOD = 1,
537 BFA_IOC_AEN_HBFAIL = 2,
538 BFA_IOC_AEN_ENABLE = 3,
539 BFA_IOC_AEN_DISABLE = 4,
540 BFA_IOC_AEN_FWMISMATCH = 5,
541 BFA_IOC_AEN_FWCFG_ERROR = 6,
542 BFA_IOC_AEN_INVALID_VENDOR = 7,
543 BFA_IOC_AEN_INVALID_NWWN = 8,
544 BFA_IOC_AEN_INVALID_PWWN = 9
545};
546
547struct bfa_ioc_aen_data_s {
548 wwn_t pwwn;
549 u16 ioc_type;
550 mac_t mac;
551};
552
553
554
555
556
557
558
559
560#define BFA_MFG_CHKSUM_SIZE 16
561
562#define BFA_MFG_PARTNUM_SIZE 14
563#define BFA_MFG_SUPPLIER_ID_SIZE 10
564#define BFA_MFG_SUPPLIER_PARTNUM_SIZE 20
565#define BFA_MFG_SUPPLIER_SERIALNUM_SIZE 20
566#define BFA_MFG_SUPPLIER_REVISION_SIZE 4
567
568
569
570#define BFA_MFG_IC_FC 0x01
571#define BFA_MFG_IC_ETH 0x02
572
573
574
575
576#define BFA_CM_HBA 0x01
577#define BFA_CM_CNA 0x02
578#define BFA_CM_NIC 0x04
579#define BFA_CM_FC16G 0x08
580#define BFA_CM_SRIOV 0x10
581#define BFA_CM_MEZZ 0x20
582
583#pragma pack(1)
584
585
586
587
588struct bfa_mfg_block_s {
589 u8 version;
590 u8 mfg_sig[3];
591 u16 mfgsize;
592 u16 u16_chksum;
593 char brcd_serialnum[STRSZ(BFA_MFG_SERIALNUM_SIZE)];
594 char brcd_partnum[STRSZ(BFA_MFG_PARTNUM_SIZE)];
595 u8 mfg_day;
596 u8 mfg_month;
597 u16 mfg_year;
598 wwn_t mfg_wwn;
599 u8 num_wwn;
600 u8 mfg_speeds;
601 u8 rsv[2];
602 char supplier_id[STRSZ(BFA_MFG_SUPPLIER_ID_SIZE)];
603 char supplier_partnum[STRSZ(BFA_MFG_SUPPLIER_PARTNUM_SIZE)];
604 char supplier_serialnum[STRSZ(BFA_MFG_SUPPLIER_SERIALNUM_SIZE)];
605 char supplier_revision[STRSZ(BFA_MFG_SUPPLIER_REVISION_SIZE)];
606 mac_t mfg_mac;
607 u8 num_mac;
608 u8 rsv2;
609 u32 card_type;
610 char cap_nic;
611 char cap_cna;
612 char cap_hba;
613 char cap_fc16g;
614 char cap_sriov;
615 char cap_mezz;
616 u8 rsv3;
617 u8 mfg_nports;
618 char media[8];
619 char initial_mode[8];
620 u8 rsv4[84];
621 u8 md5_chksum[BFA_MFG_CHKSUM_SIZE];
622};
623
624#pragma pack()
625
626
627
628
629
630
631
632
633enum {
634 BFA_PCI_VENDOR_ID_BROCADE = 0x1657,
635 BFA_PCI_DEVICE_ID_FC_8G2P = 0x13,
636 BFA_PCI_DEVICE_ID_FC_8G1P = 0x17,
637 BFA_PCI_DEVICE_ID_CT = 0x14,
638 BFA_PCI_DEVICE_ID_CT_FC = 0x21,
639 BFA_PCI_DEVICE_ID_CT2 = 0x22,
640 BFA_PCI_DEVICE_ID_CT2_QUAD = 0x23,
641};
642
643#define bfa_asic_id_cb(__d) \
644 ((__d) == BFA_PCI_DEVICE_ID_FC_8G2P || \
645 (__d) == BFA_PCI_DEVICE_ID_FC_8G1P)
646#define bfa_asic_id_ct(__d) \
647 ((__d) == BFA_PCI_DEVICE_ID_CT || \
648 (__d) == BFA_PCI_DEVICE_ID_CT_FC)
649#define bfa_asic_id_ct2(__d) \
650 ((__d) == BFA_PCI_DEVICE_ID_CT2 || \
651 (__d) == BFA_PCI_DEVICE_ID_CT2_QUAD)
652#define bfa_asic_id_ctc(__d) \
653 (bfa_asic_id_ct(__d) || bfa_asic_id_ct2(__d))
654
655
656
657
658enum {
659 BFA_PCI_FCOE_SSDEVICE_ID = 0x14,
660 BFA_PCI_CT2_SSID_FCoE = 0x22,
661 BFA_PCI_CT2_SSID_ETH = 0x23,
662 BFA_PCI_CT2_SSID_FC = 0x24,
663};
664
665
666
667
668#define BFA_PCI_ACCESS_RANGES 1
669
670
671
672
673
674enum bfa_port_speed {
675 BFA_PORT_SPEED_UNKNOWN = 0,
676 BFA_PORT_SPEED_1GBPS = 1,
677 BFA_PORT_SPEED_2GBPS = 2,
678 BFA_PORT_SPEED_4GBPS = 4,
679 BFA_PORT_SPEED_8GBPS = 8,
680 BFA_PORT_SPEED_10GBPS = 10,
681 BFA_PORT_SPEED_16GBPS = 16,
682 BFA_PORT_SPEED_AUTO = 0xf,
683};
684#define bfa_port_speed_t enum bfa_port_speed
685
686enum {
687 BFA_BOOT_BOOTLUN_MAX = 4,
688 BFA_PREBOOT_BOOTLUN_MAX = 8,
689};
690
691#define BOOT_CFG_REV1 1
692#define BOOT_CFG_VLAN 1
693
694
695
696
697
698enum bfa_boot_bootopt {
699 BFA_BOOT_AUTO_DISCOVER = 0,
700 BFA_BOOT_STORED_BLUN = 1,
701 BFA_BOOT_FIRST_LUN = 2,
702 BFA_BOOT_PBC = 3,
703};
704
705#pragma pack(1)
706
707
708
709struct bfa_boot_bootlun_s {
710 wwn_t pwwn;
711 struct scsi_lun lun;
712};
713#pragma pack()
714
715
716
717
718struct bfa_boot_cfg_s {
719 u8 version;
720 u8 rsvd1;
721 u16 chksum;
722 u8 enable;
723 u8 speed;
724 u8 topology;
725 u8 bootopt;
726 u32 nbluns;
727 u32 rsvd2;
728 struct bfa_boot_bootlun_s blun[BFA_BOOT_BOOTLUN_MAX];
729 struct bfa_boot_bootlun_s blun_disc[BFA_BOOT_BOOTLUN_MAX];
730};
731
732struct bfa_boot_pbc_s {
733 u8 enable;
734 u8 speed;
735 u8 topology;
736 u8 rsvd1;
737 u32 nbluns;
738 struct bfa_boot_bootlun_s pblun[BFA_PREBOOT_BOOTLUN_MAX];
739};
740
741struct bfa_ethboot_cfg_s {
742 u8 version;
743 u8 rsvd1;
744 u16 chksum;
745 u8 enable;
746 u8 rsvd2;
747 u16 vlan;
748};
749
750
751
752
753#define BFA_ABLK_MAX_PORTS 2
754#define BFA_ABLK_MAX_PFS 16
755#define BFA_ABLK_MAX 2
756
757#pragma pack(1)
758enum bfa_mode_s {
759 BFA_MODE_HBA = 1,
760 BFA_MODE_CNA = 2,
761 BFA_MODE_NIC = 3
762};
763
764struct bfa_adapter_cfg_mode_s {
765 u16 max_pf;
766 u16 max_vf;
767 enum bfa_mode_s mode;
768};
769
770struct bfa_ablk_cfg_pf_s {
771 u16 pers;
772 u8 port_id;
773 u8 optrom;
774 u8 valid;
775 u8 sriov;
776 u8 max_vfs;
777 u8 rsvd[1];
778 u16 num_qpairs;
779 u16 num_vectors;
780 u16 bw_min;
781 u16 bw_max;
782};
783
784struct bfa_ablk_cfg_port_s {
785 u8 mode;
786 u8 type;
787 u8 max_pfs;
788 u8 rsvd[5];
789};
790
791struct bfa_ablk_cfg_inst_s {
792 u8 nports;
793 u8 max_pfs;
794 u8 rsvd[6];
795 struct bfa_ablk_cfg_pf_s pf_cfg[BFA_ABLK_MAX_PFS];
796 struct bfa_ablk_cfg_port_s port_cfg[BFA_ABLK_MAX_PORTS];
797};
798
799struct bfa_ablk_cfg_s {
800 struct bfa_ablk_cfg_inst_s inst[BFA_ABLK_MAX];
801};
802
803
804
805
806
807#define SFP_DIAGMON_SIZE 10
808
809
810#define BFA_SFP_SCN_REMOVED 0
811#define BFA_SFP_SCN_INSERTED 1
812#define BFA_SFP_SCN_POM 2
813#define BFA_SFP_SCN_FAILED 3
814#define BFA_SFP_SCN_UNSUPPORT 4
815#define BFA_SFP_SCN_VALID 5
816
817enum bfa_defs_sfp_media_e {
818 BFA_SFP_MEDIA_UNKNOWN = 0x00,
819 BFA_SFP_MEDIA_CU = 0x01,
820 BFA_SFP_MEDIA_LW = 0x02,
821 BFA_SFP_MEDIA_SW = 0x03,
822 BFA_SFP_MEDIA_EL = 0x04,
823 BFA_SFP_MEDIA_UNSUPPORT = 0x05,
824};
825
826
827
828
829enum {
830 SFP_XMTR_TECH_CU = (1 << 0),
831 SFP_XMTR_TECH_CP = (1 << 1),
832 SFP_XMTR_TECH_CA = (1 << 2),
833 SFP_XMTR_TECH_LL = (1 << 3),
834 SFP_XMTR_TECH_SL = (1 << 4),
835 SFP_XMTR_TECH_SN = (1 << 5),
836 SFP_XMTR_TECH_EL_INTRA = (1 << 6),
837 SFP_XMTR_TECH_EL_INTER = (1 << 7),
838 SFP_XMTR_TECH_LC = (1 << 8),
839 SFP_XMTR_TECH_SA = (1 << 9)
840};
841
842
843
844
845
846struct sfp_srlid_base_s {
847 u8 id;
848 u8 extid;
849 u8 connector;
850 u8 xcvr[8];
851 u8 encoding;
852 u8 br_norm;
853 u8 rate_id;
854 u8 len_km;
855 u8 len_100m;
856 u8 len_om2;
857 u8 len_om1;
858 u8 len_cu;
859 u8 len_om3;
860 u8 vendor_name[16];
861 u8 unalloc1;
862 u8 vendor_oui[3];
863 u8 vendor_pn[16];
864 u8 vendor_rev[4];
865 u8 wavelen[2];
866 u8 unalloc2;
867 u8 cc_base;
868};
869
870
871
872
873
874struct sfp_srlid_ext_s {
875 u8 options[2];
876 u8 br_max;
877 u8 br_min;
878 u8 vendor_sn[16];
879 u8 date_code[8];
880 u8 diag_mon_type;
881 u8 en_options;
882 u8 sff_8472;
883 u8 cc_ext;
884};
885
886
887
888
889
890struct sfp_diag_base_s {
891
892
893
894 u8 temp_high_alarm[2];
895 u8 temp_low_alarm[2];
896 u8 temp_high_warning[2];
897 u8 temp_low_warning[2];
898
899 u8 volt_high_alarm[2];
900 u8 volt_low_alarm[2];
901 u8 volt_high_warning[2];
902 u8 volt_low_warning[2];
903
904 u8 bias_high_alarm[2];
905 u8 bias_low_alarm[2];
906 u8 bias_high_warning[2];
907 u8 bias_low_warning[2];
908
909 u8 tx_pwr_high_alarm[2];
910 u8 tx_pwr_low_alarm[2];
911 u8 tx_pwr_high_warning[2];
912 u8 tx_pwr_low_warning[2];
913
914 u8 rx_pwr_high_alarm[2];
915 u8 rx_pwr_low_alarm[2];
916 u8 rx_pwr_high_warning[2];
917 u8 rx_pwr_low_warning[2];
918
919 u8 unallocate_1[16];
920
921
922
923
924 u8 rx_pwr[20];
925 u8 tx_i[4];
926 u8 tx_pwr[4];
927 u8 temp[4];
928 u8 volt[4];
929 u8 unallocate_2[3];
930 u8 cc_dmi;
931};
932
933
934
935
936
937struct sfp_diag_ext_s {
938 u8 diag[SFP_DIAGMON_SIZE];
939 u8 unalloc1[4];
940 u8 status_ctl;
941 u8 rsvd;
942 u8 alarm_flags[2];
943 u8 unalloc2[2];
944 u8 warning_flags[2];
945 u8 ext_status_ctl[2];
946};
947
948
949
950
951
952
953struct sfp_usr_eeprom_s {
954 u8 rsvd1[2];
955 u8 ewrap;
956 u8 rsvd2[2];
957 u8 owrap;
958 u8 rsvd3[2];
959 u8 prbs;
960 u8 rsvd4[2];
961 u8 tx_eqz_16;
962 u8 tx_eqz_8;
963 u8 rsvd5[2];
964 u8 rx_emp_16;
965 u8 rx_emp_8;
966 u8 rsvd6[2];
967 u8 tx_eye_adj;
968 u8 rsvd7[3];
969 u8 tx_eye_qctl;
970 u8 tx_eye_qres;
971 u8 rsvd8[2];
972 u8 poh[3];
973 u8 rsvd9[2];
974};
975
976struct sfp_mem_s {
977 struct sfp_srlid_base_s srlid_base;
978 struct sfp_srlid_ext_s srlid_ext;
979 struct sfp_diag_base_s diag_base;
980 struct sfp_diag_ext_s diag_ext;
981 struct sfp_usr_eeprom_s usr_eeprom;
982};
983
984
985
986
987union sfp_xcvr_e10g_code_u {
988 u8 b;
989 struct {
990#ifdef __BIG_ENDIAN
991 u8 e10g_unall:1;
992 u8 e10g_lrm:1;
993 u8 e10g_lr:1;
994 u8 e10g_sr:1;
995 u8 ib_sx:1;
996 u8 ib_lx:1;
997 u8 ib_cu_a:1;
998 u8 ib_cu_p:1;
999#else
1000 u8 ib_cu_p:1;
1001 u8 ib_cu_a:1;
1002 u8 ib_lx:1;
1003 u8 ib_sx:1;
1004 u8 e10g_sr:1;
1005 u8 e10g_lr:1;
1006 u8 e10g_lrm:1;
1007 u8 e10g_unall:1;
1008#endif
1009 } r;
1010};
1011
1012union sfp_xcvr_so1_code_u {
1013 u8 b;
1014 struct {
1015 u8 escon:2;
1016 u8 oc192_reach:1;
1017 u8 so_reach:2;
1018 u8 oc48_reach:3;
1019 } r;
1020};
1021
1022union sfp_xcvr_so2_code_u {
1023 u8 b;
1024 struct {
1025 u8 reserved:1;
1026 u8 oc12_reach:3;
1027 u8 reserved1:1;
1028 u8 oc3_reach:3;
1029 } r;
1030};
1031
1032union sfp_xcvr_eth_code_u {
1033 u8 b;
1034 struct {
1035 u8 base_px:1;
1036 u8 base_bx10:1;
1037 u8 e100base_fx:1;
1038 u8 e100base_lx:1;
1039 u8 e1000base_t:1;
1040 u8 e1000base_cx:1;
1041 u8 e1000base_lx:1;
1042 u8 e1000base_sx:1;
1043 } r;
1044};
1045
1046struct sfp_xcvr_fc1_code_s {
1047 u8 link_len:5;
1048 u8 xmtr_tech2:3;
1049 u8 xmtr_tech1:7;
1050 u8 reserved1:1;
1051};
1052
1053union sfp_xcvr_fc2_code_u {
1054 u8 b;
1055 struct {
1056 u8 tw_media:1;
1057 u8 tp_media:1;
1058 u8 mi_media:1;
1059 u8 tv_media:1;
1060 u8 m6_media:1;
1061 u8 m5_media:1;
1062 u8 reserved:1;
1063 u8 sm_media:1;
1064 } r;
1065};
1066
1067union sfp_xcvr_fc3_code_u {
1068 u8 b;
1069 struct {
1070#ifdef __BIG_ENDIAN
1071 u8 rsv4:1;
1072 u8 mb800:1;
1073 u8 mb1600:1;
1074 u8 mb400:1;
1075 u8 rsv2:1;
1076 u8 mb200:1;
1077 u8 rsv1:1;
1078 u8 mb100:1;
1079#else
1080 u8 mb100:1;
1081 u8 rsv1:1;
1082 u8 mb200:1;
1083 u8 rsv2:1;
1084 u8 mb400:1;
1085 u8 mb1600:1;
1086 u8 mb800:1;
1087 u8 rsv4:1;
1088#endif
1089 } r;
1090};
1091
1092struct sfp_xcvr_s {
1093 union sfp_xcvr_e10g_code_u e10g;
1094 union sfp_xcvr_so1_code_u so1;
1095 union sfp_xcvr_so2_code_u so2;
1096 union sfp_xcvr_eth_code_u eth;
1097 struct sfp_xcvr_fc1_code_s fc1;
1098 union sfp_xcvr_fc2_code_u fc2;
1099 union sfp_xcvr_fc3_code_u fc3;
1100};
1101
1102
1103
1104
1105#define BFA_FLASH_PART_ENTRY_SIZE 32
1106#define BFA_FLASH_PART_MAX 32
1107
1108enum bfa_flash_part_type {
1109 BFA_FLASH_PART_OPTROM = 1,
1110 BFA_FLASH_PART_FWIMG = 2,
1111 BFA_FLASH_PART_FWCFG = 3,
1112 BFA_FLASH_PART_DRV = 4,
1113 BFA_FLASH_PART_BOOT = 5,
1114 BFA_FLASH_PART_ASIC = 6,
1115 BFA_FLASH_PART_MFG = 7,
1116 BFA_FLASH_PART_OPTROM2 = 8,
1117 BFA_FLASH_PART_VPD = 9,
1118 BFA_FLASH_PART_PBC = 10,
1119 BFA_FLASH_PART_BOOTOVL = 11,
1120 BFA_FLASH_PART_LOG = 12,
1121 BFA_FLASH_PART_PXECFG = 13,
1122 BFA_FLASH_PART_PXEOVL = 14,
1123 BFA_FLASH_PART_PORTCFG = 15,
1124 BFA_FLASH_PART_ASICBK = 16,
1125};
1126
1127
1128
1129
1130struct bfa_flash_part_attr_s {
1131 u32 part_type;
1132 u32 part_instance;
1133 u32 part_off;
1134 u32 part_size;
1135 u32 part_len;
1136 u32 part_status;
1137 char rsv[BFA_FLASH_PART_ENTRY_SIZE - 24];
1138};
1139
1140
1141
1142
1143struct bfa_flash_attr_s {
1144 u32 status;
1145 u32 npart;
1146 struct bfa_flash_part_attr_s part[BFA_FLASH_PART_MAX];
1147};
1148
1149
1150
1151
1152#define LB_PATTERN_DEFAULT 0xB5B5B5B5
1153#define QTEST_CNT_DEFAULT 10
1154#define QTEST_PAT_DEFAULT LB_PATTERN_DEFAULT
1155#define DPORT_ENABLE_LOOPCNT_DEFAULT (1024 * 1024)
1156
1157struct bfa_diag_memtest_s {
1158 u8 algo;
1159 u8 rsvd[7];
1160};
1161
1162struct bfa_diag_memtest_result {
1163 u32 status;
1164 u32 addr;
1165 u32 exp;
1166 u32 act;
1167 u32 err_status;
1168 u32 err_status1;
1169 u32 err_addr;
1170 u8 algo;
1171 u8 rsv[3];
1172};
1173
1174struct bfa_diag_loopback_result_s {
1175 u32 numtxmfrm;
1176 u32 numosffrm;
1177 u32 numrcvfrm;
1178 u32 badfrminf;
1179 u32 badfrmnum;
1180 u8 status;
1181 u8 rsvd[3];
1182};
1183
1184enum bfa_diag_dport_test_status {
1185 DPORT_TEST_ST_IDLE = 0,
1186 DPORT_TEST_ST_FINAL = 1,
1187 DPORT_TEST_ST_SKIP = 2,
1188 DPORT_TEST_ST_FAIL = 3,
1189 DPORT_TEST_ST_INPRG = 4,
1190 DPORT_TEST_ST_RESPONDER = 5,
1191 DPORT_TEST_ST_STOPPED = 6,
1192 DPORT_TEST_ST_MAX
1193};
1194
1195enum bfa_diag_dport_test_type {
1196 DPORT_TEST_ELOOP = 0,
1197 DPORT_TEST_OLOOP = 1,
1198 DPORT_TEST_ROLOOP = 2,
1199 DPORT_TEST_LINK = 3,
1200 DPORT_TEST_MAX
1201};
1202
1203enum bfa_diag_dport_test_opmode {
1204 BFA_DPORT_OPMODE_AUTO = 0,
1205 BFA_DPORT_OPMODE_MANU = 1,
1206};
1207
1208struct bfa_diag_dport_subtest_result_s {
1209 u8 status;
1210 u8 rsvd[7];
1211 u64 start_time;
1212};
1213
1214struct bfa_diag_dport_result_s {
1215 wwn_t rp_pwwn;
1216 wwn_t rp_nwwn;
1217 u64 start_time;
1218 u64 end_time;
1219 u8 status;
1220 u8 mode;
1221 u8 rsvd;
1222 u8 speed;
1223 u16 buffer_required;
1224 u16 frmsz;
1225 u32 lpcnt;
1226 u32 pat;
1227 u32 roundtrip_latency;
1228 u32 est_cable_distance;
1229 struct bfa_diag_dport_subtest_result_s subtest[DPORT_TEST_MAX];
1230};
1231
1232struct bfa_diag_ledtest_s {
1233 u32 cmd;
1234 u32 color;
1235 u16 freq;
1236 u8 led;
1237 u8 rsvd[5];
1238};
1239
1240struct bfa_diag_loopback_s {
1241 u32 loopcnt;
1242 u32 pattern;
1243 u8 lb_mode;
1244 u8 speed;
1245 u8 rsvd[2];
1246};
1247
1248
1249
1250
1251enum bfa_phy_status_e {
1252 BFA_PHY_STATUS_GOOD = 0,
1253 BFA_PHY_STATUS_NOT_PRESENT = 1,
1254 BFA_PHY_STATUS_BAD = 2,
1255};
1256
1257
1258
1259
1260struct bfa_phy_attr_s {
1261 u32 status;
1262 u32 length;
1263 u32 fw_ver;
1264 u32 an_status;
1265 u32 pma_pmd_status;
1266 u32 pma_pmd_signal;
1267 u32 pcs_status;
1268};
1269
1270
1271
1272
1273struct bfa_phy_stats_s {
1274 u32 status;
1275 u32 link_breaks;
1276 u32 pma_pmd_fault;
1277 u32 pcs_fault;
1278 u32 speed_neg;
1279 u32 tx_eq_training;
1280 u32 tx_eq_timeout;
1281 u32 crc_error;
1282};
1283
1284#pragma pack()
1285
1286#endif
1287