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57#include <linux/fs.h>
58#include <linux/init.h>
59#include <linux/types.h>
60#include <linux/errno.h>
61#include <linux/kernel.h>
62#include <linux/slab.h>
63#include <linux/vmalloc.h>
64#include <linux/ioport.h>
65#include <linux/delay.h>
66#include <linux/pci.h>
67#include <linux/wait.h>
68#include <linux/spinlock.h>
69#include <linux/sched.h>
70#include <linux/interrupt.h>
71#include <linux/blkdev.h>
72#include <linux/firmware.h>
73#include <linux/module.h>
74#include <linux/moduleparam.h>
75#include <linux/libata.h>
76#include <linux/hdreg.h>
77#include <linux/reboot.h>
78#include <linux/stringify.h>
79#include <asm/io.h>
80#include <asm/irq.h>
81#include <asm/processor.h>
82#include <scsi/scsi.h>
83#include <scsi/scsi_host.h>
84#include <scsi/scsi_tcq.h>
85#include <scsi/scsi_eh.h>
86#include <scsi/scsi_cmnd.h>
87#include "ipr.h"
88
89
90
91
92static LIST_HEAD(ipr_ioa_head);
93static unsigned int ipr_log_level = IPR_DEFAULT_LOG_LEVEL;
94static unsigned int ipr_max_speed = 1;
95static int ipr_testmode = 0;
96static unsigned int ipr_fastfail = 0;
97static unsigned int ipr_transop_timeout = 0;
98static unsigned int ipr_debug = 0;
99static unsigned int ipr_max_devs = IPR_DEFAULT_SIS64_DEVS;
100static unsigned int ipr_dual_ioa_raid = 1;
101static unsigned int ipr_number_of_msix = 2;
102static DEFINE_SPINLOCK(ipr_driver_lock);
103
104
105static const struct ipr_chip_cfg_t ipr_chip_cfg[] = {
106 {
107 .mailbox = 0x0042C,
108 .max_cmds = 100,
109 .cache_line_size = 0x20,
110 .clear_isr = 1,
111 .iopoll_weight = 0,
112 {
113 .set_interrupt_mask_reg = 0x0022C,
114 .clr_interrupt_mask_reg = 0x00230,
115 .clr_interrupt_mask_reg32 = 0x00230,
116 .sense_interrupt_mask_reg = 0x0022C,
117 .sense_interrupt_mask_reg32 = 0x0022C,
118 .clr_interrupt_reg = 0x00228,
119 .clr_interrupt_reg32 = 0x00228,
120 .sense_interrupt_reg = 0x00224,
121 .sense_interrupt_reg32 = 0x00224,
122 .ioarrin_reg = 0x00404,
123 .sense_uproc_interrupt_reg = 0x00214,
124 .sense_uproc_interrupt_reg32 = 0x00214,
125 .set_uproc_interrupt_reg = 0x00214,
126 .set_uproc_interrupt_reg32 = 0x00214,
127 .clr_uproc_interrupt_reg = 0x00218,
128 .clr_uproc_interrupt_reg32 = 0x00218
129 }
130 },
131 {
132 .mailbox = 0x0052C,
133 .max_cmds = 100,
134 .cache_line_size = 0x20,
135 .clear_isr = 1,
136 .iopoll_weight = 0,
137 {
138 .set_interrupt_mask_reg = 0x00288,
139 .clr_interrupt_mask_reg = 0x0028C,
140 .clr_interrupt_mask_reg32 = 0x0028C,
141 .sense_interrupt_mask_reg = 0x00288,
142 .sense_interrupt_mask_reg32 = 0x00288,
143 .clr_interrupt_reg = 0x00284,
144 .clr_interrupt_reg32 = 0x00284,
145 .sense_interrupt_reg = 0x00280,
146 .sense_interrupt_reg32 = 0x00280,
147 .ioarrin_reg = 0x00504,
148 .sense_uproc_interrupt_reg = 0x00290,
149 .sense_uproc_interrupt_reg32 = 0x00290,
150 .set_uproc_interrupt_reg = 0x00290,
151 .set_uproc_interrupt_reg32 = 0x00290,
152 .clr_uproc_interrupt_reg = 0x00294,
153 .clr_uproc_interrupt_reg32 = 0x00294
154 }
155 },
156 {
157 .mailbox = 0x00044,
158 .max_cmds = 1000,
159 .cache_line_size = 0x20,
160 .clear_isr = 0,
161 .iopoll_weight = 64,
162 {
163 .set_interrupt_mask_reg = 0x00010,
164 .clr_interrupt_mask_reg = 0x00018,
165 .clr_interrupt_mask_reg32 = 0x0001C,
166 .sense_interrupt_mask_reg = 0x00010,
167 .sense_interrupt_mask_reg32 = 0x00014,
168 .clr_interrupt_reg = 0x00008,
169 .clr_interrupt_reg32 = 0x0000C,
170 .sense_interrupt_reg = 0x00000,
171 .sense_interrupt_reg32 = 0x00004,
172 .ioarrin_reg = 0x00070,
173 .sense_uproc_interrupt_reg = 0x00020,
174 .sense_uproc_interrupt_reg32 = 0x00024,
175 .set_uproc_interrupt_reg = 0x00020,
176 .set_uproc_interrupt_reg32 = 0x00024,
177 .clr_uproc_interrupt_reg = 0x00028,
178 .clr_uproc_interrupt_reg32 = 0x0002C,
179 .init_feedback_reg = 0x0005C,
180 .dump_addr_reg = 0x00064,
181 .dump_data_reg = 0x00068,
182 .endian_swap_reg = 0x00084
183 }
184 },
185};
186
187static const struct ipr_chip_t ipr_chip[] = {
188 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
189 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
190 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
191 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
192 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E, IPR_USE_MSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[0] },
193 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
194 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP, IPR_USE_LSI, IPR_SIS32, IPR_PCI_CFG, &ipr_chip_cfg[1] },
195 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] },
196 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE, IPR_USE_MSI, IPR_SIS64, IPR_MMIO, &ipr_chip_cfg[2] }
197};
198
199static int ipr_max_bus_speeds[] = {
200 IPR_80MBs_SCSI_RATE, IPR_U160_SCSI_RATE, IPR_U320_SCSI_RATE
201};
202
203MODULE_AUTHOR("Brian King <brking@us.ibm.com>");
204MODULE_DESCRIPTION("IBM Power RAID SCSI Adapter Driver");
205module_param_named(max_speed, ipr_max_speed, uint, 0);
206MODULE_PARM_DESC(max_speed, "Maximum bus speed (0-2). Default: 1=U160. Speeds: 0=80 MB/s, 1=U160, 2=U320");
207module_param_named(log_level, ipr_log_level, uint, 0);
208MODULE_PARM_DESC(log_level, "Set to 0 - 4 for increasing verbosity of device driver");
209module_param_named(testmode, ipr_testmode, int, 0);
210MODULE_PARM_DESC(testmode, "DANGEROUS!!! Allows unsupported configurations");
211module_param_named(fastfail, ipr_fastfail, int, S_IRUGO | S_IWUSR);
212MODULE_PARM_DESC(fastfail, "Reduce timeouts and retries");
213module_param_named(transop_timeout, ipr_transop_timeout, int, 0);
214MODULE_PARM_DESC(transop_timeout, "Time in seconds to wait for adapter to come operational (default: 300)");
215module_param_named(debug, ipr_debug, int, S_IRUGO | S_IWUSR);
216MODULE_PARM_DESC(debug, "Enable device driver debugging logging. Set to 1 to enable. (default: 0)");
217module_param_named(dual_ioa_raid, ipr_dual_ioa_raid, int, 0);
218MODULE_PARM_DESC(dual_ioa_raid, "Enable dual adapter RAID support. Set to 1 to enable. (default: 1)");
219module_param_named(max_devs, ipr_max_devs, int, 0);
220MODULE_PARM_DESC(max_devs, "Specify the maximum number of physical devices. "
221 "[Default=" __stringify(IPR_DEFAULT_SIS64_DEVS) "]");
222module_param_named(number_of_msix, ipr_number_of_msix, int, 0);
223MODULE_PARM_DESC(number_of_msix, "Specify the number of MSIX interrupts to use on capable adapters (1 - 5). (default:2)");
224MODULE_LICENSE("GPL");
225MODULE_VERSION(IPR_DRIVER_VERSION);
226
227
228static const
229struct ipr_error_table_t ipr_error_table[] = {
230 {0x00000000, 1, IPR_DEFAULT_LOG_LEVEL,
231 "8155: An unknown error was received"},
232 {0x00330000, 0, 0,
233 "Soft underlength error"},
234 {0x005A0000, 0, 0,
235 "Command to be cancelled not found"},
236 {0x00808000, 0, 0,
237 "Qualified success"},
238 {0x01080000, 1, IPR_DEFAULT_LOG_LEVEL,
239 "FFFE: Soft device bus error recovered by the IOA"},
240 {0x01088100, 0, IPR_DEFAULT_LOG_LEVEL,
241 "4101: Soft device bus fabric error"},
242 {0x01100100, 0, IPR_DEFAULT_LOG_LEVEL,
243 "FFFC: Logical block guard error recovered by the device"},
244 {0x01100300, 0, IPR_DEFAULT_LOG_LEVEL,
245 "FFFC: Logical block reference tag error recovered by the device"},
246 {0x01108300, 0, IPR_DEFAULT_LOG_LEVEL,
247 "4171: Recovered scatter list tag / sequence number error"},
248 {0x01109000, 0, IPR_DEFAULT_LOG_LEVEL,
249 "FF3D: Recovered logical block CRC error on IOA to Host transfer"},
250 {0x01109200, 0, IPR_DEFAULT_LOG_LEVEL,
251 "4171: Recovered logical block sequence number error on IOA to Host transfer"},
252 {0x0110A000, 0, IPR_DEFAULT_LOG_LEVEL,
253 "FFFD: Recovered logical block reference tag error detected by the IOA"},
254 {0x0110A100, 0, IPR_DEFAULT_LOG_LEVEL,
255 "FFFD: Logical block guard error recovered by the IOA"},
256 {0x01170600, 0, IPR_DEFAULT_LOG_LEVEL,
257 "FFF9: Device sector reassign successful"},
258 {0x01170900, 0, IPR_DEFAULT_LOG_LEVEL,
259 "FFF7: Media error recovered by device rewrite procedures"},
260 {0x01180200, 0, IPR_DEFAULT_LOG_LEVEL,
261 "7001: IOA sector reassignment successful"},
262 {0x01180500, 0, IPR_DEFAULT_LOG_LEVEL,
263 "FFF9: Soft media error. Sector reassignment recommended"},
264 {0x01180600, 0, IPR_DEFAULT_LOG_LEVEL,
265 "FFF7: Media error recovered by IOA rewrite procedures"},
266 {0x01418000, 0, IPR_DEFAULT_LOG_LEVEL,
267 "FF3D: Soft PCI bus error recovered by the IOA"},
268 {0x01440000, 1, IPR_DEFAULT_LOG_LEVEL,
269 "FFF6: Device hardware error recovered by the IOA"},
270 {0x01448100, 0, IPR_DEFAULT_LOG_LEVEL,
271 "FFF6: Device hardware error recovered by the device"},
272 {0x01448200, 1, IPR_DEFAULT_LOG_LEVEL,
273 "FF3D: Soft IOA error recovered by the IOA"},
274 {0x01448300, 0, IPR_DEFAULT_LOG_LEVEL,
275 "FFFA: Undefined device response recovered by the IOA"},
276 {0x014A0000, 1, IPR_DEFAULT_LOG_LEVEL,
277 "FFF6: Device bus error, message or command phase"},
278 {0x014A8000, 0, IPR_DEFAULT_LOG_LEVEL,
279 "FFFE: Task Management Function failed"},
280 {0x015D0000, 0, IPR_DEFAULT_LOG_LEVEL,
281 "FFF6: Failure prediction threshold exceeded"},
282 {0x015D9200, 0, IPR_DEFAULT_LOG_LEVEL,
283 "8009: Impending cache battery pack failure"},
284 {0x02040100, 0, 0,
285 "Logical Unit in process of becoming ready"},
286 {0x02040200, 0, 0,
287 "Initializing command required"},
288 {0x02040400, 0, 0,
289 "34FF: Disk device format in progress"},
290 {0x02040C00, 0, 0,
291 "Logical unit not accessible, target port in unavailable state"},
292 {0x02048000, 0, IPR_DEFAULT_LOG_LEVEL,
293 "9070: IOA requested reset"},
294 {0x023F0000, 0, 0,
295 "Synchronization required"},
296 {0x02408500, 0, 0,
297 "IOA microcode download required"},
298 {0x02408600, 0, 0,
299 "Device bus connection is prohibited by host"},
300 {0x024E0000, 0, 0,
301 "No ready, IOA shutdown"},
302 {0x025A0000, 0, 0,
303 "Not ready, IOA has been shutdown"},
304 {0x02670100, 0, IPR_DEFAULT_LOG_LEVEL,
305 "3020: Storage subsystem configuration error"},
306 {0x03110B00, 0, 0,
307 "FFF5: Medium error, data unreadable, recommend reassign"},
308 {0x03110C00, 0, 0,
309 "7000: Medium error, data unreadable, do not reassign"},
310 {0x03310000, 0, IPR_DEFAULT_LOG_LEVEL,
311 "FFF3: Disk media format bad"},
312 {0x04050000, 0, IPR_DEFAULT_LOG_LEVEL,
313 "3002: Addressed device failed to respond to selection"},
314 {0x04080000, 1, IPR_DEFAULT_LOG_LEVEL,
315 "3100: Device bus error"},
316 {0x04080100, 0, IPR_DEFAULT_LOG_LEVEL,
317 "3109: IOA timed out a device command"},
318 {0x04088000, 0, 0,
319 "3120: SCSI bus is not operational"},
320 {0x04088100, 0, IPR_DEFAULT_LOG_LEVEL,
321 "4100: Hard device bus fabric error"},
322 {0x04100100, 0, IPR_DEFAULT_LOG_LEVEL,
323 "310C: Logical block guard error detected by the device"},
324 {0x04100300, 0, IPR_DEFAULT_LOG_LEVEL,
325 "310C: Logical block reference tag error detected by the device"},
326 {0x04108300, 1, IPR_DEFAULT_LOG_LEVEL,
327 "4170: Scatter list tag / sequence number error"},
328 {0x04109000, 1, IPR_DEFAULT_LOG_LEVEL,
329 "8150: Logical block CRC error on IOA to Host transfer"},
330 {0x04109200, 1, IPR_DEFAULT_LOG_LEVEL,
331 "4170: Logical block sequence number error on IOA to Host transfer"},
332 {0x0410A000, 0, IPR_DEFAULT_LOG_LEVEL,
333 "310D: Logical block reference tag error detected by the IOA"},
334 {0x0410A100, 0, IPR_DEFAULT_LOG_LEVEL,
335 "310D: Logical block guard error detected by the IOA"},
336 {0x04118000, 0, IPR_DEFAULT_LOG_LEVEL,
337 "9000: IOA reserved area data check"},
338 {0x04118100, 0, IPR_DEFAULT_LOG_LEVEL,
339 "9001: IOA reserved area invalid data pattern"},
340 {0x04118200, 0, IPR_DEFAULT_LOG_LEVEL,
341 "9002: IOA reserved area LRC error"},
342 {0x04118300, 1, IPR_DEFAULT_LOG_LEVEL,
343 "Hardware Error, IOA metadata access error"},
344 {0x04320000, 0, IPR_DEFAULT_LOG_LEVEL,
345 "102E: Out of alternate sectors for disk storage"},
346 {0x04330000, 1, IPR_DEFAULT_LOG_LEVEL,
347 "FFF4: Data transfer underlength error"},
348 {0x04338000, 1, IPR_DEFAULT_LOG_LEVEL,
349 "FFF4: Data transfer overlength error"},
350 {0x043E0100, 0, IPR_DEFAULT_LOG_LEVEL,
351 "3400: Logical unit failure"},
352 {0x04408500, 0, IPR_DEFAULT_LOG_LEVEL,
353 "FFF4: Device microcode is corrupt"},
354 {0x04418000, 1, IPR_DEFAULT_LOG_LEVEL,
355 "8150: PCI bus error"},
356 {0x04430000, 1, 0,
357 "Unsupported device bus message received"},
358 {0x04440000, 1, IPR_DEFAULT_LOG_LEVEL,
359 "FFF4: Disk device problem"},
360 {0x04448200, 1, IPR_DEFAULT_LOG_LEVEL,
361 "8150: Permanent IOA failure"},
362 {0x04448300, 0, IPR_DEFAULT_LOG_LEVEL,
363 "3010: Disk device returned wrong response to IOA"},
364 {0x04448400, 0, IPR_DEFAULT_LOG_LEVEL,
365 "8151: IOA microcode error"},
366 {0x04448500, 0, 0,
367 "Device bus status error"},
368 {0x04448600, 0, IPR_DEFAULT_LOG_LEVEL,
369 "8157: IOA error requiring IOA reset to recover"},
370 {0x04448700, 0, 0,
371 "ATA device status error"},
372 {0x04490000, 0, 0,
373 "Message reject received from the device"},
374 {0x04449200, 0, IPR_DEFAULT_LOG_LEVEL,
375 "8008: A permanent cache battery pack failure occurred"},
376 {0x0444A000, 0, IPR_DEFAULT_LOG_LEVEL,
377 "9090: Disk unit has been modified after the last known status"},
378 {0x0444A200, 0, IPR_DEFAULT_LOG_LEVEL,
379 "9081: IOA detected device error"},
380 {0x0444A300, 0, IPR_DEFAULT_LOG_LEVEL,
381 "9082: IOA detected device error"},
382 {0x044A0000, 1, IPR_DEFAULT_LOG_LEVEL,
383 "3110: Device bus error, message or command phase"},
384 {0x044A8000, 1, IPR_DEFAULT_LOG_LEVEL,
385 "3110: SAS Command / Task Management Function failed"},
386 {0x04670400, 0, IPR_DEFAULT_LOG_LEVEL,
387 "9091: Incorrect hardware configuration change has been detected"},
388 {0x04678000, 0, IPR_DEFAULT_LOG_LEVEL,
389 "9073: Invalid multi-adapter configuration"},
390 {0x04678100, 0, IPR_DEFAULT_LOG_LEVEL,
391 "4010: Incorrect connection between cascaded expanders"},
392 {0x04678200, 0, IPR_DEFAULT_LOG_LEVEL,
393 "4020: Connections exceed IOA design limits"},
394 {0x04678300, 0, IPR_DEFAULT_LOG_LEVEL,
395 "4030: Incorrect multipath connection"},
396 {0x04679000, 0, IPR_DEFAULT_LOG_LEVEL,
397 "4110: Unsupported enclosure function"},
398 {0x04679800, 0, IPR_DEFAULT_LOG_LEVEL,
399 "4120: SAS cable VPD cannot be read"},
400 {0x046E0000, 0, IPR_DEFAULT_LOG_LEVEL,
401 "FFF4: Command to logical unit failed"},
402 {0x05240000, 1, 0,
403 "Illegal request, invalid request type or request packet"},
404 {0x05250000, 0, 0,
405 "Illegal request, invalid resource handle"},
406 {0x05258000, 0, 0,
407 "Illegal request, commands not allowed to this device"},
408 {0x05258100, 0, 0,
409 "Illegal request, command not allowed to a secondary adapter"},
410 {0x05258200, 0, 0,
411 "Illegal request, command not allowed to a non-optimized resource"},
412 {0x05260000, 0, 0,
413 "Illegal request, invalid field in parameter list"},
414 {0x05260100, 0, 0,
415 "Illegal request, parameter not supported"},
416 {0x05260200, 0, 0,
417 "Illegal request, parameter value invalid"},
418 {0x052C0000, 0, 0,
419 "Illegal request, command sequence error"},
420 {0x052C8000, 1, 0,
421 "Illegal request, dual adapter support not enabled"},
422 {0x052C8100, 1, 0,
423 "Illegal request, another cable connector was physically disabled"},
424 {0x054E8000, 1, 0,
425 "Illegal request, inconsistent group id/group count"},
426 {0x06040500, 0, IPR_DEFAULT_LOG_LEVEL,
427 "9031: Array protection temporarily suspended, protection resuming"},
428 {0x06040600, 0, IPR_DEFAULT_LOG_LEVEL,
429 "9040: Array protection temporarily suspended, protection resuming"},
430 {0x060B0100, 0, IPR_DEFAULT_LOG_LEVEL,
431 "4080: IOA exceeded maximum operating temperature"},
432 {0x060B8000, 0, IPR_DEFAULT_LOG_LEVEL,
433 "4085: Service required"},
434 {0x06288000, 0, IPR_DEFAULT_LOG_LEVEL,
435 "3140: Device bus not ready to ready transition"},
436 {0x06290000, 0, IPR_DEFAULT_LOG_LEVEL,
437 "FFFB: SCSI bus was reset"},
438 {0x06290500, 0, 0,
439 "FFFE: SCSI bus transition to single ended"},
440 {0x06290600, 0, 0,
441 "FFFE: SCSI bus transition to LVD"},
442 {0x06298000, 0, IPR_DEFAULT_LOG_LEVEL,
443 "FFFB: SCSI bus was reset by another initiator"},
444 {0x063F0300, 0, IPR_DEFAULT_LOG_LEVEL,
445 "3029: A device replacement has occurred"},
446 {0x063F8300, 0, IPR_DEFAULT_LOG_LEVEL,
447 "4102: Device bus fabric performance degradation"},
448 {0x064C8000, 0, IPR_DEFAULT_LOG_LEVEL,
449 "9051: IOA cache data exists for a missing or failed device"},
450 {0x064C8100, 0, IPR_DEFAULT_LOG_LEVEL,
451 "9055: Auxiliary cache IOA contains cache data needed by the primary IOA"},
452 {0x06670100, 0, IPR_DEFAULT_LOG_LEVEL,
453 "9025: Disk unit is not supported at its physical location"},
454 {0x06670600, 0, IPR_DEFAULT_LOG_LEVEL,
455 "3020: IOA detected a SCSI bus configuration error"},
456 {0x06678000, 0, IPR_DEFAULT_LOG_LEVEL,
457 "3150: SCSI bus configuration error"},
458 {0x06678100, 0, IPR_DEFAULT_LOG_LEVEL,
459 "9074: Asymmetric advanced function disk configuration"},
460 {0x06678300, 0, IPR_DEFAULT_LOG_LEVEL,
461 "4040: Incomplete multipath connection between IOA and enclosure"},
462 {0x06678400, 0, IPR_DEFAULT_LOG_LEVEL,
463 "4041: Incomplete multipath connection between enclosure and device"},
464 {0x06678500, 0, IPR_DEFAULT_LOG_LEVEL,
465 "9075: Incomplete multipath connection between IOA and remote IOA"},
466 {0x06678600, 0, IPR_DEFAULT_LOG_LEVEL,
467 "9076: Configuration error, missing remote IOA"},
468 {0x06679100, 0, IPR_DEFAULT_LOG_LEVEL,
469 "4050: Enclosure does not support a required multipath function"},
470 {0x06679800, 0, IPR_DEFAULT_LOG_LEVEL,
471 "4121: Configuration error, required cable is missing"},
472 {0x06679900, 0, IPR_DEFAULT_LOG_LEVEL,
473 "4122: Cable is not plugged into the correct location on remote IOA"},
474 {0x06679A00, 0, IPR_DEFAULT_LOG_LEVEL,
475 "4123: Configuration error, invalid cable vital product data"},
476 {0x06679B00, 0, IPR_DEFAULT_LOG_LEVEL,
477 "4124: Configuration error, both cable ends are plugged into the same IOA"},
478 {0x06690000, 0, IPR_DEFAULT_LOG_LEVEL,
479 "4070: Logically bad block written on device"},
480 {0x06690200, 0, IPR_DEFAULT_LOG_LEVEL,
481 "9041: Array protection temporarily suspended"},
482 {0x06698200, 0, IPR_DEFAULT_LOG_LEVEL,
483 "9042: Corrupt array parity detected on specified device"},
484 {0x066B0200, 0, IPR_DEFAULT_LOG_LEVEL,
485 "9030: Array no longer protected due to missing or failed disk unit"},
486 {0x066B8000, 0, IPR_DEFAULT_LOG_LEVEL,
487 "9071: Link operational transition"},
488 {0x066B8100, 0, IPR_DEFAULT_LOG_LEVEL,
489 "9072: Link not operational transition"},
490 {0x066B8200, 0, IPR_DEFAULT_LOG_LEVEL,
491 "9032: Array exposed but still protected"},
492 {0x066B8300, 0, IPR_DEFAULT_LOG_LEVEL + 1,
493 "70DD: Device forced failed by disrupt device command"},
494 {0x066B9100, 0, IPR_DEFAULT_LOG_LEVEL,
495 "4061: Multipath redundancy level got better"},
496 {0x066B9200, 0, IPR_DEFAULT_LOG_LEVEL,
497 "4060: Multipath redundancy level got worse"},
498 {0x07270000, 0, 0,
499 "Failure due to other device"},
500 {0x07278000, 0, IPR_DEFAULT_LOG_LEVEL,
501 "9008: IOA does not support functions expected by devices"},
502 {0x07278100, 0, IPR_DEFAULT_LOG_LEVEL,
503 "9010: Cache data associated with attached devices cannot be found"},
504 {0x07278200, 0, IPR_DEFAULT_LOG_LEVEL,
505 "9011: Cache data belongs to devices other than those attached"},
506 {0x07278400, 0, IPR_DEFAULT_LOG_LEVEL,
507 "9020: Array missing 2 or more devices with only 1 device present"},
508 {0x07278500, 0, IPR_DEFAULT_LOG_LEVEL,
509 "9021: Array missing 2 or more devices with 2 or more devices present"},
510 {0x07278600, 0, IPR_DEFAULT_LOG_LEVEL,
511 "9022: Exposed array is missing a required device"},
512 {0x07278700, 0, IPR_DEFAULT_LOG_LEVEL,
513 "9023: Array member(s) not at required physical locations"},
514 {0x07278800, 0, IPR_DEFAULT_LOG_LEVEL,
515 "9024: Array not functional due to present hardware configuration"},
516 {0x07278900, 0, IPR_DEFAULT_LOG_LEVEL,
517 "9026: Array not functional due to present hardware configuration"},
518 {0x07278A00, 0, IPR_DEFAULT_LOG_LEVEL,
519 "9027: Array is missing a device and parity is out of sync"},
520 {0x07278B00, 0, IPR_DEFAULT_LOG_LEVEL,
521 "9028: Maximum number of arrays already exist"},
522 {0x07278C00, 0, IPR_DEFAULT_LOG_LEVEL,
523 "9050: Required cache data cannot be located for a disk unit"},
524 {0x07278D00, 0, IPR_DEFAULT_LOG_LEVEL,
525 "9052: Cache data exists for a device that has been modified"},
526 {0x07278F00, 0, IPR_DEFAULT_LOG_LEVEL,
527 "9054: IOA resources not available due to previous problems"},
528 {0x07279100, 0, IPR_DEFAULT_LOG_LEVEL,
529 "9092: Disk unit requires initialization before use"},
530 {0x07279200, 0, IPR_DEFAULT_LOG_LEVEL,
531 "9029: Incorrect hardware configuration change has been detected"},
532 {0x07279600, 0, IPR_DEFAULT_LOG_LEVEL,
533 "9060: One or more disk pairs are missing from an array"},
534 {0x07279700, 0, IPR_DEFAULT_LOG_LEVEL,
535 "9061: One or more disks are missing from an array"},
536 {0x07279800, 0, IPR_DEFAULT_LOG_LEVEL,
537 "9062: One or more disks are missing from an array"},
538 {0x07279900, 0, IPR_DEFAULT_LOG_LEVEL,
539 "9063: Maximum number of functional arrays has been exceeded"},
540 {0x07279A00, 0, 0,
541 "Data protect, other volume set problem"},
542 {0x0B260000, 0, 0,
543 "Aborted command, invalid descriptor"},
544 {0x0B3F9000, 0, 0,
545 "Target operating conditions have changed, dual adapter takeover"},
546 {0x0B530200, 0, 0,
547 "Aborted command, medium removal prevented"},
548 {0x0B5A0000, 0, 0,
549 "Command terminated by host"},
550 {0x0B5B8000, 0, 0,
551 "Aborted command, command terminated by host"}
552};
553
554static const struct ipr_ses_table_entry ipr_ses_table[] = {
555 { "2104-DL1 ", "XXXXXXXXXXXXXXXX", 80 },
556 { "2104-TL1 ", "XXXXXXXXXXXXXXXX", 80 },
557 { "HSBP07M P U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
558 { "HSBP05M P U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
559 { "HSBP05M S U2SCSI", "XXXXXXXXXXXXXXXX", 80 },
560 { "HSBP06E ASU2SCSI", "XXXXXXXXXXXXXXXX", 80 },
561 { "2104-DU3 ", "XXXXXXXXXXXXXXXX", 160 },
562 { "2104-TU3 ", "XXXXXXXXXXXXXXXX", 160 },
563 { "HSBP04C RSU2SCSI", "XXXXXXX*XXXXXXXX", 160 },
564 { "HSBP06E RSU2SCSI", "XXXXXXX*XXXXXXXX", 160 },
565 { "St V1S2 ", "XXXXXXXXXXXXXXXX", 160 },
566 { "HSBPD4M PU3SCSI", "XXXXXXX*XXXXXXXX", 160 },
567 { "VSBPD1H U3SCSI", "XXXXXXX*XXXXXXXX", 160 }
568};
569
570
571
572
573static int ipr_reset_alert(struct ipr_cmnd *);
574static void ipr_process_ccn(struct ipr_cmnd *);
575static void ipr_process_error(struct ipr_cmnd *);
576static void ipr_reset_ioa_job(struct ipr_cmnd *);
577static void ipr_initiate_ioa_reset(struct ipr_ioa_cfg *,
578 enum ipr_shutdown_type);
579
580#ifdef CONFIG_SCSI_IPR_TRACE
581
582
583
584
585
586
587
588
589
590static void ipr_trc_hook(struct ipr_cmnd *ipr_cmd,
591 u8 type, u32 add_data)
592{
593 struct ipr_trace_entry *trace_entry;
594 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
595
596 trace_entry = &ioa_cfg->trace[atomic_add_return
597 (1, &ioa_cfg->trace_index)%IPR_NUM_TRACE_ENTRIES];
598 trace_entry->time = jiffies;
599 trace_entry->op_code = ipr_cmd->ioarcb.cmd_pkt.cdb[0];
600 trace_entry->type = type;
601 if (ipr_cmd->ioa_cfg->sis64)
602 trace_entry->ata_op_code = ipr_cmd->i.ata_ioadl.regs.command;
603 else
604 trace_entry->ata_op_code = ipr_cmd->ioarcb.u.add_data.u.regs.command;
605 trace_entry->cmd_index = ipr_cmd->cmd_index & 0xff;
606 trace_entry->res_handle = ipr_cmd->ioarcb.res_handle;
607 trace_entry->u.add_data = add_data;
608 wmb();
609}
610#else
611#define ipr_trc_hook(ipr_cmd, type, add_data) do { } while (0)
612#endif
613
614
615
616
617
618
619
620
621static void ipr_lock_and_done(struct ipr_cmnd *ipr_cmd)
622{
623 unsigned long lock_flags;
624 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
625
626 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
627 ipr_cmd->done(ipr_cmd);
628 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
629}
630
631
632
633
634
635
636
637
638static void ipr_reinit_ipr_cmnd(struct ipr_cmnd *ipr_cmd)
639{
640 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
641 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
642 struct ipr_ioasa64 *ioasa64 = &ipr_cmd->s.ioasa64;
643 dma_addr_t dma_addr = ipr_cmd->dma_addr;
644 int hrrq_id;
645
646 hrrq_id = ioarcb->cmd_pkt.hrrq_id;
647 memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt));
648 ioarcb->cmd_pkt.hrrq_id = hrrq_id;
649 ioarcb->data_transfer_length = 0;
650 ioarcb->read_data_transfer_length = 0;
651 ioarcb->ioadl_len = 0;
652 ioarcb->read_ioadl_len = 0;
653
654 if (ipr_cmd->ioa_cfg->sis64) {
655 ioarcb->u.sis64_addr_data.data_ioadl_addr =
656 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
657 ioasa64->u.gata.status = 0;
658 } else {
659 ioarcb->write_ioadl_addr =
660 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
661 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
662 ioasa->u.gata.status = 0;
663 }
664
665 ioasa->hdr.ioasc = 0;
666 ioasa->hdr.residual_data_len = 0;
667 ipr_cmd->scsi_cmd = NULL;
668 ipr_cmd->qc = NULL;
669 ipr_cmd->sense_buffer[0] = 0;
670 ipr_cmd->dma_use_sg = 0;
671}
672
673
674
675
676
677
678
679
680static void ipr_init_ipr_cmnd(struct ipr_cmnd *ipr_cmd,
681 void (*fast_done) (struct ipr_cmnd *))
682{
683 ipr_reinit_ipr_cmnd(ipr_cmd);
684 ipr_cmd->u.scratch = 0;
685 ipr_cmd->sibling = NULL;
686 ipr_cmd->fast_done = fast_done;
687 init_timer(&ipr_cmd->timer);
688}
689
690
691
692
693
694
695
696
697static
698struct ipr_cmnd *__ipr_get_free_ipr_cmnd(struct ipr_hrr_queue *hrrq)
699{
700 struct ipr_cmnd *ipr_cmd = NULL;
701
702 if (likely(!list_empty(&hrrq->hrrq_free_q))) {
703 ipr_cmd = list_entry(hrrq->hrrq_free_q.next,
704 struct ipr_cmnd, queue);
705 list_del(&ipr_cmd->queue);
706 }
707
708
709 return ipr_cmd;
710}
711
712
713
714
715
716
717
718
719static
720struct ipr_cmnd *ipr_get_free_ipr_cmnd(struct ipr_ioa_cfg *ioa_cfg)
721{
722 struct ipr_cmnd *ipr_cmd =
723 __ipr_get_free_ipr_cmnd(&ioa_cfg->hrrq[IPR_INIT_HRRQ]);
724 ipr_init_ipr_cmnd(ipr_cmd, ipr_lock_and_done);
725 return ipr_cmd;
726}
727
728
729
730
731
732
733
734
735
736
737
738
739static void ipr_mask_and_clear_interrupts(struct ipr_ioa_cfg *ioa_cfg,
740 u32 clr_ints)
741{
742 volatile u32 int_reg;
743 int i;
744
745
746 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
747 spin_lock(&ioa_cfg->hrrq[i]._lock);
748 ioa_cfg->hrrq[i].allow_interrupts = 0;
749 spin_unlock(&ioa_cfg->hrrq[i]._lock);
750 }
751 wmb();
752
753
754 if (ioa_cfg->sis64)
755 writeq(~0, ioa_cfg->regs.set_interrupt_mask_reg);
756 else
757 writel(~0, ioa_cfg->regs.set_interrupt_mask_reg);
758
759
760 if (ioa_cfg->sis64)
761 writel(~0, ioa_cfg->regs.clr_interrupt_reg);
762 writel(clr_ints, ioa_cfg->regs.clr_interrupt_reg32);
763 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
764}
765
766
767
768
769
770
771
772
773static int ipr_save_pcix_cmd_reg(struct ipr_ioa_cfg *ioa_cfg)
774{
775 int pcix_cmd_reg = pci_find_capability(ioa_cfg->pdev, PCI_CAP_ID_PCIX);
776
777 if (pcix_cmd_reg == 0)
778 return 0;
779
780 if (pci_read_config_word(ioa_cfg->pdev, pcix_cmd_reg + PCI_X_CMD,
781 &ioa_cfg->saved_pcix_cmd_reg) != PCIBIOS_SUCCESSFUL) {
782 dev_err(&ioa_cfg->pdev->dev, "Failed to save PCI-X command register\n");
783 return -EIO;
784 }
785
786 ioa_cfg->saved_pcix_cmd_reg |= PCI_X_CMD_DPERR_E | PCI_X_CMD_ERO;
787 return 0;
788}
789
790
791
792
793
794
795
796
797static int ipr_set_pcix_cmd_reg(struct ipr_ioa_cfg *ioa_cfg)
798{
799 int pcix_cmd_reg = pci_find_capability(ioa_cfg->pdev, PCI_CAP_ID_PCIX);
800
801 if (pcix_cmd_reg) {
802 if (pci_write_config_word(ioa_cfg->pdev, pcix_cmd_reg + PCI_X_CMD,
803 ioa_cfg->saved_pcix_cmd_reg) != PCIBIOS_SUCCESSFUL) {
804 dev_err(&ioa_cfg->pdev->dev, "Failed to setup PCI-X command register\n");
805 return -EIO;
806 }
807 }
808
809 return 0;
810}
811
812
813
814
815
816
817
818
819
820
821
822static void ipr_sata_eh_done(struct ipr_cmnd *ipr_cmd)
823{
824 struct ata_queued_cmd *qc = ipr_cmd->qc;
825 struct ipr_sata_port *sata_port = qc->ap->private_data;
826
827 qc->err_mask |= AC_ERR_OTHER;
828 sata_port->ioasa.status |= ATA_BUSY;
829 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
830 ata_qc_complete(qc);
831}
832
833
834
835
836
837
838
839
840
841
842
843static void ipr_scsi_eh_done(struct ipr_cmnd *ipr_cmd)
844{
845 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
846
847 scsi_cmd->result |= (DID_ERROR << 16);
848
849 scsi_dma_unmap(ipr_cmd->scsi_cmd);
850 scsi_cmd->scsi_done(scsi_cmd);
851 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
852}
853
854
855
856
857
858
859
860
861
862
863static void ipr_fail_all_ops(struct ipr_ioa_cfg *ioa_cfg)
864{
865 struct ipr_cmnd *ipr_cmd, *temp;
866 struct ipr_hrr_queue *hrrq;
867
868 ENTER;
869 for_each_hrrq(hrrq, ioa_cfg) {
870 spin_lock(&hrrq->_lock);
871 list_for_each_entry_safe(ipr_cmd,
872 temp, &hrrq->hrrq_pending_q, queue) {
873 list_del(&ipr_cmd->queue);
874
875 ipr_cmd->s.ioasa.hdr.ioasc =
876 cpu_to_be32(IPR_IOASC_IOA_WAS_RESET);
877 ipr_cmd->s.ioasa.hdr.ilid =
878 cpu_to_be32(IPR_DRIVER_ILID);
879
880 if (ipr_cmd->scsi_cmd)
881 ipr_cmd->done = ipr_scsi_eh_done;
882 else if (ipr_cmd->qc)
883 ipr_cmd->done = ipr_sata_eh_done;
884
885 ipr_trc_hook(ipr_cmd, IPR_TRACE_FINISH,
886 IPR_IOASC_IOA_WAS_RESET);
887 del_timer(&ipr_cmd->timer);
888 ipr_cmd->done(ipr_cmd);
889 }
890 spin_unlock(&hrrq->_lock);
891 }
892 LEAVE;
893}
894
895
896
897
898
899
900
901
902
903
904
905
906static void ipr_send_command(struct ipr_cmnd *ipr_cmd)
907{
908 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
909 dma_addr_t send_dma_addr = ipr_cmd->dma_addr;
910
911 if (ioa_cfg->sis64) {
912
913 send_dma_addr |= 0x1;
914
915
916
917 if (ipr_cmd->dma_use_sg * sizeof(struct ipr_ioadl64_desc) > 128 )
918 send_dma_addr |= 0x4;
919 writeq(send_dma_addr, ioa_cfg->regs.ioarrin_reg);
920 } else
921 writel(send_dma_addr, ioa_cfg->regs.ioarrin_reg);
922}
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937static void ipr_do_req(struct ipr_cmnd *ipr_cmd,
938 void (*done) (struct ipr_cmnd *),
939 void (*timeout_func) (struct ipr_cmnd *), u32 timeout)
940{
941 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
942
943 ipr_cmd->done = done;
944
945 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
946 ipr_cmd->timer.expires = jiffies + timeout;
947 ipr_cmd->timer.function = (void (*)(unsigned long))timeout_func;
948
949 add_timer(&ipr_cmd->timer);
950
951 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, 0);
952
953 ipr_send_command(ipr_cmd);
954}
955
956
957
958
959
960
961
962
963
964
965
966static void ipr_internal_cmd_done(struct ipr_cmnd *ipr_cmd)
967{
968 if (ipr_cmd->sibling)
969 ipr_cmd->sibling = NULL;
970 else
971 complete(&ipr_cmd->completion);
972}
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987static void ipr_init_ioadl(struct ipr_cmnd *ipr_cmd, dma_addr_t dma_addr,
988 u32 len, int flags)
989{
990 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
991 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
992
993 ipr_cmd->dma_use_sg = 1;
994
995 if (ipr_cmd->ioa_cfg->sis64) {
996 ioadl64->flags = cpu_to_be32(flags);
997 ioadl64->data_len = cpu_to_be32(len);
998 ioadl64->address = cpu_to_be64(dma_addr);
999
1000 ipr_cmd->ioarcb.ioadl_len =
1001 cpu_to_be32(sizeof(struct ipr_ioadl64_desc));
1002 ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len);
1003 } else {
1004 ioadl->flags_and_data_len = cpu_to_be32(flags | len);
1005 ioadl->address = cpu_to_be32(dma_addr);
1006
1007 if (flags == IPR_IOADL_FLAGS_READ_LAST) {
1008 ipr_cmd->ioarcb.read_ioadl_len =
1009 cpu_to_be32(sizeof(struct ipr_ioadl_desc));
1010 ipr_cmd->ioarcb.read_data_transfer_length = cpu_to_be32(len);
1011 } else {
1012 ipr_cmd->ioarcb.ioadl_len =
1013 cpu_to_be32(sizeof(struct ipr_ioadl_desc));
1014 ipr_cmd->ioarcb.data_transfer_length = cpu_to_be32(len);
1015 }
1016 }
1017}
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028static void ipr_send_blocking_cmd(struct ipr_cmnd *ipr_cmd,
1029 void (*timeout_func) (struct ipr_cmnd *ipr_cmd),
1030 u32 timeout)
1031{
1032 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
1033
1034 init_completion(&ipr_cmd->completion);
1035 ipr_do_req(ipr_cmd, ipr_internal_cmd_done, timeout_func, timeout);
1036
1037 spin_unlock_irq(ioa_cfg->host->host_lock);
1038 wait_for_completion(&ipr_cmd->completion);
1039 spin_lock_irq(ioa_cfg->host->host_lock);
1040}
1041
1042static int ipr_get_hrrq_index(struct ipr_ioa_cfg *ioa_cfg)
1043{
1044 if (ioa_cfg->hrrq_num == 1)
1045 return 0;
1046 else
1047 return (atomic_add_return(1, &ioa_cfg->hrrq_index) % (ioa_cfg->hrrq_num - 1)) + 1;
1048}
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063static void ipr_send_hcam(struct ipr_ioa_cfg *ioa_cfg, u8 type,
1064 struct ipr_hostrcb *hostrcb)
1065{
1066 struct ipr_cmnd *ipr_cmd;
1067 struct ipr_ioarcb *ioarcb;
1068
1069 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds) {
1070 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
1071 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
1072 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_pending_q);
1073
1074 ipr_cmd->u.hostrcb = hostrcb;
1075 ioarcb = &ipr_cmd->ioarcb;
1076
1077 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
1078 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_HCAM;
1079 ioarcb->cmd_pkt.cdb[0] = IPR_HOST_CONTROLLED_ASYNC;
1080 ioarcb->cmd_pkt.cdb[1] = type;
1081 ioarcb->cmd_pkt.cdb[7] = (sizeof(hostrcb->hcam) >> 8) & 0xff;
1082 ioarcb->cmd_pkt.cdb[8] = sizeof(hostrcb->hcam) & 0xff;
1083
1084 ipr_init_ioadl(ipr_cmd, hostrcb->hostrcb_dma,
1085 sizeof(hostrcb->hcam), IPR_IOADL_FLAGS_READ_LAST);
1086
1087 if (type == IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE)
1088 ipr_cmd->done = ipr_process_ccn;
1089 else
1090 ipr_cmd->done = ipr_process_error;
1091
1092 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_IOA_RES_ADDR);
1093
1094 ipr_send_command(ipr_cmd);
1095 } else {
1096 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
1097 }
1098}
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108static void ipr_update_ata_class(struct ipr_resource_entry *res, unsigned int proto)
1109{
1110 switch (proto) {
1111 case IPR_PROTO_SATA:
1112 case IPR_PROTO_SAS_STP:
1113 res->ata_class = ATA_DEV_ATA;
1114 break;
1115 case IPR_PROTO_SATA_ATAPI:
1116 case IPR_PROTO_SAS_STP_ATAPI:
1117 res->ata_class = ATA_DEV_ATAPI;
1118 break;
1119 default:
1120 res->ata_class = ATA_DEV_UNKNOWN;
1121 break;
1122 };
1123}
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133static void ipr_init_res_entry(struct ipr_resource_entry *res,
1134 struct ipr_config_table_entry_wrapper *cfgtew)
1135{
1136 int found = 0;
1137 unsigned int proto;
1138 struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg;
1139 struct ipr_resource_entry *gscsi_res = NULL;
1140
1141 res->needs_sync_complete = 0;
1142 res->in_erp = 0;
1143 res->add_to_ml = 0;
1144 res->del_from_ml = 0;
1145 res->resetting_device = 0;
1146 res->sdev = NULL;
1147 res->sata_port = NULL;
1148
1149 if (ioa_cfg->sis64) {
1150 proto = cfgtew->u.cfgte64->proto;
1151 res->res_flags = cfgtew->u.cfgte64->res_flags;
1152 res->qmodel = IPR_QUEUEING_MODEL64(res);
1153 res->type = cfgtew->u.cfgte64->res_type;
1154
1155 memcpy(res->res_path, &cfgtew->u.cfgte64->res_path,
1156 sizeof(res->res_path));
1157
1158 res->bus = 0;
1159 memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1160 sizeof(res->dev_lun.scsi_lun));
1161 res->lun = scsilun_to_int(&res->dev_lun);
1162
1163 if (res->type == IPR_RES_TYPE_GENERIC_SCSI) {
1164 list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue) {
1165 if (gscsi_res->dev_id == cfgtew->u.cfgte64->dev_id) {
1166 found = 1;
1167 res->target = gscsi_res->target;
1168 break;
1169 }
1170 }
1171 if (!found) {
1172 res->target = find_first_zero_bit(ioa_cfg->target_ids,
1173 ioa_cfg->max_devs_supported);
1174 set_bit(res->target, ioa_cfg->target_ids);
1175 }
1176 } else if (res->type == IPR_RES_TYPE_IOAFP) {
1177 res->bus = IPR_IOAFP_VIRTUAL_BUS;
1178 res->target = 0;
1179 } else if (res->type == IPR_RES_TYPE_ARRAY) {
1180 res->bus = IPR_ARRAY_VIRTUAL_BUS;
1181 res->target = find_first_zero_bit(ioa_cfg->array_ids,
1182 ioa_cfg->max_devs_supported);
1183 set_bit(res->target, ioa_cfg->array_ids);
1184 } else if (res->type == IPR_RES_TYPE_VOLUME_SET) {
1185 res->bus = IPR_VSET_VIRTUAL_BUS;
1186 res->target = find_first_zero_bit(ioa_cfg->vset_ids,
1187 ioa_cfg->max_devs_supported);
1188 set_bit(res->target, ioa_cfg->vset_ids);
1189 } else {
1190 res->target = find_first_zero_bit(ioa_cfg->target_ids,
1191 ioa_cfg->max_devs_supported);
1192 set_bit(res->target, ioa_cfg->target_ids);
1193 }
1194 } else {
1195 proto = cfgtew->u.cfgte->proto;
1196 res->qmodel = IPR_QUEUEING_MODEL(res);
1197 res->flags = cfgtew->u.cfgte->flags;
1198 if (res->flags & IPR_IS_IOA_RESOURCE)
1199 res->type = IPR_RES_TYPE_IOAFP;
1200 else
1201 res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f;
1202
1203 res->bus = cfgtew->u.cfgte->res_addr.bus;
1204 res->target = cfgtew->u.cfgte->res_addr.target;
1205 res->lun = cfgtew->u.cfgte->res_addr.lun;
1206 res->lun_wwn = get_unaligned_be64(cfgtew->u.cfgte->lun_wwn);
1207 }
1208
1209 ipr_update_ata_class(res, proto);
1210}
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220static int ipr_is_same_device(struct ipr_resource_entry *res,
1221 struct ipr_config_table_entry_wrapper *cfgtew)
1222{
1223 if (res->ioa_cfg->sis64) {
1224 if (!memcmp(&res->dev_id, &cfgtew->u.cfgte64->dev_id,
1225 sizeof(cfgtew->u.cfgte64->dev_id)) &&
1226 !memcmp(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1227 sizeof(cfgtew->u.cfgte64->lun))) {
1228 return 1;
1229 }
1230 } else {
1231 if (res->bus == cfgtew->u.cfgte->res_addr.bus &&
1232 res->target == cfgtew->u.cfgte->res_addr.target &&
1233 res->lun == cfgtew->u.cfgte->res_addr.lun)
1234 return 1;
1235 }
1236
1237 return 0;
1238}
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249static char *__ipr_format_res_path(u8 *res_path, char *buffer, int len)
1250{
1251 int i;
1252 char *p = buffer;
1253
1254 *p = '\0';
1255 p += snprintf(p, buffer + len - p, "%02X", res_path[0]);
1256 for (i = 1; res_path[i] != 0xff && ((i * 3) < len); i++)
1257 p += snprintf(p, buffer + len - p, "-%02X", res_path[i]);
1258
1259 return buffer;
1260}
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272static char *ipr_format_res_path(struct ipr_ioa_cfg *ioa_cfg,
1273 u8 *res_path, char *buffer, int len)
1274{
1275 char *p = buffer;
1276
1277 *p = '\0';
1278 p += snprintf(p, buffer + len - p, "%d/", ioa_cfg->host->host_no);
1279 __ipr_format_res_path(res_path, p, len - (buffer - p));
1280 return buffer;
1281}
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291static void ipr_update_res_entry(struct ipr_resource_entry *res,
1292 struct ipr_config_table_entry_wrapper *cfgtew)
1293{
1294 char buffer[IPR_MAX_RES_PATH_LENGTH];
1295 unsigned int proto;
1296 int new_path = 0;
1297
1298 if (res->ioa_cfg->sis64) {
1299 res->flags = cfgtew->u.cfgte64->flags;
1300 res->res_flags = cfgtew->u.cfgte64->res_flags;
1301 res->type = cfgtew->u.cfgte64->res_type;
1302
1303 memcpy(&res->std_inq_data, &cfgtew->u.cfgte64->std_inq_data,
1304 sizeof(struct ipr_std_inq_data));
1305
1306 res->qmodel = IPR_QUEUEING_MODEL64(res);
1307 proto = cfgtew->u.cfgte64->proto;
1308 res->res_handle = cfgtew->u.cfgte64->res_handle;
1309 res->dev_id = cfgtew->u.cfgte64->dev_id;
1310
1311 memcpy(&res->dev_lun.scsi_lun, &cfgtew->u.cfgte64->lun,
1312 sizeof(res->dev_lun.scsi_lun));
1313
1314 if (memcmp(res->res_path, &cfgtew->u.cfgte64->res_path,
1315 sizeof(res->res_path))) {
1316 memcpy(res->res_path, &cfgtew->u.cfgte64->res_path,
1317 sizeof(res->res_path));
1318 new_path = 1;
1319 }
1320
1321 if (res->sdev && new_path)
1322 sdev_printk(KERN_INFO, res->sdev, "Resource path: %s\n",
1323 ipr_format_res_path(res->ioa_cfg,
1324 res->res_path, buffer, sizeof(buffer)));
1325 } else {
1326 res->flags = cfgtew->u.cfgte->flags;
1327 if (res->flags & IPR_IS_IOA_RESOURCE)
1328 res->type = IPR_RES_TYPE_IOAFP;
1329 else
1330 res->type = cfgtew->u.cfgte->rsvd_subtype & 0x0f;
1331
1332 memcpy(&res->std_inq_data, &cfgtew->u.cfgte->std_inq_data,
1333 sizeof(struct ipr_std_inq_data));
1334
1335 res->qmodel = IPR_QUEUEING_MODEL(res);
1336 proto = cfgtew->u.cfgte->proto;
1337 res->res_handle = cfgtew->u.cfgte->res_handle;
1338 }
1339
1340 ipr_update_ata_class(res, proto);
1341}
1342
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352static void ipr_clear_res_target(struct ipr_resource_entry *res)
1353{
1354 struct ipr_resource_entry *gscsi_res = NULL;
1355 struct ipr_ioa_cfg *ioa_cfg = res->ioa_cfg;
1356
1357 if (!ioa_cfg->sis64)
1358 return;
1359
1360 if (res->bus == IPR_ARRAY_VIRTUAL_BUS)
1361 clear_bit(res->target, ioa_cfg->array_ids);
1362 else if (res->bus == IPR_VSET_VIRTUAL_BUS)
1363 clear_bit(res->target, ioa_cfg->vset_ids);
1364 else if (res->bus == 0 && res->type == IPR_RES_TYPE_GENERIC_SCSI) {
1365 list_for_each_entry(gscsi_res, &ioa_cfg->used_res_q, queue)
1366 if (gscsi_res->dev_id == res->dev_id && gscsi_res != res)
1367 return;
1368 clear_bit(res->target, ioa_cfg->target_ids);
1369
1370 } else if (res->bus == 0)
1371 clear_bit(res->target, ioa_cfg->target_ids);
1372}
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382static void ipr_handle_config_change(struct ipr_ioa_cfg *ioa_cfg,
1383 struct ipr_hostrcb *hostrcb)
1384{
1385 struct ipr_resource_entry *res = NULL;
1386 struct ipr_config_table_entry_wrapper cfgtew;
1387 __be32 cc_res_handle;
1388
1389 u32 is_ndn = 1;
1390
1391 if (ioa_cfg->sis64) {
1392 cfgtew.u.cfgte64 = &hostrcb->hcam.u.ccn.u.cfgte64;
1393 cc_res_handle = cfgtew.u.cfgte64->res_handle;
1394 } else {
1395 cfgtew.u.cfgte = &hostrcb->hcam.u.ccn.u.cfgte;
1396 cc_res_handle = cfgtew.u.cfgte->res_handle;
1397 }
1398
1399 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
1400 if (res->res_handle == cc_res_handle) {
1401 is_ndn = 0;
1402 break;
1403 }
1404 }
1405
1406 if (is_ndn) {
1407 if (list_empty(&ioa_cfg->free_res_q)) {
1408 ipr_send_hcam(ioa_cfg,
1409 IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE,
1410 hostrcb);
1411 return;
1412 }
1413
1414 res = list_entry(ioa_cfg->free_res_q.next,
1415 struct ipr_resource_entry, queue);
1416
1417 list_del(&res->queue);
1418 ipr_init_res_entry(res, &cfgtew);
1419 list_add_tail(&res->queue, &ioa_cfg->used_res_q);
1420 }
1421
1422 ipr_update_res_entry(res, &cfgtew);
1423
1424 if (hostrcb->hcam.notify_type == IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY) {
1425 if (res->sdev) {
1426 res->del_from_ml = 1;
1427 res->res_handle = IPR_INVALID_RES_HANDLE;
1428 if (ioa_cfg->allow_ml_add_del)
1429 schedule_work(&ioa_cfg->work_q);
1430 } else {
1431 ipr_clear_res_target(res);
1432 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
1433 }
1434 } else if (!res->sdev || res->del_from_ml) {
1435 res->add_to_ml = 1;
1436 if (ioa_cfg->allow_ml_add_del)
1437 schedule_work(&ioa_cfg->work_q);
1438 }
1439
1440 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
1441}
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453static void ipr_process_ccn(struct ipr_cmnd *ipr_cmd)
1454{
1455 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
1456 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb;
1457 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
1458
1459 list_del(&hostrcb->queue);
1460 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
1461
1462 if (ioasc) {
1463 if (ioasc != IPR_IOASC_IOA_WAS_RESET)
1464 dev_err(&ioa_cfg->pdev->dev,
1465 "Host RCB failed with IOASC: 0x%08X\n", ioasc);
1466
1467 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
1468 } else {
1469 ipr_handle_config_change(ioa_cfg, hostrcb);
1470 }
1471}
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483
1484static int strip_and_pad_whitespace(int i, char *buf)
1485{
1486 while (i && buf[i] == ' ')
1487 i--;
1488 buf[i+1] = ' ';
1489 buf[i+2] = '\0';
1490 return i + 2;
1491}
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502static void ipr_log_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb,
1503 struct ipr_vpd *vpd)
1504{
1505 char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN + IPR_SERIAL_NUM_LEN + 3];
1506 int i = 0;
1507
1508 memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN);
1509 i = strip_and_pad_whitespace(IPR_VENDOR_ID_LEN - 1, buffer);
1510
1511 memcpy(&buffer[i], vpd->vpids.product_id, IPR_PROD_ID_LEN);
1512 i = strip_and_pad_whitespace(i + IPR_PROD_ID_LEN - 1, buffer);
1513
1514 memcpy(&buffer[i], vpd->sn, IPR_SERIAL_NUM_LEN);
1515 buffer[IPR_SERIAL_NUM_LEN + i] = '\0';
1516
1517 ipr_hcam_err(hostrcb, "%s VPID/SN: %s\n", prefix, buffer);
1518}
1519
1520
1521
1522
1523
1524
1525
1526
1527static void ipr_log_vpd(struct ipr_vpd *vpd)
1528{
1529 char buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN
1530 + IPR_SERIAL_NUM_LEN];
1531
1532 memcpy(buffer, vpd->vpids.vendor_id, IPR_VENDOR_ID_LEN);
1533 memcpy(buffer + IPR_VENDOR_ID_LEN, vpd->vpids.product_id,
1534 IPR_PROD_ID_LEN);
1535 buffer[IPR_VENDOR_ID_LEN + IPR_PROD_ID_LEN] = '\0';
1536 ipr_err("Vendor/Product ID: %s\n", buffer);
1537
1538 memcpy(buffer, vpd->sn, IPR_SERIAL_NUM_LEN);
1539 buffer[IPR_SERIAL_NUM_LEN] = '\0';
1540 ipr_err(" Serial Number: %s\n", buffer);
1541}
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552static void ipr_log_ext_vpd_compact(char *prefix, struct ipr_hostrcb *hostrcb,
1553 struct ipr_ext_vpd *vpd)
1554{
1555 ipr_log_vpd_compact(prefix, hostrcb, &vpd->vpd);
1556 ipr_hcam_err(hostrcb, "%s WWN: %08X%08X\n", prefix,
1557 be32_to_cpu(vpd->wwid[0]), be32_to_cpu(vpd->wwid[1]));
1558}
1559
1560
1561
1562
1563
1564
1565
1566
1567static void ipr_log_ext_vpd(struct ipr_ext_vpd *vpd)
1568{
1569 ipr_log_vpd(&vpd->vpd);
1570 ipr_err(" WWN: %08X%08X\n", be32_to_cpu(vpd->wwid[0]),
1571 be32_to_cpu(vpd->wwid[1]));
1572}
1573
1574
1575
1576
1577
1578
1579
1580
1581
1582static void ipr_log_enhanced_cache_error(struct ipr_ioa_cfg *ioa_cfg,
1583 struct ipr_hostrcb *hostrcb)
1584{
1585 struct ipr_hostrcb_type_12_error *error;
1586
1587 if (ioa_cfg->sis64)
1588 error = &hostrcb->hcam.u.error64.u.type_12_error;
1589 else
1590 error = &hostrcb->hcam.u.error.u.type_12_error;
1591
1592 ipr_err("-----Current Configuration-----\n");
1593 ipr_err("Cache Directory Card Information:\n");
1594 ipr_log_ext_vpd(&error->ioa_vpd);
1595 ipr_err("Adapter Card Information:\n");
1596 ipr_log_ext_vpd(&error->cfc_vpd);
1597
1598 ipr_err("-----Expected Configuration-----\n");
1599 ipr_err("Cache Directory Card Information:\n");
1600 ipr_log_ext_vpd(&error->ioa_last_attached_to_cfc_vpd);
1601 ipr_err("Adapter Card Information:\n");
1602 ipr_log_ext_vpd(&error->cfc_last_attached_to_ioa_vpd);
1603
1604 ipr_err("Additional IOA Data: %08X %08X %08X\n",
1605 be32_to_cpu(error->ioa_data[0]),
1606 be32_to_cpu(error->ioa_data[1]),
1607 be32_to_cpu(error->ioa_data[2]));
1608}
1609
1610
1611
1612
1613
1614
1615
1616
1617
1618static void ipr_log_cache_error(struct ipr_ioa_cfg *ioa_cfg,
1619 struct ipr_hostrcb *hostrcb)
1620{
1621 struct ipr_hostrcb_type_02_error *error =
1622 &hostrcb->hcam.u.error.u.type_02_error;
1623
1624 ipr_err("-----Current Configuration-----\n");
1625 ipr_err("Cache Directory Card Information:\n");
1626 ipr_log_vpd(&error->ioa_vpd);
1627 ipr_err("Adapter Card Information:\n");
1628 ipr_log_vpd(&error->cfc_vpd);
1629
1630 ipr_err("-----Expected Configuration-----\n");
1631 ipr_err("Cache Directory Card Information:\n");
1632 ipr_log_vpd(&error->ioa_last_attached_to_cfc_vpd);
1633 ipr_err("Adapter Card Information:\n");
1634 ipr_log_vpd(&error->cfc_last_attached_to_ioa_vpd);
1635
1636 ipr_err("Additional IOA Data: %08X %08X %08X\n",
1637 be32_to_cpu(error->ioa_data[0]),
1638 be32_to_cpu(error->ioa_data[1]),
1639 be32_to_cpu(error->ioa_data[2]));
1640}
1641
1642
1643
1644
1645
1646
1647
1648
1649
1650static void ipr_log_enhanced_config_error(struct ipr_ioa_cfg *ioa_cfg,
1651 struct ipr_hostrcb *hostrcb)
1652{
1653 int errors_logged, i;
1654 struct ipr_hostrcb_device_data_entry_enhanced *dev_entry;
1655 struct ipr_hostrcb_type_13_error *error;
1656
1657 error = &hostrcb->hcam.u.error.u.type_13_error;
1658 errors_logged = be32_to_cpu(error->errors_logged);
1659
1660 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1661 be32_to_cpu(error->errors_detected), errors_logged);
1662
1663 dev_entry = error->dev;
1664
1665 for (i = 0; i < errors_logged; i++, dev_entry++) {
1666 ipr_err_separator;
1667
1668 ipr_phys_res_err(ioa_cfg, dev_entry->dev_res_addr, "Device %d", i + 1);
1669 ipr_log_ext_vpd(&dev_entry->vpd);
1670
1671 ipr_err("-----New Device Information-----\n");
1672 ipr_log_ext_vpd(&dev_entry->new_vpd);
1673
1674 ipr_err("Cache Directory Card Information:\n");
1675 ipr_log_ext_vpd(&dev_entry->ioa_last_with_dev_vpd);
1676
1677 ipr_err("Adapter Card Information:\n");
1678 ipr_log_ext_vpd(&dev_entry->cfc_last_with_dev_vpd);
1679 }
1680}
1681
1682
1683
1684
1685
1686
1687
1688
1689
1690static void ipr_log_sis64_config_error(struct ipr_ioa_cfg *ioa_cfg,
1691 struct ipr_hostrcb *hostrcb)
1692{
1693 int errors_logged, i;
1694 struct ipr_hostrcb64_device_data_entry_enhanced *dev_entry;
1695 struct ipr_hostrcb_type_23_error *error;
1696 char buffer[IPR_MAX_RES_PATH_LENGTH];
1697
1698 error = &hostrcb->hcam.u.error64.u.type_23_error;
1699 errors_logged = be32_to_cpu(error->errors_logged);
1700
1701 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1702 be32_to_cpu(error->errors_detected), errors_logged);
1703
1704 dev_entry = error->dev;
1705
1706 for (i = 0; i < errors_logged; i++, dev_entry++) {
1707 ipr_err_separator;
1708
1709 ipr_err("Device %d : %s", i + 1,
1710 __ipr_format_res_path(dev_entry->res_path,
1711 buffer, sizeof(buffer)));
1712 ipr_log_ext_vpd(&dev_entry->vpd);
1713
1714 ipr_err("-----New Device Information-----\n");
1715 ipr_log_ext_vpd(&dev_entry->new_vpd);
1716
1717 ipr_err("Cache Directory Card Information:\n");
1718 ipr_log_ext_vpd(&dev_entry->ioa_last_with_dev_vpd);
1719
1720 ipr_err("Adapter Card Information:\n");
1721 ipr_log_ext_vpd(&dev_entry->cfc_last_with_dev_vpd);
1722 }
1723}
1724
1725
1726
1727
1728
1729
1730
1731
1732
1733static void ipr_log_config_error(struct ipr_ioa_cfg *ioa_cfg,
1734 struct ipr_hostrcb *hostrcb)
1735{
1736 int errors_logged, i;
1737 struct ipr_hostrcb_device_data_entry *dev_entry;
1738 struct ipr_hostrcb_type_03_error *error;
1739
1740 error = &hostrcb->hcam.u.error.u.type_03_error;
1741 errors_logged = be32_to_cpu(error->errors_logged);
1742
1743 ipr_err("Device Errors Detected/Logged: %d/%d\n",
1744 be32_to_cpu(error->errors_detected), errors_logged);
1745
1746 dev_entry = error->dev;
1747
1748 for (i = 0; i < errors_logged; i++, dev_entry++) {
1749 ipr_err_separator;
1750
1751 ipr_phys_res_err(ioa_cfg, dev_entry->dev_res_addr, "Device %d", i + 1);
1752 ipr_log_vpd(&dev_entry->vpd);
1753
1754 ipr_err("-----New Device Information-----\n");
1755 ipr_log_vpd(&dev_entry->new_vpd);
1756
1757 ipr_err("Cache Directory Card Information:\n");
1758 ipr_log_vpd(&dev_entry->ioa_last_with_dev_vpd);
1759
1760 ipr_err("Adapter Card Information:\n");
1761 ipr_log_vpd(&dev_entry->cfc_last_with_dev_vpd);
1762
1763 ipr_err("Additional IOA Data: %08X %08X %08X %08X %08X\n",
1764 be32_to_cpu(dev_entry->ioa_data[0]),
1765 be32_to_cpu(dev_entry->ioa_data[1]),
1766 be32_to_cpu(dev_entry->ioa_data[2]),
1767 be32_to_cpu(dev_entry->ioa_data[3]),
1768 be32_to_cpu(dev_entry->ioa_data[4]));
1769 }
1770}
1771
1772
1773
1774
1775
1776
1777
1778
1779
1780static void ipr_log_enhanced_array_error(struct ipr_ioa_cfg *ioa_cfg,
1781 struct ipr_hostrcb *hostrcb)
1782{
1783 int i, num_entries;
1784 struct ipr_hostrcb_type_14_error *error;
1785 struct ipr_hostrcb_array_data_entry_enhanced *array_entry;
1786 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
1787
1788 error = &hostrcb->hcam.u.error.u.type_14_error;
1789
1790 ipr_err_separator;
1791
1792 ipr_err("RAID %s Array Configuration: %d:%d:%d:%d\n",
1793 error->protection_level,
1794 ioa_cfg->host->host_no,
1795 error->last_func_vset_res_addr.bus,
1796 error->last_func_vset_res_addr.target,
1797 error->last_func_vset_res_addr.lun);
1798
1799 ipr_err_separator;
1800
1801 array_entry = error->array_member;
1802 num_entries = min_t(u32, be32_to_cpu(error->num_entries),
1803 ARRAY_SIZE(error->array_member));
1804
1805 for (i = 0; i < num_entries; i++, array_entry++) {
1806 if (!memcmp(array_entry->vpd.vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
1807 continue;
1808
1809 if (be32_to_cpu(error->exposed_mode_adn) == i)
1810 ipr_err("Exposed Array Member %d:\n", i);
1811 else
1812 ipr_err("Array Member %d:\n", i);
1813
1814 ipr_log_ext_vpd(&array_entry->vpd);
1815 ipr_phys_res_err(ioa_cfg, array_entry->dev_res_addr, "Current Location");
1816 ipr_phys_res_err(ioa_cfg, array_entry->expected_dev_res_addr,
1817 "Expected Location");
1818
1819 ipr_err_separator;
1820 }
1821}
1822
1823
1824
1825
1826
1827
1828
1829
1830
1831static void ipr_log_array_error(struct ipr_ioa_cfg *ioa_cfg,
1832 struct ipr_hostrcb *hostrcb)
1833{
1834 int i;
1835 struct ipr_hostrcb_type_04_error *error;
1836 struct ipr_hostrcb_array_data_entry *array_entry;
1837 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
1838
1839 error = &hostrcb->hcam.u.error.u.type_04_error;
1840
1841 ipr_err_separator;
1842
1843 ipr_err("RAID %s Array Configuration: %d:%d:%d:%d\n",
1844 error->protection_level,
1845 ioa_cfg->host->host_no,
1846 error->last_func_vset_res_addr.bus,
1847 error->last_func_vset_res_addr.target,
1848 error->last_func_vset_res_addr.lun);
1849
1850 ipr_err_separator;
1851
1852 array_entry = error->array_member;
1853
1854 for (i = 0; i < 18; i++) {
1855 if (!memcmp(array_entry->vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
1856 continue;
1857
1858 if (be32_to_cpu(error->exposed_mode_adn) == i)
1859 ipr_err("Exposed Array Member %d:\n", i);
1860 else
1861 ipr_err("Array Member %d:\n", i);
1862
1863 ipr_log_vpd(&array_entry->vpd);
1864
1865 ipr_phys_res_err(ioa_cfg, array_entry->dev_res_addr, "Current Location");
1866 ipr_phys_res_err(ioa_cfg, array_entry->expected_dev_res_addr,
1867 "Expected Location");
1868
1869 ipr_err_separator;
1870
1871 if (i == 9)
1872 array_entry = error->array_member2;
1873 else
1874 array_entry++;
1875 }
1876}
1877
1878
1879
1880
1881
1882
1883
1884
1885
1886
1887static void ipr_log_hex_data(struct ipr_ioa_cfg *ioa_cfg, u32 *data, int len)
1888{
1889 int i;
1890
1891 if (len == 0)
1892 return;
1893
1894 if (ioa_cfg->log_level <= IPR_DEFAULT_LOG_LEVEL)
1895 len = min_t(int, len, IPR_DEFAULT_MAX_ERROR_DUMP);
1896
1897 for (i = 0; i < len / 4; i += 4) {
1898 ipr_err("%08X: %08X %08X %08X %08X\n", i*4,
1899 be32_to_cpu(data[i]),
1900 be32_to_cpu(data[i+1]),
1901 be32_to_cpu(data[i+2]),
1902 be32_to_cpu(data[i+3]));
1903 }
1904}
1905
1906
1907
1908
1909
1910
1911
1912
1913
1914static void ipr_log_enhanced_dual_ioa_error(struct ipr_ioa_cfg *ioa_cfg,
1915 struct ipr_hostrcb *hostrcb)
1916{
1917 struct ipr_hostrcb_type_17_error *error;
1918
1919 if (ioa_cfg->sis64)
1920 error = &hostrcb->hcam.u.error64.u.type_17_error;
1921 else
1922 error = &hostrcb->hcam.u.error.u.type_17_error;
1923
1924 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
1925 strim(error->failure_reason);
1926
1927 ipr_hcam_err(hostrcb, "%s [PRC: %08X]\n", error->failure_reason,
1928 be32_to_cpu(hostrcb->hcam.u.error.prc));
1929 ipr_log_ext_vpd_compact("Remote IOA", hostrcb, &error->vpd);
1930 ipr_log_hex_data(ioa_cfg, error->data,
1931 be32_to_cpu(hostrcb->hcam.length) -
1932 (offsetof(struct ipr_hostrcb_error, u) +
1933 offsetof(struct ipr_hostrcb_type_17_error, data)));
1934}
1935
1936
1937
1938
1939
1940
1941
1942
1943
1944static void ipr_log_dual_ioa_error(struct ipr_ioa_cfg *ioa_cfg,
1945 struct ipr_hostrcb *hostrcb)
1946{
1947 struct ipr_hostrcb_type_07_error *error;
1948
1949 error = &hostrcb->hcam.u.error.u.type_07_error;
1950 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
1951 strim(error->failure_reason);
1952
1953 ipr_hcam_err(hostrcb, "%s [PRC: %08X]\n", error->failure_reason,
1954 be32_to_cpu(hostrcb->hcam.u.error.prc));
1955 ipr_log_vpd_compact("Remote IOA", hostrcb, &error->vpd);
1956 ipr_log_hex_data(ioa_cfg, error->data,
1957 be32_to_cpu(hostrcb->hcam.length) -
1958 (offsetof(struct ipr_hostrcb_error, u) +
1959 offsetof(struct ipr_hostrcb_type_07_error, data)));
1960}
1961
1962static const struct {
1963 u8 active;
1964 char *desc;
1965} path_active_desc[] = {
1966 { IPR_PATH_NO_INFO, "Path" },
1967 { IPR_PATH_ACTIVE, "Active path" },
1968 { IPR_PATH_NOT_ACTIVE, "Inactive path" }
1969};
1970
1971static const struct {
1972 u8 state;
1973 char *desc;
1974} path_state_desc[] = {
1975 { IPR_PATH_STATE_NO_INFO, "has no path state information available" },
1976 { IPR_PATH_HEALTHY, "is healthy" },
1977 { IPR_PATH_DEGRADED, "is degraded" },
1978 { IPR_PATH_FAILED, "is failed" }
1979};
1980
1981
1982
1983
1984
1985
1986
1987
1988
1989static void ipr_log_fabric_path(struct ipr_hostrcb *hostrcb,
1990 struct ipr_hostrcb_fabric_desc *fabric)
1991{
1992 int i, j;
1993 u8 path_state = fabric->path_state;
1994 u8 active = path_state & IPR_PATH_ACTIVE_MASK;
1995 u8 state = path_state & IPR_PATH_STATE_MASK;
1996
1997 for (i = 0; i < ARRAY_SIZE(path_active_desc); i++) {
1998 if (path_active_desc[i].active != active)
1999 continue;
2000
2001 for (j = 0; j < ARRAY_SIZE(path_state_desc); j++) {
2002 if (path_state_desc[j].state != state)
2003 continue;
2004
2005 if (fabric->cascaded_expander == 0xff && fabric->phy == 0xff) {
2006 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d\n",
2007 path_active_desc[i].desc, path_state_desc[j].desc,
2008 fabric->ioa_port);
2009 } else if (fabric->cascaded_expander == 0xff) {
2010 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Phy=%d\n",
2011 path_active_desc[i].desc, path_state_desc[j].desc,
2012 fabric->ioa_port, fabric->phy);
2013 } else if (fabric->phy == 0xff) {
2014 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Cascade=%d\n",
2015 path_active_desc[i].desc, path_state_desc[j].desc,
2016 fabric->ioa_port, fabric->cascaded_expander);
2017 } else {
2018 ipr_hcam_err(hostrcb, "%s %s: IOA Port=%d, Cascade=%d, Phy=%d\n",
2019 path_active_desc[i].desc, path_state_desc[j].desc,
2020 fabric->ioa_port, fabric->cascaded_expander, fabric->phy);
2021 }
2022 return;
2023 }
2024 }
2025
2026 ipr_err("Path state=%02X IOA Port=%d Cascade=%d Phy=%d\n", path_state,
2027 fabric->ioa_port, fabric->cascaded_expander, fabric->phy);
2028}
2029
2030
2031
2032
2033
2034
2035
2036
2037
2038static void ipr_log64_fabric_path(struct ipr_hostrcb *hostrcb,
2039 struct ipr_hostrcb64_fabric_desc *fabric)
2040{
2041 int i, j;
2042 u8 path_state = fabric->path_state;
2043 u8 active = path_state & IPR_PATH_ACTIVE_MASK;
2044 u8 state = path_state & IPR_PATH_STATE_MASK;
2045 char buffer[IPR_MAX_RES_PATH_LENGTH];
2046
2047 for (i = 0; i < ARRAY_SIZE(path_active_desc); i++) {
2048 if (path_active_desc[i].active != active)
2049 continue;
2050
2051 for (j = 0; j < ARRAY_SIZE(path_state_desc); j++) {
2052 if (path_state_desc[j].state != state)
2053 continue;
2054
2055 ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s\n",
2056 path_active_desc[i].desc, path_state_desc[j].desc,
2057 ipr_format_res_path(hostrcb->ioa_cfg,
2058 fabric->res_path,
2059 buffer, sizeof(buffer)));
2060 return;
2061 }
2062 }
2063
2064 ipr_err("Path state=%02X Resource Path=%s\n", path_state,
2065 ipr_format_res_path(hostrcb->ioa_cfg, fabric->res_path,
2066 buffer, sizeof(buffer)));
2067}
2068
2069static const struct {
2070 u8 type;
2071 char *desc;
2072} path_type_desc[] = {
2073 { IPR_PATH_CFG_IOA_PORT, "IOA port" },
2074 { IPR_PATH_CFG_EXP_PORT, "Expander port" },
2075 { IPR_PATH_CFG_DEVICE_PORT, "Device port" },
2076 { IPR_PATH_CFG_DEVICE_LUN, "Device LUN" }
2077};
2078
2079static const struct {
2080 u8 status;
2081 char *desc;
2082} path_status_desc[] = {
2083 { IPR_PATH_CFG_NO_PROB, "Functional" },
2084 { IPR_PATH_CFG_DEGRADED, "Degraded" },
2085 { IPR_PATH_CFG_FAILED, "Failed" },
2086 { IPR_PATH_CFG_SUSPECT, "Suspect" },
2087 { IPR_PATH_NOT_DETECTED, "Missing" },
2088 { IPR_PATH_INCORRECT_CONN, "Incorrectly connected" }
2089};
2090
2091static const char *link_rate[] = {
2092 "unknown",
2093 "disabled",
2094 "phy reset problem",
2095 "spinup hold",
2096 "port selector",
2097 "unknown",
2098 "unknown",
2099 "unknown",
2100 "1.5Gbps",
2101 "3.0Gbps",
2102 "unknown",
2103 "unknown",
2104 "unknown",
2105 "unknown",
2106 "unknown",
2107 "unknown"
2108};
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118static void ipr_log_path_elem(struct ipr_hostrcb *hostrcb,
2119 struct ipr_hostrcb_config_element *cfg)
2120{
2121 int i, j;
2122 u8 type = cfg->type_status & IPR_PATH_CFG_TYPE_MASK;
2123 u8 status = cfg->type_status & IPR_PATH_CFG_STATUS_MASK;
2124
2125 if (type == IPR_PATH_CFG_NOT_EXIST)
2126 return;
2127
2128 for (i = 0; i < ARRAY_SIZE(path_type_desc); i++) {
2129 if (path_type_desc[i].type != type)
2130 continue;
2131
2132 for (j = 0; j < ARRAY_SIZE(path_status_desc); j++) {
2133 if (path_status_desc[j].status != status)
2134 continue;
2135
2136 if (type == IPR_PATH_CFG_IOA_PORT) {
2137 ipr_hcam_err(hostrcb, "%s %s: Phy=%d, Link rate=%s, WWN=%08X%08X\n",
2138 path_status_desc[j].desc, path_type_desc[i].desc,
2139 cfg->phy, link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2140 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2141 } else {
2142 if (cfg->cascaded_expander == 0xff && cfg->phy == 0xff) {
2143 ipr_hcam_err(hostrcb, "%s %s: Link rate=%s, WWN=%08X%08X\n",
2144 path_status_desc[j].desc, path_type_desc[i].desc,
2145 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2146 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2147 } else if (cfg->cascaded_expander == 0xff) {
2148 ipr_hcam_err(hostrcb, "%s %s: Phy=%d, Link rate=%s, "
2149 "WWN=%08X%08X\n", path_status_desc[j].desc,
2150 path_type_desc[i].desc, cfg->phy,
2151 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2152 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2153 } else if (cfg->phy == 0xff) {
2154 ipr_hcam_err(hostrcb, "%s %s: Cascade=%d, Link rate=%s, "
2155 "WWN=%08X%08X\n", path_status_desc[j].desc,
2156 path_type_desc[i].desc, cfg->cascaded_expander,
2157 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2158 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2159 } else {
2160 ipr_hcam_err(hostrcb, "%s %s: Cascade=%d, Phy=%d, Link rate=%s "
2161 "WWN=%08X%08X\n", path_status_desc[j].desc,
2162 path_type_desc[i].desc, cfg->cascaded_expander, cfg->phy,
2163 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2164 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2165 }
2166 }
2167 return;
2168 }
2169 }
2170
2171 ipr_hcam_err(hostrcb, "Path element=%02X: Cascade=%d Phy=%d Link rate=%s "
2172 "WWN=%08X%08X\n", cfg->type_status, cfg->cascaded_expander, cfg->phy,
2173 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2174 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2175}
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185static void ipr_log64_path_elem(struct ipr_hostrcb *hostrcb,
2186 struct ipr_hostrcb64_config_element *cfg)
2187{
2188 int i, j;
2189 u8 desc_id = cfg->descriptor_id & IPR_DESCRIPTOR_MASK;
2190 u8 type = cfg->type_status & IPR_PATH_CFG_TYPE_MASK;
2191 u8 status = cfg->type_status & IPR_PATH_CFG_STATUS_MASK;
2192 char buffer[IPR_MAX_RES_PATH_LENGTH];
2193
2194 if (type == IPR_PATH_CFG_NOT_EXIST || desc_id != IPR_DESCRIPTOR_SIS64)
2195 return;
2196
2197 for (i = 0; i < ARRAY_SIZE(path_type_desc); i++) {
2198 if (path_type_desc[i].type != type)
2199 continue;
2200
2201 for (j = 0; j < ARRAY_SIZE(path_status_desc); j++) {
2202 if (path_status_desc[j].status != status)
2203 continue;
2204
2205 ipr_hcam_err(hostrcb, "%s %s: Resource Path=%s, Link rate=%s, WWN=%08X%08X\n",
2206 path_status_desc[j].desc, path_type_desc[i].desc,
2207 ipr_format_res_path(hostrcb->ioa_cfg,
2208 cfg->res_path, buffer, sizeof(buffer)),
2209 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2210 be32_to_cpu(cfg->wwid[0]),
2211 be32_to_cpu(cfg->wwid[1]));
2212 return;
2213 }
2214 }
2215 ipr_hcam_err(hostrcb, "Path element=%02X: Resource Path=%s, Link rate=%s "
2216 "WWN=%08X%08X\n", cfg->type_status,
2217 ipr_format_res_path(hostrcb->ioa_cfg,
2218 cfg->res_path, buffer, sizeof(buffer)),
2219 link_rate[cfg->link_rate & IPR_PHY_LINK_RATE_MASK],
2220 be32_to_cpu(cfg->wwid[0]), be32_to_cpu(cfg->wwid[1]));
2221}
2222
2223
2224
2225
2226
2227
2228
2229
2230
2231static void ipr_log_fabric_error(struct ipr_ioa_cfg *ioa_cfg,
2232 struct ipr_hostrcb *hostrcb)
2233{
2234 struct ipr_hostrcb_type_20_error *error;
2235 struct ipr_hostrcb_fabric_desc *fabric;
2236 struct ipr_hostrcb_config_element *cfg;
2237 int i, add_len;
2238
2239 error = &hostrcb->hcam.u.error.u.type_20_error;
2240 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2241 ipr_hcam_err(hostrcb, "%s\n", error->failure_reason);
2242
2243 add_len = be32_to_cpu(hostrcb->hcam.length) -
2244 (offsetof(struct ipr_hostrcb_error, u) +
2245 offsetof(struct ipr_hostrcb_type_20_error, desc));
2246
2247 for (i = 0, fabric = error->desc; i < error->num_entries; i++) {
2248 ipr_log_fabric_path(hostrcb, fabric);
2249 for_each_fabric_cfg(fabric, cfg)
2250 ipr_log_path_elem(hostrcb, cfg);
2251
2252 add_len -= be16_to_cpu(fabric->length);
2253 fabric = (struct ipr_hostrcb_fabric_desc *)
2254 ((unsigned long)fabric + be16_to_cpu(fabric->length));
2255 }
2256
2257 ipr_log_hex_data(ioa_cfg, (u32 *)fabric, add_len);
2258}
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268static void ipr_log_sis64_array_error(struct ipr_ioa_cfg *ioa_cfg,
2269 struct ipr_hostrcb *hostrcb)
2270{
2271 int i, num_entries;
2272 struct ipr_hostrcb_type_24_error *error;
2273 struct ipr_hostrcb64_array_data_entry *array_entry;
2274 char buffer[IPR_MAX_RES_PATH_LENGTH];
2275 const u8 zero_sn[IPR_SERIAL_NUM_LEN] = { [0 ... IPR_SERIAL_NUM_LEN-1] = '0' };
2276
2277 error = &hostrcb->hcam.u.error64.u.type_24_error;
2278
2279 ipr_err_separator;
2280
2281 ipr_err("RAID %s Array Configuration: %s\n",
2282 error->protection_level,
2283 ipr_format_res_path(ioa_cfg, error->last_res_path,
2284 buffer, sizeof(buffer)));
2285
2286 ipr_err_separator;
2287
2288 array_entry = error->array_member;
2289 num_entries = min_t(u32, error->num_entries,
2290 ARRAY_SIZE(error->array_member));
2291
2292 for (i = 0; i < num_entries; i++, array_entry++) {
2293
2294 if (!memcmp(array_entry->vpd.vpd.sn, zero_sn, IPR_SERIAL_NUM_LEN))
2295 continue;
2296
2297 if (error->exposed_mode_adn == i)
2298 ipr_err("Exposed Array Member %d:\n", i);
2299 else
2300 ipr_err("Array Member %d:\n", i);
2301
2302 ipr_err("Array Member %d:\n", i);
2303 ipr_log_ext_vpd(&array_entry->vpd);
2304 ipr_err("Current Location: %s\n",
2305 ipr_format_res_path(ioa_cfg, array_entry->res_path,
2306 buffer, sizeof(buffer)));
2307 ipr_err("Expected Location: %s\n",
2308 ipr_format_res_path(ioa_cfg,
2309 array_entry->expected_res_path,
2310 buffer, sizeof(buffer)));
2311
2312 ipr_err_separator;
2313 }
2314}
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324static void ipr_log_sis64_fabric_error(struct ipr_ioa_cfg *ioa_cfg,
2325 struct ipr_hostrcb *hostrcb)
2326{
2327 struct ipr_hostrcb_type_30_error *error;
2328 struct ipr_hostrcb64_fabric_desc *fabric;
2329 struct ipr_hostrcb64_config_element *cfg;
2330 int i, add_len;
2331
2332 error = &hostrcb->hcam.u.error64.u.type_30_error;
2333
2334 error->failure_reason[sizeof(error->failure_reason) - 1] = '\0';
2335 ipr_hcam_err(hostrcb, "%s\n", error->failure_reason);
2336
2337 add_len = be32_to_cpu(hostrcb->hcam.length) -
2338 (offsetof(struct ipr_hostrcb64_error, u) +
2339 offsetof(struct ipr_hostrcb_type_30_error, desc));
2340
2341 for (i = 0, fabric = error->desc; i < error->num_entries; i++) {
2342 ipr_log64_fabric_path(hostrcb, fabric);
2343 for_each_fabric_cfg(fabric, cfg)
2344 ipr_log64_path_elem(hostrcb, cfg);
2345
2346 add_len -= be16_to_cpu(fabric->length);
2347 fabric = (struct ipr_hostrcb64_fabric_desc *)
2348 ((unsigned long)fabric + be16_to_cpu(fabric->length));
2349 }
2350
2351 ipr_log_hex_data(ioa_cfg, (u32 *)fabric, add_len);
2352}
2353
2354
2355
2356
2357
2358
2359
2360
2361
2362static void ipr_log_generic_error(struct ipr_ioa_cfg *ioa_cfg,
2363 struct ipr_hostrcb *hostrcb)
2364{
2365 ipr_log_hex_data(ioa_cfg, hostrcb->hcam.u.raw.data,
2366 be32_to_cpu(hostrcb->hcam.length));
2367}
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380static u32 ipr_get_error(u32 ioasc)
2381{
2382 int i;
2383
2384 for (i = 0; i < ARRAY_SIZE(ipr_error_table); i++)
2385 if (ipr_error_table[i].ioasc == (ioasc & IPR_IOASC_IOASC_MASK))
2386 return i;
2387
2388 return 0;
2389}
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401static void ipr_handle_log_data(struct ipr_ioa_cfg *ioa_cfg,
2402 struct ipr_hostrcb *hostrcb)
2403{
2404 u32 ioasc;
2405 int error_index;
2406
2407 if (hostrcb->hcam.notify_type != IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY)
2408 return;
2409
2410 if (hostrcb->hcam.notifications_lost == IPR_HOST_RCB_NOTIFICATIONS_LOST)
2411 dev_err(&ioa_cfg->pdev->dev, "Error notifications lost\n");
2412
2413 if (ioa_cfg->sis64)
2414 ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc);
2415 else
2416 ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
2417
2418 if (!ioa_cfg->sis64 && (ioasc == IPR_IOASC_BUS_WAS_RESET ||
2419 ioasc == IPR_IOASC_BUS_WAS_RESET_BY_OTHER)) {
2420
2421 scsi_report_bus_reset(ioa_cfg->host,
2422 hostrcb->hcam.u.error.fd_res_addr.bus);
2423 }
2424
2425 error_index = ipr_get_error(ioasc);
2426
2427 if (!ipr_error_table[error_index].log_hcam)
2428 return;
2429
2430 ipr_hcam_err(hostrcb, "%s\n", ipr_error_table[error_index].error);
2431
2432
2433 ioa_cfg->errors_logged++;
2434
2435 if (ioa_cfg->log_level < ipr_error_table[error_index].log_hcam)
2436 return;
2437 if (be32_to_cpu(hostrcb->hcam.length) > sizeof(hostrcb->hcam.u.raw))
2438 hostrcb->hcam.length = cpu_to_be32(sizeof(hostrcb->hcam.u.raw));
2439
2440 switch (hostrcb->hcam.overlay_id) {
2441 case IPR_HOST_RCB_OVERLAY_ID_2:
2442 ipr_log_cache_error(ioa_cfg, hostrcb);
2443 break;
2444 case IPR_HOST_RCB_OVERLAY_ID_3:
2445 ipr_log_config_error(ioa_cfg, hostrcb);
2446 break;
2447 case IPR_HOST_RCB_OVERLAY_ID_4:
2448 case IPR_HOST_RCB_OVERLAY_ID_6:
2449 ipr_log_array_error(ioa_cfg, hostrcb);
2450 break;
2451 case IPR_HOST_RCB_OVERLAY_ID_7:
2452 ipr_log_dual_ioa_error(ioa_cfg, hostrcb);
2453 break;
2454 case IPR_HOST_RCB_OVERLAY_ID_12:
2455 ipr_log_enhanced_cache_error(ioa_cfg, hostrcb);
2456 break;
2457 case IPR_HOST_RCB_OVERLAY_ID_13:
2458 ipr_log_enhanced_config_error(ioa_cfg, hostrcb);
2459 break;
2460 case IPR_HOST_RCB_OVERLAY_ID_14:
2461 case IPR_HOST_RCB_OVERLAY_ID_16:
2462 ipr_log_enhanced_array_error(ioa_cfg, hostrcb);
2463 break;
2464 case IPR_HOST_RCB_OVERLAY_ID_17:
2465 ipr_log_enhanced_dual_ioa_error(ioa_cfg, hostrcb);
2466 break;
2467 case IPR_HOST_RCB_OVERLAY_ID_20:
2468 ipr_log_fabric_error(ioa_cfg, hostrcb);
2469 break;
2470 case IPR_HOST_RCB_OVERLAY_ID_23:
2471 ipr_log_sis64_config_error(ioa_cfg, hostrcb);
2472 break;
2473 case IPR_HOST_RCB_OVERLAY_ID_24:
2474 case IPR_HOST_RCB_OVERLAY_ID_26:
2475 ipr_log_sis64_array_error(ioa_cfg, hostrcb);
2476 break;
2477 case IPR_HOST_RCB_OVERLAY_ID_30:
2478 ipr_log_sis64_fabric_error(ioa_cfg, hostrcb);
2479 break;
2480 case IPR_HOST_RCB_OVERLAY_ID_1:
2481 case IPR_HOST_RCB_OVERLAY_ID_DEFAULT:
2482 default:
2483 ipr_log_generic_error(ioa_cfg, hostrcb);
2484 break;
2485 }
2486}
2487
2488
2489
2490
2491
2492
2493
2494
2495
2496
2497
2498
2499static void ipr_process_error(struct ipr_cmnd *ipr_cmd)
2500{
2501 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2502 struct ipr_hostrcb *hostrcb = ipr_cmd->u.hostrcb;
2503 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
2504 u32 fd_ioasc;
2505
2506 if (ioa_cfg->sis64)
2507 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error64.fd_ioasc);
2508 else
2509 fd_ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
2510
2511 list_del(&hostrcb->queue);
2512 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
2513
2514 if (!ioasc) {
2515 ipr_handle_log_data(ioa_cfg, hostrcb);
2516 if (fd_ioasc == IPR_IOASC_NR_IOA_RESET_REQUIRED)
2517 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_ABBREV);
2518 } else if (ioasc != IPR_IOASC_IOA_WAS_RESET) {
2519 dev_err(&ioa_cfg->pdev->dev,
2520 "Host RCB failed with IOASC: 0x%08X\n", ioasc);
2521 }
2522
2523 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_LOG_DATA, hostrcb);
2524}
2525
2526
2527
2528
2529
2530
2531
2532
2533
2534
2535
2536static void ipr_timeout(struct ipr_cmnd *ipr_cmd)
2537{
2538 unsigned long lock_flags = 0;
2539 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2540
2541 ENTER;
2542 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2543
2544 ioa_cfg->errors_logged++;
2545 dev_err(&ioa_cfg->pdev->dev,
2546 "Adapter being reset due to command timeout.\n");
2547
2548 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
2549 ioa_cfg->sdt_state = GET_DUMP;
2550
2551 if (!ioa_cfg->in_reset_reload || ioa_cfg->reset_cmd == ipr_cmd)
2552 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
2553
2554 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2555 LEAVE;
2556}
2557
2558
2559
2560
2561
2562
2563
2564
2565
2566
2567
2568static void ipr_oper_timeout(struct ipr_cmnd *ipr_cmd)
2569{
2570 unsigned long lock_flags = 0;
2571 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
2572
2573 ENTER;
2574 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2575
2576 ioa_cfg->errors_logged++;
2577 dev_err(&ioa_cfg->pdev->dev,
2578 "Adapter timed out transitioning to operational.\n");
2579
2580 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
2581 ioa_cfg->sdt_state = GET_DUMP;
2582
2583 if (!ioa_cfg->in_reset_reload || ioa_cfg->reset_cmd == ipr_cmd) {
2584 if (ipr_fastfail)
2585 ioa_cfg->reset_retries += IPR_NUM_RESET_RELOAD_RETRIES;
2586 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
2587 }
2588
2589 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2590 LEAVE;
2591}
2592
2593
2594
2595
2596
2597
2598
2599
2600static const struct ipr_ses_table_entry *
2601ipr_find_ses_entry(struct ipr_resource_entry *res)
2602{
2603 int i, j, matches;
2604 struct ipr_std_inq_vpids *vpids;
2605 const struct ipr_ses_table_entry *ste = ipr_ses_table;
2606
2607 for (i = 0; i < ARRAY_SIZE(ipr_ses_table); i++, ste++) {
2608 for (j = 0, matches = 0; j < IPR_PROD_ID_LEN; j++) {
2609 if (ste->compare_product_id_byte[j] == 'X') {
2610 vpids = &res->std_inq_data.vpids;
2611 if (vpids->product_id[j] == ste->product_id[j])
2612 matches++;
2613 else
2614 break;
2615 } else
2616 matches++;
2617 }
2618
2619 if (matches == IPR_PROD_ID_LEN)
2620 return ste;
2621 }
2622
2623 return NULL;
2624}
2625
2626
2627
2628
2629
2630
2631
2632
2633
2634
2635
2636
2637
2638static u32 ipr_get_max_scsi_speed(struct ipr_ioa_cfg *ioa_cfg, u8 bus, u8 bus_width)
2639{
2640 struct ipr_resource_entry *res;
2641 const struct ipr_ses_table_entry *ste;
2642 u32 max_xfer_rate = IPR_MAX_SCSI_RATE(bus_width);
2643
2644
2645 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
2646 if (!(IPR_IS_SES_DEVICE(res->std_inq_data)))
2647 continue;
2648
2649 if (bus != res->bus)
2650 continue;
2651
2652 if (!(ste = ipr_find_ses_entry(res)))
2653 continue;
2654
2655 max_xfer_rate = (ste->max_bus_speed_limit * 10) / (bus_width / 8);
2656 }
2657
2658 return max_xfer_rate;
2659}
2660
2661
2662
2663
2664
2665
2666
2667
2668
2669
2670
2671static int ipr_wait_iodbg_ack(struct ipr_ioa_cfg *ioa_cfg, int max_delay)
2672{
2673 volatile u32 pcii_reg;
2674 int delay = 1;
2675
2676
2677 while (delay < max_delay) {
2678 pcii_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
2679
2680 if (pcii_reg & IPR_PCII_IO_DEBUG_ACKNOWLEDGE)
2681 return 0;
2682
2683
2684 if ((delay / 1000) > MAX_UDELAY_MS)
2685 mdelay(delay / 1000);
2686 else
2687 udelay(delay);
2688
2689 delay += delay;
2690 }
2691 return -EIO;
2692}
2693
2694
2695
2696
2697
2698
2699
2700
2701
2702
2703
2704static int ipr_get_sis64_dump_data_section(struct ipr_ioa_cfg *ioa_cfg,
2705 u32 start_addr,
2706 __be32 *dest, u32 length_in_words)
2707{
2708 int i;
2709
2710 for (i = 0; i < length_in_words; i++) {
2711 writel(start_addr+(i*4), ioa_cfg->regs.dump_addr_reg);
2712 *dest = cpu_to_be32(readl(ioa_cfg->regs.dump_data_reg));
2713 dest++;
2714 }
2715
2716 return 0;
2717}
2718
2719
2720
2721
2722
2723
2724
2725
2726
2727
2728
2729static int ipr_get_ldump_data_section(struct ipr_ioa_cfg *ioa_cfg,
2730 u32 start_addr,
2731 __be32 *dest, u32 length_in_words)
2732{
2733 volatile u32 temp_pcii_reg;
2734 int i, delay = 0;
2735
2736 if (ioa_cfg->sis64)
2737 return ipr_get_sis64_dump_data_section(ioa_cfg, start_addr,
2738 dest, length_in_words);
2739
2740
2741 writel((IPR_UPROCI_RESET_ALERT | IPR_UPROCI_IO_DEBUG_ALERT),
2742 ioa_cfg->regs.set_uproc_interrupt_reg32);
2743
2744
2745 if (ipr_wait_iodbg_ack(ioa_cfg,
2746 IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC)) {
2747 dev_err(&ioa_cfg->pdev->dev,
2748 "IOA dump long data transfer timeout\n");
2749 return -EIO;
2750 }
2751
2752
2753 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2754 ioa_cfg->regs.clr_interrupt_reg);
2755
2756
2757 writel(start_addr, ioa_cfg->ioa_mailbox);
2758
2759
2760 writel(IPR_UPROCI_RESET_ALERT,
2761 ioa_cfg->regs.clr_uproc_interrupt_reg32);
2762
2763 for (i = 0; i < length_in_words; i++) {
2764
2765 if (ipr_wait_iodbg_ack(ioa_cfg,
2766 IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC)) {
2767 dev_err(&ioa_cfg->pdev->dev,
2768 "IOA dump short data transfer timeout\n");
2769 return -EIO;
2770 }
2771
2772
2773 *dest = cpu_to_be32(readl(ioa_cfg->ioa_mailbox));
2774 dest++;
2775
2776
2777 if (i < (length_in_words - 1)) {
2778
2779 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2780 ioa_cfg->regs.clr_interrupt_reg);
2781 }
2782 }
2783
2784
2785 writel(IPR_UPROCI_RESET_ALERT,
2786 ioa_cfg->regs.set_uproc_interrupt_reg32);
2787
2788 writel(IPR_UPROCI_IO_DEBUG_ALERT,
2789 ioa_cfg->regs.clr_uproc_interrupt_reg32);
2790
2791
2792 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE,
2793 ioa_cfg->regs.clr_interrupt_reg);
2794
2795
2796 while (delay < IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC) {
2797 temp_pcii_reg =
2798 readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
2799
2800 if (!(temp_pcii_reg & IPR_UPROCI_RESET_ALERT))
2801 return 0;
2802
2803 udelay(10);
2804 delay += 10;
2805 }
2806
2807 return 0;
2808}
2809
2810#ifdef CONFIG_SCSI_IPR_DUMP
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822static int ipr_sdt_copy(struct ipr_ioa_cfg *ioa_cfg,
2823 unsigned long pci_address, u32 length)
2824{
2825 int bytes_copied = 0;
2826 int cur_len, rc, rem_len, rem_page_len, max_dump_size;
2827 __be32 *page;
2828 unsigned long lock_flags = 0;
2829 struct ipr_ioa_dump *ioa_dump = &ioa_cfg->dump->ioa_dump;
2830
2831 if (ioa_cfg->sis64)
2832 max_dump_size = IPR_FMT3_MAX_IOA_DUMP_SIZE;
2833 else
2834 max_dump_size = IPR_FMT2_MAX_IOA_DUMP_SIZE;
2835
2836 while (bytes_copied < length &&
2837 (ioa_dump->hdr.len + bytes_copied) < max_dump_size) {
2838 if (ioa_dump->page_offset >= PAGE_SIZE ||
2839 ioa_dump->page_offset == 0) {
2840 page = (__be32 *)__get_free_page(GFP_ATOMIC);
2841
2842 if (!page) {
2843 ipr_trace;
2844 return bytes_copied;
2845 }
2846
2847 ioa_dump->page_offset = 0;
2848 ioa_dump->ioa_data[ioa_dump->next_page_index] = page;
2849 ioa_dump->next_page_index++;
2850 } else
2851 page = ioa_dump->ioa_data[ioa_dump->next_page_index - 1];
2852
2853 rem_len = length - bytes_copied;
2854 rem_page_len = PAGE_SIZE - ioa_dump->page_offset;
2855 cur_len = min(rem_len, rem_page_len);
2856
2857 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
2858 if (ioa_cfg->sdt_state == ABORT_DUMP) {
2859 rc = -EIO;
2860 } else {
2861 rc = ipr_get_ldump_data_section(ioa_cfg,
2862 pci_address + bytes_copied,
2863 &page[ioa_dump->page_offset / 4],
2864 (cur_len / sizeof(u32)));
2865 }
2866 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
2867
2868 if (!rc) {
2869 ioa_dump->page_offset += cur_len;
2870 bytes_copied += cur_len;
2871 } else {
2872 ipr_trace;
2873 break;
2874 }
2875 schedule();
2876 }
2877
2878 return bytes_copied;
2879}
2880
2881
2882
2883
2884
2885
2886
2887
2888static void ipr_init_dump_entry_hdr(struct ipr_dump_entry_header *hdr)
2889{
2890 hdr->eye_catcher = IPR_DUMP_EYE_CATCHER;
2891 hdr->num_elems = 1;
2892 hdr->offset = sizeof(*hdr);
2893 hdr->status = IPR_DUMP_STATUS_SUCCESS;
2894}
2895
2896
2897
2898
2899
2900
2901
2902
2903
2904static void ipr_dump_ioa_type_data(struct ipr_ioa_cfg *ioa_cfg,
2905 struct ipr_driver_dump *driver_dump)
2906{
2907 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
2908
2909 ipr_init_dump_entry_hdr(&driver_dump->ioa_type_entry.hdr);
2910 driver_dump->ioa_type_entry.hdr.len =
2911 sizeof(struct ipr_dump_ioa_type_entry) -
2912 sizeof(struct ipr_dump_entry_header);
2913 driver_dump->ioa_type_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
2914 driver_dump->ioa_type_entry.hdr.id = IPR_DUMP_DRIVER_TYPE_ID;
2915 driver_dump->ioa_type_entry.type = ioa_cfg->type;
2916 driver_dump->ioa_type_entry.fw_version = (ucode_vpd->major_release << 24) |
2917 (ucode_vpd->card_type << 16) | (ucode_vpd->minor_release[0] << 8) |
2918 ucode_vpd->minor_release[1];
2919 driver_dump->hdr.num_entries++;
2920}
2921
2922
2923
2924
2925
2926
2927
2928
2929
2930static void ipr_dump_version_data(struct ipr_ioa_cfg *ioa_cfg,
2931 struct ipr_driver_dump *driver_dump)
2932{
2933 ipr_init_dump_entry_hdr(&driver_dump->version_entry.hdr);
2934 driver_dump->version_entry.hdr.len =
2935 sizeof(struct ipr_dump_version_entry) -
2936 sizeof(struct ipr_dump_entry_header);
2937 driver_dump->version_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_ASCII;
2938 driver_dump->version_entry.hdr.id = IPR_DUMP_DRIVER_VERSION_ID;
2939 strcpy(driver_dump->version_entry.version, IPR_DRIVER_VERSION);
2940 driver_dump->hdr.num_entries++;
2941}
2942
2943
2944
2945
2946
2947
2948
2949
2950
2951static void ipr_dump_trace_data(struct ipr_ioa_cfg *ioa_cfg,
2952 struct ipr_driver_dump *driver_dump)
2953{
2954 ipr_init_dump_entry_hdr(&driver_dump->trace_entry.hdr);
2955 driver_dump->trace_entry.hdr.len =
2956 sizeof(struct ipr_dump_trace_entry) -
2957 sizeof(struct ipr_dump_entry_header);
2958 driver_dump->trace_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
2959 driver_dump->trace_entry.hdr.id = IPR_DUMP_TRACE_ID;
2960 memcpy(driver_dump->trace_entry.trace, ioa_cfg->trace, IPR_TRACE_SIZE);
2961 driver_dump->hdr.num_entries++;
2962}
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972static void ipr_dump_location_data(struct ipr_ioa_cfg *ioa_cfg,
2973 struct ipr_driver_dump *driver_dump)
2974{
2975 ipr_init_dump_entry_hdr(&driver_dump->location_entry.hdr);
2976 driver_dump->location_entry.hdr.len =
2977 sizeof(struct ipr_dump_location_entry) -
2978 sizeof(struct ipr_dump_entry_header);
2979 driver_dump->location_entry.hdr.data_type = IPR_DUMP_DATA_TYPE_ASCII;
2980 driver_dump->location_entry.hdr.id = IPR_DUMP_LOCATION_ID;
2981 strcpy(driver_dump->location_entry.location, dev_name(&ioa_cfg->pdev->dev));
2982 driver_dump->hdr.num_entries++;
2983}
2984
2985
2986
2987
2988
2989
2990
2991
2992
2993static void ipr_get_ioa_dump(struct ipr_ioa_cfg *ioa_cfg, struct ipr_dump *dump)
2994{
2995 unsigned long start_addr, sdt_word;
2996 unsigned long lock_flags = 0;
2997 struct ipr_driver_dump *driver_dump = &dump->driver_dump;
2998 struct ipr_ioa_dump *ioa_dump = &dump->ioa_dump;
2999 u32 num_entries, max_num_entries, start_off, end_off;
3000 u32 max_dump_size, bytes_to_copy, bytes_copied, rc;
3001 struct ipr_sdt *sdt;
3002 int valid = 1;
3003 int i;
3004
3005 ENTER;
3006
3007 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3008
3009 if (ioa_cfg->sdt_state != READ_DUMP) {
3010 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3011 return;
3012 }
3013
3014 if (ioa_cfg->sis64) {
3015 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3016 ssleep(IPR_DUMP_DELAY_SECONDS);
3017 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3018 }
3019
3020 start_addr = readl(ioa_cfg->ioa_mailbox);
3021
3022 if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(start_addr)) {
3023 dev_err(&ioa_cfg->pdev->dev,
3024 "Invalid dump table format: %lx\n", start_addr);
3025 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3026 return;
3027 }
3028
3029 dev_err(&ioa_cfg->pdev->dev, "Dump of IOA initiated\n");
3030
3031 driver_dump->hdr.eye_catcher = IPR_DUMP_EYE_CATCHER;
3032
3033
3034 driver_dump->hdr.len = sizeof(struct ipr_driver_dump);
3035 driver_dump->hdr.num_entries = 1;
3036 driver_dump->hdr.first_entry_offset = sizeof(struct ipr_dump_header);
3037 driver_dump->hdr.status = IPR_DUMP_STATUS_SUCCESS;
3038 driver_dump->hdr.os = IPR_DUMP_OS_LINUX;
3039 driver_dump->hdr.driver_name = IPR_DUMP_DRIVER_NAME;
3040
3041 ipr_dump_version_data(ioa_cfg, driver_dump);
3042 ipr_dump_location_data(ioa_cfg, driver_dump);
3043 ipr_dump_ioa_type_data(ioa_cfg, driver_dump);
3044 ipr_dump_trace_data(ioa_cfg, driver_dump);
3045
3046
3047 driver_dump->hdr.len += sizeof(struct ipr_dump_entry_header);
3048
3049
3050 ipr_init_dump_entry_hdr(&ioa_dump->hdr);
3051 ioa_dump->hdr.len = 0;
3052 ioa_dump->hdr.data_type = IPR_DUMP_DATA_TYPE_BINARY;
3053 ioa_dump->hdr.id = IPR_DUMP_IOA_DUMP_ID;
3054
3055
3056
3057
3058
3059 sdt = &ioa_dump->sdt;
3060
3061 if (ioa_cfg->sis64) {
3062 max_num_entries = IPR_FMT3_NUM_SDT_ENTRIES;
3063 max_dump_size = IPR_FMT3_MAX_IOA_DUMP_SIZE;
3064 } else {
3065 max_num_entries = IPR_FMT2_NUM_SDT_ENTRIES;
3066 max_dump_size = IPR_FMT2_MAX_IOA_DUMP_SIZE;
3067 }
3068
3069 bytes_to_copy = offsetof(struct ipr_sdt, entry) +
3070 (max_num_entries * sizeof(struct ipr_sdt_entry));
3071 rc = ipr_get_ldump_data_section(ioa_cfg, start_addr, (__be32 *)sdt,
3072 bytes_to_copy / sizeof(__be32));
3073
3074
3075 if (rc || ((be32_to_cpu(sdt->hdr.state) != IPR_FMT3_SDT_READY_TO_USE) &&
3076 (be32_to_cpu(sdt->hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) {
3077 dev_err(&ioa_cfg->pdev->dev,
3078 "Dump of IOA failed. Dump table not valid: %d, %X.\n",
3079 rc, be32_to_cpu(sdt->hdr.state));
3080 driver_dump->hdr.status = IPR_DUMP_STATUS_FAILED;
3081 ioa_cfg->sdt_state = DUMP_OBTAINED;
3082 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3083 return;
3084 }
3085
3086 num_entries = be32_to_cpu(sdt->hdr.num_entries_used);
3087
3088 if (num_entries > max_num_entries)
3089 num_entries = max_num_entries;
3090
3091
3092 dump->driver_dump.hdr.len += sizeof(struct ipr_sdt_header);
3093 if (ioa_cfg->sis64)
3094 dump->driver_dump.hdr.len += num_entries * sizeof(struct ipr_sdt_entry);
3095 else
3096 dump->driver_dump.hdr.len += max_num_entries * sizeof(struct ipr_sdt_entry);
3097
3098 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3099
3100 for (i = 0; i < num_entries; i++) {
3101 if (ioa_dump->hdr.len > max_dump_size) {
3102 driver_dump->hdr.status = IPR_DUMP_STATUS_QUAL_SUCCESS;
3103 break;
3104 }
3105
3106 if (sdt->entry[i].flags & IPR_SDT_VALID_ENTRY) {
3107 sdt_word = be32_to_cpu(sdt->entry[i].start_token);
3108 if (ioa_cfg->sis64)
3109 bytes_to_copy = be32_to_cpu(sdt->entry[i].end_token);
3110 else {
3111 start_off = sdt_word & IPR_FMT2_MBX_ADDR_MASK;
3112 end_off = be32_to_cpu(sdt->entry[i].end_token);
3113
3114 if (ipr_sdt_is_fmt2(sdt_word) && sdt_word)
3115 bytes_to_copy = end_off - start_off;
3116 else
3117 valid = 0;
3118 }
3119 if (valid) {
3120 if (bytes_to_copy > max_dump_size) {
3121 sdt->entry[i].flags &= ~IPR_SDT_VALID_ENTRY;
3122 continue;
3123 }
3124
3125
3126 bytes_copied = ipr_sdt_copy(ioa_cfg, sdt_word,
3127 bytes_to_copy);
3128
3129 ioa_dump->hdr.len += bytes_copied;
3130
3131 if (bytes_copied != bytes_to_copy) {
3132 driver_dump->hdr.status = IPR_DUMP_STATUS_QUAL_SUCCESS;
3133 break;
3134 }
3135 }
3136 }
3137 }
3138
3139 dev_err(&ioa_cfg->pdev->dev, "Dump of IOA completed.\n");
3140
3141
3142 driver_dump->hdr.len += ioa_dump->hdr.len;
3143 wmb();
3144 ioa_cfg->sdt_state = DUMP_OBTAINED;
3145 LEAVE;
3146}
3147
3148#else
3149#define ipr_get_ioa_dump(ioa_cfg, dump) do { } while (0)
3150#endif
3151
3152
3153
3154
3155
3156
3157
3158
3159static void ipr_release_dump(struct kref *kref)
3160{
3161 struct ipr_dump *dump = container_of(kref, struct ipr_dump, kref);
3162 struct ipr_ioa_cfg *ioa_cfg = dump->ioa_cfg;
3163 unsigned long lock_flags = 0;
3164 int i;
3165
3166 ENTER;
3167 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3168 ioa_cfg->dump = NULL;
3169 ioa_cfg->sdt_state = INACTIVE;
3170 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3171
3172 for (i = 0; i < dump->ioa_dump.next_page_index; i++)
3173 free_page((unsigned long) dump->ioa_dump.ioa_data[i]);
3174
3175 vfree(dump->ioa_dump.ioa_data);
3176 kfree(dump);
3177 LEAVE;
3178}
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188
3189
3190
3191static void ipr_worker_thread(struct work_struct *work)
3192{
3193 unsigned long lock_flags;
3194 struct ipr_resource_entry *res;
3195 struct scsi_device *sdev;
3196 struct ipr_dump *dump;
3197 struct ipr_ioa_cfg *ioa_cfg =
3198 container_of(work, struct ipr_ioa_cfg, work_q);
3199 u8 bus, target, lun;
3200 int did_work;
3201
3202 ENTER;
3203 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3204
3205 if (ioa_cfg->sdt_state == READ_DUMP) {
3206 dump = ioa_cfg->dump;
3207 if (!dump) {
3208 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3209 return;
3210 }
3211 kref_get(&dump->kref);
3212 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3213 ipr_get_ioa_dump(ioa_cfg, dump);
3214 kref_put(&dump->kref, ipr_release_dump);
3215
3216 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3217 if (ioa_cfg->sdt_state == DUMP_OBTAINED && !ioa_cfg->dump_timeout)
3218 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
3219 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3220 return;
3221 }
3222
3223restart:
3224 do {
3225 did_work = 0;
3226 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds ||
3227 !ioa_cfg->allow_ml_add_del) {
3228 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3229 return;
3230 }
3231
3232 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
3233 if (res->del_from_ml && res->sdev) {
3234 did_work = 1;
3235 sdev = res->sdev;
3236 if (!scsi_device_get(sdev)) {
3237 if (!res->add_to_ml)
3238 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
3239 else
3240 res->del_from_ml = 0;
3241 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3242 scsi_remove_device(sdev);
3243 scsi_device_put(sdev);
3244 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3245 }
3246 break;
3247 }
3248 }
3249 } while (did_work);
3250
3251 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
3252 if (res->add_to_ml) {
3253 bus = res->bus;
3254 target = res->target;
3255 lun = res->lun;
3256 res->add_to_ml = 0;
3257 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3258 scsi_add_device(ioa_cfg->host, bus, target, lun);
3259 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3260 goto restart;
3261 }
3262 }
3263
3264 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3265 kobject_uevent(&ioa_cfg->host->shost_dev.kobj, KOBJ_CHANGE);
3266 LEAVE;
3267}
3268
3269#ifdef CONFIG_SCSI_IPR_TRACE
3270
3271
3272
3273
3274
3275
3276
3277
3278
3279
3280
3281
3282static ssize_t ipr_read_trace(struct file *filp, struct kobject *kobj,
3283 struct bin_attribute *bin_attr,
3284 char *buf, loff_t off, size_t count)
3285{
3286 struct device *dev = container_of(kobj, struct device, kobj);
3287 struct Scsi_Host *shost = class_to_shost(dev);
3288 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3289 unsigned long lock_flags = 0;
3290 ssize_t ret;
3291
3292 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3293 ret = memory_read_from_buffer(buf, count, &off, ioa_cfg->trace,
3294 IPR_TRACE_SIZE);
3295 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3296
3297 return ret;
3298}
3299
3300static struct bin_attribute ipr_trace_attr = {
3301 .attr = {
3302 .name = "trace",
3303 .mode = S_IRUGO,
3304 },
3305 .size = 0,
3306 .read = ipr_read_trace,
3307};
3308#endif
3309
3310
3311
3312
3313
3314
3315
3316
3317
3318static ssize_t ipr_show_fw_version(struct device *dev,
3319 struct device_attribute *attr, char *buf)
3320{
3321 struct Scsi_Host *shost = class_to_shost(dev);
3322 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3323 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
3324 unsigned long lock_flags = 0;
3325 int len;
3326
3327 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3328 len = snprintf(buf, PAGE_SIZE, "%02X%02X%02X%02X\n",
3329 ucode_vpd->major_release, ucode_vpd->card_type,
3330 ucode_vpd->minor_release[0],
3331 ucode_vpd->minor_release[1]);
3332 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3333 return len;
3334}
3335
3336static struct device_attribute ipr_fw_version_attr = {
3337 .attr = {
3338 .name = "fw_version",
3339 .mode = S_IRUGO,
3340 },
3341 .show = ipr_show_fw_version,
3342};
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352static ssize_t ipr_show_log_level(struct device *dev,
3353 struct device_attribute *attr, char *buf)
3354{
3355 struct Scsi_Host *shost = class_to_shost(dev);
3356 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3357 unsigned long lock_flags = 0;
3358 int len;
3359
3360 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3361 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->log_level);
3362 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3363 return len;
3364}
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374static ssize_t ipr_store_log_level(struct device *dev,
3375 struct device_attribute *attr,
3376 const char *buf, size_t count)
3377{
3378 struct Scsi_Host *shost = class_to_shost(dev);
3379 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3380 unsigned long lock_flags = 0;
3381
3382 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3383 ioa_cfg->log_level = simple_strtoul(buf, NULL, 10);
3384 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3385 return strlen(buf);
3386}
3387
3388static struct device_attribute ipr_log_level_attr = {
3389 .attr = {
3390 .name = "log_level",
3391 .mode = S_IRUGO | S_IWUSR,
3392 },
3393 .show = ipr_show_log_level,
3394 .store = ipr_store_log_level
3395};
3396
3397
3398
3399
3400
3401
3402
3403
3404
3405
3406
3407
3408
3409static ssize_t ipr_store_diagnostics(struct device *dev,
3410 struct device_attribute *attr,
3411 const char *buf, size_t count)
3412{
3413 struct Scsi_Host *shost = class_to_shost(dev);
3414 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3415 unsigned long lock_flags = 0;
3416 int rc = count;
3417
3418 if (!capable(CAP_SYS_ADMIN))
3419 return -EACCES;
3420
3421 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3422 while (ioa_cfg->in_reset_reload) {
3423 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3424 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3425 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3426 }
3427
3428 ioa_cfg->errors_logged = 0;
3429 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3430
3431 if (ioa_cfg->in_reset_reload) {
3432 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3433 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3434
3435
3436 msleep(1000);
3437 } else {
3438 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3439 return -EIO;
3440 }
3441
3442 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3443 if (ioa_cfg->in_reset_reload || ioa_cfg->errors_logged)
3444 rc = -EIO;
3445 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3446
3447 return rc;
3448}
3449
3450static struct device_attribute ipr_diagnostics_attr = {
3451 .attr = {
3452 .name = "run_diagnostics",
3453 .mode = S_IWUSR,
3454 },
3455 .store = ipr_store_diagnostics
3456};
3457
3458
3459
3460
3461
3462
3463
3464
3465
3466static ssize_t ipr_show_adapter_state(struct device *dev,
3467 struct device_attribute *attr, char *buf)
3468{
3469 struct Scsi_Host *shost = class_to_shost(dev);
3470 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3471 unsigned long lock_flags = 0;
3472 int len;
3473
3474 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3475 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
3476 len = snprintf(buf, PAGE_SIZE, "offline\n");
3477 else
3478 len = snprintf(buf, PAGE_SIZE, "online\n");
3479 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3480 return len;
3481}
3482
3483
3484
3485
3486
3487
3488
3489
3490
3491
3492
3493
3494static ssize_t ipr_store_adapter_state(struct device *dev,
3495 struct device_attribute *attr,
3496 const char *buf, size_t count)
3497{
3498 struct Scsi_Host *shost = class_to_shost(dev);
3499 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3500 unsigned long lock_flags;
3501 int result = count, i;
3502
3503 if (!capable(CAP_SYS_ADMIN))
3504 return -EACCES;
3505
3506 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3507 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead &&
3508 !strncmp(buf, "online", 6)) {
3509 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
3510 spin_lock(&ioa_cfg->hrrq[i]._lock);
3511 ioa_cfg->hrrq[i].ioa_is_dead = 0;
3512 spin_unlock(&ioa_cfg->hrrq[i]._lock);
3513 }
3514 wmb();
3515 ioa_cfg->reset_retries = 0;
3516 ioa_cfg->in_ioa_bringdown = 0;
3517 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
3518 }
3519 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3520 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3521
3522 return result;
3523}
3524
3525static struct device_attribute ipr_ioa_state_attr = {
3526 .attr = {
3527 .name = "online_state",
3528 .mode = S_IRUGO | S_IWUSR,
3529 },
3530 .show = ipr_show_adapter_state,
3531 .store = ipr_store_adapter_state
3532};
3533
3534
3535
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545static ssize_t ipr_store_reset_adapter(struct device *dev,
3546 struct device_attribute *attr,
3547 const char *buf, size_t count)
3548{
3549 struct Scsi_Host *shost = class_to_shost(dev);
3550 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3551 unsigned long lock_flags;
3552 int result = count;
3553
3554 if (!capable(CAP_SYS_ADMIN))
3555 return -EACCES;
3556
3557 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3558 if (!ioa_cfg->in_reset_reload)
3559 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3560 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3561 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3562
3563 return result;
3564}
3565
3566static struct device_attribute ipr_ioa_reset_attr = {
3567 .attr = {
3568 .name = "reset_host",
3569 .mode = S_IWUSR,
3570 },
3571 .store = ipr_store_reset_adapter
3572};
3573
3574static int ipr_iopoll(struct blk_iopoll *iop, int budget);
3575
3576
3577
3578
3579
3580
3581
3582
3583static ssize_t ipr_show_iopoll_weight(struct device *dev,
3584 struct device_attribute *attr, char *buf)
3585{
3586 struct Scsi_Host *shost = class_to_shost(dev);
3587 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3588 unsigned long lock_flags = 0;
3589 int len;
3590
3591 spin_lock_irqsave(shost->host_lock, lock_flags);
3592 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->iopoll_weight);
3593 spin_unlock_irqrestore(shost->host_lock, lock_flags);
3594
3595 return len;
3596}
3597
3598
3599
3600
3601
3602
3603
3604
3605
3606static ssize_t ipr_store_iopoll_weight(struct device *dev,
3607 struct device_attribute *attr,
3608 const char *buf, size_t count)
3609{
3610 struct Scsi_Host *shost = class_to_shost(dev);
3611 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3612 unsigned long user_iopoll_weight;
3613 unsigned long lock_flags = 0;
3614 int i;
3615
3616 if (!ioa_cfg->sis64) {
3617 dev_info(&ioa_cfg->pdev->dev, "blk-iopoll not supported on this adapter\n");
3618 return -EINVAL;
3619 }
3620 if (kstrtoul(buf, 10, &user_iopoll_weight))
3621 return -EINVAL;
3622
3623 if (user_iopoll_weight > 256) {
3624 dev_info(&ioa_cfg->pdev->dev, "Invalid blk-iopoll weight. It must be less than 256\n");
3625 return -EINVAL;
3626 }
3627
3628 if (user_iopoll_weight == ioa_cfg->iopoll_weight) {
3629 dev_info(&ioa_cfg->pdev->dev, "Current blk-iopoll weight has the same weight\n");
3630 return strlen(buf);
3631 }
3632
3633 if (blk_iopoll_enabled && ioa_cfg->iopoll_weight &&
3634 ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
3635 for (i = 1; i < ioa_cfg->hrrq_num; i++)
3636 blk_iopoll_disable(&ioa_cfg->hrrq[i].iopoll);
3637 }
3638
3639 spin_lock_irqsave(shost->host_lock, lock_flags);
3640 ioa_cfg->iopoll_weight = user_iopoll_weight;
3641 if (blk_iopoll_enabled && ioa_cfg->iopoll_weight &&
3642 ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
3643 for (i = 1; i < ioa_cfg->hrrq_num; i++) {
3644 blk_iopoll_init(&ioa_cfg->hrrq[i].iopoll,
3645 ioa_cfg->iopoll_weight, ipr_iopoll);
3646 blk_iopoll_enable(&ioa_cfg->hrrq[i].iopoll);
3647 }
3648 }
3649 spin_unlock_irqrestore(shost->host_lock, lock_flags);
3650
3651 return strlen(buf);
3652}
3653
3654static struct device_attribute ipr_iopoll_weight_attr = {
3655 .attr = {
3656 .name = "iopoll_weight",
3657 .mode = S_IRUGO | S_IWUSR,
3658 },
3659 .show = ipr_show_iopoll_weight,
3660 .store = ipr_store_iopoll_weight
3661};
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672
3673static struct ipr_sglist *ipr_alloc_ucode_buffer(int buf_len)
3674{
3675 int sg_size, order, bsize_elem, num_elem, i, j;
3676 struct ipr_sglist *sglist;
3677 struct scatterlist *scatterlist;
3678 struct page *page;
3679
3680
3681 sg_size = buf_len / (IPR_MAX_SGLIST - 1);
3682
3683
3684 order = get_order(sg_size);
3685
3686
3687 bsize_elem = PAGE_SIZE * (1 << order);
3688
3689
3690 if (buf_len % bsize_elem)
3691 num_elem = (buf_len / bsize_elem) + 1;
3692 else
3693 num_elem = buf_len / bsize_elem;
3694
3695
3696 sglist = kzalloc(sizeof(struct ipr_sglist) +
3697 (sizeof(struct scatterlist) * (num_elem - 1)),
3698 GFP_KERNEL);
3699
3700 if (sglist == NULL) {
3701 ipr_trace;
3702 return NULL;
3703 }
3704
3705 scatterlist = sglist->scatterlist;
3706 sg_init_table(scatterlist, num_elem);
3707
3708 sglist->order = order;
3709 sglist->num_sg = num_elem;
3710
3711
3712 for (i = 0; i < num_elem; i++) {
3713 page = alloc_pages(GFP_KERNEL, order);
3714 if (!page) {
3715 ipr_trace;
3716
3717
3718 for (j = i - 1; j >= 0; j--)
3719 __free_pages(sg_page(&scatterlist[j]), order);
3720 kfree(sglist);
3721 return NULL;
3722 }
3723
3724 sg_set_page(&scatterlist[i], page, 0, 0);
3725 }
3726
3727 return sglist;
3728}
3729
3730
3731
3732
3733
3734
3735
3736
3737
3738
3739
3740static void ipr_free_ucode_buffer(struct ipr_sglist *sglist)
3741{
3742 int i;
3743
3744 for (i = 0; i < sglist->num_sg; i++)
3745 __free_pages(sg_page(&sglist->scatterlist[i]), sglist->order);
3746
3747 kfree(sglist);
3748}
3749
3750
3751
3752
3753
3754
3755
3756
3757
3758
3759
3760
3761
3762static int ipr_copy_ucode_buffer(struct ipr_sglist *sglist,
3763 u8 *buffer, u32 len)
3764{
3765 int bsize_elem, i, result = 0;
3766 struct scatterlist *scatterlist;
3767 void *kaddr;
3768
3769
3770 bsize_elem = PAGE_SIZE * (1 << sglist->order);
3771
3772 scatterlist = sglist->scatterlist;
3773
3774 for (i = 0; i < (len / bsize_elem); i++, buffer += bsize_elem) {
3775 struct page *page = sg_page(&scatterlist[i]);
3776
3777 kaddr = kmap(page);
3778 memcpy(kaddr, buffer, bsize_elem);
3779 kunmap(page);
3780
3781 scatterlist[i].length = bsize_elem;
3782
3783 if (result != 0) {
3784 ipr_trace;
3785 return result;
3786 }
3787 }
3788
3789 if (len % bsize_elem) {
3790 struct page *page = sg_page(&scatterlist[i]);
3791
3792 kaddr = kmap(page);
3793 memcpy(kaddr, buffer, len % bsize_elem);
3794 kunmap(page);
3795
3796 scatterlist[i].length = len % bsize_elem;
3797 }
3798
3799 sglist->buffer_len = len;
3800 return result;
3801}
3802
3803
3804
3805
3806
3807
3808
3809
3810
3811static void ipr_build_ucode_ioadl64(struct ipr_cmnd *ipr_cmd,
3812 struct ipr_sglist *sglist)
3813{
3814 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
3815 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
3816 struct scatterlist *scatterlist = sglist->scatterlist;
3817 int i;
3818
3819 ipr_cmd->dma_use_sg = sglist->num_dma_sg;
3820 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
3821 ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len);
3822
3823 ioarcb->ioadl_len =
3824 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
3825 for (i = 0; i < ipr_cmd->dma_use_sg; i++) {
3826 ioadl64[i].flags = cpu_to_be32(IPR_IOADL_FLAGS_WRITE);
3827 ioadl64[i].data_len = cpu_to_be32(sg_dma_len(&scatterlist[i]));
3828 ioadl64[i].address = cpu_to_be64(sg_dma_address(&scatterlist[i]));
3829 }
3830
3831 ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
3832}
3833
3834
3835
3836
3837
3838
3839
3840
3841
3842static void ipr_build_ucode_ioadl(struct ipr_cmnd *ipr_cmd,
3843 struct ipr_sglist *sglist)
3844{
3845 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
3846 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
3847 struct scatterlist *scatterlist = sglist->scatterlist;
3848 int i;
3849
3850 ipr_cmd->dma_use_sg = sglist->num_dma_sg;
3851 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
3852 ioarcb->data_transfer_length = cpu_to_be32(sglist->buffer_len);
3853
3854 ioarcb->ioadl_len =
3855 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
3856
3857 for (i = 0; i < ipr_cmd->dma_use_sg; i++) {
3858 ioadl[i].flags_and_data_len =
3859 cpu_to_be32(IPR_IOADL_FLAGS_WRITE | sg_dma_len(&scatterlist[i]));
3860 ioadl[i].address =
3861 cpu_to_be32(sg_dma_address(&scatterlist[i]));
3862 }
3863
3864 ioadl[i-1].flags_and_data_len |=
3865 cpu_to_be32(IPR_IOADL_FLAGS_LAST);
3866}
3867
3868
3869
3870
3871
3872
3873
3874
3875
3876
3877
3878static int ipr_update_ioa_ucode(struct ipr_ioa_cfg *ioa_cfg,
3879 struct ipr_sglist *sglist)
3880{
3881 unsigned long lock_flags;
3882
3883 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3884 while (ioa_cfg->in_reset_reload) {
3885 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3886 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3887 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3888 }
3889
3890 if (ioa_cfg->ucode_sglist) {
3891 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3892 dev_err(&ioa_cfg->pdev->dev,
3893 "Microcode download already in progress\n");
3894 return -EIO;
3895 }
3896
3897 sglist->num_dma_sg = pci_map_sg(ioa_cfg->pdev, sglist->scatterlist,
3898 sglist->num_sg, DMA_TO_DEVICE);
3899
3900 if (!sglist->num_dma_sg) {
3901 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3902 dev_err(&ioa_cfg->pdev->dev,
3903 "Failed to map microcode download buffer!\n");
3904 return -EIO;
3905 }
3906
3907 ioa_cfg->ucode_sglist = sglist;
3908 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NORMAL);
3909 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3910 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
3911
3912 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
3913 ioa_cfg->ucode_sglist = NULL;
3914 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
3915 return 0;
3916}
3917
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929static ssize_t ipr_store_update_fw(struct device *dev,
3930 struct device_attribute *attr,
3931 const char *buf, size_t count)
3932{
3933 struct Scsi_Host *shost = class_to_shost(dev);
3934 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
3935 struct ipr_ucode_image_header *image_hdr;
3936 const struct firmware *fw_entry;
3937 struct ipr_sglist *sglist;
3938 char fname[100];
3939 char *src;
3940 int len, result, dnld_size;
3941
3942 if (!capable(CAP_SYS_ADMIN))
3943 return -EACCES;
3944
3945 len = snprintf(fname, 99, "%s", buf);
3946 fname[len-1] = '\0';
3947
3948 if (request_firmware(&fw_entry, fname, &ioa_cfg->pdev->dev)) {
3949 dev_err(&ioa_cfg->pdev->dev, "Firmware file %s not found\n", fname);
3950 return -EIO;
3951 }
3952
3953 image_hdr = (struct ipr_ucode_image_header *)fw_entry->data;
3954
3955 src = (u8 *)image_hdr + be32_to_cpu(image_hdr->header_length);
3956 dnld_size = fw_entry->size - be32_to_cpu(image_hdr->header_length);
3957 sglist = ipr_alloc_ucode_buffer(dnld_size);
3958
3959 if (!sglist) {
3960 dev_err(&ioa_cfg->pdev->dev, "Microcode buffer allocation failed\n");
3961 release_firmware(fw_entry);
3962 return -ENOMEM;
3963 }
3964
3965 result = ipr_copy_ucode_buffer(sglist, src, dnld_size);
3966
3967 if (result) {
3968 dev_err(&ioa_cfg->pdev->dev,
3969 "Microcode buffer copy to DMA buffer failed\n");
3970 goto out;
3971 }
3972
3973 ipr_info("Updating microcode, please be patient. This may take up to 30 minutes.\n");
3974
3975 result = ipr_update_ioa_ucode(ioa_cfg, sglist);
3976
3977 if (!result)
3978 result = count;
3979out:
3980 ipr_free_ucode_buffer(sglist);
3981 release_firmware(fw_entry);
3982 return result;
3983}
3984
3985static struct device_attribute ipr_update_fw_attr = {
3986 .attr = {
3987 .name = "update_fw",
3988 .mode = S_IWUSR,
3989 },
3990 .store = ipr_store_update_fw
3991};
3992
3993
3994
3995
3996
3997
3998
3999
4000
4001static ssize_t ipr_show_fw_type(struct device *dev,
4002 struct device_attribute *attr, char *buf)
4003{
4004 struct Scsi_Host *shost = class_to_shost(dev);
4005 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4006 unsigned long lock_flags = 0;
4007 int len;
4008
4009 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4010 len = snprintf(buf, PAGE_SIZE, "%d\n", ioa_cfg->sis64);
4011 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4012 return len;
4013}
4014
4015static struct device_attribute ipr_ioa_fw_type_attr = {
4016 .attr = {
4017 .name = "fw_type",
4018 .mode = S_IRUGO,
4019 },
4020 .show = ipr_show_fw_type
4021};
4022
4023static struct device_attribute *ipr_ioa_attrs[] = {
4024 &ipr_fw_version_attr,
4025 &ipr_log_level_attr,
4026 &ipr_diagnostics_attr,
4027 &ipr_ioa_state_attr,
4028 &ipr_ioa_reset_attr,
4029 &ipr_update_fw_attr,
4030 &ipr_ioa_fw_type_attr,
4031 &ipr_iopoll_weight_attr,
4032 NULL,
4033};
4034
4035#ifdef CONFIG_SCSI_IPR_DUMP
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048static ssize_t ipr_read_dump(struct file *filp, struct kobject *kobj,
4049 struct bin_attribute *bin_attr,
4050 char *buf, loff_t off, size_t count)
4051{
4052 struct device *cdev = container_of(kobj, struct device, kobj);
4053 struct Scsi_Host *shost = class_to_shost(cdev);
4054 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4055 struct ipr_dump *dump;
4056 unsigned long lock_flags = 0;
4057 char *src;
4058 int len, sdt_end;
4059 size_t rc = count;
4060
4061 if (!capable(CAP_SYS_ADMIN))
4062 return -EACCES;
4063
4064 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4065 dump = ioa_cfg->dump;
4066
4067 if (ioa_cfg->sdt_state != DUMP_OBTAINED || !dump) {
4068 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4069 return 0;
4070 }
4071 kref_get(&dump->kref);
4072 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4073
4074 if (off > dump->driver_dump.hdr.len) {
4075 kref_put(&dump->kref, ipr_release_dump);
4076 return 0;
4077 }
4078
4079 if (off + count > dump->driver_dump.hdr.len) {
4080 count = dump->driver_dump.hdr.len - off;
4081 rc = count;
4082 }
4083
4084 if (count && off < sizeof(dump->driver_dump)) {
4085 if (off + count > sizeof(dump->driver_dump))
4086 len = sizeof(dump->driver_dump) - off;
4087 else
4088 len = count;
4089 src = (u8 *)&dump->driver_dump + off;
4090 memcpy(buf, src, len);
4091 buf += len;
4092 off += len;
4093 count -= len;
4094 }
4095
4096 off -= sizeof(dump->driver_dump);
4097
4098 if (ioa_cfg->sis64)
4099 sdt_end = offsetof(struct ipr_ioa_dump, sdt.entry) +
4100 (be32_to_cpu(dump->ioa_dump.sdt.hdr.num_entries_used) *
4101 sizeof(struct ipr_sdt_entry));
4102 else
4103 sdt_end = offsetof(struct ipr_ioa_dump, sdt.entry) +
4104 (IPR_FMT2_NUM_SDT_ENTRIES * sizeof(struct ipr_sdt_entry));
4105
4106 if (count && off < sdt_end) {
4107 if (off + count > sdt_end)
4108 len = sdt_end - off;
4109 else
4110 len = count;
4111 src = (u8 *)&dump->ioa_dump + off;
4112 memcpy(buf, src, len);
4113 buf += len;
4114 off += len;
4115 count -= len;
4116 }
4117
4118 off -= sdt_end;
4119
4120 while (count) {
4121 if ((off & PAGE_MASK) != ((off + count) & PAGE_MASK))
4122 len = PAGE_ALIGN(off) - off;
4123 else
4124 len = count;
4125 src = (u8 *)dump->ioa_dump.ioa_data[(off & PAGE_MASK) >> PAGE_SHIFT];
4126 src += off & ~PAGE_MASK;
4127 memcpy(buf, src, len);
4128 buf += len;
4129 off += len;
4130 count -= len;
4131 }
4132
4133 kref_put(&dump->kref, ipr_release_dump);
4134 return rc;
4135}
4136
4137
4138
4139
4140
4141
4142
4143
4144static int ipr_alloc_dump(struct ipr_ioa_cfg *ioa_cfg)
4145{
4146 struct ipr_dump *dump;
4147 __be32 **ioa_data;
4148 unsigned long lock_flags = 0;
4149
4150 dump = kzalloc(sizeof(struct ipr_dump), GFP_KERNEL);
4151
4152 if (!dump) {
4153 ipr_err("Dump memory allocation failed\n");
4154 return -ENOMEM;
4155 }
4156
4157 if (ioa_cfg->sis64)
4158 ioa_data = vmalloc(IPR_FMT3_MAX_NUM_DUMP_PAGES * sizeof(__be32 *));
4159 else
4160 ioa_data = vmalloc(IPR_FMT2_MAX_NUM_DUMP_PAGES * sizeof(__be32 *));
4161
4162 if (!ioa_data) {
4163 ipr_err("Dump memory allocation failed\n");
4164 kfree(dump);
4165 return -ENOMEM;
4166 }
4167
4168 dump->ioa_dump.ioa_data = ioa_data;
4169
4170 kref_init(&dump->kref);
4171 dump->ioa_cfg = ioa_cfg;
4172
4173 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4174
4175 if (INACTIVE != ioa_cfg->sdt_state) {
4176 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4177 vfree(dump->ioa_dump.ioa_data);
4178 kfree(dump);
4179 return 0;
4180 }
4181
4182 ioa_cfg->dump = dump;
4183 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
4184 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead && !ioa_cfg->dump_taken) {
4185 ioa_cfg->dump_taken = 1;
4186 schedule_work(&ioa_cfg->work_q);
4187 }
4188 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4189
4190 return 0;
4191}
4192
4193
4194
4195
4196
4197
4198
4199
4200static int ipr_free_dump(struct ipr_ioa_cfg *ioa_cfg)
4201{
4202 struct ipr_dump *dump;
4203 unsigned long lock_flags = 0;
4204
4205 ENTER;
4206
4207 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4208 dump = ioa_cfg->dump;
4209 if (!dump) {
4210 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4211 return 0;
4212 }
4213
4214 ioa_cfg->dump = NULL;
4215 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4216
4217 kref_put(&dump->kref, ipr_release_dump);
4218
4219 LEAVE;
4220 return 0;
4221}
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235static ssize_t ipr_write_dump(struct file *filp, struct kobject *kobj,
4236 struct bin_attribute *bin_attr,
4237 char *buf, loff_t off, size_t count)
4238{
4239 struct device *cdev = container_of(kobj, struct device, kobj);
4240 struct Scsi_Host *shost = class_to_shost(cdev);
4241 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
4242 int rc;
4243
4244 if (!capable(CAP_SYS_ADMIN))
4245 return -EACCES;
4246
4247 if (buf[0] == '1')
4248 rc = ipr_alloc_dump(ioa_cfg);
4249 else if (buf[0] == '0')
4250 rc = ipr_free_dump(ioa_cfg);
4251 else
4252 return -EINVAL;
4253
4254 if (rc)
4255 return rc;
4256 else
4257 return count;
4258}
4259
4260static struct bin_attribute ipr_dump_attr = {
4261 .attr = {
4262 .name = "dump",
4263 .mode = S_IRUSR | S_IWUSR,
4264 },
4265 .size = 0,
4266 .read = ipr_read_dump,
4267 .write = ipr_write_dump
4268};
4269#else
4270static int ipr_free_dump(struct ipr_ioa_cfg *ioa_cfg) { return 0; };
4271#endif
4272
4273
4274
4275
4276
4277
4278
4279
4280
4281
4282static int ipr_change_queue_depth(struct scsi_device *sdev, int qdepth,
4283 int reason)
4284{
4285 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4286 struct ipr_resource_entry *res;
4287 unsigned long lock_flags = 0;
4288
4289 if (reason != SCSI_QDEPTH_DEFAULT)
4290 return -EOPNOTSUPP;
4291
4292 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4293 res = (struct ipr_resource_entry *)sdev->hostdata;
4294
4295 if (res && ipr_is_gata(res) && qdepth > IPR_MAX_CMD_PER_ATA_LUN)
4296 qdepth = IPR_MAX_CMD_PER_ATA_LUN;
4297 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4298
4299 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
4300 return sdev->queue_depth;
4301}
4302
4303
4304
4305
4306
4307
4308
4309
4310
4311static int ipr_change_queue_type(struct scsi_device *sdev, int tag_type)
4312{
4313 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4314 struct ipr_resource_entry *res;
4315 unsigned long lock_flags = 0;
4316
4317 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4318 res = (struct ipr_resource_entry *)sdev->hostdata;
4319
4320 if (res) {
4321 if (ipr_is_gscsi(res) && sdev->tagged_supported) {
4322
4323
4324
4325
4326 scsi_set_tag_type(sdev, tag_type);
4327
4328 if (tag_type)
4329 scsi_activate_tcq(sdev, sdev->queue_depth);
4330 else
4331 scsi_deactivate_tcq(sdev, sdev->queue_depth);
4332 } else
4333 tag_type = 0;
4334 } else
4335 tag_type = 0;
4336
4337 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4338 return tag_type;
4339}
4340
4341
4342
4343
4344
4345
4346
4347
4348
4349
4350static ssize_t ipr_show_adapter_handle(struct device *dev, struct device_attribute *attr, char *buf)
4351{
4352 struct scsi_device *sdev = to_scsi_device(dev);
4353 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4354 struct ipr_resource_entry *res;
4355 unsigned long lock_flags = 0;
4356 ssize_t len = -ENXIO;
4357
4358 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4359 res = (struct ipr_resource_entry *)sdev->hostdata;
4360 if (res)
4361 len = snprintf(buf, PAGE_SIZE, "%08X\n", res->res_handle);
4362 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4363 return len;
4364}
4365
4366static struct device_attribute ipr_adapter_handle_attr = {
4367 .attr = {
4368 .name = "adapter_handle",
4369 .mode = S_IRUSR,
4370 },
4371 .show = ipr_show_adapter_handle
4372};
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382
4383
4384static ssize_t ipr_show_resource_path(struct device *dev, struct device_attribute *attr, char *buf)
4385{
4386 struct scsi_device *sdev = to_scsi_device(dev);
4387 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4388 struct ipr_resource_entry *res;
4389 unsigned long lock_flags = 0;
4390 ssize_t len = -ENXIO;
4391 char buffer[IPR_MAX_RES_PATH_LENGTH];
4392
4393 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4394 res = (struct ipr_resource_entry *)sdev->hostdata;
4395 if (res && ioa_cfg->sis64)
4396 len = snprintf(buf, PAGE_SIZE, "%s\n",
4397 __ipr_format_res_path(res->res_path, buffer,
4398 sizeof(buffer)));
4399 else if (res)
4400 len = snprintf(buf, PAGE_SIZE, "%d:%d:%d:%d\n", ioa_cfg->host->host_no,
4401 res->bus, res->target, res->lun);
4402
4403 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4404 return len;
4405}
4406
4407static struct device_attribute ipr_resource_path_attr = {
4408 .attr = {
4409 .name = "resource_path",
4410 .mode = S_IRUGO,
4411 },
4412 .show = ipr_show_resource_path
4413};
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424static ssize_t ipr_show_device_id(struct device *dev, struct device_attribute *attr, char *buf)
4425{
4426 struct scsi_device *sdev = to_scsi_device(dev);
4427 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4428 struct ipr_resource_entry *res;
4429 unsigned long lock_flags = 0;
4430 ssize_t len = -ENXIO;
4431
4432 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4433 res = (struct ipr_resource_entry *)sdev->hostdata;
4434 if (res && ioa_cfg->sis64)
4435 len = snprintf(buf, PAGE_SIZE, "0x%llx\n", res->dev_id);
4436 else if (res)
4437 len = snprintf(buf, PAGE_SIZE, "0x%llx\n", res->lun_wwn);
4438
4439 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4440 return len;
4441}
4442
4443static struct device_attribute ipr_device_id_attr = {
4444 .attr = {
4445 .name = "device_id",
4446 .mode = S_IRUGO,
4447 },
4448 .show = ipr_show_device_id
4449};
4450
4451
4452
4453
4454
4455
4456
4457
4458
4459
4460static ssize_t ipr_show_resource_type(struct device *dev, struct device_attribute *attr, char *buf)
4461{
4462 struct scsi_device *sdev = to_scsi_device(dev);
4463 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)sdev->host->hostdata;
4464 struct ipr_resource_entry *res;
4465 unsigned long lock_flags = 0;
4466 ssize_t len = -ENXIO;
4467
4468 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4469 res = (struct ipr_resource_entry *)sdev->hostdata;
4470
4471 if (res)
4472 len = snprintf(buf, PAGE_SIZE, "%x\n", res->type);
4473
4474 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4475 return len;
4476}
4477
4478static struct device_attribute ipr_resource_type_attr = {
4479 .attr = {
4480 .name = "resource_type",
4481 .mode = S_IRUGO,
4482 },
4483 .show = ipr_show_resource_type
4484};
4485
4486static struct device_attribute *ipr_dev_attrs[] = {
4487 &ipr_adapter_handle_attr,
4488 &ipr_resource_path_attr,
4489 &ipr_device_id_attr,
4490 &ipr_resource_type_attr,
4491 NULL,
4492};
4493
4494
4495
4496
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508static int ipr_biosparam(struct scsi_device *sdev,
4509 struct block_device *block_device,
4510 sector_t capacity, int *parm)
4511{
4512 int heads, sectors;
4513 sector_t cylinders;
4514
4515 heads = 128;
4516 sectors = 32;
4517
4518 cylinders = capacity;
4519 sector_div(cylinders, (128 * 32));
4520
4521
4522 parm[0] = heads;
4523 parm[1] = sectors;
4524 parm[2] = cylinders;
4525
4526 return 0;
4527}
4528
4529
4530
4531
4532
4533
4534
4535
4536static struct ipr_resource_entry *ipr_find_starget(struct scsi_target *starget)
4537{
4538 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4539 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4540 struct ipr_resource_entry *res;
4541
4542 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
4543 if ((res->bus == starget->channel) &&
4544 (res->target == starget->id)) {
4545 return res;
4546 }
4547 }
4548
4549 return NULL;
4550}
4551
4552static struct ata_port_info sata_port_info;
4553
4554
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564static int ipr_target_alloc(struct scsi_target *starget)
4565{
4566 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4567 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4568 struct ipr_sata_port *sata_port;
4569 struct ata_port *ap;
4570 struct ipr_resource_entry *res;
4571 unsigned long lock_flags;
4572
4573 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4574 res = ipr_find_starget(starget);
4575 starget->hostdata = NULL;
4576
4577 if (res && ipr_is_gata(res)) {
4578 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4579 sata_port = kzalloc(sizeof(*sata_port), GFP_KERNEL);
4580 if (!sata_port)
4581 return -ENOMEM;
4582
4583 ap = ata_sas_port_alloc(&ioa_cfg->ata_host, &sata_port_info, shost);
4584 if (ap) {
4585 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4586 sata_port->ioa_cfg = ioa_cfg;
4587 sata_port->ap = ap;
4588 sata_port->res = res;
4589
4590 res->sata_port = sata_port;
4591 ap->private_data = sata_port;
4592 starget->hostdata = sata_port;
4593 } else {
4594 kfree(sata_port);
4595 return -ENOMEM;
4596 }
4597 }
4598 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4599
4600 return 0;
4601}
4602
4603
4604
4605
4606
4607
4608
4609
4610
4611static void ipr_target_destroy(struct scsi_target *starget)
4612{
4613 struct ipr_sata_port *sata_port = starget->hostdata;
4614 struct Scsi_Host *shost = dev_to_shost(&starget->dev);
4615 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) shost->hostdata;
4616
4617 if (ioa_cfg->sis64) {
4618 if (!ipr_find_starget(starget)) {
4619 if (starget->channel == IPR_ARRAY_VIRTUAL_BUS)
4620 clear_bit(starget->id, ioa_cfg->array_ids);
4621 else if (starget->channel == IPR_VSET_VIRTUAL_BUS)
4622 clear_bit(starget->id, ioa_cfg->vset_ids);
4623 else if (starget->channel == 0)
4624 clear_bit(starget->id, ioa_cfg->target_ids);
4625 }
4626 }
4627
4628 if (sata_port) {
4629 starget->hostdata = NULL;
4630 ata_sas_port_destroy(sata_port->ap);
4631 kfree(sata_port);
4632 }
4633}
4634
4635
4636
4637
4638
4639
4640
4641
4642static struct ipr_resource_entry *ipr_find_sdev(struct scsi_device *sdev)
4643{
4644 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4645 struct ipr_resource_entry *res;
4646
4647 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
4648 if ((res->bus == sdev->channel) &&
4649 (res->target == sdev->id) &&
4650 (res->lun == sdev->lun))
4651 return res;
4652 }
4653
4654 return NULL;
4655}
4656
4657
4658
4659
4660
4661
4662
4663
4664static void ipr_slave_destroy(struct scsi_device *sdev)
4665{
4666 struct ipr_resource_entry *res;
4667 struct ipr_ioa_cfg *ioa_cfg;
4668 unsigned long lock_flags = 0;
4669
4670 ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4671
4672 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4673 res = (struct ipr_resource_entry *) sdev->hostdata;
4674 if (res) {
4675 if (res->sata_port)
4676 res->sata_port->ap->link.device[0].class = ATA_DEV_NONE;
4677 sdev->hostdata = NULL;
4678 res->sdev = NULL;
4679 res->sata_port = NULL;
4680 }
4681 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4682}
4683
4684
4685
4686
4687
4688
4689
4690
4691
4692
4693static int ipr_slave_configure(struct scsi_device *sdev)
4694{
4695 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4696 struct ipr_resource_entry *res;
4697 struct ata_port *ap = NULL;
4698 unsigned long lock_flags = 0;
4699 char buffer[IPR_MAX_RES_PATH_LENGTH];
4700
4701 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4702 res = sdev->hostdata;
4703 if (res) {
4704 if (ipr_is_af_dasd_device(res))
4705 sdev->type = TYPE_RAID;
4706 if (ipr_is_af_dasd_device(res) || ipr_is_ioa_resource(res)) {
4707 sdev->scsi_level = 4;
4708 sdev->no_uld_attach = 1;
4709 }
4710 if (ipr_is_vset_device(res)) {
4711 blk_queue_rq_timeout(sdev->request_queue,
4712 IPR_VSET_RW_TIMEOUT);
4713 blk_queue_max_hw_sectors(sdev->request_queue, IPR_VSET_MAX_SECTORS);
4714 }
4715 if (ipr_is_gata(res) && res->sata_port)
4716 ap = res->sata_port->ap;
4717 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4718
4719 if (ap) {
4720 scsi_adjust_queue_depth(sdev, 0, IPR_MAX_CMD_PER_ATA_LUN);
4721 ata_sas_slave_configure(sdev, ap);
4722 } else
4723 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
4724 if (ioa_cfg->sis64)
4725 sdev_printk(KERN_INFO, sdev, "Resource path: %s\n",
4726 ipr_format_res_path(ioa_cfg,
4727 res->res_path, buffer, sizeof(buffer)));
4728 return 0;
4729 }
4730 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4731 return 0;
4732}
4733
4734
4735
4736
4737
4738
4739
4740
4741
4742
4743
4744static int ipr_ata_slave_alloc(struct scsi_device *sdev)
4745{
4746 struct ipr_sata_port *sata_port = NULL;
4747 int rc = -ENXIO;
4748
4749 ENTER;
4750 if (sdev->sdev_target)
4751 sata_port = sdev->sdev_target->hostdata;
4752 if (sata_port) {
4753 rc = ata_sas_port_init(sata_port->ap);
4754 if (rc == 0)
4755 rc = ata_sas_sync_probe(sata_port->ap);
4756 }
4757
4758 if (rc)
4759 ipr_slave_destroy(sdev);
4760
4761 LEAVE;
4762 return rc;
4763}
4764
4765
4766
4767
4768
4769
4770
4771
4772
4773
4774
4775
4776
4777static int ipr_slave_alloc(struct scsi_device *sdev)
4778{
4779 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *) sdev->host->hostdata;
4780 struct ipr_resource_entry *res;
4781 unsigned long lock_flags;
4782 int rc = -ENXIO;
4783
4784 sdev->hostdata = NULL;
4785
4786 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4787
4788 res = ipr_find_sdev(sdev);
4789 if (res) {
4790 res->sdev = sdev;
4791 res->add_to_ml = 0;
4792 res->in_erp = 0;
4793 sdev->hostdata = res;
4794 if (!ipr_is_naca_model(res))
4795 res->needs_sync_complete = 1;
4796 rc = 0;
4797 if (ipr_is_gata(res)) {
4798 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4799 return ipr_ata_slave_alloc(sdev);
4800 }
4801 }
4802
4803 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4804
4805 return rc;
4806}
4807
4808static int ipr_eh_host_reset(struct scsi_cmnd *cmd)
4809{
4810 struct ipr_ioa_cfg *ioa_cfg;
4811 unsigned long lock_flags = 0;
4812 int rc = SUCCESS;
4813
4814 ENTER;
4815 ioa_cfg = (struct ipr_ioa_cfg *) cmd->device->host->hostdata;
4816 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4817
4818 if (!ioa_cfg->in_reset_reload && !ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
4819 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_ABBREV);
4820 dev_err(&ioa_cfg->pdev->dev,
4821 "Adapter being reset as a result of error recovery.\n");
4822
4823 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
4824 ioa_cfg->sdt_state = GET_DUMP;
4825 }
4826
4827 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4828 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
4829 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4830
4831
4832
4833 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
4834 ipr_trace;
4835 rc = FAILED;
4836 }
4837
4838 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4839 LEAVE;
4840 return rc;
4841}
4842
4843
4844
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854
4855
4856
4857static int ipr_device_reset(struct ipr_ioa_cfg *ioa_cfg,
4858 struct ipr_resource_entry *res)
4859{
4860 struct ipr_cmnd *ipr_cmd;
4861 struct ipr_ioarcb *ioarcb;
4862 struct ipr_cmd_pkt *cmd_pkt;
4863 struct ipr_ioarcb_ata_regs *regs;
4864 u32 ioasc;
4865
4866 ENTER;
4867 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
4868 ioarcb = &ipr_cmd->ioarcb;
4869 cmd_pkt = &ioarcb->cmd_pkt;
4870
4871 if (ipr_cmd->ioa_cfg->sis64) {
4872 regs = &ipr_cmd->i.ata_ioadl.regs;
4873 ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb));
4874 } else
4875 regs = &ioarcb->u.add_data.u.regs;
4876
4877 ioarcb->res_handle = res->res_handle;
4878 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
4879 cmd_pkt->cdb[0] = IPR_RESET_DEVICE;
4880 if (ipr_is_gata(res)) {
4881 cmd_pkt->cdb[2] = IPR_ATA_PHY_RESET;
4882 ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(regs->flags));
4883 regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION;
4884 }
4885
4886 ipr_send_blocking_cmd(ipr_cmd, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
4887 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
4888 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
4889 if (ipr_is_gata(res) && res->sata_port && ioasc != IPR_IOASC_IOA_WAS_RESET) {
4890 if (ipr_cmd->ioa_cfg->sis64)
4891 memcpy(&res->sata_port->ioasa, &ipr_cmd->s.ioasa64.u.gata,
4892 sizeof(struct ipr_ioasa_gata));
4893 else
4894 memcpy(&res->sata_port->ioasa, &ipr_cmd->s.ioasa.u.gata,
4895 sizeof(struct ipr_ioasa_gata));
4896 }
4897
4898 LEAVE;
4899 return IPR_IOASC_SENSE_KEY(ioasc) ? -EIO : 0;
4900}
4901
4902
4903
4904
4905
4906
4907
4908
4909
4910
4911
4912static int ipr_sata_reset(struct ata_link *link, unsigned int *classes,
4913 unsigned long deadline)
4914{
4915 struct ipr_sata_port *sata_port = link->ap->private_data;
4916 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
4917 struct ipr_resource_entry *res;
4918 unsigned long lock_flags = 0;
4919 int rc = -ENXIO;
4920
4921 ENTER;
4922 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4923 while (ioa_cfg->in_reset_reload) {
4924 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4925 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
4926 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
4927 }
4928
4929 res = sata_port->res;
4930 if (res) {
4931 rc = ipr_device_reset(ioa_cfg, res);
4932 *classes = res->ata_class;
4933 }
4934
4935 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
4936 LEAVE;
4937 return rc;
4938}
4939
4940
4941
4942
4943
4944
4945
4946
4947
4948
4949
4950
4951static int __ipr_eh_dev_reset(struct scsi_cmnd *scsi_cmd)
4952{
4953 struct ipr_cmnd *ipr_cmd;
4954 struct ipr_ioa_cfg *ioa_cfg;
4955 struct ipr_resource_entry *res;
4956 struct ata_port *ap;
4957 int rc = 0;
4958 struct ipr_hrr_queue *hrrq;
4959
4960 ENTER;
4961 ioa_cfg = (struct ipr_ioa_cfg *) scsi_cmd->device->host->hostdata;
4962 res = scsi_cmd->device->hostdata;
4963
4964 if (!res)
4965 return FAILED;
4966
4967
4968
4969
4970
4971
4972 if (ioa_cfg->in_reset_reload)
4973 return FAILED;
4974 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
4975 return FAILED;
4976
4977 for_each_hrrq(hrrq, ioa_cfg) {
4978 spin_lock(&hrrq->_lock);
4979 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
4980 if (ipr_cmd->ioarcb.res_handle == res->res_handle) {
4981 if (ipr_cmd->scsi_cmd)
4982 ipr_cmd->done = ipr_scsi_eh_done;
4983 if (ipr_cmd->qc)
4984 ipr_cmd->done = ipr_sata_eh_done;
4985 if (ipr_cmd->qc &&
4986 !(ipr_cmd->qc->flags & ATA_QCFLAG_FAILED)) {
4987 ipr_cmd->qc->err_mask |= AC_ERR_TIMEOUT;
4988 ipr_cmd->qc->flags |= ATA_QCFLAG_FAILED;
4989 }
4990 }
4991 }
4992 spin_unlock(&hrrq->_lock);
4993 }
4994 res->resetting_device = 1;
4995 scmd_printk(KERN_ERR, scsi_cmd, "Resetting device\n");
4996
4997 if (ipr_is_gata(res) && res->sata_port) {
4998 ap = res->sata_port->ap;
4999 spin_unlock_irq(scsi_cmd->device->host->host_lock);
5000 ata_std_error_handler(ap);
5001 spin_lock_irq(scsi_cmd->device->host->host_lock);
5002
5003 for_each_hrrq(hrrq, ioa_cfg) {
5004 spin_lock(&hrrq->_lock);
5005 list_for_each_entry(ipr_cmd,
5006 &hrrq->hrrq_pending_q, queue) {
5007 if (ipr_cmd->ioarcb.res_handle ==
5008 res->res_handle) {
5009 rc = -EIO;
5010 break;
5011 }
5012 }
5013 spin_unlock(&hrrq->_lock);
5014 }
5015 } else
5016 rc = ipr_device_reset(ioa_cfg, res);
5017 res->resetting_device = 0;
5018
5019 LEAVE;
5020 return rc ? FAILED : SUCCESS;
5021}
5022
5023static int ipr_eh_dev_reset(struct scsi_cmnd *cmd)
5024{
5025 int rc;
5026
5027 spin_lock_irq(cmd->device->host->host_lock);
5028 rc = __ipr_eh_dev_reset(cmd);
5029 spin_unlock_irq(cmd->device->host->host_lock);
5030
5031 return rc;
5032}
5033
5034
5035
5036
5037
5038
5039
5040
5041
5042
5043static void ipr_bus_reset_done(struct ipr_cmnd *ipr_cmd)
5044{
5045 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
5046 struct ipr_resource_entry *res;
5047
5048 ENTER;
5049 if (!ioa_cfg->sis64)
5050 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
5051 if (res->res_handle == ipr_cmd->ioarcb.res_handle) {
5052 scsi_report_bus_reset(ioa_cfg->host, res->bus);
5053 break;
5054 }
5055 }
5056
5057
5058
5059
5060
5061 if (ipr_cmd->sibling->sibling)
5062 ipr_cmd->sibling->sibling = NULL;
5063 else
5064 ipr_cmd->sibling->done(ipr_cmd->sibling);
5065
5066 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5067 LEAVE;
5068}
5069
5070
5071
5072
5073
5074
5075
5076
5077
5078
5079
5080
5081static void ipr_abort_timeout(struct ipr_cmnd *ipr_cmd)
5082{
5083 struct ipr_cmnd *reset_cmd;
5084 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
5085 struct ipr_cmd_pkt *cmd_pkt;
5086 unsigned long lock_flags = 0;
5087
5088 ENTER;
5089 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
5090 if (ipr_cmd->completion.done || ioa_cfg->in_reset_reload) {
5091 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5092 return;
5093 }
5094
5095 sdev_printk(KERN_ERR, ipr_cmd->u.sdev, "Abort timed out. Resetting bus.\n");
5096 reset_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5097 ipr_cmd->sibling = reset_cmd;
5098 reset_cmd->sibling = ipr_cmd;
5099 reset_cmd->ioarcb.res_handle = ipr_cmd->ioarcb.res_handle;
5100 cmd_pkt = &reset_cmd->ioarcb.cmd_pkt;
5101 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5102 cmd_pkt->cdb[0] = IPR_RESET_DEVICE;
5103 cmd_pkt->cdb[2] = IPR_RESET_TYPE_SELECT | IPR_BUS_RESET;
5104
5105 ipr_do_req(reset_cmd, ipr_bus_reset_done, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
5106 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
5107 LEAVE;
5108}
5109
5110
5111
5112
5113
5114
5115
5116
5117
5118
5119static int ipr_cancel_op(struct scsi_cmnd *scsi_cmd)
5120{
5121 struct ipr_cmnd *ipr_cmd;
5122 struct ipr_ioa_cfg *ioa_cfg;
5123 struct ipr_resource_entry *res;
5124 struct ipr_cmd_pkt *cmd_pkt;
5125 u32 ioasc, int_reg;
5126 int op_found = 0;
5127 struct ipr_hrr_queue *hrrq;
5128
5129 ENTER;
5130 ioa_cfg = (struct ipr_ioa_cfg *)scsi_cmd->device->host->hostdata;
5131 res = scsi_cmd->device->hostdata;
5132
5133
5134
5135
5136
5137 if (ioa_cfg->in_reset_reload ||
5138 ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
5139 return FAILED;
5140 if (!res)
5141 return FAILED;
5142
5143
5144
5145
5146
5147
5148 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
5149
5150 if (!ipr_is_gscsi(res))
5151 return FAILED;
5152
5153 for_each_hrrq(hrrq, ioa_cfg) {
5154 spin_lock(&hrrq->_lock);
5155 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
5156 if (ipr_cmd->scsi_cmd == scsi_cmd) {
5157 ipr_cmd->done = ipr_scsi_eh_done;
5158 op_found = 1;
5159 break;
5160 }
5161 }
5162 spin_unlock(&hrrq->_lock);
5163 }
5164
5165 if (!op_found)
5166 return SUCCESS;
5167
5168 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
5169 ipr_cmd->ioarcb.res_handle = res->res_handle;
5170 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
5171 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5172 cmd_pkt->cdb[0] = IPR_CANCEL_ALL_REQUESTS;
5173 ipr_cmd->u.sdev = scsi_cmd->device;
5174
5175 scmd_printk(KERN_ERR, scsi_cmd, "Aborting command: %02X\n",
5176 scsi_cmd->cmnd[0]);
5177 ipr_send_blocking_cmd(ipr_cmd, ipr_abort_timeout, IPR_CANCEL_ALL_TIMEOUT);
5178 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5179
5180
5181
5182
5183
5184 if (ioasc == IPR_IOASC_BUS_WAS_RESET || ioasc == IPR_IOASC_SYNC_REQUIRED) {
5185 ioasc = 0;
5186 ipr_trace;
5187 }
5188
5189 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5190 if (!ipr_is_naca_model(res))
5191 res->needs_sync_complete = 1;
5192
5193 LEAVE;
5194 return IPR_IOASC_SENSE_KEY(ioasc) ? FAILED : SUCCESS;
5195}
5196
5197
5198
5199
5200
5201
5202
5203
5204static int ipr_eh_abort(struct scsi_cmnd *scsi_cmd)
5205{
5206 unsigned long flags;
5207 int rc;
5208
5209 ENTER;
5210
5211 spin_lock_irqsave(scsi_cmd->device->host->host_lock, flags);
5212 rc = ipr_cancel_op(scsi_cmd);
5213 spin_unlock_irqrestore(scsi_cmd->device->host->host_lock, flags);
5214
5215 LEAVE;
5216 return rc;
5217}
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227static irqreturn_t ipr_handle_other_interrupt(struct ipr_ioa_cfg *ioa_cfg,
5228 u32 int_reg)
5229{
5230 irqreturn_t rc = IRQ_HANDLED;
5231 u32 int_mask_reg;
5232
5233 int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
5234 int_reg &= ~int_mask_reg;
5235
5236
5237
5238
5239 if ((int_reg & IPR_PCII_OPER_INTERRUPTS) == 0) {
5240 if (ioa_cfg->sis64) {
5241 int_mask_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
5242 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
5243 if (int_reg & IPR_PCII_IPL_STAGE_CHANGE) {
5244
5245
5246 writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.clr_interrupt_reg);
5247 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg) & ~int_mask_reg;
5248 list_del(&ioa_cfg->reset_cmd->queue);
5249 del_timer(&ioa_cfg->reset_cmd->timer);
5250 ipr_reset_ioa_job(ioa_cfg->reset_cmd);
5251 return IRQ_HANDLED;
5252 }
5253 }
5254
5255 return IRQ_NONE;
5256 }
5257
5258 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
5259
5260 writel(IPR_PCII_IOA_TRANS_TO_OPER, ioa_cfg->regs.set_interrupt_mask_reg);
5261
5262
5263 writel(IPR_PCII_IOA_TRANS_TO_OPER, ioa_cfg->regs.clr_interrupt_reg);
5264 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
5265
5266 list_del(&ioa_cfg->reset_cmd->queue);
5267 del_timer(&ioa_cfg->reset_cmd->timer);
5268 ipr_reset_ioa_job(ioa_cfg->reset_cmd);
5269 } else if ((int_reg & IPR_PCII_HRRQ_UPDATED) == int_reg) {
5270 if (ioa_cfg->clear_isr) {
5271 if (ipr_debug && printk_ratelimit())
5272 dev_err(&ioa_cfg->pdev->dev,
5273 "Spurious interrupt detected. 0x%08X\n", int_reg);
5274 writel(IPR_PCII_HRRQ_UPDATED, ioa_cfg->regs.clr_interrupt_reg32);
5275 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5276 return IRQ_NONE;
5277 }
5278 } else {
5279 if (int_reg & IPR_PCII_IOA_UNIT_CHECKED)
5280 ioa_cfg->ioa_unit_checked = 1;
5281 else if (int_reg & IPR_PCII_NO_HOST_RRQ)
5282 dev_err(&ioa_cfg->pdev->dev,
5283 "No Host RRQ. 0x%08X\n", int_reg);
5284 else
5285 dev_err(&ioa_cfg->pdev->dev,
5286 "Permanent IOA failure. 0x%08X\n", int_reg);
5287
5288 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5289 ioa_cfg->sdt_state = GET_DUMP;
5290
5291 ipr_mask_and_clear_interrupts(ioa_cfg, ~0);
5292 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
5293 }
5294
5295 return rc;
5296}
5297
5298
5299
5300
5301
5302
5303
5304
5305
5306static void ipr_isr_eh(struct ipr_ioa_cfg *ioa_cfg, char *msg, u16 number)
5307{
5308 ioa_cfg->errors_logged++;
5309 dev_err(&ioa_cfg->pdev->dev, "%s %d\n", msg, number);
5310
5311 if (WAIT_FOR_DUMP == ioa_cfg->sdt_state)
5312 ioa_cfg->sdt_state = GET_DUMP;
5313
5314 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
5315}
5316
5317static int ipr_process_hrrq(struct ipr_hrr_queue *hrr_queue, int budget,
5318 struct list_head *doneq)
5319{
5320 u32 ioasc;
5321 u16 cmd_index;
5322 struct ipr_cmnd *ipr_cmd;
5323 struct ipr_ioa_cfg *ioa_cfg = hrr_queue->ioa_cfg;
5324 int num_hrrq = 0;
5325
5326
5327 if (!hrr_queue->allow_interrupts)
5328 return 0;
5329
5330 while ((be32_to_cpu(*hrr_queue->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5331 hrr_queue->toggle_bit) {
5332
5333 cmd_index = (be32_to_cpu(*hrr_queue->hrrq_curr) &
5334 IPR_HRRQ_REQ_RESP_HANDLE_MASK) >>
5335 IPR_HRRQ_REQ_RESP_HANDLE_SHIFT;
5336
5337 if (unlikely(cmd_index > hrr_queue->max_cmd_id ||
5338 cmd_index < hrr_queue->min_cmd_id)) {
5339 ipr_isr_eh(ioa_cfg,
5340 "Invalid response handle from IOA: ",
5341 cmd_index);
5342 break;
5343 }
5344
5345 ipr_cmd = ioa_cfg->ipr_cmnd_list[cmd_index];
5346 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5347
5348 ipr_trc_hook(ipr_cmd, IPR_TRACE_FINISH, ioasc);
5349
5350 list_move_tail(&ipr_cmd->queue, doneq);
5351
5352 if (hrr_queue->hrrq_curr < hrr_queue->hrrq_end) {
5353 hrr_queue->hrrq_curr++;
5354 } else {
5355 hrr_queue->hrrq_curr = hrr_queue->hrrq_start;
5356 hrr_queue->toggle_bit ^= 1u;
5357 }
5358 num_hrrq++;
5359 if (budget > 0 && num_hrrq >= budget)
5360 break;
5361 }
5362
5363 return num_hrrq;
5364}
5365
5366static int ipr_iopoll(struct blk_iopoll *iop, int budget)
5367{
5368 struct ipr_ioa_cfg *ioa_cfg;
5369 struct ipr_hrr_queue *hrrq;
5370 struct ipr_cmnd *ipr_cmd, *temp;
5371 unsigned long hrrq_flags;
5372 int completed_ops;
5373 LIST_HEAD(doneq);
5374
5375 hrrq = container_of(iop, struct ipr_hrr_queue, iopoll);
5376 ioa_cfg = hrrq->ioa_cfg;
5377
5378 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5379 completed_ops = ipr_process_hrrq(hrrq, budget, &doneq);
5380
5381 if (completed_ops < budget)
5382 blk_iopoll_complete(iop);
5383 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5384
5385 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5386 list_del(&ipr_cmd->queue);
5387 del_timer(&ipr_cmd->timer);
5388 ipr_cmd->fast_done(ipr_cmd);
5389 }
5390
5391 return completed_ops;
5392}
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402static irqreturn_t ipr_isr(int irq, void *devp)
5403{
5404 struct ipr_hrr_queue *hrrq = (struct ipr_hrr_queue *)devp;
5405 struct ipr_ioa_cfg *ioa_cfg = hrrq->ioa_cfg;
5406 unsigned long hrrq_flags = 0;
5407 u32 int_reg = 0;
5408 int num_hrrq = 0;
5409 int irq_none = 0;
5410 struct ipr_cmnd *ipr_cmd, *temp;
5411 irqreturn_t rc = IRQ_NONE;
5412 LIST_HEAD(doneq);
5413
5414 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5415
5416 if (!hrrq->allow_interrupts) {
5417 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5418 return IRQ_NONE;
5419 }
5420
5421 while (1) {
5422 if (ipr_process_hrrq(hrrq, -1, &doneq)) {
5423 rc = IRQ_HANDLED;
5424
5425 if (!ioa_cfg->clear_isr)
5426 break;
5427
5428
5429 num_hrrq = 0;
5430 do {
5431 writel(IPR_PCII_HRRQ_UPDATED,
5432 ioa_cfg->regs.clr_interrupt_reg32);
5433 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5434 } while (int_reg & IPR_PCII_HRRQ_UPDATED &&
5435 num_hrrq++ < IPR_MAX_HRRQ_RETRIES);
5436
5437 } else if (rc == IRQ_NONE && irq_none == 0) {
5438 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
5439 irq_none++;
5440 } else if (num_hrrq == IPR_MAX_HRRQ_RETRIES &&
5441 int_reg & IPR_PCII_HRRQ_UPDATED) {
5442 ipr_isr_eh(ioa_cfg,
5443 "Error clearing HRRQ: ", num_hrrq);
5444 rc = IRQ_HANDLED;
5445 break;
5446 } else
5447 break;
5448 }
5449
5450 if (unlikely(rc == IRQ_NONE))
5451 rc = ipr_handle_other_interrupt(ioa_cfg, int_reg);
5452
5453 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5454 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5455 list_del(&ipr_cmd->queue);
5456 del_timer(&ipr_cmd->timer);
5457 ipr_cmd->fast_done(ipr_cmd);
5458 }
5459 return rc;
5460}
5461
5462
5463
5464
5465
5466
5467
5468
5469
5470static irqreturn_t ipr_isr_mhrrq(int irq, void *devp)
5471{
5472 struct ipr_hrr_queue *hrrq = (struct ipr_hrr_queue *)devp;
5473 struct ipr_ioa_cfg *ioa_cfg = hrrq->ioa_cfg;
5474 unsigned long hrrq_flags = 0;
5475 struct ipr_cmnd *ipr_cmd, *temp;
5476 irqreturn_t rc = IRQ_NONE;
5477 LIST_HEAD(doneq);
5478
5479 spin_lock_irqsave(hrrq->lock, hrrq_flags);
5480
5481
5482 if (!hrrq->allow_interrupts) {
5483 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5484 return IRQ_NONE;
5485 }
5486
5487 if (blk_iopoll_enabled && ioa_cfg->iopoll_weight &&
5488 ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
5489 if ((be32_to_cpu(*hrrq->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5490 hrrq->toggle_bit) {
5491 if (!blk_iopoll_sched_prep(&hrrq->iopoll))
5492 blk_iopoll_sched(&hrrq->iopoll);
5493 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5494 return IRQ_HANDLED;
5495 }
5496 } else {
5497 if ((be32_to_cpu(*hrrq->hrrq_curr) & IPR_HRRQ_TOGGLE_BIT) ==
5498 hrrq->toggle_bit)
5499
5500 if (ipr_process_hrrq(hrrq, -1, &doneq))
5501 rc = IRQ_HANDLED;
5502 }
5503
5504 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
5505
5506 list_for_each_entry_safe(ipr_cmd, temp, &doneq, queue) {
5507 list_del(&ipr_cmd->queue);
5508 del_timer(&ipr_cmd->timer);
5509 ipr_cmd->fast_done(ipr_cmd);
5510 }
5511 return rc;
5512}
5513
5514
5515
5516
5517
5518
5519
5520
5521
5522static int ipr_build_ioadl64(struct ipr_ioa_cfg *ioa_cfg,
5523 struct ipr_cmnd *ipr_cmd)
5524{
5525 int i, nseg;
5526 struct scatterlist *sg;
5527 u32 length;
5528 u32 ioadl_flags = 0;
5529 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5530 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5531 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ioadl64;
5532
5533 length = scsi_bufflen(scsi_cmd);
5534 if (!length)
5535 return 0;
5536
5537 nseg = scsi_dma_map(scsi_cmd);
5538 if (nseg < 0) {
5539 if (printk_ratelimit())
5540 dev_err(&ioa_cfg->pdev->dev, "pci_map_sg failed!\n");
5541 return -1;
5542 }
5543
5544 ipr_cmd->dma_use_sg = nseg;
5545
5546 ioarcb->data_transfer_length = cpu_to_be32(length);
5547 ioarcb->ioadl_len =
5548 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
5549
5550 if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) {
5551 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
5552 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
5553 } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE)
5554 ioadl_flags = IPR_IOADL_FLAGS_READ;
5555
5556 scsi_for_each_sg(scsi_cmd, sg, ipr_cmd->dma_use_sg, i) {
5557 ioadl64[i].flags = cpu_to_be32(ioadl_flags);
5558 ioadl64[i].data_len = cpu_to_be32(sg_dma_len(sg));
5559 ioadl64[i].address = cpu_to_be64(sg_dma_address(sg));
5560 }
5561
5562 ioadl64[i-1].flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
5563 return 0;
5564}
5565
5566
5567
5568
5569
5570
5571
5572
5573
5574static int ipr_build_ioadl(struct ipr_ioa_cfg *ioa_cfg,
5575 struct ipr_cmnd *ipr_cmd)
5576{
5577 int i, nseg;
5578 struct scatterlist *sg;
5579 u32 length;
5580 u32 ioadl_flags = 0;
5581 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5582 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5583 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
5584
5585 length = scsi_bufflen(scsi_cmd);
5586 if (!length)
5587 return 0;
5588
5589 nseg = scsi_dma_map(scsi_cmd);
5590 if (nseg < 0) {
5591 dev_err(&ioa_cfg->pdev->dev, "pci_map_sg failed!\n");
5592 return -1;
5593 }
5594
5595 ipr_cmd->dma_use_sg = nseg;
5596
5597 if (scsi_cmd->sc_data_direction == DMA_TO_DEVICE) {
5598 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
5599 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
5600 ioarcb->data_transfer_length = cpu_to_be32(length);
5601 ioarcb->ioadl_len =
5602 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
5603 } else if (scsi_cmd->sc_data_direction == DMA_FROM_DEVICE) {
5604 ioadl_flags = IPR_IOADL_FLAGS_READ;
5605 ioarcb->read_data_transfer_length = cpu_to_be32(length);
5606 ioarcb->read_ioadl_len =
5607 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
5608 }
5609
5610 if (ipr_cmd->dma_use_sg <= ARRAY_SIZE(ioarcb->u.add_data.u.ioadl)) {
5611 ioadl = ioarcb->u.add_data.u.ioadl;
5612 ioarcb->write_ioadl_addr = cpu_to_be32((ipr_cmd->dma_addr) +
5613 offsetof(struct ipr_ioarcb, u.add_data));
5614 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
5615 }
5616
5617 scsi_for_each_sg(scsi_cmd, sg, ipr_cmd->dma_use_sg, i) {
5618 ioadl[i].flags_and_data_len =
5619 cpu_to_be32(ioadl_flags | sg_dma_len(sg));
5620 ioadl[i].address = cpu_to_be32(sg_dma_address(sg));
5621 }
5622
5623 ioadl[i-1].flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
5624 return 0;
5625}
5626
5627
5628
5629
5630
5631
5632
5633
5634static u8 ipr_get_task_attributes(struct scsi_cmnd *scsi_cmd)
5635{
5636 u8 tag[2];
5637 u8 rc = IPR_FLAGS_LO_UNTAGGED_TASK;
5638
5639 if (scsi_populate_tag_msg(scsi_cmd, tag)) {
5640 switch (tag[0]) {
5641 case MSG_SIMPLE_TAG:
5642 rc = IPR_FLAGS_LO_SIMPLE_TASK;
5643 break;
5644 case MSG_HEAD_TAG:
5645 rc = IPR_FLAGS_LO_HEAD_OF_Q_TASK;
5646 break;
5647 case MSG_ORDERED_TAG:
5648 rc = IPR_FLAGS_LO_ORDERED_TASK;
5649 break;
5650 };
5651 }
5652
5653 return rc;
5654}
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664
5665
5666static void ipr_erp_done(struct ipr_cmnd *ipr_cmd)
5667{
5668 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5669 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
5670 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5671
5672 if (IPR_IOASC_SENSE_KEY(ioasc) > 0) {
5673 scsi_cmd->result |= (DID_ERROR << 16);
5674 scmd_printk(KERN_ERR, scsi_cmd,
5675 "Request Sense failed with IOASC: 0x%08X\n", ioasc);
5676 } else {
5677 memcpy(scsi_cmd->sense_buffer, ipr_cmd->sense_buffer,
5678 SCSI_SENSE_BUFFERSIZE);
5679 }
5680
5681 if (res) {
5682 if (!ipr_is_naca_model(res))
5683 res->needs_sync_complete = 1;
5684 res->in_erp = 0;
5685 }
5686 scsi_dma_unmap(ipr_cmd->scsi_cmd);
5687 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
5688 scsi_cmd->scsi_done(scsi_cmd);
5689}
5690
5691
5692
5693
5694
5695
5696
5697
5698static void ipr_reinit_ipr_cmnd_for_erp(struct ipr_cmnd *ipr_cmd)
5699{
5700 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
5701 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5702 dma_addr_t dma_addr = ipr_cmd->dma_addr;
5703
5704 memset(&ioarcb->cmd_pkt, 0, sizeof(struct ipr_cmd_pkt));
5705 ioarcb->data_transfer_length = 0;
5706 ioarcb->read_data_transfer_length = 0;
5707 ioarcb->ioadl_len = 0;
5708 ioarcb->read_ioadl_len = 0;
5709 ioasa->hdr.ioasc = 0;
5710 ioasa->hdr.residual_data_len = 0;
5711
5712 if (ipr_cmd->ioa_cfg->sis64)
5713 ioarcb->u.sis64_addr_data.data_ioadl_addr =
5714 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
5715 else {
5716 ioarcb->write_ioadl_addr =
5717 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
5718 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
5719 }
5720}
5721
5722
5723
5724
5725
5726
5727
5728
5729
5730
5731
5732static void ipr_erp_request_sense(struct ipr_cmnd *ipr_cmd)
5733{
5734 struct ipr_cmd_pkt *cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
5735 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5736
5737 if (IPR_IOASC_SENSE_KEY(ioasc) > 0) {
5738 ipr_erp_done(ipr_cmd);
5739 return;
5740 }
5741
5742 ipr_reinit_ipr_cmnd_for_erp(ipr_cmd);
5743
5744 cmd_pkt->request_type = IPR_RQTYPE_SCSICDB;
5745 cmd_pkt->cdb[0] = REQUEST_SENSE;
5746 cmd_pkt->cdb[4] = SCSI_SENSE_BUFFERSIZE;
5747 cmd_pkt->flags_hi |= IPR_FLAGS_HI_SYNC_OVERRIDE;
5748 cmd_pkt->flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
5749 cmd_pkt->timeout = cpu_to_be16(IPR_REQUEST_SENSE_TIMEOUT / HZ);
5750
5751 ipr_init_ioadl(ipr_cmd, ipr_cmd->sense_buffer_dma,
5752 SCSI_SENSE_BUFFERSIZE, IPR_IOADL_FLAGS_READ_LAST);
5753
5754 ipr_do_req(ipr_cmd, ipr_erp_done, ipr_timeout,
5755 IPR_REQUEST_SENSE_TIMEOUT * 2);
5756}
5757
5758
5759
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769
5770static void ipr_erp_cancel_all(struct ipr_cmnd *ipr_cmd)
5771{
5772 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5773 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
5774 struct ipr_cmd_pkt *cmd_pkt;
5775
5776 res->in_erp = 1;
5777
5778 ipr_reinit_ipr_cmnd_for_erp(ipr_cmd);
5779
5780 if (!scsi_get_tag_type(scsi_cmd->device)) {
5781 ipr_erp_request_sense(ipr_cmd);
5782 return;
5783 }
5784
5785 cmd_pkt = &ipr_cmd->ioarcb.cmd_pkt;
5786 cmd_pkt->request_type = IPR_RQTYPE_IOACMD;
5787 cmd_pkt->cdb[0] = IPR_CANCEL_ALL_REQUESTS;
5788
5789 ipr_do_req(ipr_cmd, ipr_erp_request_sense, ipr_timeout,
5790 IPR_CANCEL_ALL_TIMEOUT);
5791}
5792
5793
5794
5795
5796
5797
5798
5799
5800
5801
5802
5803
5804
5805
5806static void ipr_dump_ioasa(struct ipr_ioa_cfg *ioa_cfg,
5807 struct ipr_cmnd *ipr_cmd, struct ipr_resource_entry *res)
5808{
5809 int i;
5810 u16 data_len;
5811 u32 ioasc, fd_ioasc;
5812 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5813 __be32 *ioasa_data = (__be32 *)ioasa;
5814 int error_index;
5815
5816 ioasc = be32_to_cpu(ioasa->hdr.ioasc) & IPR_IOASC_IOASC_MASK;
5817 fd_ioasc = be32_to_cpu(ioasa->hdr.fd_ioasc) & IPR_IOASC_IOASC_MASK;
5818
5819 if (0 == ioasc)
5820 return;
5821
5822 if (ioa_cfg->log_level < IPR_DEFAULT_LOG_LEVEL)
5823 return;
5824
5825 if (ioasc == IPR_IOASC_BUS_WAS_RESET && fd_ioasc)
5826 error_index = ipr_get_error(fd_ioasc);
5827 else
5828 error_index = ipr_get_error(ioasc);
5829
5830 if (ioa_cfg->log_level < IPR_MAX_LOG_LEVEL) {
5831
5832 if (ioasa->hdr.ilid != 0)
5833 return;
5834
5835 if (!ipr_is_gscsi(res))
5836 return;
5837
5838 if (ipr_error_table[error_index].log_ioasa == 0)
5839 return;
5840 }
5841
5842 ipr_res_err(ioa_cfg, res, "%s\n", ipr_error_table[error_index].error);
5843
5844 data_len = be16_to_cpu(ioasa->hdr.ret_stat_len);
5845 if (ioa_cfg->sis64 && sizeof(struct ipr_ioasa64) < data_len)
5846 data_len = sizeof(struct ipr_ioasa64);
5847 else if (!ioa_cfg->sis64 && sizeof(struct ipr_ioasa) < data_len)
5848 data_len = sizeof(struct ipr_ioasa);
5849
5850 ipr_err("IOASA Dump:\n");
5851
5852 for (i = 0; i < data_len / 4; i += 4) {
5853 ipr_err("%08X: %08X %08X %08X %08X\n", i*4,
5854 be32_to_cpu(ioasa_data[i]),
5855 be32_to_cpu(ioasa_data[i+1]),
5856 be32_to_cpu(ioasa_data[i+2]),
5857 be32_to_cpu(ioasa_data[i+3]));
5858 }
5859}
5860
5861
5862
5863
5864
5865
5866
5867
5868
5869static void ipr_gen_sense(struct ipr_cmnd *ipr_cmd)
5870{
5871 u32 failing_lba;
5872 u8 *sense_buf = ipr_cmd->scsi_cmd->sense_buffer;
5873 struct ipr_resource_entry *res = ipr_cmd->scsi_cmd->device->hostdata;
5874 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5875 u32 ioasc = be32_to_cpu(ioasa->hdr.ioasc);
5876
5877 memset(sense_buf, 0, SCSI_SENSE_BUFFERSIZE);
5878
5879 if (ioasc >= IPR_FIRST_DRIVER_IOASC)
5880 return;
5881
5882 ipr_cmd->scsi_cmd->result = SAM_STAT_CHECK_CONDITION;
5883
5884 if (ipr_is_vset_device(res) &&
5885 ioasc == IPR_IOASC_MED_DO_NOT_REALLOC &&
5886 ioasa->u.vset.failing_lba_hi != 0) {
5887 sense_buf[0] = 0x72;
5888 sense_buf[1] = IPR_IOASC_SENSE_KEY(ioasc);
5889 sense_buf[2] = IPR_IOASC_SENSE_CODE(ioasc);
5890 sense_buf[3] = IPR_IOASC_SENSE_QUAL(ioasc);
5891
5892 sense_buf[7] = 12;
5893 sense_buf[8] = 0;
5894 sense_buf[9] = 0x0A;
5895 sense_buf[10] = 0x80;
5896
5897 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_hi);
5898
5899 sense_buf[12] = (failing_lba & 0xff000000) >> 24;
5900 sense_buf[13] = (failing_lba & 0x00ff0000) >> 16;
5901 sense_buf[14] = (failing_lba & 0x0000ff00) >> 8;
5902 sense_buf[15] = failing_lba & 0x000000ff;
5903
5904 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_lo);
5905
5906 sense_buf[16] = (failing_lba & 0xff000000) >> 24;
5907 sense_buf[17] = (failing_lba & 0x00ff0000) >> 16;
5908 sense_buf[18] = (failing_lba & 0x0000ff00) >> 8;
5909 sense_buf[19] = failing_lba & 0x000000ff;
5910 } else {
5911 sense_buf[0] = 0x70;
5912 sense_buf[2] = IPR_IOASC_SENSE_KEY(ioasc);
5913 sense_buf[12] = IPR_IOASC_SENSE_CODE(ioasc);
5914 sense_buf[13] = IPR_IOASC_SENSE_QUAL(ioasc);
5915
5916
5917 if ((IPR_IOASC_SENSE_KEY(ioasc) == 0x05) &&
5918 (be32_to_cpu(ioasa->hdr.ioasc_specific) & IPR_FIELD_POINTER_VALID)) {
5919 sense_buf[7] = 10;
5920
5921
5922 if (IPR_IOASC_SENSE_CODE(ioasc) == 0x24)
5923 sense_buf[15] = 0xC0;
5924 else
5925 sense_buf[15] = 0x80;
5926
5927 sense_buf[16] =
5928 ((IPR_FIELD_POINTER_MASK &
5929 be32_to_cpu(ioasa->hdr.ioasc_specific)) >> 8) & 0xff;
5930 sense_buf[17] =
5931 (IPR_FIELD_POINTER_MASK &
5932 be32_to_cpu(ioasa->hdr.ioasc_specific)) & 0xff;
5933 } else {
5934 if (ioasc == IPR_IOASC_MED_DO_NOT_REALLOC) {
5935 if (ipr_is_vset_device(res))
5936 failing_lba = be32_to_cpu(ioasa->u.vset.failing_lba_lo);
5937 else
5938 failing_lba = be32_to_cpu(ioasa->u.dasd.failing_lba);
5939
5940 sense_buf[0] |= 0x80;
5941 sense_buf[3] = (failing_lba & 0xff000000) >> 24;
5942 sense_buf[4] = (failing_lba & 0x00ff0000) >> 16;
5943 sense_buf[5] = (failing_lba & 0x0000ff00) >> 8;
5944 sense_buf[6] = failing_lba & 0x000000ff;
5945 }
5946
5947 sense_buf[7] = 6;
5948 }
5949 }
5950}
5951
5952
5953
5954
5955
5956
5957
5958
5959
5960
5961
5962static int ipr_get_autosense(struct ipr_cmnd *ipr_cmd)
5963{
5964 struct ipr_ioasa *ioasa = &ipr_cmd->s.ioasa;
5965 struct ipr_ioasa64 *ioasa64 = &ipr_cmd->s.ioasa64;
5966
5967 if ((be32_to_cpu(ioasa->hdr.ioasc_specific) & IPR_AUTOSENSE_VALID) == 0)
5968 return 0;
5969
5970 if (ipr_cmd->ioa_cfg->sis64)
5971 memcpy(ipr_cmd->scsi_cmd->sense_buffer, ioasa64->auto_sense.data,
5972 min_t(u16, be16_to_cpu(ioasa64->auto_sense.auto_sense_len),
5973 SCSI_SENSE_BUFFERSIZE));
5974 else
5975 memcpy(ipr_cmd->scsi_cmd->sense_buffer, ioasa->auto_sense.data,
5976 min_t(u16, be16_to_cpu(ioasa->auto_sense.auto_sense_len),
5977 SCSI_SENSE_BUFFERSIZE));
5978 return 1;
5979}
5980
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992static void ipr_erp_start(struct ipr_ioa_cfg *ioa_cfg,
5993 struct ipr_cmnd *ipr_cmd)
5994{
5995 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
5996 struct ipr_resource_entry *res = scsi_cmd->device->hostdata;
5997 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
5998 u32 masked_ioasc = ioasc & IPR_IOASC_IOASC_MASK;
5999
6000 if (!res) {
6001 ipr_scsi_eh_done(ipr_cmd);
6002 return;
6003 }
6004
6005 if (!ipr_is_gscsi(res) && masked_ioasc != IPR_IOASC_HW_DEV_BUS_STATUS)
6006 ipr_gen_sense(ipr_cmd);
6007
6008 ipr_dump_ioasa(ioa_cfg, ipr_cmd, res);
6009
6010 switch (masked_ioasc) {
6011 case IPR_IOASC_ABORTED_CMD_TERM_BY_HOST:
6012 if (ipr_is_naca_model(res))
6013 scsi_cmd->result |= (DID_ABORT << 16);
6014 else
6015 scsi_cmd->result |= (DID_IMM_RETRY << 16);
6016 break;
6017 case IPR_IOASC_IR_RESOURCE_HANDLE:
6018 case IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA:
6019 scsi_cmd->result |= (DID_NO_CONNECT << 16);
6020 break;
6021 case IPR_IOASC_HW_SEL_TIMEOUT:
6022 scsi_cmd->result |= (DID_NO_CONNECT << 16);
6023 if (!ipr_is_naca_model(res))
6024 res->needs_sync_complete = 1;
6025 break;
6026 case IPR_IOASC_SYNC_REQUIRED:
6027 if (!res->in_erp)
6028 res->needs_sync_complete = 1;
6029 scsi_cmd->result |= (DID_IMM_RETRY << 16);
6030 break;
6031 case IPR_IOASC_MED_DO_NOT_REALLOC:
6032 case IPR_IOASA_IR_DUAL_IOA_DISABLED:
6033 scsi_cmd->result |= (DID_PASSTHROUGH << 16);
6034 break;
6035 case IPR_IOASC_BUS_WAS_RESET:
6036 case IPR_IOASC_BUS_WAS_RESET_BY_OTHER:
6037
6038
6039
6040
6041 if (!res->resetting_device)
6042 scsi_report_bus_reset(ioa_cfg->host, scsi_cmd->device->channel);
6043 scsi_cmd->result |= (DID_ERROR << 16);
6044 if (!ipr_is_naca_model(res))
6045 res->needs_sync_complete = 1;
6046 break;
6047 case IPR_IOASC_HW_DEV_BUS_STATUS:
6048 scsi_cmd->result |= IPR_IOASC_SENSE_STATUS(ioasc);
6049 if (IPR_IOASC_SENSE_STATUS(ioasc) == SAM_STAT_CHECK_CONDITION) {
6050 if (!ipr_get_autosense(ipr_cmd)) {
6051 if (!ipr_is_naca_model(res)) {
6052 ipr_erp_cancel_all(ipr_cmd);
6053 return;
6054 }
6055 }
6056 }
6057 if (!ipr_is_naca_model(res))
6058 res->needs_sync_complete = 1;
6059 break;
6060 case IPR_IOASC_NR_INIT_CMD_REQUIRED:
6061 break;
6062 default:
6063 if (IPR_IOASC_SENSE_KEY(ioasc) > RECOVERED_ERROR)
6064 scsi_cmd->result |= (DID_ERROR << 16);
6065 if (!ipr_is_vset_device(res) && !ipr_is_naca_model(res))
6066 res->needs_sync_complete = 1;
6067 break;
6068 }
6069
6070 scsi_dma_unmap(ipr_cmd->scsi_cmd);
6071 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6072 scsi_cmd->scsi_done(scsi_cmd);
6073}
6074
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084
6085static void ipr_scsi_done(struct ipr_cmnd *ipr_cmd)
6086{
6087 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6088 struct scsi_cmnd *scsi_cmd = ipr_cmd->scsi_cmd;
6089 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6090 unsigned long hrrq_flags;
6091
6092 scsi_set_resid(scsi_cmd, be32_to_cpu(ipr_cmd->s.ioasa.hdr.residual_data_len));
6093
6094 if (likely(IPR_IOASC_SENSE_KEY(ioasc) == 0)) {
6095 scsi_dma_unmap(scsi_cmd);
6096
6097 spin_lock_irqsave(ipr_cmd->hrrq->lock, hrrq_flags);
6098 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6099 scsi_cmd->scsi_done(scsi_cmd);
6100 spin_unlock_irqrestore(ipr_cmd->hrrq->lock, hrrq_flags);
6101 } else {
6102 spin_lock_irqsave(ipr_cmd->hrrq->lock, hrrq_flags);
6103 ipr_erp_start(ioa_cfg, ipr_cmd);
6104 spin_unlock_irqrestore(ipr_cmd->hrrq->lock, hrrq_flags);
6105 }
6106}
6107
6108
6109
6110
6111
6112
6113
6114
6115
6116
6117
6118
6119
6120static int ipr_queuecommand(struct Scsi_Host *shost,
6121 struct scsi_cmnd *scsi_cmd)
6122{
6123 struct ipr_ioa_cfg *ioa_cfg;
6124 struct ipr_resource_entry *res;
6125 struct ipr_ioarcb *ioarcb;
6126 struct ipr_cmnd *ipr_cmd;
6127 unsigned long hrrq_flags, lock_flags;
6128 int rc;
6129 struct ipr_hrr_queue *hrrq;
6130 int hrrq_id;
6131
6132 ioa_cfg = (struct ipr_ioa_cfg *)shost->hostdata;
6133
6134 scsi_cmd->result = (DID_OK << 16);
6135 res = scsi_cmd->device->hostdata;
6136
6137 if (ipr_is_gata(res) && res->sata_port) {
6138 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
6139 rc = ata_sas_queuecmd(scsi_cmd, res->sata_port->ap);
6140 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
6141 return rc;
6142 }
6143
6144 hrrq_id = ipr_get_hrrq_index(ioa_cfg);
6145 hrrq = &ioa_cfg->hrrq[hrrq_id];
6146
6147 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6148
6149
6150
6151
6152
6153 if (unlikely(!hrrq->allow_cmds && !hrrq->ioa_is_dead && !hrrq->removing_ioa)) {
6154 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6155 return SCSI_MLQUEUE_HOST_BUSY;
6156 }
6157
6158
6159
6160
6161
6162 if (unlikely(hrrq->ioa_is_dead || hrrq->removing_ioa || !res)) {
6163 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6164 goto err_nodev;
6165 }
6166
6167 ipr_cmd = __ipr_get_free_ipr_cmnd(hrrq);
6168 if (ipr_cmd == NULL) {
6169 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6170 return SCSI_MLQUEUE_HOST_BUSY;
6171 }
6172 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6173
6174 ipr_init_ipr_cmnd(ipr_cmd, ipr_scsi_done);
6175 ioarcb = &ipr_cmd->ioarcb;
6176
6177 memcpy(ioarcb->cmd_pkt.cdb, scsi_cmd->cmnd, scsi_cmd->cmd_len);
6178 ipr_cmd->scsi_cmd = scsi_cmd;
6179 ipr_cmd->done = ipr_scsi_eh_done;
6180
6181 if (ipr_is_gscsi(res) || ipr_is_vset_device(res)) {
6182 if (scsi_cmd->underflow == 0)
6183 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6184
6185 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC;
6186 if (ipr_is_gscsi(res))
6187 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_DELAY_AFTER_RST;
6188 ioarcb->cmd_pkt.flags_lo |= IPR_FLAGS_LO_ALIGNED_BFR;
6189 ioarcb->cmd_pkt.flags_lo |= ipr_get_task_attributes(scsi_cmd);
6190 }
6191
6192 if (scsi_cmd->cmnd[0] >= 0xC0 &&
6193 (!ipr_is_gscsi(res) || scsi_cmd->cmnd[0] == IPR_QUERY_RSRC_STATE)) {
6194 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
6195 }
6196
6197 if (ioa_cfg->sis64)
6198 rc = ipr_build_ioadl64(ioa_cfg, ipr_cmd);
6199 else
6200 rc = ipr_build_ioadl(ioa_cfg, ipr_cmd);
6201
6202 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6203 if (unlikely(rc || (!hrrq->allow_cmds && !hrrq->ioa_is_dead))) {
6204 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_free_q);
6205 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6206 if (!rc)
6207 scsi_dma_unmap(scsi_cmd);
6208 return SCSI_MLQUEUE_HOST_BUSY;
6209 }
6210
6211 if (unlikely(hrrq->ioa_is_dead)) {
6212 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_free_q);
6213 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6214 scsi_dma_unmap(scsi_cmd);
6215 goto err_nodev;
6216 }
6217
6218 ioarcb->res_handle = res->res_handle;
6219 if (res->needs_sync_complete) {
6220 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_SYNC_COMPLETE;
6221 res->needs_sync_complete = 0;
6222 }
6223 list_add_tail(&ipr_cmd->queue, &hrrq->hrrq_pending_q);
6224 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res));
6225 ipr_send_command(ipr_cmd);
6226 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6227 return 0;
6228
6229err_nodev:
6230 spin_lock_irqsave(hrrq->lock, hrrq_flags);
6231 memset(scsi_cmd->sense_buffer, 0, SCSI_SENSE_BUFFERSIZE);
6232 scsi_cmd->result = (DID_NO_CONNECT << 16);
6233 scsi_cmd->scsi_done(scsi_cmd);
6234 spin_unlock_irqrestore(hrrq->lock, hrrq_flags);
6235 return 0;
6236}
6237
6238
6239
6240
6241
6242
6243
6244
6245
6246
6247static int ipr_ioctl(struct scsi_device *sdev, int cmd, void __user *arg)
6248{
6249 struct ipr_resource_entry *res;
6250
6251 res = (struct ipr_resource_entry *)sdev->hostdata;
6252 if (res && ipr_is_gata(res)) {
6253 if (cmd == HDIO_GET_IDENTITY)
6254 return -ENOTTY;
6255 return ata_sas_scsi_ioctl(res->sata_port->ap, sdev, cmd, arg);
6256 }
6257
6258 return -EINVAL;
6259}
6260
6261
6262
6263
6264
6265
6266
6267
6268static const char *ipr_ioa_info(struct Scsi_Host *host)
6269{
6270 static char buffer[512];
6271 struct ipr_ioa_cfg *ioa_cfg;
6272 unsigned long lock_flags = 0;
6273
6274 ioa_cfg = (struct ipr_ioa_cfg *) host->hostdata;
6275
6276 spin_lock_irqsave(host->host_lock, lock_flags);
6277 sprintf(buffer, "IBM %X Storage Adapter", ioa_cfg->type);
6278 spin_unlock_irqrestore(host->host_lock, lock_flags);
6279
6280 return buffer;
6281}
6282
6283static struct scsi_host_template driver_template = {
6284 .module = THIS_MODULE,
6285 .name = "IPR",
6286 .info = ipr_ioa_info,
6287 .ioctl = ipr_ioctl,
6288 .queuecommand = ipr_queuecommand,
6289 .eh_abort_handler = ipr_eh_abort,
6290 .eh_device_reset_handler = ipr_eh_dev_reset,
6291 .eh_host_reset_handler = ipr_eh_host_reset,
6292 .slave_alloc = ipr_slave_alloc,
6293 .slave_configure = ipr_slave_configure,
6294 .slave_destroy = ipr_slave_destroy,
6295 .target_alloc = ipr_target_alloc,
6296 .target_destroy = ipr_target_destroy,
6297 .change_queue_depth = ipr_change_queue_depth,
6298 .change_queue_type = ipr_change_queue_type,
6299 .bios_param = ipr_biosparam,
6300 .can_queue = IPR_MAX_COMMANDS,
6301 .this_id = -1,
6302 .sg_tablesize = IPR_MAX_SGLIST,
6303 .max_sectors = IPR_IOA_MAX_SECTORS,
6304 .cmd_per_lun = IPR_MAX_CMD_PER_LUN,
6305 .use_clustering = ENABLE_CLUSTERING,
6306 .shost_attrs = ipr_ioa_attrs,
6307 .sdev_attrs = ipr_dev_attrs,
6308 .proc_name = IPR_NAME
6309};
6310
6311
6312
6313
6314
6315
6316static void ipr_ata_phy_reset(struct ata_port *ap)
6317{
6318 unsigned long flags;
6319 struct ipr_sata_port *sata_port = ap->private_data;
6320 struct ipr_resource_entry *res = sata_port->res;
6321 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6322 int rc;
6323
6324 ENTER;
6325 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6326 while (ioa_cfg->in_reset_reload) {
6327 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6328 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
6329 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6330 }
6331
6332 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds)
6333 goto out_unlock;
6334
6335 rc = ipr_device_reset(ioa_cfg, res);
6336
6337 if (rc) {
6338 ap->link.device[0].class = ATA_DEV_NONE;
6339 goto out_unlock;
6340 }
6341
6342 ap->link.device[0].class = res->ata_class;
6343 if (ap->link.device[0].class == ATA_DEV_UNKNOWN)
6344 ap->link.device[0].class = ATA_DEV_NONE;
6345
6346out_unlock:
6347 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6348 LEAVE;
6349}
6350
6351
6352
6353
6354
6355
6356
6357
6358static void ipr_ata_post_internal(struct ata_queued_cmd *qc)
6359{
6360 struct ipr_sata_port *sata_port = qc->ap->private_data;
6361 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6362 struct ipr_cmnd *ipr_cmd;
6363 struct ipr_hrr_queue *hrrq;
6364 unsigned long flags;
6365
6366 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6367 while (ioa_cfg->in_reset_reload) {
6368 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6369 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
6370 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
6371 }
6372
6373 for_each_hrrq(hrrq, ioa_cfg) {
6374 spin_lock(&hrrq->_lock);
6375 list_for_each_entry(ipr_cmd, &hrrq->hrrq_pending_q, queue) {
6376 if (ipr_cmd->qc == qc) {
6377 ipr_device_reset(ioa_cfg, sata_port->res);
6378 break;
6379 }
6380 }
6381 spin_unlock(&hrrq->_lock);
6382 }
6383 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
6384}
6385
6386
6387
6388
6389
6390
6391
6392
6393
6394static void ipr_copy_sata_tf(struct ipr_ioarcb_ata_regs *regs,
6395 struct ata_taskfile *tf)
6396{
6397 regs->feature = tf->feature;
6398 regs->nsect = tf->nsect;
6399 regs->lbal = tf->lbal;
6400 regs->lbam = tf->lbam;
6401 regs->lbah = tf->lbah;
6402 regs->device = tf->device;
6403 regs->command = tf->command;
6404 regs->hob_feature = tf->hob_feature;
6405 regs->hob_nsect = tf->hob_nsect;
6406 regs->hob_lbal = tf->hob_lbal;
6407 regs->hob_lbam = tf->hob_lbam;
6408 regs->hob_lbah = tf->hob_lbah;
6409 regs->ctl = tf->ctl;
6410}
6411
6412
6413
6414
6415
6416
6417
6418
6419
6420
6421
6422static void ipr_sata_done(struct ipr_cmnd *ipr_cmd)
6423{
6424 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6425 struct ata_queued_cmd *qc = ipr_cmd->qc;
6426 struct ipr_sata_port *sata_port = qc->ap->private_data;
6427 struct ipr_resource_entry *res = sata_port->res;
6428 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
6429
6430 spin_lock(&ipr_cmd->hrrq->_lock);
6431 if (ipr_cmd->ioa_cfg->sis64)
6432 memcpy(&sata_port->ioasa, &ipr_cmd->s.ioasa64.u.gata,
6433 sizeof(struct ipr_ioasa_gata));
6434 else
6435 memcpy(&sata_port->ioasa, &ipr_cmd->s.ioasa.u.gata,
6436 sizeof(struct ipr_ioasa_gata));
6437 ipr_dump_ioasa(ioa_cfg, ipr_cmd, res);
6438
6439 if (be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc_specific) & IPR_ATA_DEVICE_WAS_RESET)
6440 scsi_report_device_reset(ioa_cfg->host, res->bus, res->target);
6441
6442 if (IPR_IOASC_SENSE_KEY(ioasc) > RECOVERED_ERROR)
6443 qc->err_mask |= __ac_err_mask(sata_port->ioasa.status);
6444 else
6445 qc->err_mask |= ac_err_mask(sata_port->ioasa.status);
6446 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6447 spin_unlock(&ipr_cmd->hrrq->_lock);
6448 ata_qc_complete(qc);
6449}
6450
6451
6452
6453
6454
6455
6456
6457static void ipr_build_ata_ioadl64(struct ipr_cmnd *ipr_cmd,
6458 struct ata_queued_cmd *qc)
6459{
6460 u32 ioadl_flags = 0;
6461 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6462 struct ipr_ioadl64_desc *ioadl64 = ipr_cmd->i.ata_ioadl.ioadl64;
6463 struct ipr_ioadl64_desc *last_ioadl64 = NULL;
6464 int len = qc->nbytes;
6465 struct scatterlist *sg;
6466 unsigned int si;
6467 dma_addr_t dma_addr = ipr_cmd->dma_addr;
6468
6469 if (len == 0)
6470 return;
6471
6472 if (qc->dma_dir == DMA_TO_DEVICE) {
6473 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
6474 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6475 } else if (qc->dma_dir == DMA_FROM_DEVICE)
6476 ioadl_flags = IPR_IOADL_FLAGS_READ;
6477
6478 ioarcb->data_transfer_length = cpu_to_be32(len);
6479 ioarcb->ioadl_len =
6480 cpu_to_be32(sizeof(struct ipr_ioadl64_desc) * ipr_cmd->dma_use_sg);
6481 ioarcb->u.sis64_addr_data.data_ioadl_addr =
6482 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ata_ioadl.ioadl64));
6483
6484 for_each_sg(qc->sg, sg, qc->n_elem, si) {
6485 ioadl64->flags = cpu_to_be32(ioadl_flags);
6486 ioadl64->data_len = cpu_to_be32(sg_dma_len(sg));
6487 ioadl64->address = cpu_to_be64(sg_dma_address(sg));
6488
6489 last_ioadl64 = ioadl64;
6490 ioadl64++;
6491 }
6492
6493 if (likely(last_ioadl64))
6494 last_ioadl64->flags |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6495}
6496
6497
6498
6499
6500
6501
6502
6503static void ipr_build_ata_ioadl(struct ipr_cmnd *ipr_cmd,
6504 struct ata_queued_cmd *qc)
6505{
6506 u32 ioadl_flags = 0;
6507 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6508 struct ipr_ioadl_desc *ioadl = ipr_cmd->i.ioadl;
6509 struct ipr_ioadl_desc *last_ioadl = NULL;
6510 int len = qc->nbytes;
6511 struct scatterlist *sg;
6512 unsigned int si;
6513
6514 if (len == 0)
6515 return;
6516
6517 if (qc->dma_dir == DMA_TO_DEVICE) {
6518 ioadl_flags = IPR_IOADL_FLAGS_WRITE;
6519 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6520 ioarcb->data_transfer_length = cpu_to_be32(len);
6521 ioarcb->ioadl_len =
6522 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6523 } else if (qc->dma_dir == DMA_FROM_DEVICE) {
6524 ioadl_flags = IPR_IOADL_FLAGS_READ;
6525 ioarcb->read_data_transfer_length = cpu_to_be32(len);
6526 ioarcb->read_ioadl_len =
6527 cpu_to_be32(sizeof(struct ipr_ioadl_desc) * ipr_cmd->dma_use_sg);
6528 }
6529
6530 for_each_sg(qc->sg, sg, qc->n_elem, si) {
6531 ioadl->flags_and_data_len = cpu_to_be32(ioadl_flags | sg_dma_len(sg));
6532 ioadl->address = cpu_to_be32(sg_dma_address(sg));
6533
6534 last_ioadl = ioadl;
6535 ioadl++;
6536 }
6537
6538 if (likely(last_ioadl))
6539 last_ioadl->flags_and_data_len |= cpu_to_be32(IPR_IOADL_FLAGS_LAST);
6540}
6541
6542
6543
6544
6545
6546
6547
6548
6549static int ipr_qc_defer(struct ata_queued_cmd *qc)
6550{
6551 struct ata_port *ap = qc->ap;
6552 struct ipr_sata_port *sata_port = ap->private_data;
6553 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6554 struct ipr_cmnd *ipr_cmd;
6555 struct ipr_hrr_queue *hrrq;
6556 int hrrq_id;
6557
6558 hrrq_id = ipr_get_hrrq_index(ioa_cfg);
6559 hrrq = &ioa_cfg->hrrq[hrrq_id];
6560
6561 qc->lldd_task = NULL;
6562 spin_lock(&hrrq->_lock);
6563 if (unlikely(hrrq->ioa_is_dead)) {
6564 spin_unlock(&hrrq->_lock);
6565 return 0;
6566 }
6567
6568 if (unlikely(!hrrq->allow_cmds)) {
6569 spin_unlock(&hrrq->_lock);
6570 return ATA_DEFER_LINK;
6571 }
6572
6573 ipr_cmd = __ipr_get_free_ipr_cmnd(hrrq);
6574 if (ipr_cmd == NULL) {
6575 spin_unlock(&hrrq->_lock);
6576 return ATA_DEFER_LINK;
6577 }
6578
6579 qc->lldd_task = ipr_cmd;
6580 spin_unlock(&hrrq->_lock);
6581 return 0;
6582}
6583
6584
6585
6586
6587
6588
6589
6590
6591static unsigned int ipr_qc_issue(struct ata_queued_cmd *qc)
6592{
6593 struct ata_port *ap = qc->ap;
6594 struct ipr_sata_port *sata_port = ap->private_data;
6595 struct ipr_resource_entry *res = sata_port->res;
6596 struct ipr_ioa_cfg *ioa_cfg = sata_port->ioa_cfg;
6597 struct ipr_cmnd *ipr_cmd;
6598 struct ipr_ioarcb *ioarcb;
6599 struct ipr_ioarcb_ata_regs *regs;
6600
6601 if (qc->lldd_task == NULL)
6602 ipr_qc_defer(qc);
6603
6604 ipr_cmd = qc->lldd_task;
6605 if (ipr_cmd == NULL)
6606 return AC_ERR_SYSTEM;
6607
6608 qc->lldd_task = NULL;
6609 spin_lock(&ipr_cmd->hrrq->_lock);
6610 if (unlikely(!ipr_cmd->hrrq->allow_cmds ||
6611 ipr_cmd->hrrq->ioa_is_dead)) {
6612 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6613 spin_unlock(&ipr_cmd->hrrq->_lock);
6614 return AC_ERR_SYSTEM;
6615 }
6616
6617 ipr_init_ipr_cmnd(ipr_cmd, ipr_lock_and_done);
6618 ioarcb = &ipr_cmd->ioarcb;
6619
6620 if (ioa_cfg->sis64) {
6621 regs = &ipr_cmd->i.ata_ioadl.regs;
6622 ioarcb->add_cmd_parms_offset = cpu_to_be16(sizeof(*ioarcb));
6623 } else
6624 regs = &ioarcb->u.add_data.u.regs;
6625
6626 memset(regs, 0, sizeof(*regs));
6627 ioarcb->add_cmd_parms_len = cpu_to_be16(sizeof(*regs));
6628
6629 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
6630 ipr_cmd->qc = qc;
6631 ipr_cmd->done = ipr_sata_done;
6632 ipr_cmd->ioarcb.res_handle = res->res_handle;
6633 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_ATA_PASSTHRU;
6634 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_LINK_DESC;
6635 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_NO_ULEN_CHK;
6636 ipr_cmd->dma_use_sg = qc->n_elem;
6637
6638 if (ioa_cfg->sis64)
6639 ipr_build_ata_ioadl64(ipr_cmd, qc);
6640 else
6641 ipr_build_ata_ioadl(ipr_cmd, qc);
6642
6643 regs->flags |= IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION;
6644 ipr_copy_sata_tf(regs, &qc->tf);
6645 memcpy(ioarcb->cmd_pkt.cdb, qc->cdb, IPR_MAX_CDB_LEN);
6646 ipr_trc_hook(ipr_cmd, IPR_TRACE_START, IPR_GET_RES_PHYS_LOC(res));
6647
6648 switch (qc->tf.protocol) {
6649 case ATA_PROT_NODATA:
6650 case ATA_PROT_PIO:
6651 break;
6652
6653 case ATA_PROT_DMA:
6654 regs->flags |= IPR_ATA_FLAG_XFER_TYPE_DMA;
6655 break;
6656
6657 case ATAPI_PROT_PIO:
6658 case ATAPI_PROT_NODATA:
6659 regs->flags |= IPR_ATA_FLAG_PACKET_CMD;
6660 break;
6661
6662 case ATAPI_PROT_DMA:
6663 regs->flags |= IPR_ATA_FLAG_PACKET_CMD;
6664 regs->flags |= IPR_ATA_FLAG_XFER_TYPE_DMA;
6665 break;
6666
6667 default:
6668 WARN_ON(1);
6669 spin_unlock(&ipr_cmd->hrrq->_lock);
6670 return AC_ERR_INVALID;
6671 }
6672
6673 ipr_send_command(ipr_cmd);
6674 spin_unlock(&ipr_cmd->hrrq->_lock);
6675
6676 return 0;
6677}
6678
6679
6680
6681
6682
6683
6684
6685
6686static bool ipr_qc_fill_rtf(struct ata_queued_cmd *qc)
6687{
6688 struct ipr_sata_port *sata_port = qc->ap->private_data;
6689 struct ipr_ioasa_gata *g = &sata_port->ioasa;
6690 struct ata_taskfile *tf = &qc->result_tf;
6691
6692 tf->feature = g->error;
6693 tf->nsect = g->nsect;
6694 tf->lbal = g->lbal;
6695 tf->lbam = g->lbam;
6696 tf->lbah = g->lbah;
6697 tf->device = g->device;
6698 tf->command = g->status;
6699 tf->hob_nsect = g->hob_nsect;
6700 tf->hob_lbal = g->hob_lbal;
6701 tf->hob_lbam = g->hob_lbam;
6702 tf->hob_lbah = g->hob_lbah;
6703
6704 return true;
6705}
6706
6707static struct ata_port_operations ipr_sata_ops = {
6708 .phy_reset = ipr_ata_phy_reset,
6709 .hardreset = ipr_sata_reset,
6710 .post_internal_cmd = ipr_ata_post_internal,
6711 .qc_prep = ata_noop_qc_prep,
6712 .qc_defer = ipr_qc_defer,
6713 .qc_issue = ipr_qc_issue,
6714 .qc_fill_rtf = ipr_qc_fill_rtf,
6715 .port_start = ata_sas_port_start,
6716 .port_stop = ata_sas_port_stop
6717};
6718
6719static struct ata_port_info sata_port_info = {
6720 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
6721 .pio_mask = ATA_PIO4_ONLY,
6722 .mwdma_mask = ATA_MWDMA2,
6723 .udma_mask = ATA_UDMA6,
6724 .port_ops = &ipr_sata_ops
6725};
6726
6727#ifdef CONFIG_PPC_PSERIES
6728static const u16 ipr_blocked_processors[] = {
6729 PVR_NORTHSTAR,
6730 PVR_PULSAR,
6731 PVR_POWER4,
6732 PVR_ICESTAR,
6733 PVR_SSTAR,
6734 PVR_POWER4p,
6735 PVR_630,
6736 PVR_630p
6737};
6738
6739
6740
6741
6742
6743
6744
6745
6746
6747
6748
6749
6750static int ipr_invalid_adapter(struct ipr_ioa_cfg *ioa_cfg)
6751{
6752 int i;
6753
6754 if ((ioa_cfg->type == 0x5702) && (ioa_cfg->pdev->revision < 4)) {
6755 for (i = 0; i < ARRAY_SIZE(ipr_blocked_processors); i++) {
6756 if (pvr_version_is(ipr_blocked_processors[i]))
6757 return 1;
6758 }
6759 }
6760 return 0;
6761}
6762#else
6763#define ipr_invalid_adapter(ioa_cfg) 0
6764#endif
6765
6766
6767
6768
6769
6770
6771
6772
6773
6774
6775
6776static int ipr_ioa_bringdown_done(struct ipr_cmnd *ipr_cmd)
6777{
6778 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6779 int i;
6780
6781 ENTER;
6782 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa) {
6783 ipr_trace;
6784 spin_unlock_irq(ioa_cfg->host->host_lock);
6785 scsi_unblock_requests(ioa_cfg->host);
6786 spin_lock_irq(ioa_cfg->host->host_lock);
6787 }
6788
6789 ioa_cfg->in_reset_reload = 0;
6790 ioa_cfg->reset_retries = 0;
6791 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
6792 spin_lock(&ioa_cfg->hrrq[i]._lock);
6793 ioa_cfg->hrrq[i].ioa_is_dead = 1;
6794 spin_unlock(&ioa_cfg->hrrq[i]._lock);
6795 }
6796 wmb();
6797
6798 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6799 wake_up_all(&ioa_cfg->reset_wait_q);
6800 LEAVE;
6801
6802 return IPR_RC_JOB_RETURN;
6803}
6804
6805
6806
6807
6808
6809
6810
6811
6812
6813
6814
6815
6816static int ipr_ioa_reset_done(struct ipr_cmnd *ipr_cmd)
6817{
6818 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6819 struct ipr_resource_entry *res;
6820 struct ipr_hostrcb *hostrcb, *temp;
6821 int i = 0, j;
6822
6823 ENTER;
6824 ioa_cfg->in_reset_reload = 0;
6825 for (j = 0; j < ioa_cfg->hrrq_num; j++) {
6826 spin_lock(&ioa_cfg->hrrq[j]._lock);
6827 ioa_cfg->hrrq[j].allow_cmds = 1;
6828 spin_unlock(&ioa_cfg->hrrq[j]._lock);
6829 }
6830 wmb();
6831 ioa_cfg->reset_cmd = NULL;
6832 ioa_cfg->doorbell |= IPR_RUNTIME_RESET;
6833
6834 list_for_each_entry(res, &ioa_cfg->used_res_q, queue) {
6835 if (ioa_cfg->allow_ml_add_del && (res->add_to_ml || res->del_from_ml)) {
6836 ipr_trace;
6837 break;
6838 }
6839 }
6840 schedule_work(&ioa_cfg->work_q);
6841
6842 list_for_each_entry_safe(hostrcb, temp, &ioa_cfg->hostrcb_free_q, queue) {
6843 list_del(&hostrcb->queue);
6844 if (i++ < IPR_NUM_LOG_HCAMS)
6845 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_LOG_DATA, hostrcb);
6846 else
6847 ipr_send_hcam(ioa_cfg, IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE, hostrcb);
6848 }
6849
6850 scsi_report_bus_reset(ioa_cfg->host, IPR_VSET_BUS);
6851 dev_info(&ioa_cfg->pdev->dev, "IOA initialized.\n");
6852
6853 ioa_cfg->reset_retries = 0;
6854 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
6855 wake_up_all(&ioa_cfg->reset_wait_q);
6856
6857 spin_unlock(ioa_cfg->host->host_lock);
6858 scsi_unblock_requests(ioa_cfg->host);
6859 spin_lock(ioa_cfg->host->host_lock);
6860
6861 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds)
6862 scsi_block_requests(ioa_cfg->host);
6863
6864 LEAVE;
6865 return IPR_RC_JOB_RETURN;
6866}
6867
6868
6869
6870
6871
6872
6873
6874
6875
6876static void ipr_set_sup_dev_dflt(struct ipr_supported_device *supported_dev,
6877 struct ipr_std_inq_vpids *vpids)
6878{
6879 memset(supported_dev, 0, sizeof(struct ipr_supported_device));
6880 memcpy(&supported_dev->vpids, vpids, sizeof(struct ipr_std_inq_vpids));
6881 supported_dev->num_records = 1;
6882 supported_dev->data_length =
6883 cpu_to_be16(sizeof(struct ipr_supported_device));
6884 supported_dev->reserved = 0;
6885}
6886
6887
6888
6889
6890
6891
6892
6893
6894
6895
6896static int ipr_set_supported_devs(struct ipr_cmnd *ipr_cmd)
6897{
6898 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
6899 struct ipr_supported_device *supp_dev = &ioa_cfg->vpd_cbs->supp_dev;
6900 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
6901 struct ipr_resource_entry *res = ipr_cmd->u.res;
6902
6903 ipr_cmd->job_step = ipr_ioa_reset_done;
6904
6905 list_for_each_entry_continue(res, &ioa_cfg->used_res_q, queue) {
6906 if (!ipr_is_scsi_disk(res))
6907 continue;
6908
6909 ipr_cmd->u.res = res;
6910 ipr_set_sup_dev_dflt(supp_dev, &res->std_inq_data.vpids);
6911
6912 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
6913 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
6914 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
6915
6916 ioarcb->cmd_pkt.cdb[0] = IPR_SET_SUPPORTED_DEVICES;
6917 ioarcb->cmd_pkt.cdb[1] = IPR_SET_ALL_SUPPORTED_DEVICES;
6918 ioarcb->cmd_pkt.cdb[7] = (sizeof(struct ipr_supported_device) >> 8) & 0xff;
6919 ioarcb->cmd_pkt.cdb[8] = sizeof(struct ipr_supported_device) & 0xff;
6920
6921 ipr_init_ioadl(ipr_cmd,
6922 ioa_cfg->vpd_cbs_dma +
6923 offsetof(struct ipr_misc_cbs, supp_dev),
6924 sizeof(struct ipr_supported_device),
6925 IPR_IOADL_FLAGS_WRITE_LAST);
6926
6927 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
6928 IPR_SET_SUP_DEVICE_TIMEOUT);
6929
6930 if (!ioa_cfg->sis64)
6931 ipr_cmd->job_step = ipr_set_supported_devs;
6932 LEAVE;
6933 return IPR_RC_JOB_RETURN;
6934 }
6935
6936 LEAVE;
6937 return IPR_RC_JOB_CONTINUE;
6938}
6939
6940
6941
6942
6943
6944
6945
6946
6947
6948
6949static void *ipr_get_mode_page(struct ipr_mode_pages *mode_pages,
6950 u32 page_code, u32 len)
6951{
6952 struct ipr_mode_page_hdr *mode_hdr;
6953 u32 page_length;
6954 u32 length;
6955
6956 if (!mode_pages || (mode_pages->hdr.length == 0))
6957 return NULL;
6958
6959 length = (mode_pages->hdr.length + 1) - 4 - mode_pages->hdr.block_desc_len;
6960 mode_hdr = (struct ipr_mode_page_hdr *)
6961 (mode_pages->data + mode_pages->hdr.block_desc_len);
6962
6963 while (length) {
6964 if (IPR_GET_MODE_PAGE_CODE(mode_hdr) == page_code) {
6965 if (mode_hdr->page_length >= (len - sizeof(struct ipr_mode_page_hdr)))
6966 return mode_hdr;
6967 break;
6968 } else {
6969 page_length = (sizeof(struct ipr_mode_page_hdr) +
6970 mode_hdr->page_length);
6971 length -= page_length;
6972 mode_hdr = (struct ipr_mode_page_hdr *)
6973 ((unsigned long)mode_hdr + page_length);
6974 }
6975 }
6976 return NULL;
6977}
6978
6979
6980
6981
6982
6983
6984
6985
6986
6987
6988
6989static void ipr_check_term_power(struct ipr_ioa_cfg *ioa_cfg,
6990 struct ipr_mode_pages *mode_pages)
6991{
6992 int i;
6993 int entry_length;
6994 struct ipr_dev_bus_entry *bus;
6995 struct ipr_mode_page28 *mode_page;
6996
6997 mode_page = ipr_get_mode_page(mode_pages, 0x28,
6998 sizeof(struct ipr_mode_page28));
6999
7000 entry_length = mode_page->entry_length;
7001
7002 bus = mode_page->bus;
7003
7004 for (i = 0; i < mode_page->num_entries; i++) {
7005 if (bus->flags & IPR_SCSI_ATTR_NO_TERM_PWR) {
7006 dev_err(&ioa_cfg->pdev->dev,
7007 "Term power is absent on scsi bus %d\n",
7008 bus->res_addr.bus);
7009 }
7010
7011 bus = (struct ipr_dev_bus_entry *)((char *)bus + entry_length);
7012 }
7013}
7014
7015
7016
7017
7018
7019
7020
7021
7022
7023
7024
7025
7026static void ipr_scsi_bus_speed_limit(struct ipr_ioa_cfg *ioa_cfg)
7027{
7028 u32 max_xfer_rate;
7029 int i;
7030
7031 for (i = 0; i < IPR_MAX_NUM_BUSES; i++) {
7032 max_xfer_rate = ipr_get_max_scsi_speed(ioa_cfg, i,
7033 ioa_cfg->bus_attr[i].bus_width);
7034
7035 if (max_xfer_rate < ioa_cfg->bus_attr[i].max_xfer_rate)
7036 ioa_cfg->bus_attr[i].max_xfer_rate = max_xfer_rate;
7037 }
7038}
7039
7040
7041
7042
7043
7044
7045
7046
7047
7048
7049
7050static void ipr_modify_ioafp_mode_page_28(struct ipr_ioa_cfg *ioa_cfg,
7051 struct ipr_mode_pages *mode_pages)
7052{
7053 int i, entry_length;
7054 struct ipr_dev_bus_entry *bus;
7055 struct ipr_bus_attributes *bus_attr;
7056 struct ipr_mode_page28 *mode_page;
7057
7058 mode_page = ipr_get_mode_page(mode_pages, 0x28,
7059 sizeof(struct ipr_mode_page28));
7060
7061 entry_length = mode_page->entry_length;
7062
7063
7064 for (i = 0, bus = mode_page->bus;
7065 i < mode_page->num_entries;
7066 i++, bus = (struct ipr_dev_bus_entry *)((u8 *)bus + entry_length)) {
7067 if (bus->res_addr.bus > IPR_MAX_NUM_BUSES) {
7068 dev_err(&ioa_cfg->pdev->dev,
7069 "Invalid resource address reported: 0x%08X\n",
7070 IPR_GET_PHYS_LOC(bus->res_addr));
7071 continue;
7072 }
7073
7074 bus_attr = &ioa_cfg->bus_attr[i];
7075 bus->extended_reset_delay = IPR_EXTENDED_RESET_DELAY;
7076 bus->bus_width = bus_attr->bus_width;
7077 bus->max_xfer_rate = cpu_to_be32(bus_attr->max_xfer_rate);
7078 bus->flags &= ~IPR_SCSI_ATTR_QAS_MASK;
7079 if (bus_attr->qas_enabled)
7080 bus->flags |= IPR_SCSI_ATTR_ENABLE_QAS;
7081 else
7082 bus->flags |= IPR_SCSI_ATTR_DISABLE_QAS;
7083 }
7084}
7085
7086
7087
7088
7089
7090
7091
7092
7093
7094
7095
7096
7097static void ipr_build_mode_select(struct ipr_cmnd *ipr_cmd,
7098 __be32 res_handle, u8 parm,
7099 dma_addr_t dma_addr, u8 xfer_len)
7100{
7101 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7102
7103 ioarcb->res_handle = res_handle;
7104 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7105 ioarcb->cmd_pkt.flags_hi |= IPR_FLAGS_HI_WRITE_NOT_READ;
7106 ioarcb->cmd_pkt.cdb[0] = MODE_SELECT;
7107 ioarcb->cmd_pkt.cdb[1] = parm;
7108 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7109
7110 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_WRITE_LAST);
7111}
7112
7113
7114
7115
7116
7117
7118
7119
7120
7121
7122
7123static int ipr_ioafp_mode_select_page28(struct ipr_cmnd *ipr_cmd)
7124{
7125 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7126 struct ipr_mode_pages *mode_pages = &ioa_cfg->vpd_cbs->mode_pages;
7127 int length;
7128
7129 ENTER;
7130 ipr_scsi_bus_speed_limit(ioa_cfg);
7131 ipr_check_term_power(ioa_cfg, mode_pages);
7132 ipr_modify_ioafp_mode_page_28(ioa_cfg, mode_pages);
7133 length = mode_pages->hdr.length + 1;
7134 mode_pages->hdr.length = 0;
7135
7136 ipr_build_mode_select(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE), 0x11,
7137 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, mode_pages),
7138 length);
7139
7140 ipr_cmd->job_step = ipr_set_supported_devs;
7141 ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next,
7142 struct ipr_resource_entry, queue);
7143 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7144
7145 LEAVE;
7146 return IPR_RC_JOB_RETURN;
7147}
7148
7149
7150
7151
7152
7153
7154
7155
7156
7157
7158
7159
7160static void ipr_build_mode_sense(struct ipr_cmnd *ipr_cmd,
7161 __be32 res_handle,
7162 u8 parm, dma_addr_t dma_addr, u8 xfer_len)
7163{
7164 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7165
7166 ioarcb->res_handle = res_handle;
7167 ioarcb->cmd_pkt.cdb[0] = MODE_SENSE;
7168 ioarcb->cmd_pkt.cdb[2] = parm;
7169 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7170 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7171
7172 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST);
7173}
7174
7175
7176
7177
7178
7179
7180
7181
7182
7183
7184static int ipr_reset_cmd_failed(struct ipr_cmnd *ipr_cmd)
7185{
7186 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7187 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7188
7189 dev_err(&ioa_cfg->pdev->dev,
7190 "0x%02X failed with IOASC: 0x%08X\n",
7191 ipr_cmd->ioarcb.cmd_pkt.cdb[0], ioasc);
7192
7193 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
7194 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
7195 return IPR_RC_JOB_RETURN;
7196}
7197
7198
7199
7200
7201
7202
7203
7204
7205
7206
7207
7208static int ipr_reset_mode_sense_failed(struct ipr_cmnd *ipr_cmd)
7209{
7210 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7211 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7212
7213 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT) {
7214 ipr_cmd->job_step = ipr_set_supported_devs;
7215 ipr_cmd->u.res = list_entry(ioa_cfg->used_res_q.next,
7216 struct ipr_resource_entry, queue);
7217 return IPR_RC_JOB_CONTINUE;
7218 }
7219
7220 return ipr_reset_cmd_failed(ipr_cmd);
7221}
7222
7223
7224
7225
7226
7227
7228
7229
7230
7231
7232
7233static int ipr_ioafp_mode_sense_page28(struct ipr_cmnd *ipr_cmd)
7234{
7235 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7236
7237 ENTER;
7238 ipr_build_mode_sense(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE),
7239 0x28, ioa_cfg->vpd_cbs_dma +
7240 offsetof(struct ipr_misc_cbs, mode_pages),
7241 sizeof(struct ipr_mode_pages));
7242
7243 ipr_cmd->job_step = ipr_ioafp_mode_select_page28;
7244 ipr_cmd->job_step_failed = ipr_reset_mode_sense_failed;
7245
7246 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7247
7248 LEAVE;
7249 return IPR_RC_JOB_RETURN;
7250}
7251
7252
7253
7254
7255
7256
7257
7258
7259
7260
7261static int ipr_ioafp_mode_select_page24(struct ipr_cmnd *ipr_cmd)
7262{
7263 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7264 struct ipr_mode_pages *mode_pages = &ioa_cfg->vpd_cbs->mode_pages;
7265 struct ipr_mode_page24 *mode_page;
7266 int length;
7267
7268 ENTER;
7269 mode_page = ipr_get_mode_page(mode_pages, 0x24,
7270 sizeof(struct ipr_mode_page24));
7271
7272 if (mode_page)
7273 mode_page->flags |= IPR_ENABLE_DUAL_IOA_AF;
7274
7275 length = mode_pages->hdr.length + 1;
7276 mode_pages->hdr.length = 0;
7277
7278 ipr_build_mode_select(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE), 0x11,
7279 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, mode_pages),
7280 length);
7281
7282 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7283 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7284
7285 LEAVE;
7286 return IPR_RC_JOB_RETURN;
7287}
7288
7289
7290
7291
7292
7293
7294
7295
7296
7297
7298
7299static int ipr_reset_mode_sense_page24_failed(struct ipr_cmnd *ipr_cmd)
7300{
7301 u32 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
7302
7303 if (ioasc == IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT) {
7304 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7305 return IPR_RC_JOB_CONTINUE;
7306 }
7307
7308 return ipr_reset_cmd_failed(ipr_cmd);
7309}
7310
7311
7312
7313
7314
7315
7316
7317
7318
7319
7320
7321static int ipr_ioafp_mode_sense_page24(struct ipr_cmnd *ipr_cmd)
7322{
7323 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7324
7325 ENTER;
7326 ipr_build_mode_sense(ipr_cmd, cpu_to_be32(IPR_IOA_RES_HANDLE),
7327 0x24, ioa_cfg->vpd_cbs_dma +
7328 offsetof(struct ipr_misc_cbs, mode_pages),
7329 sizeof(struct ipr_mode_pages));
7330
7331 ipr_cmd->job_step = ipr_ioafp_mode_select_page24;
7332 ipr_cmd->job_step_failed = ipr_reset_mode_sense_page24_failed;
7333
7334 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7335
7336 LEAVE;
7337 return IPR_RC_JOB_RETURN;
7338}
7339
7340
7341
7342
7343
7344
7345
7346
7347
7348
7349
7350
7351
7352static int ipr_init_res_table(struct ipr_cmnd *ipr_cmd)
7353{
7354 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7355 struct ipr_resource_entry *res, *temp;
7356 struct ipr_config_table_entry_wrapper cfgtew;
7357 int entries, found, flag, i;
7358 LIST_HEAD(old_res);
7359
7360 ENTER;
7361 if (ioa_cfg->sis64)
7362 flag = ioa_cfg->u.cfg_table64->hdr64.flags;
7363 else
7364 flag = ioa_cfg->u.cfg_table->hdr.flags;
7365
7366 if (flag & IPR_UCODE_DOWNLOAD_REQ)
7367 dev_err(&ioa_cfg->pdev->dev, "Microcode download required\n");
7368
7369 list_for_each_entry_safe(res, temp, &ioa_cfg->used_res_q, queue)
7370 list_move_tail(&res->queue, &old_res);
7371
7372 if (ioa_cfg->sis64)
7373 entries = be16_to_cpu(ioa_cfg->u.cfg_table64->hdr64.num_entries);
7374 else
7375 entries = ioa_cfg->u.cfg_table->hdr.num_entries;
7376
7377 for (i = 0; i < entries; i++) {
7378 if (ioa_cfg->sis64)
7379 cfgtew.u.cfgte64 = &ioa_cfg->u.cfg_table64->dev[i];
7380 else
7381 cfgtew.u.cfgte = &ioa_cfg->u.cfg_table->dev[i];
7382 found = 0;
7383
7384 list_for_each_entry_safe(res, temp, &old_res, queue) {
7385 if (ipr_is_same_device(res, &cfgtew)) {
7386 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7387 found = 1;
7388 break;
7389 }
7390 }
7391
7392 if (!found) {
7393 if (list_empty(&ioa_cfg->free_res_q)) {
7394 dev_err(&ioa_cfg->pdev->dev, "Too many devices attached\n");
7395 break;
7396 }
7397
7398 found = 1;
7399 res = list_entry(ioa_cfg->free_res_q.next,
7400 struct ipr_resource_entry, queue);
7401 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7402 ipr_init_res_entry(res, &cfgtew);
7403 res->add_to_ml = 1;
7404 } else if (res->sdev && (ipr_is_vset_device(res) || ipr_is_scsi_disk(res)))
7405 res->sdev->allow_restart = 1;
7406
7407 if (found)
7408 ipr_update_res_entry(res, &cfgtew);
7409 }
7410
7411 list_for_each_entry_safe(res, temp, &old_res, queue) {
7412 if (res->sdev) {
7413 res->del_from_ml = 1;
7414 res->res_handle = IPR_INVALID_RES_HANDLE;
7415 list_move_tail(&res->queue, &ioa_cfg->used_res_q);
7416 }
7417 }
7418
7419 list_for_each_entry_safe(res, temp, &old_res, queue) {
7420 ipr_clear_res_target(res);
7421 list_move_tail(&res->queue, &ioa_cfg->free_res_q);
7422 }
7423
7424 if (ioa_cfg->dual_raid && ipr_dual_ioa_raid)
7425 ipr_cmd->job_step = ipr_ioafp_mode_sense_page24;
7426 else
7427 ipr_cmd->job_step = ipr_ioafp_mode_sense_page28;
7428
7429 LEAVE;
7430 return IPR_RC_JOB_CONTINUE;
7431}
7432
7433
7434
7435
7436
7437
7438
7439
7440
7441
7442
7443static int ipr_ioafp_query_ioa_cfg(struct ipr_cmnd *ipr_cmd)
7444{
7445 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7446 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7447 struct ipr_inquiry_page3 *ucode_vpd = &ioa_cfg->vpd_cbs->page3_data;
7448 struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap;
7449
7450 ENTER;
7451 if (cap->cap & IPR_CAP_DUAL_IOA_RAID)
7452 ioa_cfg->dual_raid = 1;
7453 dev_info(&ioa_cfg->pdev->dev, "Adapter firmware version: %02X%02X%02X%02X\n",
7454 ucode_vpd->major_release, ucode_vpd->card_type,
7455 ucode_vpd->minor_release[0], ucode_vpd->minor_release[1]);
7456 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7457 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7458
7459 ioarcb->cmd_pkt.cdb[0] = IPR_QUERY_IOA_CONFIG;
7460 ioarcb->cmd_pkt.cdb[6] = (ioa_cfg->cfg_table_size >> 16) & 0xff;
7461 ioarcb->cmd_pkt.cdb[7] = (ioa_cfg->cfg_table_size >> 8) & 0xff;
7462 ioarcb->cmd_pkt.cdb[8] = ioa_cfg->cfg_table_size & 0xff;
7463
7464 ipr_init_ioadl(ipr_cmd, ioa_cfg->cfg_table_dma, ioa_cfg->cfg_table_size,
7465 IPR_IOADL_FLAGS_READ_LAST);
7466
7467 ipr_cmd->job_step = ipr_init_res_table;
7468
7469 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7470
7471 LEAVE;
7472 return IPR_RC_JOB_RETURN;
7473}
7474
7475
7476
7477
7478
7479
7480
7481
7482
7483
7484static void ipr_ioafp_inquiry(struct ipr_cmnd *ipr_cmd, u8 flags, u8 page,
7485 dma_addr_t dma_addr, u8 xfer_len)
7486{
7487 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7488
7489 ENTER;
7490 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
7491 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7492
7493 ioarcb->cmd_pkt.cdb[0] = INQUIRY;
7494 ioarcb->cmd_pkt.cdb[1] = flags;
7495 ioarcb->cmd_pkt.cdb[2] = page;
7496 ioarcb->cmd_pkt.cdb[4] = xfer_len;
7497
7498 ipr_init_ioadl(ipr_cmd, dma_addr, xfer_len, IPR_IOADL_FLAGS_READ_LAST);
7499
7500 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, IPR_INTERNAL_TIMEOUT);
7501 LEAVE;
7502}
7503
7504
7505
7506
7507
7508
7509
7510
7511
7512
7513
7514static int ipr_inquiry_page_supported(struct ipr_inquiry_page0 *page0, u8 page)
7515{
7516 int i;
7517
7518 for (i = 0; i < min_t(u8, page0->len, IPR_INQUIRY_PAGE0_ENTRIES); i++)
7519 if (page0->page[i] == page)
7520 return 1;
7521
7522 return 0;
7523}
7524
7525
7526
7527
7528
7529
7530
7531
7532
7533
7534
7535static int ipr_ioafp_cap_inquiry(struct ipr_cmnd *ipr_cmd)
7536{
7537 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7538 struct ipr_inquiry_page0 *page0 = &ioa_cfg->vpd_cbs->page0_data;
7539 struct ipr_inquiry_cap *cap = &ioa_cfg->vpd_cbs->cap;
7540
7541 ENTER;
7542 ipr_cmd->job_step = ipr_ioafp_query_ioa_cfg;
7543 memset(cap, 0, sizeof(*cap));
7544
7545 if (ipr_inquiry_page_supported(page0, 0xD0)) {
7546 ipr_ioafp_inquiry(ipr_cmd, 1, 0xD0,
7547 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, cap),
7548 sizeof(struct ipr_inquiry_cap));
7549 return IPR_RC_JOB_RETURN;
7550 }
7551
7552 LEAVE;
7553 return IPR_RC_JOB_CONTINUE;
7554}
7555
7556
7557
7558
7559
7560
7561
7562
7563
7564
7565
7566static int ipr_ioafp_page3_inquiry(struct ipr_cmnd *ipr_cmd)
7567{
7568 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7569
7570 ENTER;
7571
7572 ipr_cmd->job_step = ipr_ioafp_cap_inquiry;
7573
7574 ipr_ioafp_inquiry(ipr_cmd, 1, 3,
7575 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, page3_data),
7576 sizeof(struct ipr_inquiry_page3));
7577
7578 LEAVE;
7579 return IPR_RC_JOB_RETURN;
7580}
7581
7582
7583
7584
7585
7586
7587
7588
7589
7590
7591
7592static int ipr_ioafp_page0_inquiry(struct ipr_cmnd *ipr_cmd)
7593{
7594 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7595 char type[5];
7596
7597 ENTER;
7598
7599
7600 memcpy(type, ioa_cfg->vpd_cbs->ioa_vpd.std_inq_data.vpids.product_id, 4);
7601 type[4] = '\0';
7602 ioa_cfg->type = simple_strtoul((char *)type, NULL, 16);
7603
7604 ipr_cmd->job_step = ipr_ioafp_page3_inquiry;
7605
7606 ipr_ioafp_inquiry(ipr_cmd, 1, 0,
7607 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, page0_data),
7608 sizeof(struct ipr_inquiry_page0));
7609
7610 LEAVE;
7611 return IPR_RC_JOB_RETURN;
7612}
7613
7614
7615
7616
7617
7618
7619
7620
7621
7622
7623static int ipr_ioafp_std_inquiry(struct ipr_cmnd *ipr_cmd)
7624{
7625 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7626
7627 ENTER;
7628 ipr_cmd->job_step = ipr_ioafp_page0_inquiry;
7629
7630 ipr_ioafp_inquiry(ipr_cmd, 0, 0,
7631 ioa_cfg->vpd_cbs_dma + offsetof(struct ipr_misc_cbs, ioa_vpd),
7632 sizeof(struct ipr_ioa_vpd));
7633
7634 LEAVE;
7635 return IPR_RC_JOB_RETURN;
7636}
7637
7638
7639
7640
7641
7642
7643
7644
7645
7646
7647
7648static int ipr_ioafp_identify_hrrq(struct ipr_cmnd *ipr_cmd)
7649{
7650 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7651 struct ipr_ioarcb *ioarcb = &ipr_cmd->ioarcb;
7652 struct ipr_hrr_queue *hrrq;
7653
7654 ENTER;
7655 ipr_cmd->job_step = ipr_ioafp_std_inquiry;
7656 dev_info(&ioa_cfg->pdev->dev, "Starting IOA initialization sequence.\n");
7657
7658 if (ioa_cfg->identify_hrrq_index < ioa_cfg->hrrq_num) {
7659 hrrq = &ioa_cfg->hrrq[ioa_cfg->identify_hrrq_index];
7660
7661 ioarcb->cmd_pkt.cdb[0] = IPR_ID_HOST_RR_Q;
7662 ioarcb->res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
7663
7664 ioarcb->cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
7665 if (ioa_cfg->sis64)
7666 ioarcb->cmd_pkt.cdb[1] = 0x1;
7667
7668 if (ioa_cfg->nvectors == 1)
7669 ioarcb->cmd_pkt.cdb[1] &= ~IPR_ID_HRRQ_SELE_ENABLE;
7670 else
7671 ioarcb->cmd_pkt.cdb[1] |= IPR_ID_HRRQ_SELE_ENABLE;
7672
7673 ioarcb->cmd_pkt.cdb[2] =
7674 ((u64) hrrq->host_rrq_dma >> 24) & 0xff;
7675 ioarcb->cmd_pkt.cdb[3] =
7676 ((u64) hrrq->host_rrq_dma >> 16) & 0xff;
7677 ioarcb->cmd_pkt.cdb[4] =
7678 ((u64) hrrq->host_rrq_dma >> 8) & 0xff;
7679 ioarcb->cmd_pkt.cdb[5] =
7680 ((u64) hrrq->host_rrq_dma) & 0xff;
7681 ioarcb->cmd_pkt.cdb[7] =
7682 ((sizeof(u32) * hrrq->size) >> 8) & 0xff;
7683 ioarcb->cmd_pkt.cdb[8] =
7684 (sizeof(u32) * hrrq->size) & 0xff;
7685
7686 if (ioarcb->cmd_pkt.cdb[1] & IPR_ID_HRRQ_SELE_ENABLE)
7687 ioarcb->cmd_pkt.cdb[9] =
7688 ioa_cfg->identify_hrrq_index;
7689
7690 if (ioa_cfg->sis64) {
7691 ioarcb->cmd_pkt.cdb[10] =
7692 ((u64) hrrq->host_rrq_dma >> 56) & 0xff;
7693 ioarcb->cmd_pkt.cdb[11] =
7694 ((u64) hrrq->host_rrq_dma >> 48) & 0xff;
7695 ioarcb->cmd_pkt.cdb[12] =
7696 ((u64) hrrq->host_rrq_dma >> 40) & 0xff;
7697 ioarcb->cmd_pkt.cdb[13] =
7698 ((u64) hrrq->host_rrq_dma >> 32) & 0xff;
7699 }
7700
7701 if (ioarcb->cmd_pkt.cdb[1] & IPR_ID_HRRQ_SELE_ENABLE)
7702 ioarcb->cmd_pkt.cdb[14] =
7703 ioa_cfg->identify_hrrq_index;
7704
7705 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
7706 IPR_INTERNAL_TIMEOUT);
7707
7708 if (++ioa_cfg->identify_hrrq_index < ioa_cfg->hrrq_num)
7709 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
7710
7711 LEAVE;
7712 return IPR_RC_JOB_RETURN;
7713 }
7714
7715 LEAVE;
7716 return IPR_RC_JOB_CONTINUE;
7717}
7718
7719
7720
7721
7722
7723
7724
7725
7726
7727
7728
7729
7730
7731
7732static void ipr_reset_timer_done(struct ipr_cmnd *ipr_cmd)
7733{
7734 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7735 unsigned long lock_flags = 0;
7736
7737 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
7738
7739 if (ioa_cfg->reset_cmd == ipr_cmd) {
7740 list_del(&ipr_cmd->queue);
7741 ipr_cmd->done(ipr_cmd);
7742 }
7743
7744 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
7745}
7746
7747
7748
7749
7750
7751
7752
7753
7754
7755
7756
7757
7758
7759
7760
7761static void ipr_reset_start_timer(struct ipr_cmnd *ipr_cmd,
7762 unsigned long timeout)
7763{
7764
7765 ENTER;
7766 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
7767 ipr_cmd->done = ipr_reset_ioa_job;
7768
7769 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
7770 ipr_cmd->timer.expires = jiffies + timeout;
7771 ipr_cmd->timer.function = (void (*)(unsigned long))ipr_reset_timer_done;
7772 add_timer(&ipr_cmd->timer);
7773}
7774
7775
7776
7777
7778
7779
7780
7781
7782static void ipr_init_ioa_mem(struct ipr_ioa_cfg *ioa_cfg)
7783{
7784 struct ipr_hrr_queue *hrrq;
7785
7786 for_each_hrrq(hrrq, ioa_cfg) {
7787 spin_lock(&hrrq->_lock);
7788 memset(hrrq->host_rrq, 0, sizeof(u32) * hrrq->size);
7789
7790
7791 hrrq->hrrq_start = hrrq->host_rrq;
7792 hrrq->hrrq_end = &hrrq->host_rrq[hrrq->size - 1];
7793 hrrq->hrrq_curr = hrrq->hrrq_start;
7794 hrrq->toggle_bit = 1;
7795 spin_unlock(&hrrq->_lock);
7796 }
7797 wmb();
7798
7799 ioa_cfg->identify_hrrq_index = 0;
7800 if (ioa_cfg->hrrq_num == 1)
7801 atomic_set(&ioa_cfg->hrrq_index, 0);
7802 else
7803 atomic_set(&ioa_cfg->hrrq_index, 1);
7804
7805
7806 memset(ioa_cfg->u.cfg_table, 0, ioa_cfg->cfg_table_size);
7807}
7808
7809
7810
7811
7812
7813
7814
7815
7816static int ipr_reset_next_stage(struct ipr_cmnd *ipr_cmd)
7817{
7818 unsigned long stage, stage_time;
7819 u32 feedback;
7820 volatile u32 int_reg;
7821 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7822 u64 maskval = 0;
7823
7824 feedback = readl(ioa_cfg->regs.init_feedback_reg);
7825 stage = feedback & IPR_IPL_INIT_STAGE_MASK;
7826 stage_time = feedback & IPR_IPL_INIT_STAGE_TIME_MASK;
7827
7828 ipr_dbg("IPL stage = 0x%lx, IPL stage time = %ld\n", stage, stage_time);
7829
7830
7831 if (stage_time == 0)
7832 stage_time = IPR_IPL_INIT_DEFAULT_STAGE_TIME;
7833 else if (stage_time < IPR_IPL_INIT_MIN_STAGE_TIME)
7834 stage_time = IPR_IPL_INIT_MIN_STAGE_TIME;
7835 else if (stage_time > IPR_LONG_OPERATIONAL_TIMEOUT)
7836 stage_time = IPR_LONG_OPERATIONAL_TIMEOUT;
7837
7838 if (stage == IPR_IPL_INIT_STAGE_UNKNOWN) {
7839 writel(IPR_PCII_IPL_STAGE_CHANGE, ioa_cfg->regs.set_interrupt_mask_reg);
7840 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
7841 stage_time = ioa_cfg->transop_timeout;
7842 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
7843 } else if (stage == IPR_IPL_INIT_STAGE_TRANSOP) {
7844 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
7845 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
7846 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
7847 maskval = IPR_PCII_IPL_STAGE_CHANGE;
7848 maskval = (maskval << 32) | IPR_PCII_IOA_TRANS_TO_OPER;
7849 writeq(maskval, ioa_cfg->regs.set_interrupt_mask_reg);
7850 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
7851 return IPR_RC_JOB_CONTINUE;
7852 }
7853 }
7854
7855 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
7856 ipr_cmd->timer.expires = jiffies + stage_time * HZ;
7857 ipr_cmd->timer.function = (void (*)(unsigned long))ipr_oper_timeout;
7858 ipr_cmd->done = ipr_reset_ioa_job;
7859 add_timer(&ipr_cmd->timer);
7860
7861 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
7862
7863 return IPR_RC_JOB_RETURN;
7864}
7865
7866
7867
7868
7869
7870
7871
7872
7873
7874
7875
7876static int ipr_reset_enable_ioa(struct ipr_cmnd *ipr_cmd)
7877{
7878 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7879 volatile u32 int_reg;
7880 volatile u64 maskval;
7881 int i;
7882
7883 ENTER;
7884 ipr_cmd->job_step = ipr_ioafp_identify_hrrq;
7885 ipr_init_ioa_mem(ioa_cfg);
7886
7887 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
7888 spin_lock(&ioa_cfg->hrrq[i]._lock);
7889 ioa_cfg->hrrq[i].allow_interrupts = 1;
7890 spin_unlock(&ioa_cfg->hrrq[i]._lock);
7891 }
7892 wmb();
7893 if (ioa_cfg->sis64) {
7894
7895 writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
7896 int_reg = readl(ioa_cfg->regs.endian_swap_reg);
7897 }
7898
7899 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg32);
7900
7901 if (int_reg & IPR_PCII_IOA_TRANS_TO_OPER) {
7902 writel((IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED),
7903 ioa_cfg->regs.clr_interrupt_mask_reg32);
7904 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
7905 return IPR_RC_JOB_CONTINUE;
7906 }
7907
7908
7909 writel(ioa_cfg->doorbell, ioa_cfg->regs.set_uproc_interrupt_reg32);
7910
7911 if (ioa_cfg->sis64) {
7912 maskval = IPR_PCII_IPL_STAGE_CHANGE;
7913 maskval = (maskval << 32) | IPR_PCII_OPER_INTERRUPTS;
7914 writeq(maskval, ioa_cfg->regs.clr_interrupt_mask_reg);
7915 } else
7916 writel(IPR_PCII_OPER_INTERRUPTS, ioa_cfg->regs.clr_interrupt_mask_reg32);
7917
7918 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
7919
7920 dev_info(&ioa_cfg->pdev->dev, "Initializing IOA.\n");
7921
7922 if (ioa_cfg->sis64) {
7923 ipr_cmd->job_step = ipr_reset_next_stage;
7924 return IPR_RC_JOB_CONTINUE;
7925 }
7926
7927 ipr_cmd->timer.data = (unsigned long) ipr_cmd;
7928 ipr_cmd->timer.expires = jiffies + (ioa_cfg->transop_timeout * HZ);
7929 ipr_cmd->timer.function = (void (*)(unsigned long))ipr_oper_timeout;
7930 ipr_cmd->done = ipr_reset_ioa_job;
7931 add_timer(&ipr_cmd->timer);
7932 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
7933
7934 LEAVE;
7935 return IPR_RC_JOB_RETURN;
7936}
7937
7938
7939
7940
7941
7942
7943
7944
7945
7946
7947
7948static int ipr_reset_wait_for_dump(struct ipr_cmnd *ipr_cmd)
7949{
7950 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
7951
7952 if (ioa_cfg->sdt_state == GET_DUMP)
7953 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
7954 else if (ioa_cfg->sdt_state == READ_DUMP)
7955 ioa_cfg->sdt_state = ABORT_DUMP;
7956
7957 ioa_cfg->dump_timeout = 1;
7958 ipr_cmd->job_step = ipr_reset_alert;
7959
7960 return IPR_RC_JOB_CONTINUE;
7961}
7962
7963
7964
7965
7966
7967
7968
7969
7970
7971
7972
7973static void ipr_unit_check_no_data(struct ipr_ioa_cfg *ioa_cfg)
7974{
7975 ioa_cfg->errors_logged++;
7976 dev_err(&ioa_cfg->pdev->dev, "IOA unit check with no data\n");
7977}
7978
7979
7980
7981
7982
7983
7984
7985
7986
7987
7988
7989static void ipr_get_unit_check_buffer(struct ipr_ioa_cfg *ioa_cfg)
7990{
7991 unsigned long mailbox;
7992 struct ipr_hostrcb *hostrcb;
7993 struct ipr_uc_sdt sdt;
7994 int rc, length;
7995 u32 ioasc;
7996
7997 mailbox = readl(ioa_cfg->ioa_mailbox);
7998
7999 if (!ioa_cfg->sis64 && !ipr_sdt_is_fmt2(mailbox)) {
8000 ipr_unit_check_no_data(ioa_cfg);
8001 return;
8002 }
8003
8004 memset(&sdt, 0, sizeof(struct ipr_uc_sdt));
8005 rc = ipr_get_ldump_data_section(ioa_cfg, mailbox, (__be32 *) &sdt,
8006 (sizeof(struct ipr_uc_sdt)) / sizeof(__be32));
8007
8008 if (rc || !(sdt.entry[0].flags & IPR_SDT_VALID_ENTRY) ||
8009 ((be32_to_cpu(sdt.hdr.state) != IPR_FMT3_SDT_READY_TO_USE) &&
8010 (be32_to_cpu(sdt.hdr.state) != IPR_FMT2_SDT_READY_TO_USE))) {
8011 ipr_unit_check_no_data(ioa_cfg);
8012 return;
8013 }
8014
8015
8016 if (be32_to_cpu(sdt.hdr.state) == IPR_FMT3_SDT_READY_TO_USE)
8017 length = be32_to_cpu(sdt.entry[0].end_token);
8018 else
8019 length = (be32_to_cpu(sdt.entry[0].end_token) -
8020 be32_to_cpu(sdt.entry[0].start_token)) &
8021 IPR_FMT2_MBX_ADDR_MASK;
8022
8023 hostrcb = list_entry(ioa_cfg->hostrcb_free_q.next,
8024 struct ipr_hostrcb, queue);
8025 list_del(&hostrcb->queue);
8026 memset(&hostrcb->hcam, 0, sizeof(hostrcb->hcam));
8027
8028 rc = ipr_get_ldump_data_section(ioa_cfg,
8029 be32_to_cpu(sdt.entry[0].start_token),
8030 (__be32 *)&hostrcb->hcam,
8031 min(length, (int)sizeof(hostrcb->hcam)) / sizeof(__be32));
8032
8033 if (!rc) {
8034 ipr_handle_log_data(ioa_cfg, hostrcb);
8035 ioasc = be32_to_cpu(hostrcb->hcam.u.error.fd_ioasc);
8036 if (ioasc == IPR_IOASC_NR_IOA_RESET_REQUIRED &&
8037 ioa_cfg->sdt_state == GET_DUMP)
8038 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
8039 } else
8040 ipr_unit_check_no_data(ioa_cfg);
8041
8042 list_add_tail(&hostrcb->queue, &ioa_cfg->hostrcb_free_q);
8043}
8044
8045
8046
8047
8048
8049
8050
8051
8052
8053
8054static int ipr_reset_get_unit_check_job(struct ipr_cmnd *ipr_cmd)
8055{
8056 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8057
8058 ENTER;
8059 ioa_cfg->ioa_unit_checked = 0;
8060 ipr_get_unit_check_buffer(ioa_cfg);
8061 ipr_cmd->job_step = ipr_reset_alert;
8062 ipr_reset_start_timer(ipr_cmd, 0);
8063
8064 LEAVE;
8065 return IPR_RC_JOB_RETURN;
8066}
8067
8068
8069
8070
8071
8072
8073
8074
8075
8076
8077
8078
8079static int ipr_reset_restore_cfg_space(struct ipr_cmnd *ipr_cmd)
8080{
8081 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8082 u32 int_reg;
8083
8084 ENTER;
8085 ioa_cfg->pdev->state_saved = true;
8086 pci_restore_state(ioa_cfg->pdev);
8087
8088 if (ipr_set_pcix_cmd_reg(ioa_cfg)) {
8089 ipr_cmd->s.ioasa.hdr.ioasc = cpu_to_be32(IPR_IOASC_PCI_ACCESS_ERROR);
8090 return IPR_RC_JOB_CONTINUE;
8091 }
8092
8093 ipr_fail_all_ops(ioa_cfg);
8094
8095 if (ioa_cfg->sis64) {
8096
8097 writel(IPR_ENDIAN_SWAP_KEY, ioa_cfg->regs.endian_swap_reg);
8098 int_reg = readl(ioa_cfg->regs.endian_swap_reg);
8099 }
8100
8101 if (ioa_cfg->ioa_unit_checked) {
8102 if (ioa_cfg->sis64) {
8103 ipr_cmd->job_step = ipr_reset_get_unit_check_job;
8104 ipr_reset_start_timer(ipr_cmd, IPR_DUMP_DELAY_TIMEOUT);
8105 return IPR_RC_JOB_RETURN;
8106 } else {
8107 ioa_cfg->ioa_unit_checked = 0;
8108 ipr_get_unit_check_buffer(ioa_cfg);
8109 ipr_cmd->job_step = ipr_reset_alert;
8110 ipr_reset_start_timer(ipr_cmd, 0);
8111 return IPR_RC_JOB_RETURN;
8112 }
8113 }
8114
8115 if (ioa_cfg->in_ioa_bringdown) {
8116 ipr_cmd->job_step = ipr_ioa_bringdown_done;
8117 } else {
8118 ipr_cmd->job_step = ipr_reset_enable_ioa;
8119
8120 if (GET_DUMP == ioa_cfg->sdt_state) {
8121 ioa_cfg->sdt_state = READ_DUMP;
8122 ioa_cfg->dump_timeout = 0;
8123 if (ioa_cfg->sis64)
8124 ipr_reset_start_timer(ipr_cmd, IPR_SIS64_DUMP_TIMEOUT);
8125 else
8126 ipr_reset_start_timer(ipr_cmd, IPR_SIS32_DUMP_TIMEOUT);
8127 ipr_cmd->job_step = ipr_reset_wait_for_dump;
8128 schedule_work(&ioa_cfg->work_q);
8129 return IPR_RC_JOB_RETURN;
8130 }
8131 }
8132
8133 LEAVE;
8134 return IPR_RC_JOB_CONTINUE;
8135}
8136
8137
8138
8139
8140
8141
8142
8143
8144
8145
8146static int ipr_reset_bist_done(struct ipr_cmnd *ipr_cmd)
8147{
8148 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8149
8150 ENTER;
8151 if (ioa_cfg->cfg_locked)
8152 pci_cfg_access_unlock(ioa_cfg->pdev);
8153 ioa_cfg->cfg_locked = 0;
8154 ipr_cmd->job_step = ipr_reset_restore_cfg_space;
8155 LEAVE;
8156 return IPR_RC_JOB_CONTINUE;
8157}
8158
8159
8160
8161
8162
8163
8164
8165
8166
8167
8168static int ipr_reset_start_bist(struct ipr_cmnd *ipr_cmd)
8169{
8170 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8171 int rc = PCIBIOS_SUCCESSFUL;
8172
8173 ENTER;
8174 if (ioa_cfg->ipr_chip->bist_method == IPR_MMIO)
8175 writel(IPR_UPROCI_SIS64_START_BIST,
8176 ioa_cfg->regs.set_uproc_interrupt_reg32);
8177 else
8178 rc = pci_write_config_byte(ioa_cfg->pdev, PCI_BIST, PCI_BIST_START);
8179
8180 if (rc == PCIBIOS_SUCCESSFUL) {
8181 ipr_cmd->job_step = ipr_reset_bist_done;
8182 ipr_reset_start_timer(ipr_cmd, IPR_WAIT_FOR_BIST_TIMEOUT);
8183 rc = IPR_RC_JOB_RETURN;
8184 } else {
8185 if (ioa_cfg->cfg_locked)
8186 pci_cfg_access_unlock(ipr_cmd->ioa_cfg->pdev);
8187 ioa_cfg->cfg_locked = 0;
8188 ipr_cmd->s.ioasa.hdr.ioasc = cpu_to_be32(IPR_IOASC_PCI_ACCESS_ERROR);
8189 rc = IPR_RC_JOB_CONTINUE;
8190 }
8191
8192 LEAVE;
8193 return rc;
8194}
8195
8196
8197
8198
8199
8200
8201
8202
8203
8204
8205static int ipr_reset_slot_reset_done(struct ipr_cmnd *ipr_cmd)
8206{
8207 ENTER;
8208 pci_set_pcie_reset_state(ipr_cmd->ioa_cfg->pdev, pcie_deassert_reset);
8209 ipr_cmd->job_step = ipr_reset_bist_done;
8210 ipr_reset_start_timer(ipr_cmd, IPR_WAIT_FOR_BIST_TIMEOUT);
8211 LEAVE;
8212 return IPR_RC_JOB_RETURN;
8213}
8214
8215
8216
8217
8218
8219
8220
8221
8222
8223
8224static int ipr_reset_slot_reset(struct ipr_cmnd *ipr_cmd)
8225{
8226 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8227 struct pci_dev *pdev = ioa_cfg->pdev;
8228
8229 ENTER;
8230 pci_set_pcie_reset_state(pdev, pcie_warm_reset);
8231 ipr_cmd->job_step = ipr_reset_slot_reset_done;
8232 ipr_reset_start_timer(ipr_cmd, IPR_PCI_RESET_TIMEOUT);
8233 LEAVE;
8234 return IPR_RC_JOB_RETURN;
8235}
8236
8237
8238
8239
8240
8241
8242
8243
8244
8245
8246static int ipr_reset_block_config_access_wait(struct ipr_cmnd *ipr_cmd)
8247{
8248 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8249 int rc = IPR_RC_JOB_CONTINUE;
8250
8251 if (pci_cfg_access_trylock(ioa_cfg->pdev)) {
8252 ioa_cfg->cfg_locked = 1;
8253 ipr_cmd->job_step = ioa_cfg->reset;
8254 } else {
8255 if (ipr_cmd->u.time_left) {
8256 rc = IPR_RC_JOB_RETURN;
8257 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
8258 ipr_reset_start_timer(ipr_cmd,
8259 IPR_CHECK_FOR_RESET_TIMEOUT);
8260 } else {
8261 ipr_cmd->job_step = ioa_cfg->reset;
8262 dev_err(&ioa_cfg->pdev->dev,
8263 "Timed out waiting to lock config access. Resetting anyway.\n");
8264 }
8265 }
8266
8267 return rc;
8268}
8269
8270
8271
8272
8273
8274
8275
8276
8277
8278
8279static int ipr_reset_block_config_access(struct ipr_cmnd *ipr_cmd)
8280{
8281 ipr_cmd->ioa_cfg->cfg_locked = 0;
8282 ipr_cmd->job_step = ipr_reset_block_config_access_wait;
8283 ipr_cmd->u.time_left = IPR_WAIT_FOR_RESET_TIMEOUT;
8284 return IPR_RC_JOB_CONTINUE;
8285}
8286
8287
8288
8289
8290
8291
8292
8293
8294static int ipr_reset_allowed(struct ipr_ioa_cfg *ioa_cfg)
8295{
8296 volatile u32 temp_reg;
8297
8298 temp_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
8299 return ((temp_reg & IPR_PCII_CRITICAL_OPERATION) == 0);
8300}
8301
8302
8303
8304
8305
8306
8307
8308
8309
8310
8311
8312
8313
8314
8315
8316
8317static int ipr_reset_wait_to_start_bist(struct ipr_cmnd *ipr_cmd)
8318{
8319 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8320 int rc = IPR_RC_JOB_RETURN;
8321
8322 if (!ipr_reset_allowed(ioa_cfg) && ipr_cmd->u.time_left) {
8323 ipr_cmd->u.time_left -= IPR_CHECK_FOR_RESET_TIMEOUT;
8324 ipr_reset_start_timer(ipr_cmd, IPR_CHECK_FOR_RESET_TIMEOUT);
8325 } else {
8326 ipr_cmd->job_step = ipr_reset_block_config_access;
8327 rc = IPR_RC_JOB_CONTINUE;
8328 }
8329
8330 return rc;
8331}
8332
8333
8334
8335
8336
8337
8338
8339
8340
8341
8342
8343
8344
8345static int ipr_reset_alert(struct ipr_cmnd *ipr_cmd)
8346{
8347 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8348 u16 cmd_reg;
8349 int rc;
8350
8351 ENTER;
8352 rc = pci_read_config_word(ioa_cfg->pdev, PCI_COMMAND, &cmd_reg);
8353
8354 if ((rc == PCIBIOS_SUCCESSFUL) && (cmd_reg & PCI_COMMAND_MEMORY)) {
8355 ipr_mask_and_clear_interrupts(ioa_cfg, ~0);
8356 writel(IPR_UPROCI_RESET_ALERT, ioa_cfg->regs.set_uproc_interrupt_reg32);
8357 ipr_cmd->job_step = ipr_reset_wait_to_start_bist;
8358 } else {
8359 ipr_cmd->job_step = ipr_reset_block_config_access;
8360 }
8361
8362 ipr_cmd->u.time_left = IPR_WAIT_FOR_RESET_TIMEOUT;
8363 ipr_reset_start_timer(ipr_cmd, IPR_CHECK_FOR_RESET_TIMEOUT);
8364
8365 LEAVE;
8366 return IPR_RC_JOB_RETURN;
8367}
8368
8369
8370
8371
8372
8373
8374
8375
8376
8377
8378static int ipr_reset_ucode_download_done(struct ipr_cmnd *ipr_cmd)
8379{
8380 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8381 struct ipr_sglist *sglist = ioa_cfg->ucode_sglist;
8382
8383 pci_unmap_sg(ioa_cfg->pdev, sglist->scatterlist,
8384 sglist->num_sg, DMA_TO_DEVICE);
8385
8386 ipr_cmd->job_step = ipr_reset_alert;
8387 return IPR_RC_JOB_CONTINUE;
8388}
8389
8390
8391
8392
8393
8394
8395
8396
8397
8398
8399
8400static int ipr_reset_ucode_download(struct ipr_cmnd *ipr_cmd)
8401{
8402 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8403 struct ipr_sglist *sglist = ioa_cfg->ucode_sglist;
8404
8405 ENTER;
8406 ipr_cmd->job_step = ipr_reset_alert;
8407
8408 if (!sglist)
8409 return IPR_RC_JOB_CONTINUE;
8410
8411 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
8412 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_SCSICDB;
8413 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = WRITE_BUFFER;
8414 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_WR_BUF_DOWNLOAD_AND_SAVE;
8415 ipr_cmd->ioarcb.cmd_pkt.cdb[6] = (sglist->buffer_len & 0xff0000) >> 16;
8416 ipr_cmd->ioarcb.cmd_pkt.cdb[7] = (sglist->buffer_len & 0x00ff00) >> 8;
8417 ipr_cmd->ioarcb.cmd_pkt.cdb[8] = sglist->buffer_len & 0x0000ff;
8418
8419 if (ioa_cfg->sis64)
8420 ipr_build_ucode_ioadl64(ipr_cmd, sglist);
8421 else
8422 ipr_build_ucode_ioadl(ipr_cmd, sglist);
8423 ipr_cmd->job_step = ipr_reset_ucode_download_done;
8424
8425 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout,
8426 IPR_WRITE_BUFFER_TIMEOUT);
8427
8428 LEAVE;
8429 return IPR_RC_JOB_RETURN;
8430}
8431
8432
8433
8434
8435
8436
8437
8438
8439
8440
8441
8442
8443static int ipr_reset_shutdown_ioa(struct ipr_cmnd *ipr_cmd)
8444{
8445 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8446 enum ipr_shutdown_type shutdown_type = ipr_cmd->u.shutdown_type;
8447 unsigned long timeout;
8448 int rc = IPR_RC_JOB_CONTINUE;
8449
8450 ENTER;
8451 if (shutdown_type != IPR_SHUTDOWN_NONE &&
8452 !ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
8453 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
8454 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
8455 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN;
8456 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = shutdown_type;
8457
8458 if (shutdown_type == IPR_SHUTDOWN_NORMAL)
8459 timeout = IPR_SHUTDOWN_TIMEOUT;
8460 else if (shutdown_type == IPR_SHUTDOWN_PREPARE_FOR_NORMAL)
8461 timeout = IPR_INTERNAL_TIMEOUT;
8462 else if (ioa_cfg->dual_raid && ipr_dual_ioa_raid)
8463 timeout = IPR_DUAL_IOA_ABBR_SHUTDOWN_TO;
8464 else
8465 timeout = IPR_ABBREV_SHUTDOWN_TIMEOUT;
8466
8467 ipr_do_req(ipr_cmd, ipr_reset_ioa_job, ipr_timeout, timeout);
8468
8469 rc = IPR_RC_JOB_RETURN;
8470 ipr_cmd->job_step = ipr_reset_ucode_download;
8471 } else
8472 ipr_cmd->job_step = ipr_reset_alert;
8473
8474 LEAVE;
8475 return rc;
8476}
8477
8478
8479
8480
8481
8482
8483
8484
8485
8486
8487static void ipr_reset_ioa_job(struct ipr_cmnd *ipr_cmd)
8488{
8489 u32 rc, ioasc;
8490 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8491
8492 do {
8493 ioasc = be32_to_cpu(ipr_cmd->s.ioasa.hdr.ioasc);
8494
8495 if (ioa_cfg->reset_cmd != ipr_cmd) {
8496
8497
8498
8499
8500 list_add_tail(&ipr_cmd->queue,
8501 &ipr_cmd->hrrq->hrrq_free_q);
8502 return;
8503 }
8504
8505 if (IPR_IOASC_SENSE_KEY(ioasc)) {
8506 rc = ipr_cmd->job_step_failed(ipr_cmd);
8507 if (rc == IPR_RC_JOB_RETURN)
8508 return;
8509 }
8510
8511 ipr_reinit_ipr_cmnd(ipr_cmd);
8512 ipr_cmd->job_step_failed = ipr_reset_cmd_failed;
8513 rc = ipr_cmd->job_step(ipr_cmd);
8514 } while (rc == IPR_RC_JOB_CONTINUE);
8515}
8516
8517
8518
8519
8520
8521
8522
8523
8524
8525
8526
8527
8528
8529
8530
8531static void _ipr_initiate_ioa_reset(struct ipr_ioa_cfg *ioa_cfg,
8532 int (*job_step) (struct ipr_cmnd *),
8533 enum ipr_shutdown_type shutdown_type)
8534{
8535 struct ipr_cmnd *ipr_cmd;
8536 int i;
8537
8538 ioa_cfg->in_reset_reload = 1;
8539 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
8540 spin_lock(&ioa_cfg->hrrq[i]._lock);
8541 ioa_cfg->hrrq[i].allow_cmds = 0;
8542 spin_unlock(&ioa_cfg->hrrq[i]._lock);
8543 }
8544 wmb();
8545 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa)
8546 scsi_block_requests(ioa_cfg->host);
8547
8548 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
8549 ioa_cfg->reset_cmd = ipr_cmd;
8550 ipr_cmd->job_step = job_step;
8551 ipr_cmd->u.shutdown_type = shutdown_type;
8552
8553 ipr_reset_ioa_job(ipr_cmd);
8554}
8555
8556
8557
8558
8559
8560
8561
8562
8563
8564
8565
8566
8567
8568static void ipr_initiate_ioa_reset(struct ipr_ioa_cfg *ioa_cfg,
8569 enum ipr_shutdown_type shutdown_type)
8570{
8571 int i;
8572
8573 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead)
8574 return;
8575
8576 if (ioa_cfg->in_reset_reload) {
8577 if (ioa_cfg->sdt_state == GET_DUMP)
8578 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
8579 else if (ioa_cfg->sdt_state == READ_DUMP)
8580 ioa_cfg->sdt_state = ABORT_DUMP;
8581 }
8582
8583 if (ioa_cfg->reset_retries++ >= IPR_NUM_RESET_RELOAD_RETRIES) {
8584 dev_err(&ioa_cfg->pdev->dev,
8585 "IOA taken offline - error recovery failed\n");
8586
8587 ioa_cfg->reset_retries = 0;
8588 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
8589 spin_lock(&ioa_cfg->hrrq[i]._lock);
8590 ioa_cfg->hrrq[i].ioa_is_dead = 1;
8591 spin_unlock(&ioa_cfg->hrrq[i]._lock);
8592 }
8593 wmb();
8594
8595 if (ioa_cfg->in_ioa_bringdown) {
8596 ioa_cfg->reset_cmd = NULL;
8597 ioa_cfg->in_reset_reload = 0;
8598 ipr_fail_all_ops(ioa_cfg);
8599 wake_up_all(&ioa_cfg->reset_wait_q);
8600
8601 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].removing_ioa) {
8602 spin_unlock_irq(ioa_cfg->host->host_lock);
8603 scsi_unblock_requests(ioa_cfg->host);
8604 spin_lock_irq(ioa_cfg->host->host_lock);
8605 }
8606 return;
8607 } else {
8608 ioa_cfg->in_ioa_bringdown = 1;
8609 shutdown_type = IPR_SHUTDOWN_NONE;
8610 }
8611 }
8612
8613 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_shutdown_ioa,
8614 shutdown_type);
8615}
8616
8617
8618
8619
8620
8621
8622
8623
8624
8625static int ipr_reset_freeze(struct ipr_cmnd *ipr_cmd)
8626{
8627 struct ipr_ioa_cfg *ioa_cfg = ipr_cmd->ioa_cfg;
8628 int i;
8629
8630
8631 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
8632 spin_lock(&ioa_cfg->hrrq[i]._lock);
8633 ioa_cfg->hrrq[i].allow_interrupts = 0;
8634 spin_unlock(&ioa_cfg->hrrq[i]._lock);
8635 }
8636 wmb();
8637 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_pending_q);
8638 ipr_cmd->done = ipr_reset_ioa_job;
8639 return IPR_RC_JOB_RETURN;
8640}
8641
8642
8643
8644
8645
8646
8647
8648
8649
8650static void ipr_pci_frozen(struct pci_dev *pdev)
8651{
8652 unsigned long flags = 0;
8653 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
8654
8655 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
8656 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_freeze, IPR_SHUTDOWN_NONE);
8657 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
8658}
8659
8660
8661
8662
8663
8664
8665
8666
8667
8668static pci_ers_result_t ipr_pci_slot_reset(struct pci_dev *pdev)
8669{
8670 unsigned long flags = 0;
8671 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
8672
8673 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
8674 if (ioa_cfg->needs_warm_reset)
8675 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
8676 else
8677 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_restore_cfg_space,
8678 IPR_SHUTDOWN_NONE);
8679 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
8680 return PCI_ERS_RESULT_RECOVERED;
8681}
8682
8683
8684
8685
8686
8687
8688
8689
8690static void ipr_pci_perm_failure(struct pci_dev *pdev)
8691{
8692 unsigned long flags = 0;
8693 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
8694 int i;
8695
8696 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
8697 if (ioa_cfg->sdt_state == WAIT_FOR_DUMP)
8698 ioa_cfg->sdt_state = ABORT_DUMP;
8699 ioa_cfg->reset_retries = IPR_NUM_RESET_RELOAD_RETRIES - 1;
8700 ioa_cfg->in_ioa_bringdown = 1;
8701 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
8702 spin_lock(&ioa_cfg->hrrq[i]._lock);
8703 ioa_cfg->hrrq[i].allow_cmds = 0;
8704 spin_unlock(&ioa_cfg->hrrq[i]._lock);
8705 }
8706 wmb();
8707 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
8708 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
8709}
8710
8711
8712
8713
8714
8715
8716
8717
8718
8719
8720
8721static pci_ers_result_t ipr_pci_error_detected(struct pci_dev *pdev,
8722 pci_channel_state_t state)
8723{
8724 switch (state) {
8725 case pci_channel_io_frozen:
8726 ipr_pci_frozen(pdev);
8727 return PCI_ERS_RESULT_NEED_RESET;
8728 case pci_channel_io_perm_failure:
8729 ipr_pci_perm_failure(pdev);
8730 return PCI_ERS_RESULT_DISCONNECT;
8731 break;
8732 default:
8733 break;
8734 }
8735 return PCI_ERS_RESULT_NEED_RESET;
8736}
8737
8738
8739
8740
8741
8742
8743
8744
8745
8746
8747
8748
8749static int ipr_probe_ioa_part2(struct ipr_ioa_cfg *ioa_cfg)
8750{
8751 int rc = 0;
8752 unsigned long host_lock_flags = 0;
8753
8754 ENTER;
8755 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
8756 dev_dbg(&ioa_cfg->pdev->dev, "ioa_cfg adx: 0x%p\n", ioa_cfg);
8757 if (ioa_cfg->needs_hard_reset) {
8758 ioa_cfg->needs_hard_reset = 0;
8759 ipr_initiate_ioa_reset(ioa_cfg, IPR_SHUTDOWN_NONE);
8760 } else
8761 _ipr_initiate_ioa_reset(ioa_cfg, ipr_reset_enable_ioa,
8762 IPR_SHUTDOWN_NONE);
8763 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
8764 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
8765 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
8766
8767 if (ioa_cfg->hrrq[IPR_INIT_HRRQ].ioa_is_dead) {
8768 rc = -EIO;
8769 } else if (ipr_invalid_adapter(ioa_cfg)) {
8770 if (!ipr_testmode)
8771 rc = -EIO;
8772
8773 dev_err(&ioa_cfg->pdev->dev,
8774 "Adapter not supported in this hardware configuration.\n");
8775 }
8776
8777 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
8778
8779 LEAVE;
8780 return rc;
8781}
8782
8783
8784
8785
8786
8787
8788
8789
8790static void ipr_free_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
8791{
8792 int i;
8793
8794 for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
8795 if (ioa_cfg->ipr_cmnd_list[i])
8796 pci_pool_free(ioa_cfg->ipr_cmd_pool,
8797 ioa_cfg->ipr_cmnd_list[i],
8798 ioa_cfg->ipr_cmnd_list_dma[i]);
8799
8800 ioa_cfg->ipr_cmnd_list[i] = NULL;
8801 }
8802
8803 if (ioa_cfg->ipr_cmd_pool)
8804 pci_pool_destroy(ioa_cfg->ipr_cmd_pool);
8805
8806 kfree(ioa_cfg->ipr_cmnd_list);
8807 kfree(ioa_cfg->ipr_cmnd_list_dma);
8808 ioa_cfg->ipr_cmnd_list = NULL;
8809 ioa_cfg->ipr_cmnd_list_dma = NULL;
8810 ioa_cfg->ipr_cmd_pool = NULL;
8811}
8812
8813
8814
8815
8816
8817
8818
8819
8820static void ipr_free_mem(struct ipr_ioa_cfg *ioa_cfg)
8821{
8822 int i;
8823
8824 kfree(ioa_cfg->res_entries);
8825 pci_free_consistent(ioa_cfg->pdev, sizeof(struct ipr_misc_cbs),
8826 ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
8827 ipr_free_cmd_blks(ioa_cfg);
8828
8829 for (i = 0; i < ioa_cfg->hrrq_num; i++)
8830 pci_free_consistent(ioa_cfg->pdev,
8831 sizeof(u32) * ioa_cfg->hrrq[i].size,
8832 ioa_cfg->hrrq[i].host_rrq,
8833 ioa_cfg->hrrq[i].host_rrq_dma);
8834
8835 pci_free_consistent(ioa_cfg->pdev, ioa_cfg->cfg_table_size,
8836 ioa_cfg->u.cfg_table,
8837 ioa_cfg->cfg_table_dma);
8838
8839 for (i = 0; i < IPR_NUM_HCAMS; i++) {
8840 pci_free_consistent(ioa_cfg->pdev,
8841 sizeof(struct ipr_hostrcb),
8842 ioa_cfg->hostrcb[i],
8843 ioa_cfg->hostrcb_dma[i]);
8844 }
8845
8846 ipr_free_dump(ioa_cfg);
8847 kfree(ioa_cfg->trace);
8848}
8849
8850
8851
8852
8853
8854
8855
8856
8857
8858
8859
8860static void ipr_free_all_resources(struct ipr_ioa_cfg *ioa_cfg)
8861{
8862 struct pci_dev *pdev = ioa_cfg->pdev;
8863
8864 ENTER;
8865 if (ioa_cfg->intr_flag == IPR_USE_MSI ||
8866 ioa_cfg->intr_flag == IPR_USE_MSIX) {
8867 int i;
8868 for (i = 0; i < ioa_cfg->nvectors; i++)
8869 free_irq(ioa_cfg->vectors_info[i].vec,
8870 &ioa_cfg->hrrq[i]);
8871 } else
8872 free_irq(pdev->irq, &ioa_cfg->hrrq[0]);
8873
8874 if (ioa_cfg->intr_flag == IPR_USE_MSI) {
8875 pci_disable_msi(pdev);
8876 ioa_cfg->intr_flag &= ~IPR_USE_MSI;
8877 } else if (ioa_cfg->intr_flag == IPR_USE_MSIX) {
8878 pci_disable_msix(pdev);
8879 ioa_cfg->intr_flag &= ~IPR_USE_MSIX;
8880 }
8881
8882 iounmap(ioa_cfg->hdw_dma_regs);
8883 pci_release_regions(pdev);
8884 ipr_free_mem(ioa_cfg);
8885 scsi_host_put(ioa_cfg->host);
8886 pci_disable_device(pdev);
8887 LEAVE;
8888}
8889
8890
8891
8892
8893
8894
8895
8896
8897static int ipr_alloc_cmd_blks(struct ipr_ioa_cfg *ioa_cfg)
8898{
8899 struct ipr_cmnd *ipr_cmd;
8900 struct ipr_ioarcb *ioarcb;
8901 dma_addr_t dma_addr;
8902 int i, entries_each_hrrq, hrrq_id = 0;
8903
8904 ioa_cfg->ipr_cmd_pool = pci_pool_create(IPR_NAME, ioa_cfg->pdev,
8905 sizeof(struct ipr_cmnd), 512, 0);
8906
8907 if (!ioa_cfg->ipr_cmd_pool)
8908 return -ENOMEM;
8909
8910 ioa_cfg->ipr_cmnd_list = kcalloc(IPR_NUM_CMD_BLKS, sizeof(struct ipr_cmnd *), GFP_KERNEL);
8911 ioa_cfg->ipr_cmnd_list_dma = kcalloc(IPR_NUM_CMD_BLKS, sizeof(dma_addr_t), GFP_KERNEL);
8912
8913 if (!ioa_cfg->ipr_cmnd_list || !ioa_cfg->ipr_cmnd_list_dma) {
8914 ipr_free_cmd_blks(ioa_cfg);
8915 return -ENOMEM;
8916 }
8917
8918 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
8919 if (ioa_cfg->hrrq_num > 1) {
8920 if (i == 0) {
8921 entries_each_hrrq = IPR_NUM_INTERNAL_CMD_BLKS;
8922 ioa_cfg->hrrq[i].min_cmd_id = 0;
8923 ioa_cfg->hrrq[i].max_cmd_id =
8924 (entries_each_hrrq - 1);
8925 } else {
8926 entries_each_hrrq =
8927 IPR_NUM_BASE_CMD_BLKS/
8928 (ioa_cfg->hrrq_num - 1);
8929 ioa_cfg->hrrq[i].min_cmd_id =
8930 IPR_NUM_INTERNAL_CMD_BLKS +
8931 (i - 1) * entries_each_hrrq;
8932 ioa_cfg->hrrq[i].max_cmd_id =
8933 (IPR_NUM_INTERNAL_CMD_BLKS +
8934 i * entries_each_hrrq - 1);
8935 }
8936 } else {
8937 entries_each_hrrq = IPR_NUM_CMD_BLKS;
8938 ioa_cfg->hrrq[i].min_cmd_id = 0;
8939 ioa_cfg->hrrq[i].max_cmd_id = (entries_each_hrrq - 1);
8940 }
8941 ioa_cfg->hrrq[i].size = entries_each_hrrq;
8942 }
8943
8944 BUG_ON(ioa_cfg->hrrq_num == 0);
8945
8946 i = IPR_NUM_CMD_BLKS -
8947 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].max_cmd_id - 1;
8948 if (i > 0) {
8949 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].size += i;
8950 ioa_cfg->hrrq[ioa_cfg->hrrq_num - 1].max_cmd_id += i;
8951 }
8952
8953 for (i = 0; i < IPR_NUM_CMD_BLKS; i++) {
8954 ipr_cmd = pci_pool_alloc(ioa_cfg->ipr_cmd_pool, GFP_KERNEL, &dma_addr);
8955
8956 if (!ipr_cmd) {
8957 ipr_free_cmd_blks(ioa_cfg);
8958 return -ENOMEM;
8959 }
8960
8961 memset(ipr_cmd, 0, sizeof(*ipr_cmd));
8962 ioa_cfg->ipr_cmnd_list[i] = ipr_cmd;
8963 ioa_cfg->ipr_cmnd_list_dma[i] = dma_addr;
8964
8965 ioarcb = &ipr_cmd->ioarcb;
8966 ipr_cmd->dma_addr = dma_addr;
8967 if (ioa_cfg->sis64)
8968 ioarcb->a.ioarcb_host_pci_addr64 = cpu_to_be64(dma_addr);
8969 else
8970 ioarcb->a.ioarcb_host_pci_addr = cpu_to_be32(dma_addr);
8971
8972 ioarcb->host_response_handle = cpu_to_be32(i << 2);
8973 if (ioa_cfg->sis64) {
8974 ioarcb->u.sis64_addr_data.data_ioadl_addr =
8975 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, i.ioadl64));
8976 ioarcb->u.sis64_addr_data.ioasa_host_pci_addr =
8977 cpu_to_be64(dma_addr + offsetof(struct ipr_cmnd, s.ioasa64));
8978 } else {
8979 ioarcb->write_ioadl_addr =
8980 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, i.ioadl));
8981 ioarcb->read_ioadl_addr = ioarcb->write_ioadl_addr;
8982 ioarcb->ioasa_host_pci_addr =
8983 cpu_to_be32(dma_addr + offsetof(struct ipr_cmnd, s.ioasa));
8984 }
8985 ioarcb->ioasa_len = cpu_to_be16(sizeof(struct ipr_ioasa));
8986 ipr_cmd->cmd_index = i;
8987 ipr_cmd->ioa_cfg = ioa_cfg;
8988 ipr_cmd->sense_buffer_dma = dma_addr +
8989 offsetof(struct ipr_cmnd, sense_buffer);
8990
8991 ipr_cmd->ioarcb.cmd_pkt.hrrq_id = hrrq_id;
8992 ipr_cmd->hrrq = &ioa_cfg->hrrq[hrrq_id];
8993 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
8994 if (i >= ioa_cfg->hrrq[hrrq_id].max_cmd_id)
8995 hrrq_id++;
8996 }
8997
8998 return 0;
8999}
9000
9001
9002
9003
9004
9005
9006
9007
9008static int ipr_alloc_mem(struct ipr_ioa_cfg *ioa_cfg)
9009{
9010 struct pci_dev *pdev = ioa_cfg->pdev;
9011 int i, rc = -ENOMEM;
9012
9013 ENTER;
9014 ioa_cfg->res_entries = kzalloc(sizeof(struct ipr_resource_entry) *
9015 ioa_cfg->max_devs_supported, GFP_KERNEL);
9016
9017 if (!ioa_cfg->res_entries)
9018 goto out;
9019
9020 for (i = 0; i < ioa_cfg->max_devs_supported; i++) {
9021 list_add_tail(&ioa_cfg->res_entries[i].queue, &ioa_cfg->free_res_q);
9022 ioa_cfg->res_entries[i].ioa_cfg = ioa_cfg;
9023 }
9024
9025 ioa_cfg->vpd_cbs = pci_alloc_consistent(ioa_cfg->pdev,
9026 sizeof(struct ipr_misc_cbs),
9027 &ioa_cfg->vpd_cbs_dma);
9028
9029 if (!ioa_cfg->vpd_cbs)
9030 goto out_free_res_entries;
9031
9032 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9033 INIT_LIST_HEAD(&ioa_cfg->hrrq[i].hrrq_free_q);
9034 INIT_LIST_HEAD(&ioa_cfg->hrrq[i].hrrq_pending_q);
9035 spin_lock_init(&ioa_cfg->hrrq[i]._lock);
9036 if (i == 0)
9037 ioa_cfg->hrrq[i].lock = ioa_cfg->host->host_lock;
9038 else
9039 ioa_cfg->hrrq[i].lock = &ioa_cfg->hrrq[i]._lock;
9040 }
9041
9042 if (ipr_alloc_cmd_blks(ioa_cfg))
9043 goto out_free_vpd_cbs;
9044
9045 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9046 ioa_cfg->hrrq[i].host_rrq = pci_alloc_consistent(ioa_cfg->pdev,
9047 sizeof(u32) * ioa_cfg->hrrq[i].size,
9048 &ioa_cfg->hrrq[i].host_rrq_dma);
9049
9050 if (!ioa_cfg->hrrq[i].host_rrq) {
9051 while (--i > 0)
9052 pci_free_consistent(pdev,
9053 sizeof(u32) * ioa_cfg->hrrq[i].size,
9054 ioa_cfg->hrrq[i].host_rrq,
9055 ioa_cfg->hrrq[i].host_rrq_dma);
9056 goto out_ipr_free_cmd_blocks;
9057 }
9058 ioa_cfg->hrrq[i].ioa_cfg = ioa_cfg;
9059 }
9060
9061 ioa_cfg->u.cfg_table = pci_alloc_consistent(ioa_cfg->pdev,
9062 ioa_cfg->cfg_table_size,
9063 &ioa_cfg->cfg_table_dma);
9064
9065 if (!ioa_cfg->u.cfg_table)
9066 goto out_free_host_rrq;
9067
9068 for (i = 0; i < IPR_NUM_HCAMS; i++) {
9069 ioa_cfg->hostrcb[i] = pci_alloc_consistent(ioa_cfg->pdev,
9070 sizeof(struct ipr_hostrcb),
9071 &ioa_cfg->hostrcb_dma[i]);
9072
9073 if (!ioa_cfg->hostrcb[i])
9074 goto out_free_hostrcb_dma;
9075
9076 ioa_cfg->hostrcb[i]->hostrcb_dma =
9077 ioa_cfg->hostrcb_dma[i] + offsetof(struct ipr_hostrcb, hcam);
9078 ioa_cfg->hostrcb[i]->ioa_cfg = ioa_cfg;
9079 list_add_tail(&ioa_cfg->hostrcb[i]->queue, &ioa_cfg->hostrcb_free_q);
9080 }
9081
9082 ioa_cfg->trace = kzalloc(sizeof(struct ipr_trace_entry) *
9083 IPR_NUM_TRACE_ENTRIES, GFP_KERNEL);
9084
9085 if (!ioa_cfg->trace)
9086 goto out_free_hostrcb_dma;
9087
9088 rc = 0;
9089out:
9090 LEAVE;
9091 return rc;
9092
9093out_free_hostrcb_dma:
9094 while (i-- > 0) {
9095 pci_free_consistent(pdev, sizeof(struct ipr_hostrcb),
9096 ioa_cfg->hostrcb[i],
9097 ioa_cfg->hostrcb_dma[i]);
9098 }
9099 pci_free_consistent(pdev, ioa_cfg->cfg_table_size,
9100 ioa_cfg->u.cfg_table,
9101 ioa_cfg->cfg_table_dma);
9102out_free_host_rrq:
9103 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9104 pci_free_consistent(pdev,
9105 sizeof(u32) * ioa_cfg->hrrq[i].size,
9106 ioa_cfg->hrrq[i].host_rrq,
9107 ioa_cfg->hrrq[i].host_rrq_dma);
9108 }
9109out_ipr_free_cmd_blocks:
9110 ipr_free_cmd_blks(ioa_cfg);
9111out_free_vpd_cbs:
9112 pci_free_consistent(pdev, sizeof(struct ipr_misc_cbs),
9113 ioa_cfg->vpd_cbs, ioa_cfg->vpd_cbs_dma);
9114out_free_res_entries:
9115 kfree(ioa_cfg->res_entries);
9116 goto out;
9117}
9118
9119
9120
9121
9122
9123
9124
9125
9126static void ipr_initialize_bus_attr(struct ipr_ioa_cfg *ioa_cfg)
9127{
9128 int i;
9129
9130 for (i = 0; i < IPR_MAX_NUM_BUSES; i++) {
9131 ioa_cfg->bus_attr[i].bus = i;
9132 ioa_cfg->bus_attr[i].qas_enabled = 0;
9133 ioa_cfg->bus_attr[i].bus_width = IPR_DEFAULT_BUS_WIDTH;
9134 if (ipr_max_speed < ARRAY_SIZE(ipr_max_bus_speeds))
9135 ioa_cfg->bus_attr[i].max_xfer_rate = ipr_max_bus_speeds[ipr_max_speed];
9136 else
9137 ioa_cfg->bus_attr[i].max_xfer_rate = IPR_U160_SCSI_RATE;
9138 }
9139}
9140
9141
9142
9143
9144
9145
9146
9147
9148
9149
9150static void ipr_init_ioa_cfg(struct ipr_ioa_cfg *ioa_cfg,
9151 struct Scsi_Host *host, struct pci_dev *pdev)
9152{
9153 const struct ipr_interrupt_offsets *p;
9154 struct ipr_interrupts *t;
9155 void __iomem *base;
9156
9157 ioa_cfg->host = host;
9158 ioa_cfg->pdev = pdev;
9159 ioa_cfg->log_level = ipr_log_level;
9160 ioa_cfg->doorbell = IPR_DOORBELL;
9161 sprintf(ioa_cfg->eye_catcher, IPR_EYECATCHER);
9162 sprintf(ioa_cfg->trace_start, IPR_TRACE_START_LABEL);
9163 sprintf(ioa_cfg->cfg_table_start, IPR_CFG_TBL_START);
9164 sprintf(ioa_cfg->resource_table_label, IPR_RES_TABLE_LABEL);
9165 sprintf(ioa_cfg->ipr_hcam_label, IPR_HCAM_LABEL);
9166 sprintf(ioa_cfg->ipr_cmd_label, IPR_CMD_LABEL);
9167
9168 INIT_LIST_HEAD(&ioa_cfg->hostrcb_free_q);
9169 INIT_LIST_HEAD(&ioa_cfg->hostrcb_pending_q);
9170 INIT_LIST_HEAD(&ioa_cfg->free_res_q);
9171 INIT_LIST_HEAD(&ioa_cfg->used_res_q);
9172 INIT_WORK(&ioa_cfg->work_q, ipr_worker_thread);
9173 init_waitqueue_head(&ioa_cfg->reset_wait_q);
9174 init_waitqueue_head(&ioa_cfg->msi_wait_q);
9175 ioa_cfg->sdt_state = INACTIVE;
9176
9177 ipr_initialize_bus_attr(ioa_cfg);
9178 ioa_cfg->max_devs_supported = ipr_max_devs;
9179
9180 if (ioa_cfg->sis64) {
9181 host->max_id = IPR_MAX_SIS64_TARGETS_PER_BUS;
9182 host->max_lun = IPR_MAX_SIS64_LUNS_PER_TARGET;
9183 if (ipr_max_devs > IPR_MAX_SIS64_DEVS)
9184 ioa_cfg->max_devs_supported = IPR_MAX_SIS64_DEVS;
9185 } else {
9186 host->max_id = IPR_MAX_NUM_TARGETS_PER_BUS;
9187 host->max_lun = IPR_MAX_NUM_LUNS_PER_TARGET;
9188 if (ipr_max_devs > IPR_MAX_PHYSICAL_DEVS)
9189 ioa_cfg->max_devs_supported = IPR_MAX_PHYSICAL_DEVS;
9190 }
9191 host->max_channel = IPR_MAX_BUS_TO_SCAN;
9192 host->unique_id = host->host_no;
9193 host->max_cmd_len = IPR_MAX_CDB_LEN;
9194 host->can_queue = ioa_cfg->max_cmds;
9195 pci_set_drvdata(pdev, ioa_cfg);
9196
9197 p = &ioa_cfg->chip_cfg->regs;
9198 t = &ioa_cfg->regs;
9199 base = ioa_cfg->hdw_dma_regs;
9200
9201 t->set_interrupt_mask_reg = base + p->set_interrupt_mask_reg;
9202 t->clr_interrupt_mask_reg = base + p->clr_interrupt_mask_reg;
9203 t->clr_interrupt_mask_reg32 = base + p->clr_interrupt_mask_reg32;
9204 t->sense_interrupt_mask_reg = base + p->sense_interrupt_mask_reg;
9205 t->sense_interrupt_mask_reg32 = base + p->sense_interrupt_mask_reg32;
9206 t->clr_interrupt_reg = base + p->clr_interrupt_reg;
9207 t->clr_interrupt_reg32 = base + p->clr_interrupt_reg32;
9208 t->sense_interrupt_reg = base + p->sense_interrupt_reg;
9209 t->sense_interrupt_reg32 = base + p->sense_interrupt_reg32;
9210 t->ioarrin_reg = base + p->ioarrin_reg;
9211 t->sense_uproc_interrupt_reg = base + p->sense_uproc_interrupt_reg;
9212 t->sense_uproc_interrupt_reg32 = base + p->sense_uproc_interrupt_reg32;
9213 t->set_uproc_interrupt_reg = base + p->set_uproc_interrupt_reg;
9214 t->set_uproc_interrupt_reg32 = base + p->set_uproc_interrupt_reg32;
9215 t->clr_uproc_interrupt_reg = base + p->clr_uproc_interrupt_reg;
9216 t->clr_uproc_interrupt_reg32 = base + p->clr_uproc_interrupt_reg32;
9217
9218 if (ioa_cfg->sis64) {
9219 t->init_feedback_reg = base + p->init_feedback_reg;
9220 t->dump_addr_reg = base + p->dump_addr_reg;
9221 t->dump_data_reg = base + p->dump_data_reg;
9222 t->endian_swap_reg = base + p->endian_swap_reg;
9223 }
9224}
9225
9226
9227
9228
9229
9230
9231
9232
9233static const struct ipr_chip_t *
9234ipr_get_chip_info(const struct pci_device_id *dev_id)
9235{
9236 int i;
9237
9238 for (i = 0; i < ARRAY_SIZE(ipr_chip); i++)
9239 if (ipr_chip[i].vendor == dev_id->vendor &&
9240 ipr_chip[i].device == dev_id->device)
9241 return &ipr_chip[i];
9242 return NULL;
9243}
9244
9245static int ipr_enable_msix(struct ipr_ioa_cfg *ioa_cfg)
9246{
9247 struct msix_entry entries[IPR_MAX_MSIX_VECTORS];
9248 int i, err, vectors;
9249
9250 for (i = 0; i < ARRAY_SIZE(entries); ++i)
9251 entries[i].entry = i;
9252
9253 vectors = ipr_number_of_msix;
9254
9255 while ((err = pci_enable_msix(ioa_cfg->pdev, entries, vectors)) > 0)
9256 vectors = err;
9257
9258 if (err < 0) {
9259 pci_disable_msix(ioa_cfg->pdev);
9260 return err;
9261 }
9262
9263 if (!err) {
9264 for (i = 0; i < vectors; i++)
9265 ioa_cfg->vectors_info[i].vec = entries[i].vector;
9266 ioa_cfg->nvectors = vectors;
9267 }
9268
9269 return err;
9270}
9271
9272static int ipr_enable_msi(struct ipr_ioa_cfg *ioa_cfg)
9273{
9274 int i, err, vectors;
9275
9276 vectors = ipr_number_of_msix;
9277
9278 while ((err = pci_enable_msi_block(ioa_cfg->pdev, vectors)) > 0)
9279 vectors = err;
9280
9281 if (err < 0) {
9282 pci_disable_msi(ioa_cfg->pdev);
9283 return err;
9284 }
9285
9286 if (!err) {
9287 for (i = 0; i < vectors; i++)
9288 ioa_cfg->vectors_info[i].vec = ioa_cfg->pdev->irq + i;
9289 ioa_cfg->nvectors = vectors;
9290 }
9291
9292 return err;
9293}
9294
9295static void name_msi_vectors(struct ipr_ioa_cfg *ioa_cfg)
9296{
9297 int vec_idx, n = sizeof(ioa_cfg->vectors_info[0].desc) - 1;
9298
9299 for (vec_idx = 0; vec_idx < ioa_cfg->nvectors; vec_idx++) {
9300 snprintf(ioa_cfg->vectors_info[vec_idx].desc, n,
9301 "host%d-%d", ioa_cfg->host->host_no, vec_idx);
9302 ioa_cfg->vectors_info[vec_idx].
9303 desc[strlen(ioa_cfg->vectors_info[vec_idx].desc)] = 0;
9304 }
9305}
9306
9307static int ipr_request_other_msi_irqs(struct ipr_ioa_cfg *ioa_cfg)
9308{
9309 int i, rc;
9310
9311 for (i = 1; i < ioa_cfg->nvectors; i++) {
9312 rc = request_irq(ioa_cfg->vectors_info[i].vec,
9313 ipr_isr_mhrrq,
9314 0,
9315 ioa_cfg->vectors_info[i].desc,
9316 &ioa_cfg->hrrq[i]);
9317 if (rc) {
9318 while (--i >= 0)
9319 free_irq(ioa_cfg->vectors_info[i].vec,
9320 &ioa_cfg->hrrq[i]);
9321 return rc;
9322 }
9323 }
9324 return 0;
9325}
9326
9327
9328
9329
9330
9331
9332
9333
9334
9335
9336
9337static irqreturn_t ipr_test_intr(int irq, void *devp)
9338{
9339 struct ipr_ioa_cfg *ioa_cfg = (struct ipr_ioa_cfg *)devp;
9340 unsigned long lock_flags = 0;
9341 irqreturn_t rc = IRQ_HANDLED;
9342
9343 dev_info(&ioa_cfg->pdev->dev, "Received IRQ : %d\n", irq);
9344 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9345
9346 ioa_cfg->msi_received = 1;
9347 wake_up(&ioa_cfg->msi_wait_q);
9348
9349 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9350 return rc;
9351}
9352
9353
9354
9355
9356
9357
9358
9359
9360
9361
9362
9363
9364
9365static int ipr_test_msi(struct ipr_ioa_cfg *ioa_cfg, struct pci_dev *pdev)
9366{
9367 int rc;
9368 volatile u32 int_reg;
9369 unsigned long lock_flags = 0;
9370
9371 ENTER;
9372
9373 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9374 init_waitqueue_head(&ioa_cfg->msi_wait_q);
9375 ioa_cfg->msi_received = 0;
9376 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
9377 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.clr_interrupt_mask_reg32);
9378 int_reg = readl(ioa_cfg->regs.sense_interrupt_mask_reg);
9379 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9380
9381 if (ioa_cfg->intr_flag == IPR_USE_MSIX)
9382 rc = request_irq(ioa_cfg->vectors_info[0].vec, ipr_test_intr, 0, IPR_NAME, ioa_cfg);
9383 else
9384 rc = request_irq(pdev->irq, ipr_test_intr, 0, IPR_NAME, ioa_cfg);
9385 if (rc) {
9386 dev_err(&pdev->dev, "Can not assign irq %d\n", pdev->irq);
9387 return rc;
9388 } else if (ipr_debug)
9389 dev_info(&pdev->dev, "IRQ assigned: %d\n", pdev->irq);
9390
9391 writel(IPR_PCII_IO_DEBUG_ACKNOWLEDGE, ioa_cfg->regs.sense_interrupt_reg32);
9392 int_reg = readl(ioa_cfg->regs.sense_interrupt_reg);
9393 wait_event_timeout(ioa_cfg->msi_wait_q, ioa_cfg->msi_received, HZ);
9394 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9395 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
9396
9397 if (!ioa_cfg->msi_received) {
9398
9399 dev_info(&pdev->dev, "MSI test failed. Falling back to LSI.\n");
9400 rc = -EOPNOTSUPP;
9401 } else if (ipr_debug)
9402 dev_info(&pdev->dev, "MSI test succeeded.\n");
9403
9404 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9405
9406 if (ioa_cfg->intr_flag == IPR_USE_MSIX)
9407 free_irq(ioa_cfg->vectors_info[0].vec, ioa_cfg);
9408 else
9409 free_irq(pdev->irq, ioa_cfg);
9410
9411 LEAVE;
9412
9413 return rc;
9414}
9415
9416
9417
9418
9419
9420
9421
9422
9423static int ipr_probe_ioa(struct pci_dev *pdev,
9424 const struct pci_device_id *dev_id)
9425{
9426 struct ipr_ioa_cfg *ioa_cfg;
9427 struct Scsi_Host *host;
9428 unsigned long ipr_regs_pci;
9429 void __iomem *ipr_regs;
9430 int rc = PCIBIOS_SUCCESSFUL;
9431 volatile u32 mask, uproc, interrupts;
9432 unsigned long lock_flags, driver_lock_flags;
9433
9434 ENTER;
9435
9436 if ((rc = pci_enable_device(pdev))) {
9437 dev_err(&pdev->dev, "Cannot enable adapter\n");
9438 goto out;
9439 }
9440
9441 dev_info(&pdev->dev, "Found IOA with IRQ: %d\n", pdev->irq);
9442
9443 host = scsi_host_alloc(&driver_template, sizeof(*ioa_cfg));
9444
9445 if (!host) {
9446 dev_err(&pdev->dev, "call to scsi_host_alloc failed!\n");
9447 rc = -ENOMEM;
9448 goto out_disable;
9449 }
9450
9451 ioa_cfg = (struct ipr_ioa_cfg *)host->hostdata;
9452 memset(ioa_cfg, 0, sizeof(struct ipr_ioa_cfg));
9453 ata_host_init(&ioa_cfg->ata_host, &pdev->dev, &ipr_sata_ops);
9454
9455 ioa_cfg->ipr_chip = ipr_get_chip_info(dev_id);
9456
9457 if (!ioa_cfg->ipr_chip) {
9458 dev_err(&pdev->dev, "Unknown adapter chipset 0x%04X 0x%04X\n",
9459 dev_id->vendor, dev_id->device);
9460 goto out_scsi_host_put;
9461 }
9462
9463
9464 ioa_cfg->sis64 = ioa_cfg->ipr_chip->sis_type == IPR_SIS64 ? 1 : 0;
9465 ioa_cfg->chip_cfg = ioa_cfg->ipr_chip->cfg;
9466 ioa_cfg->clear_isr = ioa_cfg->chip_cfg->clear_isr;
9467 ioa_cfg->max_cmds = ioa_cfg->chip_cfg->max_cmds;
9468
9469 if (ipr_transop_timeout)
9470 ioa_cfg->transop_timeout = ipr_transop_timeout;
9471 else if (dev_id->driver_data & IPR_USE_LONG_TRANSOP_TIMEOUT)
9472 ioa_cfg->transop_timeout = IPR_LONG_OPERATIONAL_TIMEOUT;
9473 else
9474 ioa_cfg->transop_timeout = IPR_OPERATIONAL_TIMEOUT;
9475
9476 ioa_cfg->revid = pdev->revision;
9477
9478 ipr_regs_pci = pci_resource_start(pdev, 0);
9479
9480 rc = pci_request_regions(pdev, IPR_NAME);
9481 if (rc < 0) {
9482 dev_err(&pdev->dev,
9483 "Couldn't register memory range of registers\n");
9484 goto out_scsi_host_put;
9485 }
9486
9487 ipr_regs = pci_ioremap_bar(pdev, 0);
9488
9489 if (!ipr_regs) {
9490 dev_err(&pdev->dev,
9491 "Couldn't map memory range of registers\n");
9492 rc = -ENOMEM;
9493 goto out_release_regions;
9494 }
9495
9496 ioa_cfg->hdw_dma_regs = ipr_regs;
9497 ioa_cfg->hdw_dma_regs_pci = ipr_regs_pci;
9498 ioa_cfg->ioa_mailbox = ioa_cfg->chip_cfg->mailbox + ipr_regs;
9499
9500 ipr_init_ioa_cfg(ioa_cfg, host, pdev);
9501
9502 pci_set_master(pdev);
9503
9504 if (ioa_cfg->sis64) {
9505 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
9506 if (rc < 0) {
9507 dev_dbg(&pdev->dev, "Failed to set 64 bit PCI DMA mask\n");
9508 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9509 }
9510
9511 } else
9512 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
9513
9514 if (rc < 0) {
9515 dev_err(&pdev->dev, "Failed to set PCI DMA mask\n");
9516 goto cleanup_nomem;
9517 }
9518
9519 rc = pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
9520 ioa_cfg->chip_cfg->cache_line_size);
9521
9522 if (rc != PCIBIOS_SUCCESSFUL) {
9523 dev_err(&pdev->dev, "Write of cache line size failed\n");
9524 rc = -EIO;
9525 goto cleanup_nomem;
9526 }
9527
9528 if (ipr_number_of_msix > IPR_MAX_MSIX_VECTORS) {
9529 dev_err(&pdev->dev, "The max number of MSIX is %d\n",
9530 IPR_MAX_MSIX_VECTORS);
9531 ipr_number_of_msix = IPR_MAX_MSIX_VECTORS;
9532 }
9533
9534 if (ioa_cfg->ipr_chip->intr_type == IPR_USE_MSI &&
9535 ipr_enable_msix(ioa_cfg) == 0)
9536 ioa_cfg->intr_flag = IPR_USE_MSIX;
9537 else if (ioa_cfg->ipr_chip->intr_type == IPR_USE_MSI &&
9538 ipr_enable_msi(ioa_cfg) == 0)
9539 ioa_cfg->intr_flag = IPR_USE_MSI;
9540 else {
9541 ioa_cfg->intr_flag = IPR_USE_LSI;
9542 ioa_cfg->nvectors = 1;
9543 dev_info(&pdev->dev, "Cannot enable MSI.\n");
9544 }
9545
9546 if (ioa_cfg->intr_flag == IPR_USE_MSI ||
9547 ioa_cfg->intr_flag == IPR_USE_MSIX) {
9548 rc = ipr_test_msi(ioa_cfg, pdev);
9549 if (rc == -EOPNOTSUPP) {
9550 if (ioa_cfg->intr_flag == IPR_USE_MSI) {
9551 ioa_cfg->intr_flag &= ~IPR_USE_MSI;
9552 pci_disable_msi(pdev);
9553 } else if (ioa_cfg->intr_flag == IPR_USE_MSIX) {
9554 ioa_cfg->intr_flag &= ~IPR_USE_MSIX;
9555 pci_disable_msix(pdev);
9556 }
9557
9558 ioa_cfg->intr_flag = IPR_USE_LSI;
9559 ioa_cfg->nvectors = 1;
9560 }
9561 else if (rc)
9562 goto out_msi_disable;
9563 else {
9564 if (ioa_cfg->intr_flag == IPR_USE_MSI)
9565 dev_info(&pdev->dev,
9566 "Request for %d MSIs succeeded with starting IRQ: %d\n",
9567 ioa_cfg->nvectors, pdev->irq);
9568 else if (ioa_cfg->intr_flag == IPR_USE_MSIX)
9569 dev_info(&pdev->dev,
9570 "Request for %d MSIXs succeeded.",
9571 ioa_cfg->nvectors);
9572 }
9573 }
9574
9575 ioa_cfg->hrrq_num = min3(ioa_cfg->nvectors,
9576 (unsigned int)num_online_cpus(),
9577 (unsigned int)IPR_MAX_HRRQ_NUM);
9578
9579
9580 rc = pci_save_state(pdev);
9581
9582 if (rc != PCIBIOS_SUCCESSFUL) {
9583 dev_err(&pdev->dev, "Failed to save PCI config space\n");
9584 rc = -EIO;
9585 goto out_msi_disable;
9586 }
9587
9588 if ((rc = ipr_save_pcix_cmd_reg(ioa_cfg)))
9589 goto out_msi_disable;
9590
9591 if ((rc = ipr_set_pcix_cmd_reg(ioa_cfg)))
9592 goto out_msi_disable;
9593
9594 if (ioa_cfg->sis64)
9595 ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr64)
9596 + ((sizeof(struct ipr_config_table_entry64)
9597 * ioa_cfg->max_devs_supported)));
9598 else
9599 ioa_cfg->cfg_table_size = (sizeof(struct ipr_config_table_hdr)
9600 + ((sizeof(struct ipr_config_table_entry)
9601 * ioa_cfg->max_devs_supported)));
9602
9603 rc = ipr_alloc_mem(ioa_cfg);
9604 if (rc < 0) {
9605 dev_err(&pdev->dev,
9606 "Couldn't allocate enough memory for device driver!\n");
9607 goto out_msi_disable;
9608 }
9609
9610
9611
9612
9613
9614 mask = readl(ioa_cfg->regs.sense_interrupt_mask_reg32);
9615 interrupts = readl(ioa_cfg->regs.sense_interrupt_reg32);
9616 uproc = readl(ioa_cfg->regs.sense_uproc_interrupt_reg32);
9617 if ((mask & IPR_PCII_HRRQ_UPDATED) == 0 || (uproc & IPR_UPROCI_RESET_ALERT))
9618 ioa_cfg->needs_hard_reset = 1;
9619 if ((interrupts & IPR_PCII_ERROR_INTERRUPTS) || reset_devices)
9620 ioa_cfg->needs_hard_reset = 1;
9621 if (interrupts & IPR_PCII_IOA_UNIT_CHECKED)
9622 ioa_cfg->ioa_unit_checked = 1;
9623
9624 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9625 ipr_mask_and_clear_interrupts(ioa_cfg, ~IPR_PCII_IOA_TRANS_TO_OPER);
9626 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9627
9628 if (ioa_cfg->intr_flag == IPR_USE_MSI
9629 || ioa_cfg->intr_flag == IPR_USE_MSIX) {
9630 name_msi_vectors(ioa_cfg);
9631 rc = request_irq(ioa_cfg->vectors_info[0].vec, ipr_isr,
9632 0,
9633 ioa_cfg->vectors_info[0].desc,
9634 &ioa_cfg->hrrq[0]);
9635 if (!rc)
9636 rc = ipr_request_other_msi_irqs(ioa_cfg);
9637 } else {
9638 rc = request_irq(pdev->irq, ipr_isr,
9639 IRQF_SHARED,
9640 IPR_NAME, &ioa_cfg->hrrq[0]);
9641 }
9642 if (rc) {
9643 dev_err(&pdev->dev, "Couldn't register IRQ %d! rc=%d\n",
9644 pdev->irq, rc);
9645 goto cleanup_nolog;
9646 }
9647
9648 if ((dev_id->driver_data & IPR_USE_PCI_WARM_RESET) ||
9649 (dev_id->device == PCI_DEVICE_ID_IBM_OBSIDIAN_E && !ioa_cfg->revid)) {
9650 ioa_cfg->needs_warm_reset = 1;
9651 ioa_cfg->reset = ipr_reset_slot_reset;
9652 } else
9653 ioa_cfg->reset = ipr_reset_start_bist;
9654
9655 spin_lock_irqsave(&ipr_driver_lock, driver_lock_flags);
9656 list_add_tail(&ioa_cfg->queue, &ipr_ioa_head);
9657 spin_unlock_irqrestore(&ipr_driver_lock, driver_lock_flags);
9658
9659 LEAVE;
9660out:
9661 return rc;
9662
9663cleanup_nolog:
9664 ipr_free_mem(ioa_cfg);
9665out_msi_disable:
9666 if (ioa_cfg->intr_flag == IPR_USE_MSI)
9667 pci_disable_msi(pdev);
9668 else if (ioa_cfg->intr_flag == IPR_USE_MSIX)
9669 pci_disable_msix(pdev);
9670cleanup_nomem:
9671 iounmap(ipr_regs);
9672out_release_regions:
9673 pci_release_regions(pdev);
9674out_scsi_host_put:
9675 scsi_host_put(host);
9676out_disable:
9677 pci_disable_device(pdev);
9678 goto out;
9679}
9680
9681
9682
9683
9684
9685
9686
9687
9688
9689
9690
9691static void ipr_scan_vsets(struct ipr_ioa_cfg *ioa_cfg)
9692{
9693 int target, lun;
9694
9695 for (target = 0; target < IPR_MAX_NUM_TARGETS_PER_BUS; target++)
9696 for (lun = 0; lun < IPR_MAX_NUM_VSET_LUNS_PER_TARGET; lun++)
9697 scsi_add_device(ioa_cfg->host, IPR_VSET_BUS, target, lun);
9698}
9699
9700
9701
9702
9703
9704
9705
9706
9707
9708
9709
9710
9711
9712
9713
9714static void ipr_initiate_ioa_bringdown(struct ipr_ioa_cfg *ioa_cfg,
9715 enum ipr_shutdown_type shutdown_type)
9716{
9717 ENTER;
9718 if (ioa_cfg->sdt_state == WAIT_FOR_DUMP)
9719 ioa_cfg->sdt_state = ABORT_DUMP;
9720 ioa_cfg->reset_retries = 0;
9721 ioa_cfg->in_ioa_bringdown = 1;
9722 ipr_initiate_ioa_reset(ioa_cfg, shutdown_type);
9723 LEAVE;
9724}
9725
9726
9727
9728
9729
9730
9731
9732
9733
9734
9735static void __ipr_remove(struct pci_dev *pdev)
9736{
9737 unsigned long host_lock_flags = 0;
9738 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9739 int i;
9740 unsigned long driver_lock_flags;
9741 ENTER;
9742
9743 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
9744 while (ioa_cfg->in_reset_reload) {
9745 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
9746 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
9747 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
9748 }
9749
9750 for (i = 0; i < ioa_cfg->hrrq_num; i++) {
9751 spin_lock(&ioa_cfg->hrrq[i]._lock);
9752 ioa_cfg->hrrq[i].removing_ioa = 1;
9753 spin_unlock(&ioa_cfg->hrrq[i]._lock);
9754 }
9755 wmb();
9756 ipr_initiate_ioa_bringdown(ioa_cfg, IPR_SHUTDOWN_NORMAL);
9757
9758 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
9759 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
9760 flush_work(&ioa_cfg->work_q);
9761 INIT_LIST_HEAD(&ioa_cfg->used_res_q);
9762 spin_lock_irqsave(ioa_cfg->host->host_lock, host_lock_flags);
9763
9764 spin_lock_irqsave(&ipr_driver_lock, driver_lock_flags);
9765 list_del(&ioa_cfg->queue);
9766 spin_unlock_irqrestore(&ipr_driver_lock, driver_lock_flags);
9767
9768 if (ioa_cfg->sdt_state == ABORT_DUMP)
9769 ioa_cfg->sdt_state = WAIT_FOR_DUMP;
9770 spin_unlock_irqrestore(ioa_cfg->host->host_lock, host_lock_flags);
9771
9772 ipr_free_all_resources(ioa_cfg);
9773
9774 LEAVE;
9775}
9776
9777
9778
9779
9780
9781
9782
9783
9784
9785
9786static void ipr_remove(struct pci_dev *pdev)
9787{
9788 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9789
9790 ENTER;
9791
9792 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
9793 &ipr_trace_attr);
9794 ipr_remove_dump_file(&ioa_cfg->host->shost_dev.kobj,
9795 &ipr_dump_attr);
9796 scsi_remove_host(ioa_cfg->host);
9797
9798 __ipr_remove(pdev);
9799
9800 LEAVE;
9801}
9802
9803
9804
9805
9806
9807
9808
9809static int ipr_probe(struct pci_dev *pdev, const struct pci_device_id *dev_id)
9810{
9811 struct ipr_ioa_cfg *ioa_cfg;
9812 int rc, i;
9813
9814 rc = ipr_probe_ioa(pdev, dev_id);
9815
9816 if (rc)
9817 return rc;
9818
9819 ioa_cfg = pci_get_drvdata(pdev);
9820 rc = ipr_probe_ioa_part2(ioa_cfg);
9821
9822 if (rc) {
9823 __ipr_remove(pdev);
9824 return rc;
9825 }
9826
9827 rc = scsi_add_host(ioa_cfg->host, &pdev->dev);
9828
9829 if (rc) {
9830 __ipr_remove(pdev);
9831 return rc;
9832 }
9833
9834 rc = ipr_create_trace_file(&ioa_cfg->host->shost_dev.kobj,
9835 &ipr_trace_attr);
9836
9837 if (rc) {
9838 scsi_remove_host(ioa_cfg->host);
9839 __ipr_remove(pdev);
9840 return rc;
9841 }
9842
9843 rc = ipr_create_dump_file(&ioa_cfg->host->shost_dev.kobj,
9844 &ipr_dump_attr);
9845
9846 if (rc) {
9847 ipr_remove_trace_file(&ioa_cfg->host->shost_dev.kobj,
9848 &ipr_trace_attr);
9849 scsi_remove_host(ioa_cfg->host);
9850 __ipr_remove(pdev);
9851 return rc;
9852 }
9853
9854 scsi_scan_host(ioa_cfg->host);
9855 ipr_scan_vsets(ioa_cfg);
9856 scsi_add_device(ioa_cfg->host, IPR_IOA_BUS, IPR_IOA_TARGET, IPR_IOA_LUN);
9857 ioa_cfg->allow_ml_add_del = 1;
9858 ioa_cfg->host->max_channel = IPR_VSET_BUS;
9859 ioa_cfg->iopoll_weight = ioa_cfg->chip_cfg->iopoll_weight;
9860
9861 if (blk_iopoll_enabled && ioa_cfg->iopoll_weight &&
9862 ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
9863 for (i = 1; i < ioa_cfg->hrrq_num; i++) {
9864 blk_iopoll_init(&ioa_cfg->hrrq[i].iopoll,
9865 ioa_cfg->iopoll_weight, ipr_iopoll);
9866 blk_iopoll_enable(&ioa_cfg->hrrq[i].iopoll);
9867 }
9868 }
9869
9870 schedule_work(&ioa_cfg->work_q);
9871 return 0;
9872}
9873
9874
9875
9876
9877
9878
9879
9880
9881
9882
9883
9884static void ipr_shutdown(struct pci_dev *pdev)
9885{
9886 struct ipr_ioa_cfg *ioa_cfg = pci_get_drvdata(pdev);
9887 unsigned long lock_flags = 0;
9888 int i;
9889
9890 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9891 if (blk_iopoll_enabled && ioa_cfg->iopoll_weight &&
9892 ioa_cfg->sis64 && ioa_cfg->nvectors > 1) {
9893 ioa_cfg->iopoll_weight = 0;
9894 for (i = 1; i < ioa_cfg->hrrq_num; i++)
9895 blk_iopoll_disable(&ioa_cfg->hrrq[i].iopoll);
9896 }
9897
9898 while (ioa_cfg->in_reset_reload) {
9899 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9900 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
9901 spin_lock_irqsave(ioa_cfg->host->host_lock, lock_flags);
9902 }
9903
9904 ipr_initiate_ioa_bringdown(ioa_cfg, IPR_SHUTDOWN_NORMAL);
9905 spin_unlock_irqrestore(ioa_cfg->host->host_lock, lock_flags);
9906 wait_event(ioa_cfg->reset_wait_q, !ioa_cfg->in_reset_reload);
9907}
9908
9909static struct pci_device_id ipr_pci_table[] = {
9910 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
9911 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_5702, 0, 0, 0 },
9912 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
9913 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_5703, 0, 0, 0 },
9914 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
9915 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_573D, 0, 0, 0 },
9916 { PCI_VENDOR_ID_MYLEX, PCI_DEVICE_ID_IBM_GEMSTONE,
9917 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_573E, 0, 0, 0 },
9918 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
9919 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571B, 0, 0, 0 },
9920 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
9921 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572E, 0, 0, 0 },
9922 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
9923 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571A, 0, 0, 0 },
9924 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE,
9925 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575B, 0, 0,
9926 IPR_USE_LONG_TRANSOP_TIMEOUT },
9927 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
9928 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572A, 0, 0, 0 },
9929 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
9930 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572B, 0, 0,
9931 IPR_USE_LONG_TRANSOP_TIMEOUT },
9932 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_OBSIDIAN,
9933 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575C, 0, 0,
9934 IPR_USE_LONG_TRANSOP_TIMEOUT },
9935 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
9936 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572A, 0, 0, 0 },
9937 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
9938 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572B, 0, 0,
9939 IPR_USE_LONG_TRANSOP_TIMEOUT},
9940 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN,
9941 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_575C, 0, 0,
9942 IPR_USE_LONG_TRANSOP_TIMEOUT },
9943 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
9944 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574E, 0, 0,
9945 IPR_USE_LONG_TRANSOP_TIMEOUT },
9946 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
9947 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B3, 0, 0, 0 },
9948 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
9949 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CC, 0, 0, 0 },
9950 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_OBSIDIAN_E,
9951 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B7, 0, 0,
9952 IPR_USE_LONG_TRANSOP_TIMEOUT | IPR_USE_PCI_WARM_RESET },
9953 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_SNIPE,
9954 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_2780, 0, 0, 0 },
9955 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
9956 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571E, 0, 0, 0 },
9957 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
9958 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_571F, 0, 0,
9959 IPR_USE_LONG_TRANSOP_TIMEOUT },
9960 { PCI_VENDOR_ID_ADAPTEC2, PCI_DEVICE_ID_ADAPTEC2_SCAMP,
9961 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_572F, 0, 0,
9962 IPR_USE_LONG_TRANSOP_TIMEOUT },
9963 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9964 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B5, 0, 0, 0 },
9965 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9966 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_574D, 0, 0, 0 },
9967 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9968 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B2, 0, 0, 0 },
9969 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9970 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C0, 0, 0, 0 },
9971 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9972 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C3, 0, 0, 0 },
9973 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROC_FPGA_E2,
9974 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C4, 0, 0, 0 },
9975 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9976 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B4, 0, 0, 0 },
9977 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9978 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57B1, 0, 0, 0 },
9979 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9980 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C6, 0, 0, 0 },
9981 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9982 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57C8, 0, 0, 0 },
9983 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9984 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57CE, 0, 0, 0 },
9985 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9986 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D5, 0, 0, 0 },
9987 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9988 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D6, 0, 0, 0 },
9989 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9990 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D7, 0, 0, 0 },
9991 { PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CROCODILE,
9992 PCI_VENDOR_ID_IBM, IPR_SUBS_DEV_ID_57D8, 0, 0, 0 },
9993 { }
9994};
9995MODULE_DEVICE_TABLE(pci, ipr_pci_table);
9996
9997static const struct pci_error_handlers ipr_err_handler = {
9998 .error_detected = ipr_pci_error_detected,
9999 .slot_reset = ipr_pci_slot_reset,
10000};
10001
10002static struct pci_driver ipr_driver = {
10003 .name = IPR_NAME,
10004 .id_table = ipr_pci_table,
10005 .probe = ipr_probe,
10006 .remove = ipr_remove,
10007 .shutdown = ipr_shutdown,
10008 .err_handler = &ipr_err_handler,
10009};
10010
10011
10012
10013
10014
10015
10016
10017static void ipr_halt_done(struct ipr_cmnd *ipr_cmd)
10018{
10019 list_add_tail(&ipr_cmd->queue, &ipr_cmd->hrrq->hrrq_free_q);
10020}
10021
10022
10023
10024
10025
10026
10027
10028static int ipr_halt(struct notifier_block *nb, ulong event, void *buf)
10029{
10030 struct ipr_cmnd *ipr_cmd;
10031 struct ipr_ioa_cfg *ioa_cfg;
10032 unsigned long flags = 0, driver_lock_flags;
10033
10034 if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
10035 return NOTIFY_DONE;
10036
10037 spin_lock_irqsave(&ipr_driver_lock, driver_lock_flags);
10038
10039 list_for_each_entry(ioa_cfg, &ipr_ioa_head, queue) {
10040 spin_lock_irqsave(ioa_cfg->host->host_lock, flags);
10041 if (!ioa_cfg->hrrq[IPR_INIT_HRRQ].allow_cmds) {
10042 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
10043 continue;
10044 }
10045
10046 ipr_cmd = ipr_get_free_ipr_cmnd(ioa_cfg);
10047 ipr_cmd->ioarcb.res_handle = cpu_to_be32(IPR_IOA_RES_HANDLE);
10048 ipr_cmd->ioarcb.cmd_pkt.request_type = IPR_RQTYPE_IOACMD;
10049 ipr_cmd->ioarcb.cmd_pkt.cdb[0] = IPR_IOA_SHUTDOWN;
10050 ipr_cmd->ioarcb.cmd_pkt.cdb[1] = IPR_SHUTDOWN_PREPARE_FOR_NORMAL;
10051
10052 ipr_do_req(ipr_cmd, ipr_halt_done, ipr_timeout, IPR_DEVICE_RESET_TIMEOUT);
10053 spin_unlock_irqrestore(ioa_cfg->host->host_lock, flags);
10054 }
10055 spin_unlock_irqrestore(&ipr_driver_lock, driver_lock_flags);
10056
10057 return NOTIFY_OK;
10058}
10059
10060static struct notifier_block ipr_notifier = {
10061 ipr_halt, NULL, 0
10062};
10063
10064
10065
10066
10067
10068
10069
10070static int __init ipr_init(void)
10071{
10072 ipr_info("IBM Power RAID SCSI Device Driver version: %s %s\n",
10073 IPR_DRIVER_VERSION, IPR_DRIVER_DATE);
10074
10075 register_reboot_notifier(&ipr_notifier);
10076 return pci_register_driver(&ipr_driver);
10077}
10078
10079
10080
10081
10082
10083
10084
10085
10086
10087static void __exit ipr_exit(void)
10088{
10089 unregister_reboot_notifier(&ipr_notifier);
10090 pci_unregister_driver(&ipr_driver);
10091}
10092
10093module_init(ipr_init);
10094module_exit(ipr_exit);
10095
