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26#ifndef _IPR_H
27#define _IPR_H
28
29#include <asm/unaligned.h>
30#include <linux/types.h>
31#include <linux/completion.h>
32#include <linux/libata.h>
33#include <linux/list.h>
34#include <linux/kref.h>
35#include <linux/blk-iopoll.h>
36#include <scsi/scsi.h>
37#include <scsi/scsi_cmnd.h>
38
39
40
41
42#define IPR_DRIVER_VERSION "2.6.0"
43#define IPR_DRIVER_DATE "(November 16, 2012)"
44
45
46
47
48
49
50#define IPR_MAX_CMD_PER_LUN 6
51#define IPR_MAX_CMD_PER_ATA_LUN 1
52
53
54
55
56
57#define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds)
58
59#define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339
60
61#define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D
62#define PCI_DEVICE_ID_IBM_CROCODILE 0x034A
63
64#define IPR_SUBS_DEV_ID_2780 0x0264
65#define IPR_SUBS_DEV_ID_5702 0x0266
66#define IPR_SUBS_DEV_ID_5703 0x0278
67#define IPR_SUBS_DEV_ID_572E 0x028D
68#define IPR_SUBS_DEV_ID_573E 0x02D3
69#define IPR_SUBS_DEV_ID_573D 0x02D4
70#define IPR_SUBS_DEV_ID_571A 0x02C0
71#define IPR_SUBS_DEV_ID_571B 0x02BE
72#define IPR_SUBS_DEV_ID_571E 0x02BF
73#define IPR_SUBS_DEV_ID_571F 0x02D5
74#define IPR_SUBS_DEV_ID_572A 0x02C1
75#define IPR_SUBS_DEV_ID_572B 0x02C2
76#define IPR_SUBS_DEV_ID_572F 0x02C3
77#define IPR_SUBS_DEV_ID_574E 0x030A
78#define IPR_SUBS_DEV_ID_575B 0x030D
79#define IPR_SUBS_DEV_ID_575C 0x0338
80#define IPR_SUBS_DEV_ID_57B3 0x033A
81#define IPR_SUBS_DEV_ID_57B7 0x0360
82#define IPR_SUBS_DEV_ID_57B8 0x02C2
83
84#define IPR_SUBS_DEV_ID_57B4 0x033B
85#define IPR_SUBS_DEV_ID_57B2 0x035F
86#define IPR_SUBS_DEV_ID_57C0 0x0352
87#define IPR_SUBS_DEV_ID_57C3 0x0353
88#define IPR_SUBS_DEV_ID_57C4 0x0354
89#define IPR_SUBS_DEV_ID_57C6 0x0357
90#define IPR_SUBS_DEV_ID_57CC 0x035C
91
92#define IPR_SUBS_DEV_ID_57B5 0x033C
93#define IPR_SUBS_DEV_ID_57CE 0x035E
94#define IPR_SUBS_DEV_ID_57B1 0x0355
95
96#define IPR_SUBS_DEV_ID_574D 0x0356
97#define IPR_SUBS_DEV_ID_57C8 0x035D
98
99#define IPR_SUBS_DEV_ID_57D5 0x03FB
100#define IPR_SUBS_DEV_ID_57D6 0x03FC
101#define IPR_SUBS_DEV_ID_57D7 0x03FF
102#define IPR_SUBS_DEV_ID_57D8 0x03FE
103#define IPR_NAME "ipr"
104
105
106
107
108#define IPR_RC_JOB_CONTINUE 1
109#define IPR_RC_JOB_RETURN 2
110
111
112
113
114#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
115#define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000
116#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
117#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
118#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
119#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
120#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
121#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
122#define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000
123#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
124#define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
125#define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
126#define IPR_IOASC_BUS_WAS_RESET 0x06290000
127#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
128#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
129
130#define IPR_FIRST_DRIVER_IOASC 0x10000000
131#define IPR_IOASC_IOA_WAS_RESET 0x10000001
132#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
133
134
135#define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001
136#define IPR_USE_PCI_WARM_RESET 0x00000002
137
138#define IPR_DEFAULT_MAX_ERROR_DUMP 984
139#define IPR_NUM_LOG_HCAMS 2
140#define IPR_NUM_CFG_CHG_HCAMS 2
141#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
142
143#define IPR_MAX_SIS64_TARGETS_PER_BUS 1024
144#define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff
145
146#define IPR_MAX_NUM_TARGETS_PER_BUS 256
147#define IPR_MAX_NUM_LUNS_PER_TARGET 256
148#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
149#define IPR_VSET_BUS 0xff
150#define IPR_IOA_BUS 0xff
151#define IPR_IOA_TARGET 0xff
152#define IPR_IOA_LUN 0xff
153#define IPR_MAX_NUM_BUSES 16
154#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
155
156#define IPR_NUM_RESET_RELOAD_RETRIES 3
157
158
159#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
160 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4)
161
162#define IPR_MAX_COMMANDS 100
163#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
164 IPR_NUM_INTERNAL_CMD_BLKS)
165
166#define IPR_MAX_PHYSICAL_DEVS 192
167#define IPR_DEFAULT_SIS64_DEVS 1024
168#define IPR_MAX_SIS64_DEVS 4096
169
170#define IPR_MAX_SGLIST 64
171#define IPR_IOA_MAX_SECTORS 32767
172#define IPR_VSET_MAX_SECTORS 512
173#define IPR_MAX_CDB_LEN 16
174#define IPR_MAX_HRRQ_RETRIES 3
175
176#define IPR_DEFAULT_BUS_WIDTH 16
177#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
178#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
179#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
180#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
181
182#define IPR_IOA_RES_HANDLE 0xffffffff
183#define IPR_INVALID_RES_HANDLE 0
184#define IPR_IOA_RES_ADDR 0x00ffffff
185
186
187
188
189#define IPR_QUERY_RSRC_STATE 0xC2
190#define IPR_RESET_DEVICE 0xC3
191#define IPR_RESET_TYPE_SELECT 0x80
192#define IPR_LUN_RESET 0x40
193#define IPR_TARGET_RESET 0x20
194#define IPR_BUS_RESET 0x10
195#define IPR_ATA_PHY_RESET 0x80
196#define IPR_ID_HOST_RR_Q 0xC4
197#define IPR_QUERY_IOA_CONFIG 0xC5
198#define IPR_CANCEL_ALL_REQUESTS 0xCE
199#define IPR_HOST_CONTROLLED_ASYNC 0xCF
200#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
201#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
202#define IPR_SET_SUPPORTED_DEVICES 0xFB
203#define IPR_SET_ALL_SUPPORTED_DEVICES 0x80
204#define IPR_IOA_SHUTDOWN 0xF7
205#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
206
207
208
209
210#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
211#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
212#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
213#define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ)
214#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
215#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
216#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
217#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
218#define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ)
219#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
220#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
221#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
222#define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60)
223#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
224#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
225#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
226#define IPR_PCI_RESET_TIMEOUT (HZ / 2)
227#define IPR_SIS32_DUMP_TIMEOUT (15 * HZ)
228#define IPR_SIS64_DUMP_TIMEOUT (40 * HZ)
229#define IPR_DUMP_DELAY_SECONDS 4
230#define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ)
231
232
233
234
235#define IPR_VENDOR_ID_LEN 8
236#define IPR_PROD_ID_LEN 16
237#define IPR_SERIAL_NUM_LEN 8
238
239
240
241
242#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
243#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
244#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
245#define IPR_GET_FMT2_BAR_SEL(mbx) \
246(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
247#define IPR_SDT_FMT2_BAR0_SEL 0x0
248#define IPR_SDT_FMT2_BAR1_SEL 0x1
249#define IPR_SDT_FMT2_BAR2_SEL 0x2
250#define IPR_SDT_FMT2_BAR3_SEL 0x3
251#define IPR_SDT_FMT2_BAR4_SEL 0x4
252#define IPR_SDT_FMT2_BAR5_SEL 0x5
253#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
254#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
255#define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3
256#define IPR_DOORBELL 0x82800000
257#define IPR_RUNTIME_RESET 0x40000000
258
259#define IPR_IPL_INIT_MIN_STAGE_TIME 5
260#define IPR_IPL_INIT_DEFAULT_STAGE_TIME 15
261#define IPR_IPL_INIT_STAGE_UNKNOWN 0x0
262#define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000
263#define IPR_IPL_INIT_STAGE_MASK 0xff000000
264#define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff
265#define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0)
266
267#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
268#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
269#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
270#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
271#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
272#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
273#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
274#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
275#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
276#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
277#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
278
279#define IPR_PCII_ERROR_INTERRUPTS \
280(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
281IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
282
283#define IPR_PCII_OPER_INTERRUPTS \
284(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
285
286#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
287#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
288#define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23)
289
290#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000
291#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000
292
293
294
295
296#define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
297#define IPR_FMT3_MAX_IOA_DUMP_SIZE (32 * 1024 * 1024)
298#define IPR_FMT2_NUM_SDT_ENTRIES 511
299#define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF
300#define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
301#define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
302
303
304
305
306#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
307#define IPR_MAX_MSIX_VECTORS 0x5
308#define IPR_MAX_HRRQ_NUM 0x10
309#define IPR_INIT_HRRQ 0x0
310
311
312
313
314
315struct ipr_res_addr {
316 u8 reserved;
317 u8 bus;
318 u8 target;
319 u8 lun;
320#define IPR_GET_PHYS_LOC(res_addr) \
321 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
322}__attribute__((packed, aligned (4)));
323
324struct ipr_std_inq_vpids {
325 u8 vendor_id[IPR_VENDOR_ID_LEN];
326 u8 product_id[IPR_PROD_ID_LEN];
327}__attribute__((packed));
328
329struct ipr_vpd {
330 struct ipr_std_inq_vpids vpids;
331 u8 sn[IPR_SERIAL_NUM_LEN];
332}__attribute__((packed));
333
334struct ipr_ext_vpd {
335 struct ipr_vpd vpd;
336 __be32 wwid[2];
337}__attribute__((packed));
338
339struct ipr_ext_vpd64 {
340 struct ipr_vpd vpd;
341 __be32 wwid[4];
342}__attribute__((packed));
343
344struct ipr_std_inq_data {
345 u8 peri_qual_dev_type;
346#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
347#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
348
349 u8 removeable_medium_rsvd;
350#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
351
352#define IPR_IS_DASD_DEVICE(std_inq) \
353((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
354!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
355
356#define IPR_IS_SES_DEVICE(std_inq) \
357(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
358
359 u8 version;
360 u8 aen_naca_fmt;
361 u8 additional_len;
362 u8 sccs_rsvd;
363 u8 bq_enc_multi;
364 u8 sync_cmdq_flags;
365
366 struct ipr_std_inq_vpids vpids;
367
368 u8 ros_rsvd_ram_rsvd[4];
369
370 u8 serial_num[IPR_SERIAL_NUM_LEN];
371}__attribute__ ((packed));
372
373#define IPR_RES_TYPE_AF_DASD 0x00
374#define IPR_RES_TYPE_GENERIC_SCSI 0x01
375#define IPR_RES_TYPE_VOLUME_SET 0x02
376#define IPR_RES_TYPE_REMOTE_AF_DASD 0x03
377#define IPR_RES_TYPE_GENERIC_ATA 0x04
378#define IPR_RES_TYPE_ARRAY 0x05
379#define IPR_RES_TYPE_IOAFP 0xff
380
381struct ipr_config_table_entry {
382 u8 proto;
383#define IPR_PROTO_SATA 0x02
384#define IPR_PROTO_SATA_ATAPI 0x03
385#define IPR_PROTO_SAS_STP 0x06
386#define IPR_PROTO_SAS_STP_ATAPI 0x07
387 u8 array_id;
388 u8 flags;
389#define IPR_IS_IOA_RESOURCE 0x80
390 u8 rsvd_subtype;
391
392#define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4)
393#define IPR_QUEUE_FROZEN_MODEL 0
394#define IPR_QUEUE_NACA_MODEL 1
395
396 struct ipr_res_addr res_addr;
397 __be32 res_handle;
398 __be32 lun_wwn[2];
399 struct ipr_std_inq_data std_inq_data;
400}__attribute__ ((packed, aligned (4)));
401
402struct ipr_config_table_entry64 {
403 u8 res_type;
404 u8 proto;
405 u8 vset_num;
406 u8 array_id;
407 __be16 flags;
408 __be16 res_flags;
409#define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12)
410 __be32 res_handle;
411 u8 dev_id_type;
412 u8 reserved[3];
413 __be64 dev_id;
414 __be64 lun;
415 __be64 lun_wwn[2];
416#define IPR_MAX_RES_PATH_LENGTH 48
417 __be64 res_path;
418 struct ipr_std_inq_data std_inq_data;
419 u8 reserved2[4];
420 __be64 reserved3[2];
421 u8 reserved4[8];
422}__attribute__ ((packed, aligned (8)));
423
424struct ipr_config_table_hdr {
425 u8 num_entries;
426 u8 flags;
427#define IPR_UCODE_DOWNLOAD_REQ 0x10
428 __be16 reserved;
429}__attribute__((packed, aligned (4)));
430
431struct ipr_config_table_hdr64 {
432 __be16 num_entries;
433 __be16 reserved;
434 u8 flags;
435 u8 reserved2[11];
436}__attribute__((packed, aligned (4)));
437
438struct ipr_config_table {
439 struct ipr_config_table_hdr hdr;
440 struct ipr_config_table_entry dev[0];
441}__attribute__((packed, aligned (4)));
442
443struct ipr_config_table64 {
444 struct ipr_config_table_hdr64 hdr64;
445 struct ipr_config_table_entry64 dev[0];
446}__attribute__((packed, aligned (8)));
447
448struct ipr_config_table_entry_wrapper {
449 union {
450 struct ipr_config_table_entry *cfgte;
451 struct ipr_config_table_entry64 *cfgte64;
452 } u;
453};
454
455struct ipr_hostrcb_cfg_ch_not {
456 union {
457 struct ipr_config_table_entry cfgte;
458 struct ipr_config_table_entry64 cfgte64;
459 } u;
460 u8 reserved[936];
461}__attribute__((packed, aligned (4)));
462
463struct ipr_supported_device {
464 __be16 data_length;
465 u8 reserved;
466 u8 num_records;
467 struct ipr_std_inq_vpids vpids;
468 u8 reserved2[16];
469}__attribute__((packed, aligned (4)));
470
471struct ipr_hrr_queue {
472 struct ipr_ioa_cfg *ioa_cfg;
473 __be32 *host_rrq;
474 dma_addr_t host_rrq_dma;
475#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
476#define IPR_HRRQ_RESP_BIT_SET 0x00000002
477#define IPR_HRRQ_TOGGLE_BIT 0x00000001
478#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
479#define IPR_ID_HRRQ_SELE_ENABLE 0x02
480 volatile __be32 *hrrq_start;
481 volatile __be32 *hrrq_end;
482 volatile __be32 *hrrq_curr;
483
484 struct list_head hrrq_free_q;
485 struct list_head hrrq_pending_q;
486 spinlock_t _lock;
487 spinlock_t *lock;
488
489 volatile u32 toggle_bit;
490 u32 size;
491 u32 min_cmd_id;
492 u32 max_cmd_id;
493 u8 allow_interrupts:1;
494 u8 ioa_is_dead:1;
495 u8 allow_cmds:1;
496 u8 removing_ioa:1;
497
498 struct blk_iopoll iopoll;
499};
500
501
502struct ipr_cmd_pkt {
503 u8 reserved;
504 u8 hrrq_id;
505 u8 request_type;
506#define IPR_RQTYPE_SCSICDB 0x00
507#define IPR_RQTYPE_IOACMD 0x01
508#define IPR_RQTYPE_HCAM 0x02
509#define IPR_RQTYPE_ATA_PASSTHRU 0x04
510
511 u8 reserved2;
512
513 u8 flags_hi;
514#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
515#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
516#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
517#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
518#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
519
520 u8 flags_lo;
521#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
522#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
523#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
524#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
525#define IPR_FLAGS_LO_ORDERED_TASK 0x04
526#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
527#define IPR_FLAGS_LO_ACA_TASK 0x08
528
529 u8 cdb[16];
530 __be16 timeout;
531}__attribute__ ((packed, aligned(4)));
532
533struct ipr_ioarcb_ata_regs {
534 u8 flags;
535#define IPR_ATA_FLAG_PACKET_CMD 0x80
536#define IPR_ATA_FLAG_XFER_TYPE_DMA 0x40
537#define IPR_ATA_FLAG_STATUS_ON_GOOD_COMPLETION 0x20
538 u8 reserved[3];
539
540 __be16 data;
541 u8 feature;
542 u8 nsect;
543 u8 lbal;
544 u8 lbam;
545 u8 lbah;
546 u8 device;
547 u8 command;
548 u8 reserved2[3];
549 u8 hob_feature;
550 u8 hob_nsect;
551 u8 hob_lbal;
552 u8 hob_lbam;
553 u8 hob_lbah;
554 u8 ctl;
555}__attribute__ ((packed, aligned(2)));
556
557struct ipr_ioadl_desc {
558 __be32 flags_and_data_len;
559#define IPR_IOADL_FLAGS_MASK 0xff000000
560#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
561#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
562#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
563#define IPR_IOADL_FLAGS_READ 0x48000000
564#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
565#define IPR_IOADL_FLAGS_WRITE 0x68000000
566#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
567#define IPR_IOADL_FLAGS_LAST 0x01000000
568
569 __be32 address;
570}__attribute__((packed, aligned (8)));
571
572struct ipr_ioadl64_desc {
573 __be32 flags;
574 __be32 data_len;
575 __be64 address;
576}__attribute__((packed, aligned (16)));
577
578struct ipr_ata64_ioadl {
579 struct ipr_ioarcb_ata_regs regs;
580 u16 reserved[5];
581 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
582}__attribute__((packed, aligned (16)));
583
584struct ipr_ioarcb_add_data {
585 union {
586 struct ipr_ioarcb_ata_regs regs;
587 struct ipr_ioadl_desc ioadl[5];
588 __be32 add_cmd_parms[10];
589 } u;
590}__attribute__ ((packed, aligned (4)));
591
592struct ipr_ioarcb_sis64_add_addr_ecb {
593 __be64 ioasa_host_pci_addr;
594 __be64 data_ioadl_addr;
595 __be64 reserved;
596 __be32 ext_control_buf[4];
597}__attribute__((packed, aligned (8)));
598
599
600struct ipr_ioarcb {
601 union {
602 __be32 ioarcb_host_pci_addr;
603 __be64 ioarcb_host_pci_addr64;
604 } a;
605 __be32 res_handle;
606 __be32 host_response_handle;
607 __be32 reserved1;
608 __be32 reserved2;
609 __be32 reserved3;
610
611 __be32 data_transfer_length;
612 __be32 read_data_transfer_length;
613 __be32 write_ioadl_addr;
614 __be32 ioadl_len;
615 __be32 read_ioadl_addr;
616 __be32 read_ioadl_len;
617
618 __be32 ioasa_host_pci_addr;
619 __be16 ioasa_len;
620 __be16 reserved4;
621
622 struct ipr_cmd_pkt cmd_pkt;
623
624 __be16 add_cmd_parms_offset;
625 __be16 add_cmd_parms_len;
626
627 union {
628 struct ipr_ioarcb_add_data add_data;
629 struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data;
630 } u;
631
632}__attribute__((packed, aligned (4)));
633
634struct ipr_ioasa_vset {
635 __be32 failing_lba_hi;
636 __be32 failing_lba_lo;
637 __be32 reserved;
638}__attribute__((packed, aligned (4)));
639
640struct ipr_ioasa_af_dasd {
641 __be32 failing_lba;
642 __be32 reserved[2];
643}__attribute__((packed, aligned (4)));
644
645struct ipr_ioasa_gpdd {
646 u8 end_state;
647 u8 bus_phase;
648 __be16 reserved;
649 __be32 ioa_data[2];
650}__attribute__((packed, aligned (4)));
651
652struct ipr_ioasa_gata {
653 u8 error;
654 u8 nsect;
655 u8 lbal;
656 u8 lbam;
657 u8 lbah;
658 u8 device;
659 u8 status;
660 u8 alt_status;
661 u8 hob_nsect;
662 u8 hob_lbal;
663 u8 hob_lbam;
664 u8 hob_lbah;
665}__attribute__((packed, aligned (4)));
666
667struct ipr_auto_sense {
668 __be16 auto_sense_len;
669 __be16 ioa_data_len;
670 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
671};
672
673struct ipr_ioasa_hdr {
674 __be32 ioasc;
675#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
676#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
677#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
678#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
679
680 __be16 ret_stat_len;
681
682 __be16 avail_stat_len;
683
684 __be32 residual_data_len;
685
686
687 __be32 ilid;
688#define IPR_NO_ILID 0
689#define IPR_DRIVER_ILID 0xffffffff
690
691 __be32 fd_ioasc;
692
693 __be32 fd_phys_locator;
694
695 __be32 fd_res_handle;
696
697 __be32 ioasc_specific;
698#define IPR_ADDITIONAL_STATUS_FMT 0x80000000
699#define IPR_AUTOSENSE_VALID 0x40000000
700#define IPR_ATA_DEVICE_WAS_RESET 0x20000000
701#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
702#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
703#define IPR_FIELD_POINTER_MASK 0x0000ffff
704
705}__attribute__((packed, aligned (4)));
706
707struct ipr_ioasa {
708 struct ipr_ioasa_hdr hdr;
709
710 union {
711 struct ipr_ioasa_vset vset;
712 struct ipr_ioasa_af_dasd dasd;
713 struct ipr_ioasa_gpdd gpdd;
714 struct ipr_ioasa_gata gata;
715 } u;
716
717 struct ipr_auto_sense auto_sense;
718}__attribute__((packed, aligned (4)));
719
720struct ipr_ioasa64 {
721 struct ipr_ioasa_hdr hdr;
722 u8 fd_res_path[8];
723
724 union {
725 struct ipr_ioasa_vset vset;
726 struct ipr_ioasa_af_dasd dasd;
727 struct ipr_ioasa_gpdd gpdd;
728 struct ipr_ioasa_gata gata;
729 } u;
730
731 struct ipr_auto_sense auto_sense;
732}__attribute__((packed, aligned (4)));
733
734struct ipr_mode_parm_hdr {
735 u8 length;
736 u8 medium_type;
737 u8 device_spec_parms;
738 u8 block_desc_len;
739}__attribute__((packed));
740
741struct ipr_mode_pages {
742 struct ipr_mode_parm_hdr hdr;
743 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
744}__attribute__((packed));
745
746struct ipr_mode_page_hdr {
747 u8 ps_page_code;
748#define IPR_MODE_PAGE_PS 0x80
749#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
750 u8 page_length;
751}__attribute__ ((packed));
752
753struct ipr_dev_bus_entry {
754 struct ipr_res_addr res_addr;
755 u8 flags;
756#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
757#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
758#define IPR_SCSI_ATTR_QAS_MASK 0xC0
759#define IPR_SCSI_ATTR_ENABLE_TM 0x20
760#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
761#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
762#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
763
764 u8 scsi_id;
765 u8 bus_width;
766 u8 extended_reset_delay;
767#define IPR_EXTENDED_RESET_DELAY 7
768
769 __be32 max_xfer_rate;
770
771 u8 spinup_delay;
772 u8 reserved3;
773 __be16 reserved4;
774}__attribute__((packed, aligned (4)));
775
776struct ipr_mode_page28 {
777 struct ipr_mode_page_hdr hdr;
778 u8 num_entries;
779 u8 entry_length;
780 struct ipr_dev_bus_entry bus[0];
781}__attribute__((packed));
782
783struct ipr_mode_page24 {
784 struct ipr_mode_page_hdr hdr;
785 u8 flags;
786#define IPR_ENABLE_DUAL_IOA_AF 0x80
787}__attribute__((packed));
788
789struct ipr_ioa_vpd {
790 struct ipr_std_inq_data std_inq_data;
791 u8 ascii_part_num[12];
792 u8 reserved[40];
793 u8 ascii_plant_code[4];
794}__attribute__((packed));
795
796struct ipr_inquiry_page3 {
797 u8 peri_qual_dev_type;
798 u8 page_code;
799 u8 reserved1;
800 u8 page_length;
801 u8 ascii_len;
802 u8 reserved2[3];
803 u8 load_id[4];
804 u8 major_release;
805 u8 card_type;
806 u8 minor_release[2];
807 u8 ptf_number[4];
808 u8 patch_number[4];
809}__attribute__((packed));
810
811struct ipr_inquiry_cap {
812 u8 peri_qual_dev_type;
813 u8 page_code;
814 u8 reserved1;
815 u8 page_length;
816 u8 ascii_len;
817 u8 reserved2;
818 u8 sis_version[2];
819 u8 cap;
820#define IPR_CAP_DUAL_IOA_RAID 0x80
821 u8 reserved3[15];
822}__attribute__((packed));
823
824#define IPR_INQUIRY_PAGE0_ENTRIES 20
825struct ipr_inquiry_page0 {
826 u8 peri_qual_dev_type;
827 u8 page_code;
828 u8 reserved1;
829 u8 len;
830 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
831}__attribute__((packed));
832
833struct ipr_hostrcb_device_data_entry {
834 struct ipr_vpd vpd;
835 struct ipr_res_addr dev_res_addr;
836 struct ipr_vpd new_vpd;
837 struct ipr_vpd ioa_last_with_dev_vpd;
838 struct ipr_vpd cfc_last_with_dev_vpd;
839 __be32 ioa_data[5];
840}__attribute__((packed, aligned (4)));
841
842struct ipr_hostrcb_device_data_entry_enhanced {
843 struct ipr_ext_vpd vpd;
844 u8 ccin[4];
845 struct ipr_res_addr dev_res_addr;
846 struct ipr_ext_vpd new_vpd;
847 u8 new_ccin[4];
848 struct ipr_ext_vpd ioa_last_with_dev_vpd;
849 struct ipr_ext_vpd cfc_last_with_dev_vpd;
850}__attribute__((packed, aligned (4)));
851
852struct ipr_hostrcb64_device_data_entry_enhanced {
853 struct ipr_ext_vpd vpd;
854 u8 ccin[4];
855 u8 res_path[8];
856 struct ipr_ext_vpd new_vpd;
857 u8 new_ccin[4];
858 struct ipr_ext_vpd ioa_last_with_dev_vpd;
859 struct ipr_ext_vpd cfc_last_with_dev_vpd;
860}__attribute__((packed, aligned (4)));
861
862struct ipr_hostrcb_array_data_entry {
863 struct ipr_vpd vpd;
864 struct ipr_res_addr expected_dev_res_addr;
865 struct ipr_res_addr dev_res_addr;
866}__attribute__((packed, aligned (4)));
867
868struct ipr_hostrcb64_array_data_entry {
869 struct ipr_ext_vpd vpd;
870 u8 ccin[4];
871 u8 expected_res_path[8];
872 u8 res_path[8];
873}__attribute__((packed, aligned (4)));
874
875struct ipr_hostrcb_array_data_entry_enhanced {
876 struct ipr_ext_vpd vpd;
877 u8 ccin[4];
878 struct ipr_res_addr expected_dev_res_addr;
879 struct ipr_res_addr dev_res_addr;
880}__attribute__((packed, aligned (4)));
881
882struct ipr_hostrcb_type_ff_error {
883 __be32 ioa_data[758];
884}__attribute__((packed, aligned (4)));
885
886struct ipr_hostrcb_type_01_error {
887 __be32 seek_counter;
888 __be32 read_counter;
889 u8 sense_data[32];
890 __be32 ioa_data[236];
891}__attribute__((packed, aligned (4)));
892
893struct ipr_hostrcb_type_02_error {
894 struct ipr_vpd ioa_vpd;
895 struct ipr_vpd cfc_vpd;
896 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
897 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
898 __be32 ioa_data[3];
899}__attribute__((packed, aligned (4)));
900
901struct ipr_hostrcb_type_12_error {
902 struct ipr_ext_vpd ioa_vpd;
903 struct ipr_ext_vpd cfc_vpd;
904 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
905 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
906 __be32 ioa_data[3];
907}__attribute__((packed, aligned (4)));
908
909struct ipr_hostrcb_type_03_error {
910 struct ipr_vpd ioa_vpd;
911 struct ipr_vpd cfc_vpd;
912 __be32 errors_detected;
913 __be32 errors_logged;
914 u8 ioa_data[12];
915 struct ipr_hostrcb_device_data_entry dev[3];
916}__attribute__((packed, aligned (4)));
917
918struct ipr_hostrcb_type_13_error {
919 struct ipr_ext_vpd ioa_vpd;
920 struct ipr_ext_vpd cfc_vpd;
921 __be32 errors_detected;
922 __be32 errors_logged;
923 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
924}__attribute__((packed, aligned (4)));
925
926struct ipr_hostrcb_type_23_error {
927 struct ipr_ext_vpd ioa_vpd;
928 struct ipr_ext_vpd cfc_vpd;
929 __be32 errors_detected;
930 __be32 errors_logged;
931 struct ipr_hostrcb64_device_data_entry_enhanced dev[3];
932}__attribute__((packed, aligned (4)));
933
934struct ipr_hostrcb_type_04_error {
935 struct ipr_vpd ioa_vpd;
936 struct ipr_vpd cfc_vpd;
937 u8 ioa_data[12];
938 struct ipr_hostrcb_array_data_entry array_member[10];
939 __be32 exposed_mode_adn;
940 __be32 array_id;
941 struct ipr_vpd incomp_dev_vpd;
942 __be32 ioa_data2;
943 struct ipr_hostrcb_array_data_entry array_member2[8];
944 struct ipr_res_addr last_func_vset_res_addr;
945 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
946 u8 protection_level[8];
947}__attribute__((packed, aligned (4)));
948
949struct ipr_hostrcb_type_14_error {
950 struct ipr_ext_vpd ioa_vpd;
951 struct ipr_ext_vpd cfc_vpd;
952 __be32 exposed_mode_adn;
953 __be32 array_id;
954 struct ipr_res_addr last_func_vset_res_addr;
955 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
956 u8 protection_level[8];
957 __be32 num_entries;
958 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
959}__attribute__((packed, aligned (4)));
960
961struct ipr_hostrcb_type_24_error {
962 struct ipr_ext_vpd ioa_vpd;
963 struct ipr_ext_vpd cfc_vpd;
964 u8 reserved[2];
965 u8 exposed_mode_adn;
966#define IPR_INVALID_ARRAY_DEV_NUM 0xff
967 u8 array_id;
968 u8 last_res_path[8];
969 u8 protection_level[8];
970 struct ipr_ext_vpd64 array_vpd;
971 u8 description[16];
972 u8 reserved2[3];
973 u8 num_entries;
974 struct ipr_hostrcb64_array_data_entry array_member[32];
975}__attribute__((packed, aligned (4)));
976
977struct ipr_hostrcb_type_07_error {
978 u8 failure_reason[64];
979 struct ipr_vpd vpd;
980 u32 data[222];
981}__attribute__((packed, aligned (4)));
982
983struct ipr_hostrcb_type_17_error {
984 u8 failure_reason[64];
985 struct ipr_ext_vpd vpd;
986 u32 data[476];
987}__attribute__((packed, aligned (4)));
988
989struct ipr_hostrcb_config_element {
990 u8 type_status;
991#define IPR_PATH_CFG_TYPE_MASK 0xF0
992#define IPR_PATH_CFG_NOT_EXIST 0x00
993#define IPR_PATH_CFG_IOA_PORT 0x10
994#define IPR_PATH_CFG_EXP_PORT 0x20
995#define IPR_PATH_CFG_DEVICE_PORT 0x30
996#define IPR_PATH_CFG_DEVICE_LUN 0x40
997
998#define IPR_PATH_CFG_STATUS_MASK 0x0F
999#define IPR_PATH_CFG_NO_PROB 0x00
1000#define IPR_PATH_CFG_DEGRADED 0x01
1001#define IPR_PATH_CFG_FAILED 0x02
1002#define IPR_PATH_CFG_SUSPECT 0x03
1003#define IPR_PATH_NOT_DETECTED 0x04
1004#define IPR_PATH_INCORRECT_CONN 0x05
1005
1006 u8 cascaded_expander;
1007 u8 phy;
1008 u8 link_rate;
1009#define IPR_PHY_LINK_RATE_MASK 0x0F
1010
1011 __be32 wwid[2];
1012}__attribute__((packed, aligned (4)));
1013
1014struct ipr_hostrcb64_config_element {
1015 __be16 length;
1016 u8 descriptor_id;
1017#define IPR_DESCRIPTOR_MASK 0xC0
1018#define IPR_DESCRIPTOR_SIS64 0x00
1019
1020 u8 reserved;
1021 u8 type_status;
1022
1023 u8 reserved2[2];
1024 u8 link_rate;
1025
1026 u8 res_path[8];
1027 __be32 wwid[2];
1028}__attribute__((packed, aligned (8)));
1029
1030struct ipr_hostrcb_fabric_desc {
1031 __be16 length;
1032 u8 ioa_port;
1033 u8 cascaded_expander;
1034 u8 phy;
1035 u8 path_state;
1036#define IPR_PATH_ACTIVE_MASK 0xC0
1037#define IPR_PATH_NO_INFO 0x00
1038#define IPR_PATH_ACTIVE 0x40
1039#define IPR_PATH_NOT_ACTIVE 0x80
1040
1041#define IPR_PATH_STATE_MASK 0x0F
1042#define IPR_PATH_STATE_NO_INFO 0x00
1043#define IPR_PATH_HEALTHY 0x01
1044#define IPR_PATH_DEGRADED 0x02
1045#define IPR_PATH_FAILED 0x03
1046
1047 __be16 num_entries;
1048 struct ipr_hostrcb_config_element elem[1];
1049}__attribute__((packed, aligned (4)));
1050
1051struct ipr_hostrcb64_fabric_desc {
1052 __be16 length;
1053 u8 descriptor_id;
1054
1055 u8 reserved[2];
1056 u8 path_state;
1057
1058 u8 reserved2[2];
1059 u8 res_path[8];
1060 u8 reserved3[6];
1061 __be16 num_entries;
1062 struct ipr_hostrcb64_config_element elem[1];
1063}__attribute__((packed, aligned (8)));
1064
1065#define for_each_hrrq(hrrq, ioa_cfg) \
1066 for (hrrq = (ioa_cfg)->hrrq; \
1067 hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++)
1068
1069#define for_each_fabric_cfg(fabric, cfg) \
1070 for (cfg = (fabric)->elem; \
1071 cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \
1072 cfg++)
1073
1074struct ipr_hostrcb_type_20_error {
1075 u8 failure_reason[64];
1076 u8 reserved[3];
1077 u8 num_entries;
1078 struct ipr_hostrcb_fabric_desc desc[1];
1079}__attribute__((packed, aligned (4)));
1080
1081struct ipr_hostrcb_type_30_error {
1082 u8 failure_reason[64];
1083 u8 reserved[3];
1084 u8 num_entries;
1085 struct ipr_hostrcb64_fabric_desc desc[1];
1086}__attribute__((packed, aligned (4)));
1087
1088struct ipr_hostrcb_error {
1089 __be32 fd_ioasc;
1090 struct ipr_res_addr fd_res_addr;
1091 __be32 fd_res_handle;
1092 __be32 prc;
1093 union {
1094 struct ipr_hostrcb_type_ff_error type_ff_error;
1095 struct ipr_hostrcb_type_01_error type_01_error;
1096 struct ipr_hostrcb_type_02_error type_02_error;
1097 struct ipr_hostrcb_type_03_error type_03_error;
1098 struct ipr_hostrcb_type_04_error type_04_error;
1099 struct ipr_hostrcb_type_07_error type_07_error;
1100 struct ipr_hostrcb_type_12_error type_12_error;
1101 struct ipr_hostrcb_type_13_error type_13_error;
1102 struct ipr_hostrcb_type_14_error type_14_error;
1103 struct ipr_hostrcb_type_17_error type_17_error;
1104 struct ipr_hostrcb_type_20_error type_20_error;
1105 } u;
1106}__attribute__((packed, aligned (4)));
1107
1108struct ipr_hostrcb64_error {
1109 __be32 fd_ioasc;
1110 __be32 ioa_fw_level;
1111 __be32 fd_res_handle;
1112 __be32 prc;
1113 __be64 fd_dev_id;
1114 __be64 fd_lun;
1115 u8 fd_res_path[8];
1116 __be64 time_stamp;
1117 u8 reserved[16];
1118 union {
1119 struct ipr_hostrcb_type_ff_error type_ff_error;
1120 struct ipr_hostrcb_type_12_error type_12_error;
1121 struct ipr_hostrcb_type_17_error type_17_error;
1122 struct ipr_hostrcb_type_23_error type_23_error;
1123 struct ipr_hostrcb_type_24_error type_24_error;
1124 struct ipr_hostrcb_type_30_error type_30_error;
1125 } u;
1126}__attribute__((packed, aligned (8)));
1127
1128struct ipr_hostrcb_raw {
1129 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
1130}__attribute__((packed, aligned (4)));
1131
1132struct ipr_hcam {
1133 u8 op_code;
1134#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
1135#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
1136
1137 u8 notify_type;
1138#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
1139#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
1140#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
1141#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
1142#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
1143
1144 u8 notifications_lost;
1145#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
1146#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
1147
1148 u8 flags;
1149#define IPR_HOSTRCB_INTERNAL_OPER 0x80
1150#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
1151
1152 u8 overlay_id;
1153#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
1154#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
1155#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
1156#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
1157#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
1158#define IPR_HOST_RCB_OVERLAY_ID_7 0x07
1159#define IPR_HOST_RCB_OVERLAY_ID_12 0x12
1160#define IPR_HOST_RCB_OVERLAY_ID_13 0x13
1161#define IPR_HOST_RCB_OVERLAY_ID_14 0x14
1162#define IPR_HOST_RCB_OVERLAY_ID_16 0x16
1163#define IPR_HOST_RCB_OVERLAY_ID_17 0x17
1164#define IPR_HOST_RCB_OVERLAY_ID_20 0x20
1165#define IPR_HOST_RCB_OVERLAY_ID_23 0x23
1166#define IPR_HOST_RCB_OVERLAY_ID_24 0x24
1167#define IPR_HOST_RCB_OVERLAY_ID_26 0x26
1168#define IPR_HOST_RCB_OVERLAY_ID_30 0x30
1169#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
1170
1171 u8 reserved1[3];
1172 __be32 ilid;
1173 __be32 time_since_last_ioa_reset;
1174 __be32 reserved2;
1175 __be32 length;
1176
1177 union {
1178 struct ipr_hostrcb_error error;
1179 struct ipr_hostrcb64_error error64;
1180 struct ipr_hostrcb_cfg_ch_not ccn;
1181 struct ipr_hostrcb_raw raw;
1182 } u;
1183}__attribute__((packed, aligned (4)));
1184
1185struct ipr_hostrcb {
1186 struct ipr_hcam hcam;
1187 dma_addr_t hostrcb_dma;
1188 struct list_head queue;
1189 struct ipr_ioa_cfg *ioa_cfg;
1190 char rp_buffer[IPR_MAX_RES_PATH_LENGTH];
1191};
1192
1193
1194struct ipr_sdt_entry {
1195 __be32 start_token;
1196 __be32 end_token;
1197 u8 reserved[4];
1198
1199 u8 flags;
1200#define IPR_SDT_ENDIAN 0x80
1201#define IPR_SDT_VALID_ENTRY 0x20
1202
1203 u8 resv;
1204 __be16 priority;
1205}__attribute__((packed, aligned (4)));
1206
1207struct ipr_sdt_header {
1208 __be32 state;
1209 __be32 num_entries;
1210 __be32 num_entries_used;
1211 __be32 dump_size;
1212}__attribute__((packed, aligned (4)));
1213
1214struct ipr_sdt {
1215 struct ipr_sdt_header hdr;
1216 struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES];
1217}__attribute__((packed, aligned (4)));
1218
1219struct ipr_uc_sdt {
1220 struct ipr_sdt_header hdr;
1221 struct ipr_sdt_entry entry[1];
1222}__attribute__((packed, aligned (4)));
1223
1224
1225
1226
1227struct ipr_bus_attributes {
1228 u8 bus;
1229 u8 qas_enabled;
1230 u8 bus_width;
1231 u8 reserved;
1232 u32 max_xfer_rate;
1233};
1234
1235struct ipr_sata_port {
1236 struct ipr_ioa_cfg *ioa_cfg;
1237 struct ata_port *ap;
1238 struct ipr_resource_entry *res;
1239 struct ipr_ioasa_gata ioasa;
1240};
1241
1242struct ipr_resource_entry {
1243 u8 needs_sync_complete:1;
1244 u8 in_erp:1;
1245 u8 add_to_ml:1;
1246 u8 del_from_ml:1;
1247 u8 resetting_device:1;
1248
1249 u32 bus;
1250 u32 target;
1251 u32 lun;
1252#define IPR_ARRAY_VIRTUAL_BUS 0x1
1253#define IPR_VSET_VIRTUAL_BUS 0x2
1254#define IPR_IOAFP_VIRTUAL_BUS 0x3
1255
1256#define IPR_GET_RES_PHYS_LOC(res) \
1257 (((res)->bus << 24) | ((res)->target << 8) | (res)->lun)
1258
1259 u8 ata_class;
1260
1261 u8 flags;
1262 __be16 res_flags;
1263
1264 u8 type;
1265
1266 u8 qmodel;
1267 struct ipr_std_inq_data std_inq_data;
1268
1269 __be32 res_handle;
1270 __be64 dev_id;
1271 __be64 lun_wwn;
1272 struct scsi_lun dev_lun;
1273 u8 res_path[8];
1274
1275 struct ipr_ioa_cfg *ioa_cfg;
1276 struct scsi_device *sdev;
1277 struct ipr_sata_port *sata_port;
1278 struct list_head queue;
1279};
1280
1281struct ipr_resource_hdr {
1282 u16 num_entries;
1283 u16 reserved;
1284};
1285
1286struct ipr_misc_cbs {
1287 struct ipr_ioa_vpd ioa_vpd;
1288 struct ipr_inquiry_page0 page0_data;
1289 struct ipr_inquiry_page3 page3_data;
1290 struct ipr_inquiry_cap cap;
1291 struct ipr_mode_pages mode_pages;
1292 struct ipr_supported_device supp_dev;
1293};
1294
1295struct ipr_interrupt_offsets {
1296 unsigned long set_interrupt_mask_reg;
1297 unsigned long clr_interrupt_mask_reg;
1298 unsigned long clr_interrupt_mask_reg32;
1299 unsigned long sense_interrupt_mask_reg;
1300 unsigned long sense_interrupt_mask_reg32;
1301 unsigned long clr_interrupt_reg;
1302 unsigned long clr_interrupt_reg32;
1303
1304 unsigned long sense_interrupt_reg;
1305 unsigned long sense_interrupt_reg32;
1306 unsigned long ioarrin_reg;
1307 unsigned long sense_uproc_interrupt_reg;
1308 unsigned long sense_uproc_interrupt_reg32;
1309 unsigned long set_uproc_interrupt_reg;
1310 unsigned long set_uproc_interrupt_reg32;
1311 unsigned long clr_uproc_interrupt_reg;
1312 unsigned long clr_uproc_interrupt_reg32;
1313
1314 unsigned long init_feedback_reg;
1315
1316 unsigned long dump_addr_reg;
1317 unsigned long dump_data_reg;
1318
1319#define IPR_ENDIAN_SWAP_KEY 0x00080800
1320 unsigned long endian_swap_reg;
1321};
1322
1323struct ipr_interrupts {
1324 void __iomem *set_interrupt_mask_reg;
1325 void __iomem *clr_interrupt_mask_reg;
1326 void __iomem *clr_interrupt_mask_reg32;
1327 void __iomem *sense_interrupt_mask_reg;
1328 void __iomem *sense_interrupt_mask_reg32;
1329 void __iomem *clr_interrupt_reg;
1330 void __iomem *clr_interrupt_reg32;
1331
1332 void __iomem *sense_interrupt_reg;
1333 void __iomem *sense_interrupt_reg32;
1334 void __iomem *ioarrin_reg;
1335 void __iomem *sense_uproc_interrupt_reg;
1336 void __iomem *sense_uproc_interrupt_reg32;
1337 void __iomem *set_uproc_interrupt_reg;
1338 void __iomem *set_uproc_interrupt_reg32;
1339 void __iomem *clr_uproc_interrupt_reg;
1340 void __iomem *clr_uproc_interrupt_reg32;
1341
1342 void __iomem *init_feedback_reg;
1343
1344 void __iomem *dump_addr_reg;
1345 void __iomem *dump_data_reg;
1346
1347 void __iomem *endian_swap_reg;
1348};
1349
1350struct ipr_chip_cfg_t {
1351 u32 mailbox;
1352 u16 max_cmds;
1353 u8 cache_line_size;
1354 u8 clear_isr;
1355 u32 iopoll_weight;
1356 struct ipr_interrupt_offsets regs;
1357};
1358
1359struct ipr_chip_t {
1360 u16 vendor;
1361 u16 device;
1362 u16 intr_type;
1363#define IPR_USE_LSI 0x00
1364#define IPR_USE_MSI 0x01
1365#define IPR_USE_MSIX 0x02
1366 u16 sis_type;
1367#define IPR_SIS32 0x00
1368#define IPR_SIS64 0x01
1369 u16 bist_method;
1370#define IPR_PCI_CFG 0x00
1371#define IPR_MMIO 0x01
1372 const struct ipr_chip_cfg_t *cfg;
1373};
1374
1375enum ipr_shutdown_type {
1376 IPR_SHUTDOWN_NORMAL = 0x00,
1377 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
1378 IPR_SHUTDOWN_ABBREV = 0x80,
1379 IPR_SHUTDOWN_NONE = 0x100
1380};
1381
1382struct ipr_trace_entry {
1383 u32 time;
1384
1385 u8 op_code;
1386 u8 ata_op_code;
1387 u8 type;
1388#define IPR_TRACE_START 0x00
1389#define IPR_TRACE_FINISH 0xff
1390 u8 cmd_index;
1391
1392 __be32 res_handle;
1393 union {
1394 u32 ioasc;
1395 u32 add_data;
1396 u32 res_addr;
1397 } u;
1398};
1399
1400struct ipr_sglist {
1401 u32 order;
1402 u32 num_sg;
1403 u32 num_dma_sg;
1404 u32 buffer_len;
1405 struct scatterlist scatterlist[1];
1406};
1407
1408enum ipr_sdt_state {
1409 INACTIVE,
1410 WAIT_FOR_DUMP,
1411 GET_DUMP,
1412 READ_DUMP,
1413 ABORT_DUMP,
1414 DUMP_OBTAINED
1415};
1416
1417
1418struct ipr_ioa_cfg {
1419 char eye_catcher[8];
1420#define IPR_EYECATCHER "iprcfg"
1421
1422 struct list_head queue;
1423
1424 u8 in_reset_reload:1;
1425 u8 in_ioa_bringdown:1;
1426 u8 ioa_unit_checked:1;
1427 u8 dump_taken:1;
1428 u8 allow_ml_add_del:1;
1429 u8 needs_hard_reset:1;
1430 u8 dual_raid:1;
1431 u8 needs_warm_reset:1;
1432 u8 msi_received:1;
1433 u8 sis64:1;
1434 u8 dump_timeout:1;
1435 u8 cfg_locked:1;
1436 u8 clear_isr:1;
1437
1438 u8 revid;
1439
1440
1441
1442
1443 unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1444 unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1445 unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)];
1446
1447 u16 type;
1448
1449 u8 log_level;
1450#define IPR_MAX_LOG_LEVEL 4
1451#define IPR_DEFAULT_LOG_LEVEL 2
1452
1453#define IPR_NUM_TRACE_INDEX_BITS 8
1454#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
1455#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
1456 char trace_start[8];
1457#define IPR_TRACE_START_LABEL "trace"
1458 struct ipr_trace_entry *trace;
1459 atomic_t trace_index;
1460
1461 char cfg_table_start[8];
1462#define IPR_CFG_TBL_START "cfg"
1463 union {
1464 struct ipr_config_table *cfg_table;
1465 struct ipr_config_table64 *cfg_table64;
1466 } u;
1467 dma_addr_t cfg_table_dma;
1468 u32 cfg_table_size;
1469 u32 max_devs_supported;
1470
1471 char resource_table_label[8];
1472#define IPR_RES_TABLE_LABEL "res_tbl"
1473 struct ipr_resource_entry *res_entries;
1474 struct list_head free_res_q;
1475 struct list_head used_res_q;
1476
1477 char ipr_hcam_label[8];
1478#define IPR_HCAM_LABEL "hcams"
1479 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
1480 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
1481 struct list_head hostrcb_free_q;
1482 struct list_head hostrcb_pending_q;
1483
1484 struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM];
1485 u32 hrrq_num;
1486 atomic_t hrrq_index;
1487 u16 identify_hrrq_index;
1488
1489 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
1490
1491 unsigned int transop_timeout;
1492 const struct ipr_chip_cfg_t *chip_cfg;
1493 const struct ipr_chip_t *ipr_chip;
1494
1495 void __iomem *hdw_dma_regs;
1496 unsigned long hdw_dma_regs_pci;
1497 void __iomem *ioa_mailbox;
1498 struct ipr_interrupts regs;
1499
1500 u16 saved_pcix_cmd_reg;
1501 u16 reset_retries;
1502
1503 u32 errors_logged;
1504 u32 doorbell;
1505
1506 struct Scsi_Host *host;
1507 struct pci_dev *pdev;
1508 struct ipr_sglist *ucode_sglist;
1509 u8 saved_mode_page_len;
1510
1511 struct work_struct work_q;
1512
1513 wait_queue_head_t reset_wait_q;
1514 wait_queue_head_t msi_wait_q;
1515
1516 struct ipr_dump *dump;
1517 enum ipr_sdt_state sdt_state;
1518
1519 struct ipr_misc_cbs *vpd_cbs;
1520 dma_addr_t vpd_cbs_dma;
1521
1522 struct pci_pool *ipr_cmd_pool;
1523
1524 struct ipr_cmnd *reset_cmd;
1525 int (*reset) (struct ipr_cmnd *);
1526
1527 struct ata_host ata_host;
1528 char ipr_cmd_label[8];
1529#define IPR_CMD_LABEL "ipr_cmd"
1530 u32 max_cmds;
1531 struct ipr_cmnd **ipr_cmnd_list;
1532 dma_addr_t *ipr_cmnd_list_dma;
1533
1534 u16 intr_flag;
1535 unsigned int nvectors;
1536
1537 struct {
1538 unsigned short vec;
1539 char desc[22];
1540 } vectors_info[IPR_MAX_MSIX_VECTORS];
1541
1542 u32 iopoll_weight;
1543
1544};
1545
1546struct ipr_cmnd {
1547 struct ipr_ioarcb ioarcb;
1548 union {
1549 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1550 struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES];
1551 struct ipr_ata64_ioadl ata_ioadl;
1552 } i;
1553 union {
1554 struct ipr_ioasa ioasa;
1555 struct ipr_ioasa64 ioasa64;
1556 } s;
1557 struct list_head queue;
1558 struct scsi_cmnd *scsi_cmd;
1559 struct ata_queued_cmd *qc;
1560 struct completion completion;
1561 struct timer_list timer;
1562 void (*fast_done) (struct ipr_cmnd *);
1563 void (*done) (struct ipr_cmnd *);
1564 int (*job_step) (struct ipr_cmnd *);
1565 int (*job_step_failed) (struct ipr_cmnd *);
1566 u16 cmd_index;
1567 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1568 dma_addr_t sense_buffer_dma;
1569 unsigned short dma_use_sg;
1570 dma_addr_t dma_addr;
1571 struct ipr_cmnd *sibling;
1572 union {
1573 enum ipr_shutdown_type shutdown_type;
1574 struct ipr_hostrcb *hostrcb;
1575 unsigned long time_left;
1576 unsigned long scratch;
1577 struct ipr_resource_entry *res;
1578 struct scsi_device *sdev;
1579 } u;
1580
1581 struct ipr_hrr_queue *hrrq;
1582 struct ipr_ioa_cfg *ioa_cfg;
1583};
1584
1585struct ipr_ses_table_entry {
1586 char product_id[17];
1587 char compare_product_id_byte[17];
1588 u32 max_bus_speed_limit;
1589};
1590
1591struct ipr_dump_header {
1592 u32 eye_catcher;
1593#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1594 u32 len;
1595 u32 num_entries;
1596 u32 first_entry_offset;
1597 u32 status;
1598#define IPR_DUMP_STATUS_SUCCESS 0
1599#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1600#define IPR_DUMP_STATUS_FAILED 0xffffffff
1601 u32 os;
1602#define IPR_DUMP_OS_LINUX 0x4C4E5558
1603 u32 driver_name;
1604#define IPR_DUMP_DRIVER_NAME 0x49505232
1605}__attribute__((packed, aligned (4)));
1606
1607struct ipr_dump_entry_header {
1608 u32 eye_catcher;
1609#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1610 u32 len;
1611 u32 num_elems;
1612 u32 offset;
1613 u32 data_type;
1614#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1615#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1616 u32 id;
1617#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1618#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1619#define IPR_DUMP_TRACE_ID 0x54524143
1620#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1621#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1622#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1623#define IPR_DUMP_PEND_OPS 0x414F5053
1624 u32 status;
1625}__attribute__((packed, aligned (4)));
1626
1627struct ipr_dump_location_entry {
1628 struct ipr_dump_entry_header hdr;
1629 u8 location[20];
1630}__attribute__((packed));
1631
1632struct ipr_dump_trace_entry {
1633 struct ipr_dump_entry_header hdr;
1634 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1635}__attribute__((packed, aligned (4)));
1636
1637struct ipr_dump_version_entry {
1638 struct ipr_dump_entry_header hdr;
1639 u8 version[sizeof(IPR_DRIVER_VERSION)];
1640};
1641
1642struct ipr_dump_ioa_type_entry {
1643 struct ipr_dump_entry_header hdr;
1644 u32 type;
1645 u32 fw_version;
1646};
1647
1648struct ipr_driver_dump {
1649 struct ipr_dump_header hdr;
1650 struct ipr_dump_version_entry version_entry;
1651 struct ipr_dump_location_entry location_entry;
1652 struct ipr_dump_ioa_type_entry ioa_type_entry;
1653 struct ipr_dump_trace_entry trace_entry;
1654}__attribute__((packed));
1655
1656struct ipr_ioa_dump {
1657 struct ipr_dump_entry_header hdr;
1658 struct ipr_sdt sdt;
1659 __be32 **ioa_data;
1660 u32 reserved;
1661 u32 next_page_index;
1662 u32 page_offset;
1663 u32 format;
1664}__attribute__((packed, aligned (4)));
1665
1666struct ipr_dump {
1667 struct kref kref;
1668 struct ipr_ioa_cfg *ioa_cfg;
1669 struct ipr_driver_dump driver_dump;
1670 struct ipr_ioa_dump ioa_dump;
1671};
1672
1673struct ipr_error_table_t {
1674 u32 ioasc;
1675 int log_ioasa;
1676 int log_hcam;
1677 char *error;
1678};
1679
1680struct ipr_software_inq_lid_info {
1681 __be32 load_id;
1682 __be32 timestamp[3];
1683}__attribute__((packed, aligned (4)));
1684
1685struct ipr_ucode_image_header {
1686 __be32 header_length;
1687 __be32 lid_table_offset;
1688 u8 major_release;
1689 u8 card_type;
1690 u8 minor_release[2];
1691 u8 reserved[20];
1692 char eyecatcher[16];
1693 __be32 num_lids;
1694 struct ipr_software_inq_lid_info lid[1];
1695}__attribute__((packed, aligned (4)));
1696
1697
1698
1699
1700#define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1701
1702#ifdef CONFIG_SCSI_IPR_TRACE
1703#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1704#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1705#else
1706#define ipr_create_trace_file(kobj, attr) 0
1707#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1708#endif
1709
1710#ifdef CONFIG_SCSI_IPR_DUMP
1711#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1712#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1713#else
1714#define ipr_create_dump_file(kobj, attr) 0
1715#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1716#endif
1717
1718
1719
1720
1721#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1722#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1723#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1724
1725#define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \
1726 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1727 bus, target, lun, ##__VA_ARGS__)
1728
1729#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1730 ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__)
1731
1732#define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \
1733 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \
1734 (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__)
1735
1736#define ipr_ra_err(ioa_cfg, ra, fmt, ...) \
1737 ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__)
1738
1739#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1740{ \
1741 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1742 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1743 } else { \
1744 ipr_err(fmt": %d:%d:%d:%d\n", \
1745 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1746 (res).bus, (res).target, (res).lun); \
1747 } \
1748}
1749
1750#define ipr_hcam_err(hostrcb, fmt, ...) \
1751{ \
1752 if (ipr_is_device(hostrcb)) { \
1753 if ((hostrcb)->ioa_cfg->sis64) { \
1754 printk(KERN_ERR IPR_NAME ": %s: " fmt, \
1755 ipr_format_res_path(hostrcb->ioa_cfg, \
1756 hostrcb->hcam.u.error64.fd_res_path, \
1757 hostrcb->rp_buffer, \
1758 sizeof(hostrcb->rp_buffer)), \
1759 __VA_ARGS__); \
1760 } else { \
1761 ipr_ra_err((hostrcb)->ioa_cfg, \
1762 (hostrcb)->hcam.u.error.fd_res_addr, \
1763 fmt, __VA_ARGS__); \
1764 } \
1765 } else { \
1766 dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \
1767 } \
1768}
1769
1770#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1771 __FILE__, __func__, __LINE__)
1772
1773#define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__))
1774#define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__))
1775
1776#define ipr_err_separator \
1777ipr_err("----------------------------------------------------------\n")
1778
1779
1780
1781
1782
1783
1784
1785
1786
1787
1788
1789
1790
1791static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1792{
1793 return res->type == IPR_RES_TYPE_IOAFP;
1794}
1795
1796
1797
1798
1799
1800
1801
1802
1803static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1804{
1805 return res->type == IPR_RES_TYPE_AF_DASD ||
1806 res->type == IPR_RES_TYPE_REMOTE_AF_DASD;
1807}
1808
1809
1810
1811
1812
1813
1814
1815
1816static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1817{
1818 return res->type == IPR_RES_TYPE_VOLUME_SET;
1819}
1820
1821
1822
1823
1824
1825
1826
1827
1828static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1829{
1830 return res->type == IPR_RES_TYPE_GENERIC_SCSI;
1831}
1832
1833
1834
1835
1836
1837
1838
1839
1840static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res)
1841{
1842 if (ipr_is_af_dasd_device(res) ||
1843 (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data)))
1844 return 1;
1845 else
1846 return 0;
1847}
1848
1849
1850
1851
1852
1853
1854
1855
1856static inline int ipr_is_gata(struct ipr_resource_entry *res)
1857{
1858 return res->type == IPR_RES_TYPE_GENERIC_ATA;
1859}
1860
1861
1862
1863
1864
1865
1866
1867
1868static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1869{
1870 if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL)
1871 return 1;
1872 return 0;
1873}
1874
1875
1876
1877
1878
1879
1880
1881
1882static inline int ipr_is_device(struct ipr_hostrcb *hostrcb)
1883{
1884 struct ipr_res_addr *res_addr;
1885 u8 *res_path;
1886
1887 if (hostrcb->ioa_cfg->sis64) {
1888 res_path = &hostrcb->hcam.u.error64.fd_res_path[0];
1889 if ((res_path[0] == 0x00 || res_path[0] == 0x80 ||
1890 res_path[0] == 0x81) && res_path[2] != 0xFF)
1891 return 1;
1892 } else {
1893 res_addr = &hostrcb->hcam.u.error.fd_res_addr;
1894
1895 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1896 (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1)))
1897 return 1;
1898 }
1899 return 0;
1900}
1901
1902
1903
1904
1905
1906
1907
1908
1909static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1910{
1911 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1912
1913 switch (bar_sel) {
1914 case IPR_SDT_FMT2_BAR0_SEL:
1915 case IPR_SDT_FMT2_BAR1_SEL:
1916 case IPR_SDT_FMT2_BAR2_SEL:
1917 case IPR_SDT_FMT2_BAR3_SEL:
1918 case IPR_SDT_FMT2_BAR4_SEL:
1919 case IPR_SDT_FMT2_BAR5_SEL:
1920 case IPR_SDT_FMT2_EXP_ROM_SEL:
1921 return 1;
1922 };
1923
1924 return 0;
1925}
1926
1927#ifndef writeq
1928static inline void writeq(u64 val, void __iomem *addr)
1929{
1930 writel(((u32) (val >> 32)), addr);
1931 writel(((u32) (val)), (addr + 4));
1932}
1933#endif
1934
1935#endif
1936
