LXR linux/drivers/scsi/mac53c94.h

   1/*
   2 * mac53c94.h: definitions for the driver for the 53c94 SCSI bus adaptor
   3 * found on Power Macintosh computers, controlling the external SCSI chain.
   4 *
   5 * Copyright (C) 1996 Paul Mackerras.
   6 */
   7#ifndef _MAC53C94_H
   8#define _MAC53C94_H
   9
  10/*
  11 * Registers in the 53C94 controller.
  12 */
  13
  14struct mac53c94_regs {
  15        unsigned char   count_lo;
  16        char pad0[15];
  17        unsigned char   count_mid;
  18        char pad1[15];
  19        unsigned char   fifo;
  20        char pad2[15];
  21        unsigned char   command;
  22        char pad3[15];
  23        unsigned char   status;
  24        char pad4[15];
  25        unsigned char   interrupt;
  26        char pad5[15];
  27        unsigned char   seqstep;
  28        char pad6[15];
  29        unsigned char   flags;
  30        char pad7[15];
  31        unsigned char   config1;
  32        char pad8[15];
  33        unsigned char   clk_factor;
  34        char pad9[15];
  35        unsigned char   test;
  36        char pad10[15];
  37        unsigned char   config2;
  38        char pad11[15];
  39        unsigned char   config3;
  40        char pad12[15];
  41        unsigned char   config4;
  42        char pad13[15];
  43        unsigned char   count_hi;
  44        char pad14[15];
  45        unsigned char   fifo_res;
  46        char pad15[15];
  47};
  48
  49/*
  50 * Alternate functions for some registers.
  51 */
  52#define dest_id         status
  53#define sel_timeout     interrupt
  54#define sync_period     seqstep
  55#define sync_offset     flags
  56
  57/*
  58 * Bits in command register.
  59 */
  60#define CMD_DMA_MODE    0x80
  61#define CMD_MODE_MASK   0x70
  62#define CMD_MODE_INIT   0x10
  63#define CMD_MODE_TARG   0x20
  64#define CMD_MODE_DISC   0x40
  65
  66#define CMD_NOP         0
  67#define CMD_FLUSH       1
  68#define CMD_RESET       2
  69#define CMD_SCSI_RESET  3
  70
  71#define CMD_XFER_DATA   0x10
  72#define CMD_I_COMPLETE  0x11
  73#define CMD_ACCEPT_MSG  0x12
  74#define CMD_XFER_PAD    0x18
  75#define CMD_SET_ATN     0x1a
  76#define CMD_CLR_ATN     0x1b
  77
  78#define CMD_SEND_MSG    0x20
  79#define CMD_SEND_STATUS 0x21
  80#define CMD_SEND_DATA   0x22
  81#define CMD_DISC_SEQ    0x23
  82#define CMD_TERMINATE   0x24
  83#define CMD_T_COMPLETE  0x25
  84#define CMD_DISCONNECT  0x27
  85#define CMD_RECV_MSG    0x28
  86#define CMD_RECV_CDB    0x29
  87#define CMD_RECV_DATA   0x2a
  88#define CMD_RECV_CMD    0x2b
  89#define CMD_ABORT_DMA   0x04
  90
  91#define CMD_RESELECT    0x40
  92#define CMD_SELECT      0x41
  93#define CMD_SELECT_ATN  0x42
  94#define CMD_SELATN_STOP 0x43
  95#define CMD_ENABLE_SEL  0x44
  96#define CMD_DISABLE_SEL 0x45
  97#define CMD_SEL_ATN3    0x46
  98#define CMD_RESEL_ATN3  0x47
  99
 100/*
 101 * Bits in status register.
 102 */
 103#define STAT_IRQ        0x80
 104#define STAT_ERROR      0x40
 105#define STAT_PARITY     0x20
 106#define STAT_TC_ZERO    0x10
 107#define STAT_DONE       0x08
 108#define STAT_PHASE      0x07
 109#define STAT_MSG        0x04
 110#define STAT_CD         0x02
 111#define STAT_IO         0x01
 112
 113/*
 114 * Bits in interrupt register.
 115 */
 116#define INTR_RESET      0x80    /* SCSI bus was reset */
 117#define INTR_ILL_CMD    0x40    /* illegal command */
 118#define INTR_DISCONNECT 0x20    /* we got disconnected */
 119#define INTR_BUS_SERV   0x10    /* bus service requested */
 120#define INTR_DONE       0x08    /* function completed */
 121#define INTR_RESELECTED 0x04    /* we were reselected */
 122#define INTR_SEL_ATN    0x02    /* we were selected, ATN asserted */
 123#define INTR_SELECT     0x01    /* we were selected, ATN negated */
 124
 125/*
 126 * Encoding for the select timeout.
 127 */
 128#define TIMO_VAL(x)     ((x) * 5000 / 7682)
 129
 130/*
 131 * Bits in sequence step register.
 132 */
 133#define SS_MASK         7
 134#define SS_ARB_SEL      0       /* Selection & arbitration complete */
 135#define SS_MSG_SENT     1       /* One message byte sent */
 136#define SS_NOT_CMD      2       /* Not in command phase */
 137#define SS_PHASE_CHG    3       /* Early phase change, cmd bytes lost */
 138#define SS_DONE         4       /* Command was sent OK */
 139
 140/*
 141 * Encoding for sync transfer period.
 142 */
 143#define SYNCP_MASK      0x1f
 144#define SYNCP_MIN       4
 145#define SYNCP_MAX       31
 146
 147/*
 148 * Bits in flags register.
 149 */
 150#define FLAGS_FIFO_LEV  0x1f
 151#define FLAGS_SEQ_STEP  0xe0
 152
 153/*
 154 * Encoding for sync offset.
 155 */
 156#define SYNCO_MASK      0x0f
 157#define SYNCO_ASS_CTRL  0x30    /* REQ/ACK assertion control */
 158#define SYNCO_NEG_CTRL  0xc0    /* REQ/ACK negation control */
 159
 160/*
 161 * Bits in config1 register.
 162 */
 163#define CF1_SLOW_CABLE  0x80    /* Slow cable mode */
 164#define CF1_NO_RES_REP  0x40    /* Disable SCSI reset reports */
 165#define CF1_PAR_TEST    0x20    /* Parity test mode enable */
 166#define CF1_PAR_ENABLE  0x10    /* Enable parity checks */
 167#define CF1_TEST        0x08    /* Chip tests */
 168#define CF1_MY_ID       0x07    /* Controller's address on bus */
 169
 170/*
 171 * Encoding for clk_factor register.
 172 */
 173#define CLKF_MASK       7
 174#define CLKF_VAL(freq)  ((((freq) + 4999999) / 5000000) & CLKF_MASK)
 175
 176/*
 177 * Bits in test mode register.
 178 */
 179#define TEST_TARGET     1       /* target test mode */
 180#define TEST_INITIATOR  2       /* initiator test mode */
 181#define TEST_TRISTATE   4       /* tristate (hi-z) test mode */
 182
 183/*
 184 * Bits in config2 register.
 185 */
 186#define CF2_RFB         0x80
 187#define CF2_FEATURE_EN  0x40    /* enable features / phase latch */
 188#define CF2_BYTECTRL    0x20
 189#define CF2_DREQ_HIZ    0x10
 190#define CF2_SCSI2       0x08
 191#define CF2_PAR_ABORT   0x04    /* bad parity target abort */
 192#define CF2_REG_PARERR  0x02    /* register parity error */
 193#define CF2_DMA_PARERR  0x01    /* DMA parity error */
 194
 195/*
 196 * Bits in the config3 register.
 197 */
 198#define CF3_ID_MSG_CHK  0x80
 199#define CF3_3B_MSGS     0x40
 200#define CF3_CDB10       0x20
 201#define CF3_FASTSCSI    0x10    /* enable fast SCSI support */
 202#define CF3_FASTCLOCK   0x08
 203#define CF3_SAVERESID   0x04
 204#define CF3_ALT_DMA     0x02
 205#define CF3_THRESH_8    0x01
 206
 207/*
 208 * Bits in the config4 register.
 209 */
 210#define CF4_EAN         0x04
 211#define CF4_TEST        0x02
 212#define CF4_BBTE        0x01
 213
 214#endif /* _MAC53C94_H */
 215