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26#ifndef _MV_SAS_H_
27#define _MV_SAS_H_
28
29#include <linux/kernel.h>
30#include <linux/module.h>
31#include <linux/spinlock.h>
32#include <linux/delay.h>
33#include <linux/types.h>
34#include <linux/ctype.h>
35#include <linux/dma-mapping.h>
36#include <linux/pci.h>
37#include <linux/platform_device.h>
38#include <linux/interrupt.h>
39#include <linux/irq.h>
40#include <linux/slab.h>
41#include <linux/vmalloc.h>
42#include <asm/unaligned.h>
43#include <scsi/libsas.h>
44#include <scsi/scsi.h>
45#include <scsi/scsi_tcq.h>
46#include <scsi/sas_ata.h>
47#include "mv_defs.h"
48
49#define DRV_NAME "mvsas"
50#define DRV_VERSION "0.8.16"
51#define MVS_ID_NOT_MAPPED 0x7f
52#define WIDE_PORT_MAX_PHY 4
53#define mv_printk(fmt, arg ...) \
54 printk(KERN_DEBUG"%s %d:" fmt, __FILE__, __LINE__, ## arg)
55#ifdef MV_DEBUG
56#define mv_dprintk(format, arg...) \
57 printk(KERN_DEBUG"%s %d:" format, __FILE__, __LINE__, ## arg)
58#else
59#define mv_dprintk(format, arg...)
60#endif
61#define MV_MAX_U32 0xffffffff
62
63extern int interrupt_coalescing;
64extern struct mvs_tgt_initiator mvs_tgt;
65extern struct mvs_info *tgt_mvi;
66extern const struct mvs_dispatch mvs_64xx_dispatch;
67extern const struct mvs_dispatch mvs_94xx_dispatch;
68extern struct kmem_cache *mvs_task_list_cache;
69
70#define DEV_IS_EXPANDER(type) \
71 ((type == SAS_EDGE_EXPANDER_DEVICE) || (type == SAS_FANOUT_EXPANDER_DEVICE))
72
73#define bit(n) ((u64)1 << n)
74
75#define for_each_phy(__lseq_mask, __mc, __lseq) \
76 for ((__mc) = (__lseq_mask), (__lseq) = 0; \
77 (__mc) != 0 ; \
78 (++__lseq), (__mc) >>= 1)
79
80#define MVS_PHY_ID (1U << sas_phy->id)
81#define MV_INIT_DELAYED_WORK(w, f, d) INIT_DELAYED_WORK(w, f)
82#define UNASSOC_D2H_FIS(id) \
83 ((void *) mvi->rx_fis + 0x100 * id)
84#define SATA_RECEIVED_FIS_LIST(reg_set) \
85 ((void *) mvi->rx_fis + mvi->chip->fis_offs + 0x100 * reg_set)
86#define SATA_RECEIVED_SDB_FIS(reg_set) \
87 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x58)
88#define SATA_RECEIVED_D2H_FIS(reg_set) \
89 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x40)
90#define SATA_RECEIVED_PIO_FIS(reg_set) \
91 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x20)
92#define SATA_RECEIVED_DMA_FIS(reg_set) \
93 (SATA_RECEIVED_FIS_LIST(reg_set) + 0x00)
94
95enum dev_status {
96 MVS_DEV_NORMAL = 0x0,
97 MVS_DEV_EH = 0x1,
98};
99
100enum dev_reset {
101 MVS_SOFT_RESET = 0,
102 MVS_HARD_RESET = 1,
103 MVS_PHY_TUNE = 2,
104};
105
106struct mvs_info;
107
108struct mvs_dispatch {
109 char *name;
110 int (*chip_init)(struct mvs_info *mvi);
111 int (*spi_init)(struct mvs_info *mvi);
112 int (*chip_ioremap)(struct mvs_info *mvi);
113 void (*chip_iounmap)(struct mvs_info *mvi);
114 irqreturn_t (*isr)(struct mvs_info *mvi, int irq, u32 stat);
115 u32 (*isr_status)(struct mvs_info *mvi, int irq);
116 void (*interrupt_enable)(struct mvs_info *mvi);
117 void (*interrupt_disable)(struct mvs_info *mvi);
118
119 u32 (*read_phy_ctl)(struct mvs_info *mvi, u32 port);
120 void (*write_phy_ctl)(struct mvs_info *mvi, u32 port, u32 val);
121
122 u32 (*read_port_cfg_data)(struct mvs_info *mvi, u32 port);
123 void (*write_port_cfg_data)(struct mvs_info *mvi, u32 port, u32 val);
124 void (*write_port_cfg_addr)(struct mvs_info *mvi, u32 port, u32 addr);
125
126 u32 (*read_port_vsr_data)(struct mvs_info *mvi, u32 port);
127 void (*write_port_vsr_data)(struct mvs_info *mvi, u32 port, u32 val);
128 void (*write_port_vsr_addr)(struct mvs_info *mvi, u32 port, u32 addr);
129
130 u32 (*read_port_irq_stat)(struct mvs_info *mvi, u32 port);
131 void (*write_port_irq_stat)(struct mvs_info *mvi, u32 port, u32 val);
132
133 u32 (*read_port_irq_mask)(struct mvs_info *mvi, u32 port);
134 void (*write_port_irq_mask)(struct mvs_info *mvi, u32 port, u32 val);
135
136 void (*command_active)(struct mvs_info *mvi, u32 slot_idx);
137 void (*clear_srs_irq)(struct mvs_info *mvi, u8 reg_set, u8 clear_all);
138 void (*issue_stop)(struct mvs_info *mvi, enum mvs_port_type type,
139 u32 tfs);
140 void (*start_delivery)(struct mvs_info *mvi, u32 tx);
141 u32 (*rx_update)(struct mvs_info *mvi);
142 void (*int_full)(struct mvs_info *mvi);
143 u8 (*assign_reg_set)(struct mvs_info *mvi, u8 *tfs);
144 void (*free_reg_set)(struct mvs_info *mvi, u8 *tfs);
145 u32 (*prd_size)(void);
146 u32 (*prd_count)(void);
147 void (*make_prd)(struct scatterlist *scatter, int nr, void *prd);
148 void (*detect_porttype)(struct mvs_info *mvi, int i);
149 int (*oob_done)(struct mvs_info *mvi, int i);
150 void (*fix_phy_info)(struct mvs_info *mvi, int i,
151 struct sas_identify_frame *id);
152 void (*phy_work_around)(struct mvs_info *mvi, int i);
153 void (*phy_set_link_rate)(struct mvs_info *mvi, u32 phy_id,
154 struct sas_phy_linkrates *rates);
155 u32 (*phy_max_link_rate)(void);
156 void (*phy_disable)(struct mvs_info *mvi, u32 phy_id);
157 void (*phy_enable)(struct mvs_info *mvi, u32 phy_id);
158 void (*phy_reset)(struct mvs_info *mvi, u32 phy_id, int hard);
159 void (*stp_reset)(struct mvs_info *mvi, u32 phy_id);
160 void (*clear_active_cmds)(struct mvs_info *mvi);
161 u32 (*spi_read_data)(struct mvs_info *mvi);
162 void (*spi_write_data)(struct mvs_info *mvi, u32 data);
163 int (*spi_buildcmd)(struct mvs_info *mvi,
164 u32 *dwCmd,
165 u8 cmd,
166 u8 read,
167 u8 length,
168 u32 addr
169 );
170 int (*spi_issuecmd)(struct mvs_info *mvi, u32 cmd);
171 int (*spi_waitdataready)(struct mvs_info *mvi, u32 timeout);
172 void (*dma_fix)(struct mvs_info *mvi, u32 phy_mask,
173 int buf_len, int from, void *prd);
174 void (*tune_interrupt)(struct mvs_info *mvi, u32 time);
175 void (*non_spec_ncq_error)(struct mvs_info *mvi);
176
177};
178
179struct mvs_chip_info {
180 u32 n_host;
181 u32 n_phy;
182 u32 fis_offs;
183 u32 fis_count;
184 u32 srs_sz;
185 u32 sg_width;
186 u32 slot_width;
187 const struct mvs_dispatch *dispatch;
188};
189#define MVS_MAX_SG (1U << mvi->chip->sg_width)
190#define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
191#define MVS_RX_FISL_SZ \
192 (mvi->chip->fis_offs + (mvi->chip->fis_count * 0x100))
193#define MVS_CHIP_DISP (mvi->chip->dispatch)
194
195struct mvs_err_info {
196 __le32 flags;
197 __le32 flags2;
198};
199
200struct mvs_cmd_hdr {
201 __le32 flags;
202 __le32 lens;
203 __le32 tags;
204 __le32 data_len;
205 __le64 cmd_tbl;
206 __le64 open_frame;
207 __le64 status_buf;
208 __le64 prd_tbl;
209 __le32 reserved[4];
210};
211
212struct mvs_port {
213 struct asd_sas_port sas_port;
214 u8 port_attached;
215 u8 wide_port_phymap;
216 struct list_head list;
217};
218
219struct mvs_phy {
220 struct mvs_info *mvi;
221 struct mvs_port *port;
222 struct asd_sas_phy sas_phy;
223 struct sas_identify identify;
224 struct scsi_device *sdev;
225 struct timer_list timer;
226 u64 dev_sas_addr;
227 u64 att_dev_sas_addr;
228 u32 att_dev_info;
229 u32 dev_info;
230 u32 phy_type;
231 u32 phy_status;
232 u32 irq_status;
233 u32 frame_rcvd_size;
234 u8 frame_rcvd[32];
235 u8 phy_attached;
236 u8 phy_mode;
237 u8 reserved[2];
238 u32 phy_event;
239 enum sas_linkrate minimum_linkrate;
240 enum sas_linkrate maximum_linkrate;
241};
242
243struct mvs_device {
244 struct list_head dev_entry;
245 enum sas_device_type dev_type;
246 struct mvs_info *mvi_info;
247 struct domain_device *sas_device;
248 struct timer_list timer;
249 u32 attached_phy;
250 u32 device_id;
251 u32 running_req;
252 u8 taskfileset;
253 u8 dev_status;
254 u16 reserved;
255};
256
257
258struct phy_tuning {
259
260 u8 trans_emp_en:1;
261
262 u8 trans_emp_amp:4;
263
264 u8 Reserved_2bit_1:3;
265
266 u8 trans_amp:5;
267
268 u8 trans_amp_adj:2;
269
270 u8 resv_2bit_2:1;
271
272 u8 reserved[2];
273};
274
275struct ffe_control {
276
277 u8 ffe_cap_sel:4;
278
279 u8 ffe_rss_sel:3;
280
281 u8 reserved:1;
282};
283
284
285
286
287
288
289struct hba_info_page {
290
291
292 u8 signature[4];
293
294
295 u32 reserved1[13];
296
297
298
299 u64 sas_addr[8];
300
301
302
303
304
305
306
307
308 struct ffe_control ffe_ctl[8];
309
310 u32 reserved2[12];
311
312
313
314 u8 phy_rate[8];
315
316
317
318 struct phy_tuning phy_tuning[8];
319
320
321 u32 reserved3[10];
322};
323
324struct mvs_slot_info {
325 struct list_head entry;
326 union {
327 struct sas_task *task;
328 void *tdata;
329 };
330 u32 n_elem;
331 u32 tx;
332 u32 slot_tag;
333
334
335
336
337 void *buf;
338 dma_addr_t buf_dma;
339 void *response;
340 struct mvs_port *port;
341 struct mvs_device *device;
342 void *open_frame;
343};
344
345struct mvs_info {
346 unsigned long flags;
347
348
349 spinlock_t lock;
350
351
352 struct pci_dev *pdev;
353 struct device *dev;
354
355
356 void __iomem *regs;
357
358
359 void __iomem *regs_ex;
360 u8 sas_addr[SAS_ADDR_SIZE];
361
362
363 struct sas_ha_struct *sas;
364 struct Scsi_Host *shost;
365
366
367 __le32 *tx;
368 dma_addr_t tx_dma;
369
370
371 u32 tx_prod;
372
373
374 __le32 *rx;
375 dma_addr_t rx_dma;
376
377
378 u32 rx_cons;
379
380
381 __le32 *rx_fis;
382 dma_addr_t rx_fis_dma;
383
384
385 struct mvs_cmd_hdr *slot;
386 dma_addr_t slot_dma;
387
388 u32 chip_id;
389 const struct mvs_chip_info *chip;
390
391 int tags_num;
392 unsigned long *tags;
393
394 struct mvs_phy phy[MVS_MAX_PHYS];
395 struct mvs_port port[MVS_MAX_PHYS];
396 u32 id;
397 u64 sata_reg_set;
398 struct list_head *hba_list;
399 struct list_head soc_entry;
400 struct list_head wq_list;
401 unsigned long instance;
402 u16 flashid;
403 u32 flashsize;
404 u32 flashsectSize;
405
406 void *addon;
407 struct hba_info_page hba_info_param;
408 struct mvs_device devices[MVS_MAX_DEVICES];
409 void *bulk_buffer;
410 dma_addr_t bulk_buffer_dma;
411 void *bulk_buffer1;
412 dma_addr_t bulk_buffer_dma1;
413#define TRASH_BUCKET_SIZE 0x20000
414 void *dma_pool;
415 struct mvs_slot_info slot_info[0];
416};
417
418struct mvs_prv_info{
419 u8 n_host;
420 u8 n_phy;
421 u8 scan_finished;
422 u8 reserve;
423 struct mvs_info *mvi[2];
424 struct tasklet_struct mv_tasklet;
425};
426
427struct mvs_wq {
428 struct delayed_work work_q;
429 struct mvs_info *mvi;
430 void *data;
431 int handler;
432 struct list_head entry;
433};
434
435struct mvs_task_exec_info {
436 struct sas_task *task;
437 struct mvs_cmd_hdr *hdr;
438 struct mvs_port *port;
439 u32 tag;
440 int n_elem;
441};
442
443struct mvs_task_list {
444 struct sas_task *task;
445 struct list_head list;
446};
447
448
449
450void mvs_get_sas_addr(void *buf, u32 buflen);
451void mvs_tag_clear(struct mvs_info *mvi, u32 tag);
452void mvs_tag_free(struct mvs_info *mvi, u32 tag);
453void mvs_tag_set(struct mvs_info *mvi, unsigned int tag);
454int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out);
455void mvs_tag_init(struct mvs_info *mvi);
456void mvs_iounmap(void __iomem *regs);
457int mvs_ioremap(struct mvs_info *mvi, int bar, int bar_ex);
458void mvs_phys_reset(struct mvs_info *mvi, u32 phy_mask, int hard);
459int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
460 void *funcdata);
461void mvs_set_sas_addr(struct mvs_info *mvi, int port_id, u32 off_lo,
462 u32 off_hi, u64 sas_addr);
463void mvs_scan_start(struct Scsi_Host *shost);
464int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time);
465int mvs_queue_command(struct sas_task *task, const int num,
466 gfp_t gfp_flags);
467int mvs_abort_task(struct sas_task *task);
468int mvs_abort_task_set(struct domain_device *dev, u8 *lun);
469int mvs_clear_aca(struct domain_device *dev, u8 *lun);
470int mvs_clear_task_set(struct domain_device *dev, u8 * lun);
471void mvs_port_formed(struct asd_sas_phy *sas_phy);
472void mvs_port_deformed(struct asd_sas_phy *sas_phy);
473int mvs_dev_found(struct domain_device *dev);
474void mvs_dev_gone(struct domain_device *dev);
475int mvs_lu_reset(struct domain_device *dev, u8 *lun);
476int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc, u32 flags);
477int mvs_I_T_nexus_reset(struct domain_device *dev);
478int mvs_query_task(struct sas_task *task);
479void mvs_release_task(struct mvs_info *mvi,
480 struct domain_device *dev);
481void mvs_do_release_task(struct mvs_info *mvi, int phy_no,
482 struct domain_device *dev);
483void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events);
484void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
485int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
486struct mvs_device *mvs_find_dev_by_reg_set(struct mvs_info *mvi, u8 reg_set);
487#endif
488
489