1
2
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5
6
7#include "qla_def.h"
8
9#include <linux/delay.h>
10#include <linux/slab.h>
11#include <linux/vmalloc.h>
12#include <asm/uaccess.h>
13
14
15
16
17
18
19
20
21
22static void
23qla2x00_lock_nvram_access(struct qla_hw_data *ha)
24{
25 uint16_t data;
26 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
27
28 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
29 data = RD_REG_WORD(®->nvram);
30 while (data & NVR_BUSY) {
31 udelay(100);
32 data = RD_REG_WORD(®->nvram);
33 }
34
35
36 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
37 RD_REG_WORD(®->u.isp2300.host_semaphore);
38 udelay(5);
39 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
40 while ((data & BIT_0) == 0) {
41
42 udelay(100);
43 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
44 RD_REG_WORD(®->u.isp2300.host_semaphore);
45 udelay(5);
46 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
47 }
48 }
49}
50
51
52
53
54
55static void
56qla2x00_unlock_nvram_access(struct qla_hw_data *ha)
57{
58 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
59
60 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
61 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0);
62 RD_REG_WORD(®->u.isp2300.host_semaphore);
63 }
64}
65
66
67
68
69
70
71static void
72qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data)
73{
74 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
75
76 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
77 RD_REG_WORD(®->nvram);
78 NVRAM_DELAY();
79 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_CLOCK |
80 NVR_WRT_ENABLE);
81 RD_REG_WORD(®->nvram);
82 NVRAM_DELAY();
83 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
84 RD_REG_WORD(®->nvram);
85 NVRAM_DELAY();
86}
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103static uint16_t
104qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd)
105{
106 uint8_t cnt;
107 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
108 uint16_t data = 0;
109 uint16_t reg_data;
110
111
112 nv_cmd <<= 5;
113 for (cnt = 0; cnt < 11; cnt++) {
114 if (nv_cmd & BIT_31)
115 qla2x00_nv_write(ha, NVR_DATA_OUT);
116 else
117 qla2x00_nv_write(ha, 0);
118 nv_cmd <<= 1;
119 }
120
121
122 for (cnt = 0; cnt < 16; cnt++) {
123 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK);
124 RD_REG_WORD(®->nvram);
125 NVRAM_DELAY();
126 data <<= 1;
127 reg_data = RD_REG_WORD(®->nvram);
128 if (reg_data & NVR_DATA_IN)
129 data |= BIT_0;
130 WRT_REG_WORD(®->nvram, NVR_SELECT);
131 RD_REG_WORD(®->nvram);
132 NVRAM_DELAY();
133 }
134
135
136 WRT_REG_WORD(®->nvram, NVR_DESELECT);
137 RD_REG_WORD(®->nvram);
138 NVRAM_DELAY();
139
140 return data;
141}
142
143
144
145
146
147
148
149
150
151
152static uint16_t
153qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr)
154{
155 uint16_t data;
156 uint32_t nv_cmd;
157
158 nv_cmd = addr << 16;
159 nv_cmd |= NV_READ_OP;
160 data = qla2x00_nvram_request(ha, nv_cmd);
161
162 return (data);
163}
164
165
166
167
168
169static void
170qla2x00_nv_deselect(struct qla_hw_data *ha)
171{
172 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
173
174 WRT_REG_WORD(®->nvram, NVR_DESELECT);
175 RD_REG_WORD(®->nvram);
176 NVRAM_DELAY();
177}
178
179
180
181
182
183
184
185static void
186qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, uint16_t data)
187{
188 int count;
189 uint16_t word;
190 uint32_t nv_cmd, wait_cnt;
191 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
192 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
193
194 qla2x00_nv_write(ha, NVR_DATA_OUT);
195 qla2x00_nv_write(ha, 0);
196 qla2x00_nv_write(ha, 0);
197
198 for (word = 0; word < 8; word++)
199 qla2x00_nv_write(ha, NVR_DATA_OUT);
200
201 qla2x00_nv_deselect(ha);
202
203
204 nv_cmd = (addr << 16) | NV_WRITE_OP;
205 nv_cmd |= data;
206 nv_cmd <<= 5;
207 for (count = 0; count < 27; count++) {
208 if (nv_cmd & BIT_31)
209 qla2x00_nv_write(ha, NVR_DATA_OUT);
210 else
211 qla2x00_nv_write(ha, 0);
212
213 nv_cmd <<= 1;
214 }
215
216 qla2x00_nv_deselect(ha);
217
218
219 WRT_REG_WORD(®->nvram, NVR_SELECT);
220 RD_REG_WORD(®->nvram);
221 wait_cnt = NVR_WAIT_CNT;
222 do {
223 if (!--wait_cnt) {
224 ql_dbg(ql_dbg_user, vha, 0x708d,
225 "NVRAM didn't go ready...\n");
226 break;
227 }
228 NVRAM_DELAY();
229 word = RD_REG_WORD(®->nvram);
230 } while ((word & NVR_DATA_IN) == 0);
231
232 qla2x00_nv_deselect(ha);
233
234
235 qla2x00_nv_write(ha, NVR_DATA_OUT);
236 for (count = 0; count < 10; count++)
237 qla2x00_nv_write(ha, 0);
238
239 qla2x00_nv_deselect(ha);
240}
241
242static int
243qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr,
244 uint16_t data, uint32_t tmo)
245{
246 int ret, count;
247 uint16_t word;
248 uint32_t nv_cmd;
249 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
250
251 ret = QLA_SUCCESS;
252
253 qla2x00_nv_write(ha, NVR_DATA_OUT);
254 qla2x00_nv_write(ha, 0);
255 qla2x00_nv_write(ha, 0);
256
257 for (word = 0; word < 8; word++)
258 qla2x00_nv_write(ha, NVR_DATA_OUT);
259
260 qla2x00_nv_deselect(ha);
261
262
263 nv_cmd = (addr << 16) | NV_WRITE_OP;
264 nv_cmd |= data;
265 nv_cmd <<= 5;
266 for (count = 0; count < 27; count++) {
267 if (nv_cmd & BIT_31)
268 qla2x00_nv_write(ha, NVR_DATA_OUT);
269 else
270 qla2x00_nv_write(ha, 0);
271
272 nv_cmd <<= 1;
273 }
274
275 qla2x00_nv_deselect(ha);
276
277
278 WRT_REG_WORD(®->nvram, NVR_SELECT);
279 RD_REG_WORD(®->nvram);
280 do {
281 NVRAM_DELAY();
282 word = RD_REG_WORD(®->nvram);
283 if (!--tmo) {
284 ret = QLA_FUNCTION_FAILED;
285 break;
286 }
287 } while ((word & NVR_DATA_IN) == 0);
288
289 qla2x00_nv_deselect(ha);
290
291
292 qla2x00_nv_write(ha, NVR_DATA_OUT);
293 for (count = 0; count < 10; count++)
294 qla2x00_nv_write(ha, 0);
295
296 qla2x00_nv_deselect(ha);
297
298 return ret;
299}
300
301
302
303
304
305static int
306qla2x00_clear_nvram_protection(struct qla_hw_data *ha)
307{
308 int ret, stat;
309 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
310 uint32_t word, wait_cnt;
311 uint16_t wprot, wprot_old;
312 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
313
314
315 ret = QLA_FUNCTION_FAILED;
316
317 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
318 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
319 __constant_cpu_to_le16(0x1234), 100000);
320 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
321 if (stat != QLA_SUCCESS || wprot != 0x1234) {
322
323 qla2x00_nv_write(ha, NVR_DATA_OUT);
324 qla2x00_nv_write(ha, 0);
325 qla2x00_nv_write(ha, 0);
326 for (word = 0; word < 8; word++)
327 qla2x00_nv_write(ha, NVR_DATA_OUT);
328
329 qla2x00_nv_deselect(ha);
330
331
332 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
333 qla2x00_nv_write(ha, NVR_PR_ENABLE);
334 qla2x00_nv_write(ha, NVR_PR_ENABLE);
335 for (word = 0; word < 8; word++)
336 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
337
338 qla2x00_nv_deselect(ha);
339
340
341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
343 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
344 for (word = 0; word < 8; word++)
345 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
346
347 qla2x00_nv_deselect(ha);
348
349
350 WRT_REG_WORD(®->nvram, NVR_SELECT);
351 RD_REG_WORD(®->nvram);
352 wait_cnt = NVR_WAIT_CNT;
353 do {
354 if (!--wait_cnt) {
355 ql_dbg(ql_dbg_user, vha, 0x708e,
356 "NVRAM didn't go ready...\n");
357 break;
358 }
359 NVRAM_DELAY();
360 word = RD_REG_WORD(®->nvram);
361 } while ((word & NVR_DATA_IN) == 0);
362
363 if (wait_cnt)
364 ret = QLA_SUCCESS;
365 } else
366 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
367
368 return ret;
369}
370
371static void
372qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat)
373{
374 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
375 uint32_t word, wait_cnt;
376 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
377
378 if (stat != QLA_SUCCESS)
379 return;
380
381
382
383 qla2x00_nv_write(ha, NVR_DATA_OUT);
384 qla2x00_nv_write(ha, 0);
385 qla2x00_nv_write(ha, 0);
386 for (word = 0; word < 8; word++)
387 qla2x00_nv_write(ha, NVR_DATA_OUT);
388
389 qla2x00_nv_deselect(ha);
390
391
392 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
393 qla2x00_nv_write(ha, NVR_PR_ENABLE);
394 qla2x00_nv_write(ha, NVR_PR_ENABLE);
395 for (word = 0; word < 8; word++)
396 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
397
398 qla2x00_nv_deselect(ha);
399
400
401 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
402 qla2x00_nv_write(ha, NVR_PR_ENABLE);
403 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
404 for (word = 0; word < 8; word++)
405 qla2x00_nv_write(ha, NVR_PR_ENABLE);
406
407 qla2x00_nv_deselect(ha);
408
409
410 WRT_REG_WORD(®->nvram, NVR_SELECT);
411 RD_REG_WORD(®->nvram);
412 wait_cnt = NVR_WAIT_CNT;
413 do {
414 if (!--wait_cnt) {
415 ql_dbg(ql_dbg_user, vha, 0x708f,
416 "NVRAM didn't go ready...\n");
417 break;
418 }
419 NVRAM_DELAY();
420 word = RD_REG_WORD(®->nvram);
421 } while ((word & NVR_DATA_IN) == 0);
422}
423
424
425
426
427
428
429static inline uint32_t
430flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr)
431{
432 return ha->flash_conf_off | faddr;
433}
434
435static inline uint32_t
436flash_data_addr(struct qla_hw_data *ha, uint32_t faddr)
437{
438 return ha->flash_data_off | faddr;
439}
440
441static inline uint32_t
442nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr)
443{
444 return ha->nvram_conf_off | naddr;
445}
446
447static inline uint32_t
448nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr)
449{
450 return ha->nvram_data_off | naddr;
451}
452
453static uint32_t
454qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr)
455{
456 int rval;
457 uint32_t cnt, data;
458 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
459
460 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG);
461
462 rval = QLA_SUCCESS;
463 for (cnt = 3000;
464 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 &&
465 rval == QLA_SUCCESS; cnt--) {
466 if (cnt)
467 udelay(10);
468 else
469 rval = QLA_FUNCTION_TIMEOUT;
470 cond_resched();
471 }
472
473
474 data = 0xDEADDEAD;
475 if (rval == QLA_SUCCESS)
476 data = RD_REG_DWORD(®->flash_data);
477
478 return data;
479}
480
481uint32_t *
482qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
483 uint32_t dwords)
484{
485 uint32_t i;
486 struct qla_hw_data *ha = vha->hw;
487
488
489 for (i = 0; i < dwords; i++, faddr++)
490 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
491 flash_data_addr(ha, faddr)));
492
493 return dwptr;
494}
495
496static int
497qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data)
498{
499 int rval;
500 uint32_t cnt;
501 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
502
503 WRT_REG_DWORD(®->flash_data, data);
504 RD_REG_DWORD(®->flash_data);
505 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG);
506
507 rval = QLA_SUCCESS;
508 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) &&
509 rval == QLA_SUCCESS; cnt--) {
510 if (cnt)
511 udelay(10);
512 else
513 rval = QLA_FUNCTION_TIMEOUT;
514 cond_resched();
515 }
516 return rval;
517}
518
519static void
520qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
521 uint8_t *flash_id)
522{
523 uint32_t ids;
524
525 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x03ab));
526 *man_id = LSB(ids);
527 *flash_id = MSB(ids);
528
529
530 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
531
532
533
534
535
536
537 ids = qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x009f));
538 *man_id = LSB(ids);
539 *flash_id = MSB(ids);
540 }
541}
542
543static int
544qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start)
545{
546 const char *loc, *locations[] = { "DEF", "PCI" };
547 uint32_t pcihdr, pcids;
548 uint32_t *dcode;
549 uint8_t *buf, *bcode, last_image;
550 uint16_t cnt, chksum, *wptr;
551 struct qla_flt_location *fltl;
552 struct qla_hw_data *ha = vha->hw;
553 struct req_que *req = ha->req_q_map[0];
554
555
556
557
558
559
560 loc = locations[0];
561 *start = 0;
562 if (IS_QLA24XX_TYPE(ha))
563 *start = FA_FLASH_LAYOUT_ADDR_24;
564 else if (IS_QLA25XX(ha))
565 *start = FA_FLASH_LAYOUT_ADDR;
566 else if (IS_QLA81XX(ha))
567 *start = FA_FLASH_LAYOUT_ADDR_81;
568 else if (IS_QLA82XX(ha)) {
569 *start = FA_FLASH_LAYOUT_ADDR_82;
570 goto end;
571 } else if (IS_QLA83XX(ha)) {
572 *start = FA_FLASH_LAYOUT_ADDR_83;
573 goto end;
574 }
575
576 buf = (uint8_t *)req->ring;
577 dcode = (uint32_t *)req->ring;
578 pcihdr = 0;
579 last_image = 1;
580 do {
581
582 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
583 bcode = buf + (pcihdr % 4);
584 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa)
585 goto end;
586
587
588 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
589 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
590 bcode = buf + (pcihdr % 4);
591
592
593 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
594 bcode[0x2] != 'I' || bcode[0x3] != 'R')
595 goto end;
596
597 last_image = bcode[0x15] & BIT_7;
598
599
600 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
601 } while (!last_image);
602
603
604 fltl = (struct qla_flt_location *)req->ring;
605 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2,
606 sizeof(struct qla_flt_location) >> 2);
607 if (fltl->sig[0] != 'Q' || fltl->sig[1] != 'F' ||
608 fltl->sig[2] != 'L' || fltl->sig[3] != 'T')
609 goto end;
610
611 wptr = (uint16_t *)req->ring;
612 cnt = sizeof(struct qla_flt_location) >> 1;
613 for (chksum = 0; cnt; cnt--)
614 chksum += le16_to_cpu(*wptr++);
615 if (chksum) {
616 ql_log(ql_log_fatal, vha, 0x0045,
617 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum);
618 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e,
619 buf, sizeof(struct qla_flt_location));
620 return QLA_FUNCTION_FAILED;
621 }
622
623
624 loc = locations[1];
625 *start = (le16_to_cpu(fltl->start_hi) << 16 |
626 le16_to_cpu(fltl->start_lo)) >> 2;
627end:
628 ql_dbg(ql_dbg_init, vha, 0x0046,
629 "FLTL[%s] = 0x%x.\n",
630 loc, *start);
631 return QLA_SUCCESS;
632}
633
634static void
635qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr)
636{
637 const char *loc, *locations[] = { "DEF", "FLT" };
638 const uint32_t def_fw[] =
639 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 };
640 const uint32_t def_boot[] =
641 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 };
642 const uint32_t def_vpd_nvram[] =
643 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 };
644 const uint32_t def_vpd0[] =
645 { 0, 0, FA_VPD0_ADDR_81 };
646 const uint32_t def_vpd1[] =
647 { 0, 0, FA_VPD1_ADDR_81 };
648 const uint32_t def_nvram0[] =
649 { 0, 0, FA_NVRAM0_ADDR_81 };
650 const uint32_t def_nvram1[] =
651 { 0, 0, FA_NVRAM1_ADDR_81 };
652 const uint32_t def_fdt[] =
653 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR,
654 FA_FLASH_DESCR_ADDR_81 };
655 const uint32_t def_npiv_conf0[] =
656 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR,
657 FA_NPIV_CONF0_ADDR_81 };
658 const uint32_t def_npiv_conf1[] =
659 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR,
660 FA_NPIV_CONF1_ADDR_81 };
661 const uint32_t fcp_prio_cfg0[] =
662 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25,
663 0 };
664 const uint32_t fcp_prio_cfg1[] =
665 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25,
666 0 };
667 uint32_t def;
668 uint16_t *wptr;
669 uint16_t cnt, chksum;
670 uint32_t start;
671 struct qla_flt_header *flt;
672 struct qla_flt_region *region;
673 struct qla_hw_data *ha = vha->hw;
674 struct req_que *req = ha->req_q_map[0];
675
676 def = 0;
677 if (IS_QLA25XX(ha))
678 def = 1;
679 else if (IS_QLA81XX(ha))
680 def = 2;
681
682
683
684
685 ha->flt_region_fcp_prio = ha->flags.port0 ?
686 fcp_prio_cfg0[def] : fcp_prio_cfg1[def];
687
688 ha->flt_region_flt = flt_addr;
689 wptr = (uint16_t *)req->ring;
690 flt = (struct qla_flt_header *)req->ring;
691 region = (struct qla_flt_region *)&flt[1];
692 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
693 flt_addr << 2, OPTROM_BURST_SIZE);
694 if (*wptr == __constant_cpu_to_le16(0xffff))
695 goto no_flash_data;
696 if (flt->version != __constant_cpu_to_le16(1)) {
697 ql_log(ql_log_warn, vha, 0x0047,
698 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
699 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
700 le16_to_cpu(flt->checksum));
701 goto no_flash_data;
702 }
703
704 cnt = (sizeof(struct qla_flt_header) + le16_to_cpu(flt->length)) >> 1;
705 for (chksum = 0; cnt; cnt--)
706 chksum += le16_to_cpu(*wptr++);
707 if (chksum) {
708 ql_log(ql_log_fatal, vha, 0x0048,
709 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n",
710 le16_to_cpu(flt->version), le16_to_cpu(flt->length),
711 le16_to_cpu(flt->checksum));
712 goto no_flash_data;
713 }
714
715 loc = locations[1];
716 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region);
717 for ( ; cnt; cnt--, region++) {
718
719 start = le32_to_cpu(region->start) >> 2;
720 ql_dbg(ql_dbg_init, vha, 0x0049,
721 "FLT[%02x]: start=0x%x "
722 "end=0x%x size=0x%x.\n", le32_to_cpu(region->code),
723 start, le32_to_cpu(region->end) >> 2,
724 le32_to_cpu(region->size));
725
726 switch (le32_to_cpu(region->code) & 0xff) {
727 case FLT_REG_FCOE_FW:
728 if (!IS_QLA8031(ha))
729 break;
730 ha->flt_region_fw = start;
731 break;
732 case FLT_REG_FW:
733 if (IS_QLA8031(ha))
734 break;
735 ha->flt_region_fw = start;
736 break;
737 case FLT_REG_BOOT_CODE:
738 ha->flt_region_boot = start;
739 break;
740 case FLT_REG_VPD_0:
741 if (IS_QLA8031(ha))
742 break;
743 ha->flt_region_vpd_nvram = start;
744 if (IS_QLA82XX(ha))
745 break;
746 if (ha->flags.port0)
747 ha->flt_region_vpd = start;
748 break;
749 case FLT_REG_VPD_1:
750 if (IS_QLA82XX(ha) || IS_QLA8031(ha))
751 break;
752 if (!ha->flags.port0)
753 ha->flt_region_vpd = start;
754 break;
755 case FLT_REG_NVRAM_0:
756 if (IS_QLA8031(ha))
757 break;
758 if (ha->flags.port0)
759 ha->flt_region_nvram = start;
760 break;
761 case FLT_REG_NVRAM_1:
762 if (IS_QLA8031(ha))
763 break;
764 if (!ha->flags.port0)
765 ha->flt_region_nvram = start;
766 break;
767 case FLT_REG_FDT:
768 ha->flt_region_fdt = start;
769 break;
770 case FLT_REG_NPIV_CONF_0:
771 if (ha->flags.port0)
772 ha->flt_region_npiv_conf = start;
773 break;
774 case FLT_REG_NPIV_CONF_1:
775 if (!ha->flags.port0)
776 ha->flt_region_npiv_conf = start;
777 break;
778 case FLT_REG_GOLD_FW:
779 ha->flt_region_gold_fw = start;
780 break;
781 case FLT_REG_FCP_PRIO_0:
782 if (ha->flags.port0)
783 ha->flt_region_fcp_prio = start;
784 break;
785 case FLT_REG_FCP_PRIO_1:
786 if (!ha->flags.port0)
787 ha->flt_region_fcp_prio = start;
788 break;
789 case FLT_REG_BOOT_CODE_82XX:
790 ha->flt_region_boot = start;
791 break;
792 case FLT_REG_FW_82XX:
793 ha->flt_region_fw = start;
794 break;
795 case FLT_REG_GOLD_FW_82XX:
796 ha->flt_region_gold_fw = start;
797 break;
798 case FLT_REG_BOOTLOAD_82XX:
799 ha->flt_region_bootload = start;
800 break;
801 case FLT_REG_VPD_8XXX:
802 if (IS_CNA_CAPABLE(ha))
803 ha->flt_region_vpd = start;
804 break;
805 case FLT_REG_FCOE_NVRAM_0:
806 if (!IS_QLA8031(ha))
807 break;
808 if (ha->flags.port0)
809 ha->flt_region_nvram = start;
810 break;
811 case FLT_REG_FCOE_NVRAM_1:
812 if (!IS_QLA8031(ha))
813 break;
814 if (!ha->flags.port0)
815 ha->flt_region_nvram = start;
816 break;
817 }
818 }
819 goto done;
820
821no_flash_data:
822
823 loc = locations[0];
824 ha->flt_region_fw = def_fw[def];
825 ha->flt_region_boot = def_boot[def];
826 ha->flt_region_vpd_nvram = def_vpd_nvram[def];
827 ha->flt_region_vpd = ha->flags.port0 ?
828 def_vpd0[def] : def_vpd1[def];
829 ha->flt_region_nvram = ha->flags.port0 ?
830 def_nvram0[def] : def_nvram1[def];
831 ha->flt_region_fdt = def_fdt[def];
832 ha->flt_region_npiv_conf = ha->flags.port0 ?
833 def_npiv_conf0[def] : def_npiv_conf1[def];
834done:
835 ql_dbg(ql_dbg_init, vha, 0x004a,
836 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x "
837 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n",
838 loc, ha->flt_region_boot, ha->flt_region_fw,
839 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram,
840 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf,
841 ha->flt_region_fcp_prio);
842}
843
844static void
845qla2xxx_get_fdt_info(scsi_qla_host_t *vha)
846{
847#define FLASH_BLK_SIZE_4K 0x1000
848#define FLASH_BLK_SIZE_32K 0x8000
849#define FLASH_BLK_SIZE_64K 0x10000
850 const char *loc, *locations[] = { "MID", "FDT" };
851 uint16_t cnt, chksum;
852 uint16_t *wptr;
853 struct qla_fdt_layout *fdt;
854 uint8_t man_id, flash_id;
855 uint16_t mid = 0, fid = 0;
856 struct qla_hw_data *ha = vha->hw;
857 struct req_que *req = ha->req_q_map[0];
858
859 wptr = (uint16_t *)req->ring;
860 fdt = (struct qla_fdt_layout *)req->ring;
861 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
862 ha->flt_region_fdt << 2, OPTROM_BURST_SIZE);
863 if (*wptr == __constant_cpu_to_le16(0xffff))
864 goto no_flash_data;
865 if (fdt->sig[0] != 'Q' || fdt->sig[1] != 'L' || fdt->sig[2] != 'I' ||
866 fdt->sig[3] != 'D')
867 goto no_flash_data;
868
869 for (cnt = 0, chksum = 0; cnt < sizeof(struct qla_fdt_layout) >> 1;
870 cnt++)
871 chksum += le16_to_cpu(*wptr++);
872 if (chksum) {
873 ql_dbg(ql_dbg_init, vha, 0x004c,
874 "Inconsistent FDT detected:"
875 " checksum=0x%x id=%c version0x%x.\n", chksum,
876 fdt->sig[0], le16_to_cpu(fdt->version));
877 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113,
878 (uint8_t *)fdt, sizeof(*fdt));
879 goto no_flash_data;
880 }
881
882 loc = locations[1];
883 mid = le16_to_cpu(fdt->man_id);
884 fid = le16_to_cpu(fdt->id);
885 ha->fdt_wrt_disable = fdt->wrt_disable_bits;
886 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0300 | fdt->erase_cmd);
887 ha->fdt_block_size = le32_to_cpu(fdt->block_size);
888 if (fdt->unprotect_sec_cmd) {
889 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 |
890 fdt->unprotect_sec_cmd);
891 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ?
892 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd):
893 flash_conf_addr(ha, 0x0336);
894 }
895 goto done;
896no_flash_data:
897 loc = locations[0];
898 if (IS_QLA82XX(ha)) {
899 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
900 goto done;
901 }
902 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
903 mid = man_id;
904 fid = flash_id;
905 ha->fdt_wrt_disable = 0x9c;
906 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8);
907 switch (man_id) {
908 case 0xbf:
909 if (flash_id == 0x8e)
910 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
911 else
912 ha->fdt_block_size = FLASH_BLK_SIZE_32K;
913
914 if (flash_id == 0x80)
915 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352);
916 break;
917 case 0x13:
918 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
919 break;
920 case 0x1f:
921 ha->fdt_block_size = FLASH_BLK_SIZE_4K;
922 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320);
923 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339);
924 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336);
925 break;
926 default:
927
928 ha->fdt_block_size = FLASH_BLK_SIZE_64K;
929 break;
930 }
931done:
932 ql_dbg(ql_dbg_init, vha, 0x004d,
933 "FDT[%s]: (0x%x/0x%x) erase=0x%x "
934 "pr=%x wrtd=0x%x blk=0x%x.\n",
935 loc, mid, fid,
936 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd,
937 ha->fdt_wrt_disable, ha->fdt_block_size);
938
939}
940
941static void
942qla2xxx_get_idc_param(scsi_qla_host_t *vha)
943{
944#define QLA82XX_IDC_PARAM_ADDR 0x003e885c
945 uint32_t *wptr;
946 struct qla_hw_data *ha = vha->hw;
947 struct req_que *req = ha->req_q_map[0];
948
949 if (!IS_QLA82XX(ha))
950 return;
951
952 wptr = (uint32_t *)req->ring;
953 ha->isp_ops->read_optrom(vha, (uint8_t *)req->ring,
954 QLA82XX_IDC_PARAM_ADDR , 8);
955
956 if (*wptr == __constant_cpu_to_le32(0xffffffff)) {
957 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT;
958 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT;
959 } else {
960 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr++);
961 ha->fcoe_reset_timeout = le32_to_cpu(*wptr);
962 }
963 ql_dbg(ql_dbg_init, vha, 0x004e,
964 "fcoe_dev_init_timeout=%d "
965 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout,
966 ha->fcoe_reset_timeout);
967 return;
968}
969
970int
971qla2xxx_get_flash_info(scsi_qla_host_t *vha)
972{
973 int ret;
974 uint32_t flt_addr;
975 struct qla_hw_data *ha = vha->hw;
976
977 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
978 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
979 return QLA_SUCCESS;
980
981 ret = qla2xxx_find_flt_start(vha, &flt_addr);
982 if (ret != QLA_SUCCESS)
983 return ret;
984
985 qla2xxx_get_flt_info(vha, flt_addr);
986 qla2xxx_get_fdt_info(vha);
987 qla2xxx_get_idc_param(vha);
988
989 return QLA_SUCCESS;
990}
991
992void
993qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha)
994{
995#define NPIV_CONFIG_SIZE (16*1024)
996 void *data;
997 uint16_t *wptr;
998 uint16_t cnt, chksum;
999 int i;
1000 struct qla_npiv_header hdr;
1001 struct qla_npiv_entry *entry;
1002 struct qla_hw_data *ha = vha->hw;
1003
1004 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
1005 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha))
1006 return;
1007
1008 if (ha->flags.nic_core_reset_hdlr_active)
1009 return;
1010
1011 ha->isp_ops->read_optrom(vha, (uint8_t *)&hdr,
1012 ha->flt_region_npiv_conf << 2, sizeof(struct qla_npiv_header));
1013 if (hdr.version == __constant_cpu_to_le16(0xffff))
1014 return;
1015 if (hdr.version != __constant_cpu_to_le16(1)) {
1016 ql_dbg(ql_dbg_user, vha, 0x7090,
1017 "Unsupported NPIV-Config "
1018 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1019 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1020 le16_to_cpu(hdr.checksum));
1021 return;
1022 }
1023
1024 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL);
1025 if (!data) {
1026 ql_log(ql_log_warn, vha, 0x7091,
1027 "Unable to allocate memory for data.\n");
1028 return;
1029 }
1030
1031 ha->isp_ops->read_optrom(vha, (uint8_t *)data,
1032 ha->flt_region_npiv_conf << 2, NPIV_CONFIG_SIZE);
1033
1034 cnt = (sizeof(struct qla_npiv_header) + le16_to_cpu(hdr.entries) *
1035 sizeof(struct qla_npiv_entry)) >> 1;
1036 for (wptr = data, chksum = 0; cnt; cnt--)
1037 chksum += le16_to_cpu(*wptr++);
1038 if (chksum) {
1039 ql_dbg(ql_dbg_user, vha, 0x7092,
1040 "Inconsistent NPIV-Config "
1041 "detected: version=0x%x entries=0x%x checksum=0x%x.\n",
1042 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries),
1043 le16_to_cpu(hdr.checksum));
1044 goto done;
1045 }
1046
1047 entry = data + sizeof(struct qla_npiv_header);
1048 cnt = le16_to_cpu(hdr.entries);
1049 for (i = 0; cnt; cnt--, entry++, i++) {
1050 uint16_t flags;
1051 struct fc_vport_identifiers vid;
1052 struct fc_vport *vport;
1053
1054 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry));
1055
1056 flags = le16_to_cpu(entry->flags);
1057 if (flags == 0xffff)
1058 continue;
1059 if ((flags & BIT_0) == 0)
1060 continue;
1061
1062 memset(&vid, 0, sizeof(vid));
1063 vid.roles = FC_PORT_ROLE_FCP_INITIATOR;
1064 vid.vport_type = FC_PORTTYPE_NPIV;
1065 vid.disable = false;
1066 vid.port_name = wwn_to_u64(entry->port_name);
1067 vid.node_name = wwn_to_u64(entry->node_name);
1068
1069 ql_dbg(ql_dbg_user, vha, 0x7093,
1070 "NPIV[%02x]: wwpn=%llx "
1071 "wwnn=%llx vf_id=0x%x Q_qos=0x%x F_qos=0x%x.\n", cnt,
1072 (unsigned long long)vid.port_name,
1073 (unsigned long long)vid.node_name,
1074 le16_to_cpu(entry->vf_id),
1075 entry->q_qos, entry->f_qos);
1076
1077 if (i < QLA_PRECONFIG_VPORTS) {
1078 vport = fc_vport_create(vha->host, 0, &vid);
1079 if (!vport)
1080 ql_log(ql_log_warn, vha, 0x7094,
1081 "NPIV-Config Failed to create vport [%02x]: "
1082 "wwpn=%llx wwnn=%llx.\n", cnt,
1083 (unsigned long long)vid.port_name,
1084 (unsigned long long)vid.node_name);
1085 }
1086 }
1087done:
1088 kfree(data);
1089}
1090
1091static int
1092qla24xx_unprotect_flash(scsi_qla_host_t *vha)
1093{
1094 struct qla_hw_data *ha = vha->hw;
1095 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1096
1097 if (ha->flags.fac_supported)
1098 return qla81xx_fac_do_write_enable(vha, 1);
1099
1100
1101 WRT_REG_DWORD(®->ctrl_status,
1102 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
1103 RD_REG_DWORD(®->ctrl_status);
1104
1105 if (!ha->fdt_wrt_disable)
1106 goto done;
1107
1108
1109 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1110
1111 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0);
1112done:
1113 return QLA_SUCCESS;
1114}
1115
1116static int
1117qla24xx_protect_flash(scsi_qla_host_t *vha)
1118{
1119 uint32_t cnt;
1120 struct qla_hw_data *ha = vha->hw;
1121 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1122
1123 if (ha->flags.fac_supported)
1124 return qla81xx_fac_do_write_enable(vha, 0);
1125
1126 if (!ha->fdt_wrt_disable)
1127 goto skip_wrt_protect;
1128
1129
1130 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101),
1131 ha->fdt_wrt_disable);
1132 for (cnt = 300; cnt &&
1133 qla24xx_read_flash_dword(ha, flash_conf_addr(ha, 0x005)) & BIT_0;
1134 cnt--) {
1135 udelay(10);
1136 }
1137
1138skip_wrt_protect:
1139
1140 WRT_REG_DWORD(®->ctrl_status,
1141 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
1142 RD_REG_DWORD(®->ctrl_status);
1143
1144 return QLA_SUCCESS;
1145}
1146
1147static int
1148qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata)
1149{
1150 struct qla_hw_data *ha = vha->hw;
1151 uint32_t start, finish;
1152
1153 if (ha->flags.fac_supported) {
1154 start = fdata >> 2;
1155 finish = start + (ha->fdt_block_size >> 2) - 1;
1156 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha,
1157 start), flash_data_addr(ha, finish));
1158 }
1159
1160 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd,
1161 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) |
1162 ((fdata >> 16) & 0xff));
1163}
1164
1165static int
1166qla24xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
1167 uint32_t dwords)
1168{
1169 int ret;
1170 uint32_t liter;
1171 uint32_t sec_mask, rest_addr;
1172 uint32_t fdata;
1173 dma_addr_t optrom_dma;
1174 void *optrom = NULL;
1175 struct qla_hw_data *ha = vha->hw;
1176
1177
1178 if ((IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha)) &&
1179 !(faddr & 0xfff) && dwords > OPTROM_BURST_DWORDS) {
1180 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1181 &optrom_dma, GFP_KERNEL);
1182 if (!optrom) {
1183 ql_log(ql_log_warn, vha, 0x7095,
1184 "Unable to allocate "
1185 "memory for optrom burst write (%x KB).\n",
1186 OPTROM_BURST_SIZE / 1024);
1187 }
1188 }
1189
1190 rest_addr = (ha->fdt_block_size >> 2) - 1;
1191 sec_mask = ~rest_addr;
1192
1193 ret = qla24xx_unprotect_flash(vha);
1194 if (ret != QLA_SUCCESS) {
1195 ql_log(ql_log_warn, vha, 0x7096,
1196 "Unable to unprotect flash for update.\n");
1197 goto done;
1198 }
1199
1200 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
1201 fdata = (faddr & sec_mask) << 2;
1202
1203
1204 if ((faddr & rest_addr) == 0) {
1205
1206 if (ha->fdt_unprotect_sec_cmd)
1207 qla24xx_write_flash_dword(ha,
1208 ha->fdt_unprotect_sec_cmd,
1209 (fdata & 0xff00) | ((fdata << 16) &
1210 0xff0000) | ((fdata >> 16) & 0xff));
1211 ret = qla24xx_erase_sector(vha, fdata);
1212 if (ret != QLA_SUCCESS) {
1213 ql_dbg(ql_dbg_user, vha, 0x7007,
1214 "Unable to erase erase sector: address=%x.\n",
1215 faddr);
1216 break;
1217 }
1218 }
1219
1220
1221 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
1222
1223 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
1224
1225 ret = qla2x00_load_ram(vha, optrom_dma,
1226 flash_data_addr(ha, faddr),
1227 OPTROM_BURST_DWORDS);
1228 if (ret != QLA_SUCCESS) {
1229 ql_log(ql_log_warn, vha, 0x7097,
1230 "Unable to burst-write optrom segment "
1231 "(%x/%x/%llx).\n", ret,
1232 flash_data_addr(ha, faddr),
1233 (unsigned long long)optrom_dma);
1234 ql_log(ql_log_warn, vha, 0x7098,
1235 "Reverting to slow-write.\n");
1236
1237 dma_free_coherent(&ha->pdev->dev,
1238 OPTROM_BURST_SIZE, optrom, optrom_dma);
1239 optrom = NULL;
1240 } else {
1241 liter += OPTROM_BURST_DWORDS - 1;
1242 faddr += OPTROM_BURST_DWORDS - 1;
1243 dwptr += OPTROM_BURST_DWORDS - 1;
1244 continue;
1245 }
1246 }
1247
1248 ret = qla24xx_write_flash_dword(ha,
1249 flash_data_addr(ha, faddr), cpu_to_le32(*dwptr));
1250 if (ret != QLA_SUCCESS) {
1251 ql_dbg(ql_dbg_user, vha, 0x7006,
1252 "Unable to program flash address=%x data=%x.\n",
1253 faddr, *dwptr);
1254 break;
1255 }
1256
1257
1258 if (ha->fdt_unprotect_sec_cmd &&
1259 ((faddr & rest_addr) == rest_addr))
1260 qla24xx_write_flash_dword(ha,
1261 ha->fdt_protect_sec_cmd,
1262 (fdata & 0xff00) | ((fdata << 16) &
1263 0xff0000) | ((fdata >> 16) & 0xff));
1264 }
1265
1266 ret = qla24xx_protect_flash(vha);
1267 if (ret != QLA_SUCCESS)
1268 ql_log(ql_log_warn, vha, 0x7099,
1269 "Unable to protect flash after update.\n");
1270done:
1271 if (optrom)
1272 dma_free_coherent(&ha->pdev->dev,
1273 OPTROM_BURST_SIZE, optrom, optrom_dma);
1274
1275 return ret;
1276}
1277
1278uint8_t *
1279qla2x00_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1280 uint32_t bytes)
1281{
1282 uint32_t i;
1283 uint16_t *wptr;
1284 struct qla_hw_data *ha = vha->hw;
1285
1286
1287 wptr = (uint16_t *)buf;
1288 qla2x00_lock_nvram_access(ha);
1289 for (i = 0; i < bytes >> 1; i++, naddr++)
1290 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
1291 naddr));
1292 qla2x00_unlock_nvram_access(ha);
1293
1294 return buf;
1295}
1296
1297uint8_t *
1298qla24xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1299 uint32_t bytes)
1300{
1301 uint32_t i;
1302 uint32_t *dwptr;
1303 struct qla_hw_data *ha = vha->hw;
1304
1305 if (IS_QLA82XX(ha))
1306 return buf;
1307
1308
1309 dwptr = (uint32_t *)buf;
1310 for (i = 0; i < bytes >> 2; i++, naddr++)
1311 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1312 nvram_data_addr(ha, naddr)));
1313
1314 return buf;
1315}
1316
1317int
1318qla2x00_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1319 uint32_t bytes)
1320{
1321 int ret, stat;
1322 uint32_t i;
1323 uint16_t *wptr;
1324 unsigned long flags;
1325 struct qla_hw_data *ha = vha->hw;
1326
1327 ret = QLA_SUCCESS;
1328
1329 spin_lock_irqsave(&ha->hardware_lock, flags);
1330 qla2x00_lock_nvram_access(ha);
1331
1332
1333 stat = qla2x00_clear_nvram_protection(ha);
1334
1335 wptr = (uint16_t *)buf;
1336 for (i = 0; i < bytes >> 1; i++, naddr++) {
1337 qla2x00_write_nvram_word(ha, naddr,
1338 cpu_to_le16(*wptr));
1339 wptr++;
1340 }
1341
1342
1343 qla2x00_set_nvram_protection(ha, stat);
1344
1345 qla2x00_unlock_nvram_access(ha);
1346 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1347
1348 return ret;
1349}
1350
1351int
1352qla24xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1353 uint32_t bytes)
1354{
1355 int ret;
1356 uint32_t i;
1357 uint32_t *dwptr;
1358 struct qla_hw_data *ha = vha->hw;
1359 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1360
1361 ret = QLA_SUCCESS;
1362
1363 if (IS_QLA82XX(ha))
1364 return ret;
1365
1366
1367 WRT_REG_DWORD(®->ctrl_status,
1368 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
1369 RD_REG_DWORD(®->ctrl_status);
1370
1371
1372 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1373 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0);
1374
1375
1376 dwptr = (uint32_t *)buf;
1377 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
1378 ret = qla24xx_write_flash_dword(ha,
1379 nvram_data_addr(ha, naddr), cpu_to_le32(*dwptr));
1380 if (ret != QLA_SUCCESS) {
1381 ql_dbg(ql_dbg_user, vha, 0x709a,
1382 "Unable to program nvram address=%x data=%x.\n",
1383 naddr, *dwptr);
1384 break;
1385 }
1386 }
1387
1388
1389 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c);
1390
1391
1392 WRT_REG_DWORD(®->ctrl_status,
1393 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
1394 RD_REG_DWORD(®->ctrl_status);
1395
1396 return ret;
1397}
1398
1399uint8_t *
1400qla25xx_read_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1401 uint32_t bytes)
1402{
1403 uint32_t i;
1404 uint32_t *dwptr;
1405 struct qla_hw_data *ha = vha->hw;
1406
1407
1408 dwptr = (uint32_t *)buf;
1409 for (i = 0; i < bytes >> 2; i++, naddr++)
1410 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
1411 flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr)));
1412
1413 return buf;
1414}
1415
1416int
1417qla25xx_write_nvram_data(scsi_qla_host_t *vha, uint8_t *buf, uint32_t naddr,
1418 uint32_t bytes)
1419{
1420 struct qla_hw_data *ha = vha->hw;
1421#define RMW_BUFFER_SIZE (64 * 1024)
1422 uint8_t *dbuf;
1423
1424 dbuf = vmalloc(RMW_BUFFER_SIZE);
1425 if (!dbuf)
1426 return QLA_MEMORY_ALLOC_FAILED;
1427 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1428 RMW_BUFFER_SIZE);
1429 memcpy(dbuf + (naddr << 2), buf, bytes);
1430 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2,
1431 RMW_BUFFER_SIZE);
1432 vfree(dbuf);
1433
1434 return QLA_SUCCESS;
1435}
1436
1437static inline void
1438qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1439{
1440 if (IS_QLA2322(ha)) {
1441
1442 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1443
1444 ha->beacon_color_state = 0;
1445 *pflags = GPIO_LED_ALL_OFF;
1446 } else {
1447
1448 ha->beacon_color_state = QLA_LED_ALL_ON;
1449 *pflags = GPIO_LED_RGA_ON;
1450 }
1451 } else {
1452
1453 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
1454
1455 ha->beacon_color_state = 0;
1456 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
1457 } else {
1458
1459 ha->beacon_color_state = QLA_LED_GRN_ON;
1460 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
1461 }
1462 }
1463}
1464
1465#define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
1466
1467void
1468qla2x00_beacon_blink(struct scsi_qla_host *vha)
1469{
1470 uint16_t gpio_enable;
1471 uint16_t gpio_data;
1472 uint16_t led_color = 0;
1473 unsigned long flags;
1474 struct qla_hw_data *ha = vha->hw;
1475 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1476
1477 if (IS_QLA82XX(ha))
1478 return;
1479
1480 spin_lock_irqsave(&ha->hardware_lock, flags);
1481
1482
1483 if (ha->pio_address) {
1484 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1485 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1486 } else {
1487 gpio_enable = RD_REG_WORD(®->gpioe);
1488 gpio_data = RD_REG_WORD(®->gpiod);
1489 }
1490
1491
1492 gpio_enable |= GPIO_LED_MASK;
1493
1494 if (ha->pio_address) {
1495 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1496 } else {
1497 WRT_REG_WORD(®->gpioe, gpio_enable);
1498 RD_REG_WORD(®->gpioe);
1499 }
1500
1501 qla2x00_flip_colors(ha, &led_color);
1502
1503
1504 gpio_data &= ~GPIO_LED_MASK;
1505
1506
1507 gpio_data |= led_color;
1508
1509
1510 if (ha->pio_address) {
1511 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1512 } else {
1513 WRT_REG_WORD(®->gpiod, gpio_data);
1514 RD_REG_WORD(®->gpiod);
1515 }
1516
1517 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1518}
1519
1520int
1521qla2x00_beacon_on(struct scsi_qla_host *vha)
1522{
1523 uint16_t gpio_enable;
1524 uint16_t gpio_data;
1525 unsigned long flags;
1526 struct qla_hw_data *ha = vha->hw;
1527 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1528
1529 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1530 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
1531
1532 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1533 ql_log(ql_log_warn, vha, 0x709b,
1534 "Unable to update fw options (beacon on).\n");
1535 return QLA_FUNCTION_FAILED;
1536 }
1537
1538
1539 spin_lock_irqsave(&ha->hardware_lock, flags);
1540 if (ha->pio_address) {
1541 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
1542 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
1543 } else {
1544 gpio_enable = RD_REG_WORD(®->gpioe);
1545 gpio_data = RD_REG_WORD(®->gpiod);
1546 }
1547 gpio_enable |= GPIO_LED_MASK;
1548
1549
1550 if (ha->pio_address) {
1551 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
1552 } else {
1553 WRT_REG_WORD(®->gpioe, gpio_enable);
1554 RD_REG_WORD(®->gpioe);
1555 }
1556
1557
1558 gpio_data &= ~GPIO_LED_MASK;
1559 if (ha->pio_address) {
1560 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1561 } else {
1562 WRT_REG_WORD(®->gpiod, gpio_data);
1563 RD_REG_WORD(®->gpiod);
1564 }
1565 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1566
1567
1568
1569
1570
1571 ha->beacon_blink_led = 1;
1572 ha->beacon_color_state = 0;
1573
1574 return QLA_SUCCESS;
1575}
1576
1577int
1578qla2x00_beacon_off(struct scsi_qla_host *vha)
1579{
1580 int rval = QLA_SUCCESS;
1581 struct qla_hw_data *ha = vha->hw;
1582
1583 ha->beacon_blink_led = 0;
1584
1585
1586 if (IS_QLA2322(ha))
1587 ha->beacon_color_state = QLA_LED_ALL_ON;
1588 else
1589 ha->beacon_color_state = QLA_LED_GRN_ON;
1590
1591 ha->isp_ops->beacon_blink(vha);
1592
1593 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1594 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1595
1596 rval = qla2x00_set_fw_options(vha, ha->fw_options);
1597 if (rval != QLA_SUCCESS)
1598 ql_log(ql_log_warn, vha, 0x709c,
1599 "Unable to update fw options (beacon off).\n");
1600 return rval;
1601}
1602
1603
1604static inline void
1605qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags)
1606{
1607
1608 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1609
1610 ha->beacon_color_state = 0;
1611 *pflags = 0;
1612 } else {
1613
1614 ha->beacon_color_state = QLA_LED_ALL_ON;
1615 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1616 }
1617}
1618
1619void
1620qla24xx_beacon_blink(struct scsi_qla_host *vha)
1621{
1622 uint16_t led_color = 0;
1623 uint32_t gpio_data;
1624 unsigned long flags;
1625 struct qla_hw_data *ha = vha->hw;
1626 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1627
1628
1629 spin_lock_irqsave(&ha->hardware_lock, flags);
1630 gpio_data = RD_REG_DWORD(®->gpiod);
1631
1632
1633 gpio_data |= GPDX_LED_UPDATE_MASK;
1634
1635 WRT_REG_DWORD(®->gpiod, gpio_data);
1636 gpio_data = RD_REG_DWORD(®->gpiod);
1637
1638
1639 qla24xx_flip_colors(ha, &led_color);
1640
1641
1642 gpio_data &= ~GPDX_LED_COLOR_MASK;
1643
1644
1645 gpio_data |= led_color;
1646
1647
1648 WRT_REG_DWORD(®->gpiod, gpio_data);
1649 gpio_data = RD_REG_DWORD(®->gpiod);
1650 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1651}
1652
1653static uint32_t
1654qla83xx_select_led_port(struct qla_hw_data *ha)
1655{
1656 uint32_t led_select_value = 0;
1657
1658 if (!IS_QLA83XX(ha))
1659 goto out;
1660
1661 if (ha->flags.port0)
1662 led_select_value = QLA83XX_LED_PORT0;
1663 else
1664 led_select_value = QLA83XX_LED_PORT1;
1665
1666out:
1667 return led_select_value;
1668}
1669
1670void
1671qla83xx_beacon_blink(struct scsi_qla_host *vha)
1672{
1673 uint32_t led_select_value;
1674 struct qla_hw_data *ha = vha->hw;
1675 uint16_t led_cfg[6];
1676 uint16_t orig_led_cfg[6];
1677 uint32_t led_10_value, led_43_value;
1678
1679 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha))
1680 return;
1681
1682 if (!ha->beacon_blink_led)
1683 return;
1684
1685 if (IS_QLA2031(ha)) {
1686 led_select_value = qla83xx_select_led_port(ha);
1687
1688 qla83xx_wr_reg(vha, led_select_value, 0x40002000);
1689 qla83xx_wr_reg(vha, led_select_value + 4, 0x40002000);
1690 msleep(1000);
1691 qla83xx_wr_reg(vha, led_select_value, 0x40004000);
1692 qla83xx_wr_reg(vha, led_select_value + 4, 0x40004000);
1693 } else if (IS_QLA8031(ha)) {
1694 led_select_value = qla83xx_select_led_port(ha);
1695
1696 qla83xx_rd_reg(vha, led_select_value, &led_10_value);
1697 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value);
1698 qla83xx_wr_reg(vha, led_select_value, 0x01f44000);
1699 msleep(500);
1700 qla83xx_wr_reg(vha, led_select_value, 0x400001f4);
1701 msleep(1000);
1702 qla83xx_wr_reg(vha, led_select_value, led_10_value);
1703 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value);
1704 } else if (IS_QLA81XX(ha)) {
1705 int rval;
1706
1707
1708 rval = qla81xx_get_led_config(vha, orig_led_cfg);
1709
1710 if (rval == QLA_SUCCESS) {
1711 if (IS_QLA81XX(ha)) {
1712 led_cfg[0] = 0x4000;
1713 led_cfg[1] = 0x2000;
1714 led_cfg[2] = 0;
1715 led_cfg[3] = 0;
1716 led_cfg[4] = 0;
1717 led_cfg[5] = 0;
1718 } else {
1719 led_cfg[0] = 0x4000;
1720 led_cfg[1] = 0x4000;
1721 led_cfg[2] = 0x4000;
1722 led_cfg[3] = 0x2000;
1723 led_cfg[4] = 0;
1724 led_cfg[5] = 0x2000;
1725 }
1726 rval = qla81xx_set_led_config(vha, led_cfg);
1727 msleep(1000);
1728 if (IS_QLA81XX(ha)) {
1729 led_cfg[0] = 0x4000;
1730 led_cfg[1] = 0x2000;
1731 led_cfg[2] = 0;
1732 } else {
1733 led_cfg[0] = 0x4000;
1734 led_cfg[1] = 0x2000;
1735 led_cfg[2] = 0x4000;
1736 led_cfg[3] = 0x4000;
1737 led_cfg[4] = 0;
1738 led_cfg[5] = 0x2000;
1739 }
1740 rval = qla81xx_set_led_config(vha, led_cfg);
1741 }
1742
1743 qla81xx_set_led_config(vha, orig_led_cfg);
1744 }
1745}
1746
1747int
1748qla24xx_beacon_on(struct scsi_qla_host *vha)
1749{
1750 uint32_t gpio_data;
1751 unsigned long flags;
1752 struct qla_hw_data *ha = vha->hw;
1753 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1754
1755 if (IS_QLA82XX(ha))
1756 return QLA_SUCCESS;
1757
1758 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1759 goto skip_gpio;
1760
1761 if (ha->beacon_blink_led == 0) {
1762
1763 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1764
1765 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS)
1766 return QLA_FUNCTION_FAILED;
1767
1768 if (qla2x00_get_fw_options(vha, ha->fw_options) !=
1769 QLA_SUCCESS) {
1770 ql_log(ql_log_warn, vha, 0x7009,
1771 "Unable to update fw options (beacon on).\n");
1772 return QLA_FUNCTION_FAILED;
1773 }
1774
1775 if (IS_QLA2031(ha))
1776 goto skip_gpio;
1777
1778 spin_lock_irqsave(&ha->hardware_lock, flags);
1779 gpio_data = RD_REG_DWORD(®->gpiod);
1780
1781
1782 gpio_data |= GPDX_LED_UPDATE_MASK;
1783 WRT_REG_DWORD(®->gpiod, gpio_data);
1784 RD_REG_DWORD(®->gpiod);
1785
1786 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1787 }
1788
1789
1790 ha->beacon_color_state = 0;
1791
1792skip_gpio:
1793
1794 ha->beacon_blink_led = 1;
1795
1796 return QLA_SUCCESS;
1797}
1798
1799int
1800qla24xx_beacon_off(struct scsi_qla_host *vha)
1801{
1802 uint32_t gpio_data;
1803 unsigned long flags;
1804 struct qla_hw_data *ha = vha->hw;
1805 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1806
1807 if (IS_QLA82XX(ha))
1808 return QLA_SUCCESS;
1809
1810 ha->beacon_blink_led = 0;
1811
1812 if (IS_QLA2031(ha))
1813 goto set_fw_options;
1814
1815 if (IS_QLA8031(ha) || IS_QLA81XX(ha))
1816 return QLA_SUCCESS;
1817
1818 ha->beacon_color_state = QLA_LED_ALL_ON;
1819
1820 ha->isp_ops->beacon_blink(vha);
1821
1822
1823 spin_lock_irqsave(&ha->hardware_lock, flags);
1824 gpio_data = RD_REG_DWORD(®->gpiod);
1825
1826
1827 gpio_data &= ~GPDX_LED_UPDATE_MASK;
1828 WRT_REG_DWORD(®->gpiod, gpio_data);
1829 RD_REG_DWORD(®->gpiod);
1830 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1831
1832set_fw_options:
1833 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1834
1835 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1836 ql_log(ql_log_warn, vha, 0x704d,
1837 "Unable to update fw options (beacon on).\n");
1838 return QLA_FUNCTION_FAILED;
1839 }
1840
1841 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) {
1842 ql_log(ql_log_warn, vha, 0x704e,
1843 "Unable to update fw options (beacon on).\n");
1844 return QLA_FUNCTION_FAILED;
1845 }
1846
1847 return QLA_SUCCESS;
1848}
1849
1850
1851
1852
1853
1854
1855
1856
1857
1858
1859static void
1860qla2x00_flash_enable(struct qla_hw_data *ha)
1861{
1862 uint16_t data;
1863 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1864
1865 data = RD_REG_WORD(®->ctrl_status);
1866 data |= CSR_FLASH_ENABLE;
1867 WRT_REG_WORD(®->ctrl_status, data);
1868 RD_REG_WORD(®->ctrl_status);
1869}
1870
1871
1872
1873
1874
1875static void
1876qla2x00_flash_disable(struct qla_hw_data *ha)
1877{
1878 uint16_t data;
1879 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1880
1881 data = RD_REG_WORD(®->ctrl_status);
1882 data &= ~(CSR_FLASH_ENABLE);
1883 WRT_REG_WORD(®->ctrl_status, data);
1884 RD_REG_WORD(®->ctrl_status);
1885}
1886
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896static uint8_t
1897qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr)
1898{
1899 uint16_t data;
1900 uint16_t bank_select;
1901 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1902
1903 bank_select = RD_REG_WORD(®->ctrl_status);
1904
1905 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1906
1907
1908 bank_select &= ~0xf8;
1909 bank_select |= addr >> 12 & 0xf0;
1910 bank_select |= CSR_FLASH_64K_BANK;
1911 WRT_REG_WORD(®->ctrl_status, bank_select);
1912 RD_REG_WORD(®->ctrl_status);
1913
1914 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1915 data = RD_REG_WORD(®->flash_data);
1916
1917 return (uint8_t)data;
1918 }
1919
1920
1921 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1922 bank_select |= CSR_FLASH_64K_BANK;
1923 WRT_REG_WORD(®->ctrl_status, bank_select);
1924 RD_REG_WORD(®->ctrl_status);
1925 } else if (((addr & BIT_16) == 0) &&
1926 (bank_select & CSR_FLASH_64K_BANK)) {
1927 bank_select &= ~(CSR_FLASH_64K_BANK);
1928 WRT_REG_WORD(®->ctrl_status, bank_select);
1929 RD_REG_WORD(®->ctrl_status);
1930 }
1931
1932
1933 if (ha->pio_address) {
1934 uint16_t data2;
1935
1936 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1937 do {
1938 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1939 barrier();
1940 cpu_relax();
1941 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1942 } while (data != data2);
1943 } else {
1944 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1945 data = qla2x00_debounce_register(®->flash_data);
1946 }
1947
1948 return (uint8_t)data;
1949}
1950
1951
1952
1953
1954
1955
1956
1957static void
1958qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data)
1959{
1960 uint16_t bank_select;
1961 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1962
1963 bank_select = RD_REG_WORD(®->ctrl_status);
1964 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1965
1966
1967 bank_select &= ~0xf8;
1968 bank_select |= addr >> 12 & 0xf0;
1969 bank_select |= CSR_FLASH_64K_BANK;
1970 WRT_REG_WORD(®->ctrl_status, bank_select);
1971 RD_REG_WORD(®->ctrl_status);
1972
1973 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1974 RD_REG_WORD(®->ctrl_status);
1975 WRT_REG_WORD(®->flash_data, (uint16_t)data);
1976 RD_REG_WORD(®->ctrl_status);
1977
1978 return;
1979 }
1980
1981
1982 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1983 bank_select |= CSR_FLASH_64K_BANK;
1984 WRT_REG_WORD(®->ctrl_status, bank_select);
1985 RD_REG_WORD(®->ctrl_status);
1986 } else if (((addr & BIT_16) == 0) &&
1987 (bank_select & CSR_FLASH_64K_BANK)) {
1988 bank_select &= ~(CSR_FLASH_64K_BANK);
1989 WRT_REG_WORD(®->ctrl_status, bank_select);
1990 RD_REG_WORD(®->ctrl_status);
1991 }
1992
1993
1994 if (ha->pio_address) {
1995 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1996 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1997 } else {
1998 WRT_REG_WORD(®->flash_address, (uint16_t)addr);
1999 RD_REG_WORD(®->ctrl_status);
2000 WRT_REG_WORD(®->flash_data, (uint16_t)data);
2001 RD_REG_WORD(®->ctrl_status);
2002 }
2003}
2004
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014
2015
2016
2017
2018
2019
2020static int
2021qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data,
2022 uint8_t man_id, uint8_t flash_id)
2023{
2024 int status;
2025 uint8_t flash_data;
2026 uint32_t cnt;
2027
2028 status = 1;
2029
2030
2031 poll_data &= BIT_7;
2032 for (cnt = 3000000; cnt; cnt--) {
2033 flash_data = qla2x00_read_flash_byte(ha, addr);
2034 if ((flash_data & BIT_7) == poll_data) {
2035 status = 0;
2036 break;
2037 }
2038
2039 if (man_id != 0x40 && man_id != 0xda) {
2040 if ((flash_data & BIT_5) && cnt > 2)
2041 cnt = 2;
2042 }
2043 udelay(10);
2044 barrier();
2045 cond_resched();
2046 }
2047 return status;
2048}
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058
2059
2060static int
2061qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr,
2062 uint8_t data, uint8_t man_id, uint8_t flash_id)
2063{
2064
2065 if (IS_OEM_001(ha)) {
2066 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2067 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2068 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
2069 qla2x00_write_flash_byte(ha, addr, data);
2070 } else {
2071 if (man_id == 0xda && flash_id == 0xc1) {
2072 qla2x00_write_flash_byte(ha, addr, data);
2073 if (addr & 0x7e)
2074 return 0;
2075 } else {
2076 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2077 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2078 qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
2079 qla2x00_write_flash_byte(ha, addr, data);
2080 }
2081 }
2082
2083 udelay(150);
2084
2085
2086 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
2087}
2088
2089
2090
2091
2092
2093
2094
2095
2096
2097static int
2098qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id)
2099{
2100
2101 if (IS_OEM_001(ha)) {
2102 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2103 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2104 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
2105 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
2106 qla2x00_write_flash_byte(ha, 0x555, 0x55);
2107 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
2108 } else {
2109 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2110 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2111 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2112 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2113 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2114 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
2115 }
2116
2117 udelay(150);
2118
2119
2120 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
2121}
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133static int
2134qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr,
2135 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
2136{
2137
2138 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2139 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2140 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
2141 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2142 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2143 if (man_id == 0x1f && flash_id == 0x13)
2144 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
2145 else
2146 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
2147
2148 udelay(150);
2149
2150
2151 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
2152}
2153
2154
2155
2156
2157
2158
2159static void
2160qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id,
2161 uint8_t *flash_id)
2162{
2163 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2164 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2165 qla2x00_write_flash_byte(ha, 0x5555, 0x90);
2166 *man_id = qla2x00_read_flash_byte(ha, 0x0000);
2167 *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
2168 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
2169 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
2170 qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
2171}
2172
2173static void
2174qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf,
2175 uint32_t saddr, uint32_t length)
2176{
2177 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2178 uint32_t midpoint, ilength;
2179 uint8_t data;
2180
2181 midpoint = length / 2;
2182
2183 WRT_REG_WORD(®->nvram, 0);
2184 RD_REG_WORD(®->nvram);
2185 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
2186 if (ilength == midpoint) {
2187 WRT_REG_WORD(®->nvram, NVR_SELECT);
2188 RD_REG_WORD(®->nvram);
2189 }
2190 data = qla2x00_read_flash_byte(ha, saddr);
2191 if (saddr % 100)
2192 udelay(10);
2193 *tmp_buf = data;
2194 cond_resched();
2195 }
2196}
2197
2198static inline void
2199qla2x00_suspend_hba(struct scsi_qla_host *vha)
2200{
2201 int cnt;
2202 unsigned long flags;
2203 struct qla_hw_data *ha = vha->hw;
2204 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2205
2206
2207 scsi_block_requests(vha->host);
2208 ha->isp_ops->disable_intrs(ha);
2209 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2210
2211
2212 spin_lock_irqsave(&ha->hardware_lock, flags);
2213 WRT_REG_WORD(®->hccr, HCCR_PAUSE_RISC);
2214 RD_REG_WORD(®->hccr);
2215 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2216 for (cnt = 0; cnt < 30000; cnt++) {
2217 if ((RD_REG_WORD(®->hccr) & HCCR_RISC_PAUSE) != 0)
2218 break;
2219 udelay(100);
2220 }
2221 } else {
2222 udelay(10);
2223 }
2224 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2225}
2226
2227static inline void
2228qla2x00_resume_hba(struct scsi_qla_host *vha)
2229{
2230 struct qla_hw_data *ha = vha->hw;
2231
2232
2233 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2234 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2235 qla2xxx_wake_dpc(vha);
2236 qla2x00_wait_for_chip_reset(vha);
2237 scsi_unblock_requests(vha->host);
2238}
2239
2240uint8_t *
2241qla2x00_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2242 uint32_t offset, uint32_t length)
2243{
2244 uint32_t addr, midpoint;
2245 uint8_t *data;
2246 struct qla_hw_data *ha = vha->hw;
2247 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2248
2249
2250 qla2x00_suspend_hba(vha);
2251
2252
2253 midpoint = ha->optrom_size / 2;
2254
2255 qla2x00_flash_enable(ha);
2256 WRT_REG_WORD(®->nvram, 0);
2257 RD_REG_WORD(®->nvram);
2258 for (addr = offset, data = buf; addr < length; addr++, data++) {
2259 if (addr == midpoint) {
2260 WRT_REG_WORD(®->nvram, NVR_SELECT);
2261 RD_REG_WORD(®->nvram);
2262 }
2263
2264 *data = qla2x00_read_flash_byte(ha, addr);
2265 }
2266 qla2x00_flash_disable(ha);
2267
2268
2269 qla2x00_resume_hba(vha);
2270
2271 return buf;
2272}
2273
2274int
2275qla2x00_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2276 uint32_t offset, uint32_t length)
2277{
2278
2279 int rval;
2280 uint8_t man_id, flash_id, sec_number, data;
2281 uint16_t wd;
2282 uint32_t addr, liter, sec_mask, rest_addr;
2283 struct qla_hw_data *ha = vha->hw;
2284 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2285
2286
2287 qla2x00_suspend_hba(vha);
2288
2289 rval = QLA_SUCCESS;
2290 sec_number = 0;
2291
2292
2293 WRT_REG_WORD(®->ctrl_status, CSR_ISP_SOFT_RESET);
2294 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2295
2296
2297 qla2x00_flash_enable(ha);
2298 do {
2299
2300 if (IS_OEM_001(ha)) {
2301
2302 man_id = flash_id = 0;
2303 rest_addr = 0xffff;
2304 sec_mask = 0x10000;
2305 goto update_flash;
2306 }
2307 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
2308 switch (man_id) {
2309 case 0x20:
2310 if (flash_id == 0xd2 || flash_id == 0xe3) {
2311
2312
2313
2314
2315
2316 rest_addr = 0xffff;
2317 sec_mask = 0x10000;
2318 break;
2319 }
2320
2321
2322
2323
2324 rest_addr = 0x3fff;
2325 sec_mask = 0x1c000;
2326 break;
2327 case 0x40:
2328
2329 rest_addr = 0x1ff;
2330 sec_mask = 0x1fe00;
2331 break;
2332 case 0xbf:
2333
2334 rest_addr = 0xfff;
2335 sec_mask = 0x1f000;
2336 break;
2337 case 0xda:
2338
2339 rest_addr = 0x7f;
2340 sec_mask = 0x1ff80;
2341 break;
2342 case 0xc2:
2343
2344 if (flash_id == 0x38 || flash_id == 0x4f) {
2345 rest_addr = 0xffff;
2346 sec_mask = 0x10000;
2347 break;
2348 }
2349
2350
2351 case 0x1f:
2352
2353 if (flash_id == 0x13) {
2354 rest_addr = 0x7fffffff;
2355 sec_mask = 0x80000000;
2356 break;
2357 }
2358
2359
2360 case 0x01:
2361 if (flash_id == 0x38 || flash_id == 0x40 ||
2362 flash_id == 0x4f) {
2363
2364
2365 rest_addr = 0xffff;
2366 sec_mask = 0x10000;
2367 break;
2368 } else if (flash_id == 0x3e) {
2369
2370
2371
2372
2373
2374 rest_addr = 0xffff;
2375 sec_mask = 0x10000;
2376 break;
2377 } else if (flash_id == 0x20 || flash_id == 0x6e) {
2378
2379
2380
2381
2382 rest_addr = 0x3fff;
2383 sec_mask = 0x1c000;
2384 break;
2385 } else if (flash_id == 0x6d) {
2386
2387 rest_addr = 0x1fff;
2388 sec_mask = 0x1e000;
2389 break;
2390 }
2391 default:
2392
2393 rest_addr = 0x3fff;
2394 sec_mask = 0x1c000;
2395 break;
2396 }
2397
2398update_flash:
2399 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2400 if (qla2x00_erase_flash(ha, man_id, flash_id)) {
2401 rval = QLA_FUNCTION_FAILED;
2402 break;
2403 }
2404 }
2405
2406 for (addr = offset, liter = 0; liter < length; liter++,
2407 addr++) {
2408 data = buf[liter];
2409
2410 if ((addr & rest_addr) == 0) {
2411 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
2412 if (addr >= 0x10000UL) {
2413 if (((addr >> 12) & 0xf0) &&
2414 ((man_id == 0x01 &&
2415 flash_id == 0x3e) ||
2416 (man_id == 0x20 &&
2417 flash_id == 0xd2))) {
2418 sec_number++;
2419 if (sec_number == 1) {
2420 rest_addr =
2421 0x7fff;
2422 sec_mask =
2423 0x18000;
2424 } else if (
2425 sec_number == 2 ||
2426 sec_number == 3) {
2427 rest_addr =
2428 0x1fff;
2429 sec_mask =
2430 0x1e000;
2431 } else if (
2432 sec_number == 4) {
2433 rest_addr =
2434 0x3fff;
2435 sec_mask =
2436 0x1c000;
2437 }
2438 }
2439 }
2440 } else if (addr == ha->optrom_size / 2) {
2441 WRT_REG_WORD(®->nvram, NVR_SELECT);
2442 RD_REG_WORD(®->nvram);
2443 }
2444
2445 if (flash_id == 0xda && man_id == 0xc1) {
2446 qla2x00_write_flash_byte(ha, 0x5555,
2447 0xaa);
2448 qla2x00_write_flash_byte(ha, 0x2aaa,
2449 0x55);
2450 qla2x00_write_flash_byte(ha, 0x5555,
2451 0xa0);
2452 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
2453
2454 if (qla2x00_erase_flash_sector(ha,
2455 addr, sec_mask, man_id,
2456 flash_id)) {
2457 rval = QLA_FUNCTION_FAILED;
2458 break;
2459 }
2460 if (man_id == 0x01 && flash_id == 0x6d)
2461 sec_number++;
2462 }
2463 }
2464
2465 if (man_id == 0x01 && flash_id == 0x6d) {
2466 if (sec_number == 1 &&
2467 addr == (rest_addr - 1)) {
2468 rest_addr = 0x0fff;
2469 sec_mask = 0x1f000;
2470 } else if (sec_number == 3 && (addr & 0x7ffe)) {
2471 rest_addr = 0x3fff;
2472 sec_mask = 0x1c000;
2473 }
2474 }
2475
2476 if (qla2x00_program_flash_address(ha, addr, data,
2477 man_id, flash_id)) {
2478 rval = QLA_FUNCTION_FAILED;
2479 break;
2480 }
2481 cond_resched();
2482 }
2483 } while (0);
2484 qla2x00_flash_disable(ha);
2485
2486
2487 qla2x00_resume_hba(vha);
2488
2489 return rval;
2490}
2491
2492uint8_t *
2493qla24xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2494 uint32_t offset, uint32_t length)
2495{
2496 struct qla_hw_data *ha = vha->hw;
2497
2498
2499 scsi_block_requests(vha->host);
2500 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2501
2502
2503 qla24xx_read_flash_data(vha, (uint32_t *)buf, offset >> 2, length >> 2);
2504
2505
2506 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2507 scsi_unblock_requests(vha->host);
2508
2509 return buf;
2510}
2511
2512int
2513qla24xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2514 uint32_t offset, uint32_t length)
2515{
2516 int rval;
2517 struct qla_hw_data *ha = vha->hw;
2518
2519
2520 scsi_block_requests(vha->host);
2521 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2522
2523
2524 rval = qla24xx_write_flash_data(vha, (uint32_t *)buf, offset >> 2,
2525 length >> 2);
2526
2527 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
2528 scsi_unblock_requests(vha->host);
2529
2530 return rval;
2531}
2532
2533uint8_t *
2534qla25xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2535 uint32_t offset, uint32_t length)
2536{
2537 int rval;
2538 dma_addr_t optrom_dma;
2539 void *optrom;
2540 uint8_t *pbuf;
2541 uint32_t faddr, left, burst;
2542 struct qla_hw_data *ha = vha->hw;
2543
2544 if (IS_QLA25XX(ha) || IS_QLA81XX(ha))
2545 goto try_fast;
2546 if (offset & 0xfff)
2547 goto slow_read;
2548 if (length < OPTROM_BURST_SIZE)
2549 goto slow_read;
2550
2551try_fast:
2552 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2553 &optrom_dma, GFP_KERNEL);
2554 if (!optrom) {
2555 ql_log(ql_log_warn, vha, 0x00cc,
2556 "Unable to allocate memory for optrom burst read (%x KB).\n",
2557 OPTROM_BURST_SIZE / 1024);
2558 goto slow_read;
2559 }
2560
2561 pbuf = buf;
2562 faddr = offset >> 2;
2563 left = length >> 2;
2564 burst = OPTROM_BURST_DWORDS;
2565 while (left != 0) {
2566 if (burst > left)
2567 burst = left;
2568
2569 rval = qla2x00_dump_ram(vha, optrom_dma,
2570 flash_data_addr(ha, faddr), burst);
2571 if (rval) {
2572 ql_log(ql_log_warn, vha, 0x00f5,
2573 "Unable to burst-read optrom segment (%x/%x/%llx).\n",
2574 rval, flash_data_addr(ha, faddr),
2575 (unsigned long long)optrom_dma);
2576 ql_log(ql_log_warn, vha, 0x00f6,
2577 "Reverting to slow-read.\n");
2578
2579 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2580 optrom, optrom_dma);
2581 goto slow_read;
2582 }
2583
2584 memcpy(pbuf, optrom, burst * 4);
2585
2586 left -= burst;
2587 faddr += burst;
2588 pbuf += burst * 4;
2589 }
2590
2591 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
2592 optrom_dma);
2593
2594 return buf;
2595
2596slow_read:
2597 return qla24xx_read_optrom_data(vha, buf, offset, length);
2598}
2599
2600
2601
2602
2603
2604
2605
2606
2607
2608
2609
2610
2611
2612
2613
2614
2615
2616
2617
2618static void
2619qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids)
2620{
2621 int ret = QLA_FUNCTION_FAILED;
2622 uint32_t istart, iend, iter, vend;
2623 uint8_t do_next, rbyte, *vbyte;
2624
2625 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2626
2627
2628 istart = pcids +
2629 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
2630 qla2x00_read_flash_byte(ha, pcids + 0x0A));
2631 iend = istart + 0x100;
2632 do {
2633
2634 do_next = 0;
2635 iter = istart;
2636 while ((iter < iend) && !do_next) {
2637 iter++;
2638 if (qla2x00_read_flash_byte(ha, iter) == '/') {
2639 if (qla2x00_read_flash_byte(ha, iter + 2) ==
2640 '/')
2641 do_next++;
2642 else if (qla2x00_read_flash_byte(ha,
2643 iter + 3) == '/')
2644 do_next++;
2645 }
2646 }
2647 if (!do_next)
2648 break;
2649
2650
2651 do_next = 0;
2652 while ((iter > istart) && !do_next) {
2653 iter--;
2654 if (qla2x00_read_flash_byte(ha, iter) == ' ')
2655 do_next++;
2656 }
2657 if (!do_next)
2658 break;
2659
2660
2661
2662
2663
2664 vend = iter - 1;
2665 do_next = 0;
2666 while ((iter > istart) && !do_next) {
2667 iter--;
2668 rbyte = qla2x00_read_flash_byte(ha, iter);
2669 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
2670 do_next++;
2671 }
2672 if (!do_next)
2673 break;
2674
2675
2676 iter++;
2677 if ((vend - iter) &&
2678 ((vend - iter) < sizeof(ha->fcode_revision))) {
2679 vbyte = ha->fcode_revision;
2680 while (iter <= vend) {
2681 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
2682 iter++;
2683 }
2684 ret = QLA_SUCCESS;
2685 }
2686 } while (0);
2687
2688 if (ret != QLA_SUCCESS)
2689 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2690}
2691
2692int
2693qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2694{
2695 int ret = QLA_SUCCESS;
2696 uint8_t code_type, last_image;
2697 uint32_t pcihdr, pcids;
2698 uint8_t *dbyte;
2699 uint16_t *dcode;
2700 struct qla_hw_data *ha = vha->hw;
2701
2702 if (!ha->pio_address || !mbuf)
2703 return QLA_FUNCTION_FAILED;
2704
2705 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2706 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2707 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2708 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2709
2710 qla2x00_flash_enable(ha);
2711
2712
2713 pcihdr = 0;
2714 last_image = 1;
2715 do {
2716
2717 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2718 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2719
2720 ql_log(ql_log_fatal, vha, 0x0050,
2721 "No matching ROM signature.\n");
2722 ret = QLA_FUNCTION_FAILED;
2723 break;
2724 }
2725
2726
2727 pcids = pcihdr +
2728 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2729 qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2730
2731
2732 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2733 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2734 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2735 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2736
2737 ql_log(ql_log_fatal, vha, 0x0051,
2738 "PCI data struct not found pcir_adr=%x.\n", pcids);
2739 ret = QLA_FUNCTION_FAILED;
2740 break;
2741 }
2742
2743
2744 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2745 switch (code_type) {
2746 case ROM_CODE_TYPE_BIOS:
2747
2748 ha->bios_revision[0] =
2749 qla2x00_read_flash_byte(ha, pcids + 0x12);
2750 ha->bios_revision[1] =
2751 qla2x00_read_flash_byte(ha, pcids + 0x13);
2752 ql_dbg(ql_dbg_init, vha, 0x0052,
2753 "Read BIOS %d.%d.\n",
2754 ha->bios_revision[1], ha->bios_revision[0]);
2755 break;
2756 case ROM_CODE_TYPE_FCODE:
2757
2758
2759 qla2x00_get_fcode_version(ha, pcids);
2760 break;
2761 case ROM_CODE_TYPE_EFI:
2762
2763 ha->efi_revision[0] =
2764 qla2x00_read_flash_byte(ha, pcids + 0x12);
2765 ha->efi_revision[1] =
2766 qla2x00_read_flash_byte(ha, pcids + 0x13);
2767 ql_dbg(ql_dbg_init, vha, 0x0053,
2768 "Read EFI %d.%d.\n",
2769 ha->efi_revision[1], ha->efi_revision[0]);
2770 break;
2771 default:
2772 ql_log(ql_log_warn, vha, 0x0054,
2773 "Unrecognized code type %x at pcids %x.\n",
2774 code_type, pcids);
2775 break;
2776 }
2777
2778 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2779
2780
2781 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2782 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2783 } while (!last_image);
2784
2785 if (IS_QLA2322(ha)) {
2786
2787 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2788 dbyte = mbuf;
2789 memset(dbyte, 0, 8);
2790 dcode = (uint16_t *)dbyte;
2791
2792 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10,
2793 8);
2794 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a,
2795 "Dumping fw "
2796 "ver from flash:.\n");
2797 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b,
2798 (uint8_t *)dbyte, 8);
2799
2800 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2801 dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2802 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2803 dcode[3] == 0)) {
2804 ql_log(ql_log_warn, vha, 0x0057,
2805 "Unrecognized fw revision at %x.\n",
2806 ha->flt_region_fw * 4);
2807 } else {
2808
2809 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2810 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2811 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2812 ql_dbg(ql_dbg_init, vha, 0x0058,
2813 "FW Version: "
2814 "%d.%d.%d.\n", ha->fw_revision[0],
2815 ha->fw_revision[1], ha->fw_revision[2]);
2816 }
2817 }
2818
2819 qla2x00_flash_disable(ha);
2820
2821 return ret;
2822}
2823
2824int
2825qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf)
2826{
2827 int ret = QLA_SUCCESS;
2828 uint32_t pcihdr, pcids;
2829 uint32_t *dcode;
2830 uint8_t *bcode;
2831 uint8_t code_type, last_image;
2832 int i;
2833 struct qla_hw_data *ha = vha->hw;
2834
2835 if (IS_QLA82XX(ha))
2836 return ret;
2837
2838 if (!mbuf)
2839 return QLA_FUNCTION_FAILED;
2840
2841 memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2842 memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2843 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2844 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2845
2846 dcode = mbuf;
2847
2848
2849 pcihdr = ha->flt_region_boot << 2;
2850 last_image = 1;
2851 do {
2852
2853 qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20);
2854 bcode = mbuf + (pcihdr % 4);
2855 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2856
2857 ql_log(ql_log_fatal, vha, 0x0059,
2858 "No matching ROM signature.\n");
2859 ret = QLA_FUNCTION_FAILED;
2860 break;
2861 }
2862
2863
2864 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2865
2866 qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20);
2867 bcode = mbuf + (pcihdr % 4);
2868
2869
2870 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2871 bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2872
2873 ql_log(ql_log_fatal, vha, 0x005a,
2874 "PCI data struct not found pcir_adr=%x.\n", pcids);
2875 ret = QLA_FUNCTION_FAILED;
2876 break;
2877 }
2878
2879
2880 code_type = bcode[0x14];
2881 switch (code_type) {
2882 case ROM_CODE_TYPE_BIOS:
2883
2884 ha->bios_revision[0] = bcode[0x12];
2885 ha->bios_revision[1] = bcode[0x13];
2886 ql_dbg(ql_dbg_init, vha, 0x005b,
2887 "Read BIOS %d.%d.\n",
2888 ha->bios_revision[1], ha->bios_revision[0]);
2889 break;
2890 case ROM_CODE_TYPE_FCODE:
2891
2892 ha->fcode_revision[0] = bcode[0x12];
2893 ha->fcode_revision[1] = bcode[0x13];
2894 ql_dbg(ql_dbg_init, vha, 0x005c,
2895 "Read FCODE %d.%d.\n",
2896 ha->fcode_revision[1], ha->fcode_revision[0]);
2897 break;
2898 case ROM_CODE_TYPE_EFI:
2899
2900 ha->efi_revision[0] = bcode[0x12];
2901 ha->efi_revision[1] = bcode[0x13];
2902 ql_dbg(ql_dbg_init, vha, 0x005d,
2903 "Read EFI %d.%d.\n",
2904 ha->efi_revision[1], ha->efi_revision[0]);
2905 break;
2906 default:
2907 ql_log(ql_log_warn, vha, 0x005e,
2908 "Unrecognized code type %x at pcids %x.\n",
2909 code_type, pcids);
2910 break;
2911 }
2912
2913 last_image = bcode[0x15] & BIT_7;
2914
2915
2916 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2917 } while (!last_image);
2918
2919
2920 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2921 dcode = mbuf;
2922
2923 qla24xx_read_flash_data(vha, dcode, ha->flt_region_fw + 4, 4);
2924 for (i = 0; i < 4; i++)
2925 dcode[i] = be32_to_cpu(dcode[i]);
2926
2927 if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2928 dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2929 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2930 dcode[3] == 0)) {
2931 ql_log(ql_log_warn, vha, 0x005f,
2932 "Unrecognized fw revision at %x.\n",
2933 ha->flt_region_fw * 4);
2934 } else {
2935 ha->fw_revision[0] = dcode[0];
2936 ha->fw_revision[1] = dcode[1];
2937 ha->fw_revision[2] = dcode[2];
2938 ha->fw_revision[3] = dcode[3];
2939 ql_dbg(ql_dbg_init, vha, 0x0060,
2940 "Firmware revision %d.%d.%d.%d.\n",
2941 ha->fw_revision[0], ha->fw_revision[1],
2942 ha->fw_revision[2], ha->fw_revision[3]);
2943 }
2944
2945
2946 if (!IS_QLA81XX(ha)) {
2947
2948 return ret;
2949 }
2950
2951 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version));
2952 dcode = mbuf;
2953 ha->isp_ops->read_optrom(vha, (uint8_t *)dcode,
2954 ha->flt_region_gold_fw << 2, 32);
2955
2956 if (dcode[4] == 0xFFFFFFFF && dcode[5] == 0xFFFFFFFF &&
2957 dcode[6] == 0xFFFFFFFF && dcode[7] == 0xFFFFFFFF) {
2958 ql_log(ql_log_warn, vha, 0x0056,
2959 "Unrecognized golden fw at 0x%x.\n",
2960 ha->flt_region_gold_fw * 4);
2961 return ret;
2962 }
2963
2964 for (i = 4; i < 8; i++)
2965 ha->gold_fw_version[i-4] = be32_to_cpu(dcode[i]);
2966
2967 return ret;
2968}
2969
2970static int
2971qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end)
2972{
2973 if (pos >= end || *pos != 0x82)
2974 return 0;
2975
2976 pos += 3 + pos[1];
2977 if (pos >= end || *pos != 0x90)
2978 return 0;
2979
2980 pos += 3 + pos[1];
2981 if (pos >= end || *pos != 0x78)
2982 return 0;
2983
2984 return 1;
2985}
2986
2987int
2988qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size)
2989{
2990 struct qla_hw_data *ha = vha->hw;
2991 uint8_t *pos = ha->vpd;
2992 uint8_t *end = pos + ha->vpd_size;
2993 int len = 0;
2994
2995 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end))
2996 return 0;
2997
2998 while (pos < end && *pos != 0x78) {
2999 len = (*pos == 0x82) ? pos[1] : pos[2];
3000
3001 if (!strncmp(pos, key, strlen(key)))
3002 break;
3003
3004 if (*pos != 0x90 && *pos != 0x91)
3005 pos += len;
3006
3007 pos += 3;
3008 }
3009
3010 if (pos < end - len && *pos != 0x78)
3011 return snprintf(str, size, "%.*s", len, pos + 3);
3012
3013 return 0;
3014}
3015
3016int
3017qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha)
3018{
3019 int len, max_len;
3020 uint32_t fcp_prio_addr;
3021 struct qla_hw_data *ha = vha->hw;
3022
3023 if (!ha->fcp_prio_cfg) {
3024 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE);
3025 if (!ha->fcp_prio_cfg) {
3026 ql_log(ql_log_warn, vha, 0x00d5,
3027 "Unable to allocate memory for fcp priorty data (%x).\n",
3028 FCP_PRIO_CFG_SIZE);
3029 return QLA_FUNCTION_FAILED;
3030 }
3031 }
3032 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE);
3033
3034 fcp_prio_addr = ha->flt_region_fcp_prio;
3035
3036
3037 ha->isp_ops->read_optrom(vha, (uint8_t *)ha->fcp_prio_cfg,
3038 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE);
3039
3040 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0))
3041 goto fail;
3042
3043
3044 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2);
3045 len = ha->fcp_prio_cfg->num_entries * FCP_PRIO_CFG_ENTRY_SIZE;
3046 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE;
3047
3048 ha->isp_ops->read_optrom(vha, (uint8_t *)&ha->fcp_prio_cfg->entry[0],
3049 fcp_prio_addr << 2, (len < max_len ? len : max_len));
3050
3051
3052 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1))
3053 goto fail;
3054
3055 ha->flags.fcp_prio_enabled = 1;
3056 return QLA_SUCCESS;
3057fail:
3058 vfree(ha->fcp_prio_cfg);
3059 ha->fcp_prio_cfg = NULL;
3060 return QLA_FUNCTION_FAILED;
3061}
3062