LXR linux/drivers/scsi/t128.h

   1/*
   2 * Trantor T128/T128F/T228 defines
   3 *      Note : architecturally, the T100 and T128 are different and won't work
   4 *
   5 * Copyright 1993, Drew Eckhardt
   6 *      Visionary Computing
   7 *      (Unix and Linux consulting and custom programming)
   8 *      drew@colorado.edu
   9 *      +1 (303) 440-4894
  10 *
  11 * DISTRIBUTION RELEASE 3.
  12 *
  13 * For more information, please consult
  14 *
  15 * Trantor Systems, Ltd.
  16 * T128/T128F/T228 SCSI Host Adapter
  17 * Hardware Specifications
  18 *
  19 * Trantor Systems, Ltd.
  20 * 5415 Randall Place
  21 * Fremont, CA 94538
  22 * 1+ (415) 770-1400, FAX 1+ (415) 770-9910
  23 *
  24 * and
  25 *
  26 * NCR 5380 Family
  27 * SCSI Protocol Controller
  28 * Databook
  29 *
  30 * NCR Microelectronics
  31 * 1635 Aeroplaza Drive
  32 * Colorado Springs, CO 80916
  33 * 1+ (719) 578-3400
  34 * 1+ (800) 334-5454
  35 */
  36
  37/*
  38 * $Log: t128.h,v $
  39 */
  40
  41#ifndef T128_H
  42#define T128_H
  43
  44#define T128_PUBLIC_RELEASE 3
  45
  46#define TDEBUG          0
  47#define TDEBUG_INIT     0x1
  48#define TDEBUG_TRANSFER 0x2
  49
  50/*
  51 * The trantor boards are memory mapped. They use an NCR5380 or
  52 * equivalent (my sample board had part second sourced from ZILOG).
  53 * NCR's recommended "Pseudo-DMA" architecture is used, where
  54 * a PAL drives the DMA signals on the 5380 allowing fast, blind
  55 * transfers with proper handshaking.
  56 */
  57
  58/*
  59 * Note : a boot switch is provided for the purpose of informing the
  60 * firmware to boot or not boot from attached SCSI devices.  So, I imagine
  61 * there are fewer people who've yanked the ROM like they do on the Seagate
  62 * to make bootup faster, and I'll probably use this for autodetection.
  63 */
  64#define T_ROM_OFFSET            0
  65
  66/*
  67 * Note : my sample board *WAS NOT* populated with the SRAM, so this
  68 * can't be used for autodetection without a ROM present.
  69 */
  70#define T_RAM_OFFSET            0x1800
  71
  72/*
  73 * All of the registers are allocated 32 bytes of address space, except
  74 * for the data register (read/write to/from the 5380 in pseudo-DMA mode)
  75 */ 
  76#define T_CONTROL_REG_OFFSET    0x1c00  /* rw */
  77#define T_CR_INT                0x10    /* Enable interrupts */
  78#define T_CR_CT                 0x02    /* Reset watchdog timer */
  79
  80#define T_STATUS_REG_OFFSET     0x1c20  /* ro */
  81#define T_ST_BOOT               0x80    /* Boot switch */
  82#define T_ST_S3                 0x40    /* User settable switches, */
  83#define T_ST_S2                 0x20    /* read 0 when switch is on, 1 off */
  84#define T_ST_S1                 0x10
  85#define T_ST_PS2                0x08    /* Set for Microchannel 228 */
  86#define T_ST_RDY                0x04    /* 5380 DRQ */
  87#define T_ST_TIM                0x02    /* indicates 40us watchdog timer fired */
  88#define T_ST_ZERO               0x01    /* Always zero */
  89
  90#define T_5380_OFFSET           0x1d00  /* 8 registers here, see NCR5380.h */
  91
  92#define T_DATA_REG_OFFSET       0x1e00  /* rw 512 bytes long */
  93
  94#ifndef ASM
  95static int t128_abort(struct scsi_cmnd *);
  96static int t128_biosparam(struct scsi_device *, struct block_device *,
  97                          sector_t, int*);
  98static int t128_detect(struct scsi_host_template *);
  99static int t128_queue_command(struct Scsi_Host *, struct scsi_cmnd *);
 100static int t128_bus_reset(struct scsi_cmnd *);
 101
 102#ifndef CMD_PER_LUN
 103#define CMD_PER_LUN 2
 104#endif
 105
 106#ifndef CAN_QUEUE
 107#define CAN_QUEUE 32
 108#endif
 109
 110#ifndef HOSTS_C
 111
 112#define NCR5380_implementation_fields \
 113    void __iomem *base
 114
 115#define NCR5380_local_declare() \
 116    void __iomem *base
 117
 118#define NCR5380_setup(instance) \
 119    base = ((struct NCR5380_hostdata *)(instance->hostdata))->base
 120
 121#define T128_address(reg) (base + T_5380_OFFSET + ((reg) * 0x20))
 122
 123#if !(TDEBUG & TDEBUG_TRANSFER)
 124#define NCR5380_read(reg) readb(T128_address(reg))
 125#define NCR5380_write(reg, value) writeb((value),(T128_address(reg)))
 126#else
 127#define NCR5380_read(reg)                                               \
 128    (((unsigned char) printk("scsi%d : read register %d at address %08x\n"\
 129    , instance->hostno, (reg), T128_address(reg))), readb(T128_address(reg)))
 130
 131#define NCR5380_write(reg, value) {                                     \
 132    printk("scsi%d : write %02x to register %d at address %08x\n",      \
 133            instance->hostno, (value), (reg), T128_address(reg));       \
 134    writeb((value), (T128_address(reg)));                               \
 135}
 136#endif
 137
 138#define NCR5380_intr t128_intr
 139#define do_NCR5380_intr do_t128_intr
 140#define NCR5380_queue_command t128_queue_command
 141#define NCR5380_abort t128_abort
 142#define NCR5380_bus_reset t128_bus_reset
 143#define NCR5380_show_info t128_show_info
 144#define NCR5380_write_info t128_write_info
 145
 146/* 15 14 12 10 7 5 3
 147   1101 0100 1010 1000 */
 148
 149#define T128_IRQS 0xc4a8
 150
 151#endif /* else def HOSTS_C */
 152#endif /* ndef ASM */
 153#endif /* T128_H */
 154