LXR linux/drivers/staging/crystalhd/bc_dts_glob

   1/********************************************************************
   2 * Copyright(c) 2006-2009 Broadcom Corporation.
   3 *
   4 *  Name: bc_dts_glob_lnx.h
   5 *
   6 *  Description: Wrapper to Windows dts_glob.h for Link-Linux usage.
   7 *               The idea is to define additional Linux related defs
   8 *               in this file to avoid changes to existing Windows
   9 *               glob file.
  10 *
  11 *  AU
  12 *
  13 *  HISTORY:
  14 *
  15 ********************************************************************
  16 * This header is free software: you can redistribute it and/or modify
  17 * it under the terms of the GNU Lesser General Public License as published
  18 * by the Free Software Foundation, either version 2.1 of the License.
  19 *
  20 * This header is distributed in the hope that it will be useful,
  21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 * GNU Lesser General Public License for more details.
  24 * You should have received a copy of the GNU Lesser General Public License
  25 * along with this header.  If not, see <http://www.gnu.org/licenses/>.
  26 *******************************************************************/
  27
  28#ifndef _BC_DTS_GLOB_LNX_H_
  29#define _BC_DTS_GLOB_LNX_H_
  30
  31#ifdef __LINUX_USER__
  32#include <stdio.h>
  33#include <stdlib.h>
  34#include <unistd.h>
  35#include <fcntl.h>
  36#include <ctype.h>
  37#include <string.h>
  38#include <errno.h>
  39#include <netdb.h>
  40#include <sys/time.h>
  41#include <time.h>
  42#include <arpa/inet.h>
  43#include <linux/param.h>
  44#include <linux/ioctl.h>
  45#include <sys/select.h>
  46
  47#define DRVIFLIB_INT_API
  48
  49#endif
  50
  51#include "crystalhd.h"
  52
  53#define CRYSTALHD_API_NAME      "crystalhd"
  54#define CRYSTALHD_API_DEV_NAME  "/dev/crystalhd"
  55
  56/*
  57 * These are SW stack tunable parameters shared
  58 * between the driver and the application.
  59 */
  60enum BC_DTS_GLOBALS {
  61        BC_MAX_FW_CMD_BUFF_SZ = 0x40, /* FW passthrough cmd/rsp buffer size */
  62        PCI_CFG_SIZE            = 256,          /* PCI config size buffer */
  63        BC_IOCTL_DATA_POOL_SIZE = 8,            /* BC_IOCTL_DATA Pool size */
  64        BC_LINK_MAX_OPENS       = 3,    /* Maximum simultaneous opens*/
  65        BC_LINK_MAX_SGLS        = 1024, /* Maximum SG elements 4M/4K */
  66        BC_TX_LIST_CNT          = 2,            /* Max Tx DMA Rings */
  67        BC_RX_LIST_CNT          = 8,            /* Max Rx DMA Rings*/
  68        BC_PROC_OUTPUT_TIMEOUT  = 3000,         /* Milliseconds */
  69        BC_INFIFO_THRESHOLD     = 0x10000,
  70};
  71
  72struct BC_CMD_REG_ACC {
  73        uint32_t                Offset;
  74        uint32_t                Value;
  75};
  76
  77struct BC_CMD_DEV_MEM {
  78        uint32_t                StartOff;
  79        uint32_t                NumDwords;
  80        uint32_t                Rsrd;
  81};
  82
  83/* FW Passthrough command structure */
  84enum bc_fw_cmd_flags {
  85        BC_FW_CMD_FLAGS_NONE    = 0,
  86        BC_FW_CMD_PIB_QS        = 0x01,
  87};
  88
  89struct BC_FW_CMD {
  90        uint32_t                cmd[BC_MAX_FW_CMD_BUFF_SZ];
  91        uint32_t                rsp[BC_MAX_FW_CMD_BUFF_SZ];
  92        uint32_t                flags;
  93        uint32_t                add_data;
  94};
  95
  96struct BC_HW_TYPE {
  97        uint16_t                PciDevId;
  98        uint16_t                PciVenId;
  99        uint8_t                 HwRev;
 100        uint8_t                 Align[3];
 101};
 102
 103struct BC_PCI_CFG {
 104        uint32_t                Size;
 105        uint32_t                Offset;
 106        uint8_t                 pci_cfg_space[PCI_CFG_SIZE];
 107};
 108
 109struct BC_VERSION_INFO {
 110        uint8_t                 DriverMajor;
 111        uint8_t                 DriverMinor;
 112        uint16_t                DriverRevision;
 113};
 114
 115struct BC_START_RX_CAP {
 116        uint32_t                Rsrd;
 117        uint32_t                StartDeliveryThsh;
 118        uint32_t                PauseThsh;
 119        uint32_t                ResumeThsh;
 120};
 121
 122struct BC_FLUSH_RX_CAP {
 123        uint32_t                Rsrd;
 124        uint32_t                bDiscardOnly;
 125};
 126
 127struct BC_DTS_STATS {
 128        uint8_t                 drvRLL;
 129        uint8_t                 drvFLL;
 130        uint8_t                 eosDetected;
 131        uint8_t                 pwr_state_change;
 132
 133        /* Stats from App */
 134        uint32_t                opFrameDropped;
 135        uint32_t                opFrameCaptured;
 136        uint32_t                ipSampleCnt;
 137        uint64_t                ipTotalSize;
 138        uint32_t                reptdFrames;
 139        uint32_t                pauseCount;
 140        uint32_t                pibMisses;
 141        uint32_t                discCounter;
 142
 143        /* Stats from Driver */
 144        uint32_t                TxFifoBsyCnt;
 145        uint32_t                intCount;
 146        uint32_t                DrvIgnIntrCnt;
 147        uint32_t                DrvTotalFrmDropped;
 148        uint32_t                DrvTotalHWErrs;
 149        uint32_t                DrvTotalPIBFlushCnt;
 150        uint32_t                DrvTotalFrmCaptured;
 151        uint32_t                DrvPIBMisses;
 152        uint32_t                DrvPauseTime;
 153        uint32_t                DrvRepeatedFrms;
 154        uint32_t                res1[13];
 155
 156};
 157
 158struct BC_PROC_INPUT {
 159        uint8_t                 *pDmaBuff;
 160        uint32_t                BuffSz;
 161        uint8_t                 Mapped;
 162        uint8_t                 Encrypted;
 163        uint8_t                 Rsrd[2];
 164        uint32_t                DramOffset;     /* For debug use only */
 165};
 166
 167struct BC_DEC_YUV_BUFFS {
 168        uint32_t                b422Mode;
 169        uint8_t                 *YuvBuff;
 170        uint32_t                YuvBuffSz;
 171        uint32_t                UVbuffOffset;
 172        uint32_t                YBuffDoneSz;
 173        uint32_t                UVBuffDoneSz;
 174        uint32_t                RefCnt;
 175};
 176
 177enum DECOUT_COMPLETION_FLAGS {
 178        COMP_FLAG_NO_INFO       = 0x00,
 179        COMP_FLAG_FMT_CHANGE    = 0x01,
 180        COMP_FLAG_PIB_VALID     = 0x02,
 181        COMP_FLAG_DATA_VALID    = 0x04,
 182        COMP_FLAG_DATA_ENC      = 0x08,
 183        COMP_FLAG_DATA_BOT      = 0x10,
 184};
 185
 186struct BC_DEC_OUT_BUFF {
 187        struct BC_DEC_YUV_BUFFS OutPutBuffs;
 188        struct BC_PIC_INFO_BLOCK PibInfo;
 189        uint32_t                Flags;
 190        uint32_t                BadFrCnt;
 191};
 192
 193struct BC_NOTIFY_MODE {
 194        uint32_t                Mode;
 195        uint32_t                Rsvr[3];
 196};
 197
 198struct BC_CLOCK {
 199        uint32_t                clk;
 200        uint32_t                Rsvr[3];
 201};
 202
 203struct BC_IOCTL_DATA {
 204        enum BC_STATUS          RetSts;
 205        uint32_t                IoctlDataSz;
 206        uint32_t                Timeout;
 207        union {
 208                struct BC_CMD_REG_ACC   regAcc;
 209                struct BC_CMD_DEV_MEM   devMem;
 210                struct BC_FW_CMD        fwCmd;
 211                struct BC_HW_TYPE       hwType;
 212                struct BC_PCI_CFG       pciCfg;
 213                struct BC_VERSION_INFO  VerInfo;
 214                struct BC_PROC_INPUT    ProcInput;
 215                struct BC_DEC_YUV_BUFFS RxBuffs;
 216                struct BC_DEC_OUT_BUFF  DecOutData;
 217                struct BC_START_RX_CAP  RxCap;
 218                struct BC_FLUSH_RX_CAP  FlushRxCap;
 219                struct BC_DTS_STATS     drvStat;
 220                struct BC_NOTIFY_MODE   NotifyMode;
 221                struct BC_CLOCK         clockValue;
 222        } u;
 223        struct _BC_IOCTL_DATA   *next;
 224};
 225
 226enum BC_DRV_CMD {
 227        DRV_CMD_VERSION = 0,    /* Get SW version */
 228        DRV_CMD_GET_HWTYPE,     /* Get HW version and type Dozer/Tank */
 229        DRV_CMD_REG_RD,         /* Read Device Register */
 230        DRV_CMD_REG_WR,         /* Write Device Register */
 231        DRV_CMD_FPGA_RD,        /* Read FPGA Register */
 232        DRV_CMD_FPGA_WR,        /* Wrtie FPGA Reister */
 233        DRV_CMD_MEM_RD,         /* Read Device Memory */
 234        DRV_CMD_MEM_WR,         /* Write Device Memory */
 235        DRV_CMD_RD_PCI_CFG,     /* Read PCI Config Space */
 236        DRV_CMD_WR_PCI_CFG,     /* Write the PCI Configuration Space*/
 237        DRV_CMD_FW_DOWNLOAD,    /* Download Firmware */
 238        DRV_ISSUE_FW_CMD,       /* Issue FW Cmd (pass through mode) */
 239        DRV_CMD_PROC_INPUT,     /* Process Input Sample */
 240        DRV_CMD_ADD_RXBUFFS,    /* Add Rx side buffers to driver pool */
 241        DRV_CMD_FETCH_RXBUFF,   /* Get Rx DMAed buffer */
 242        DRV_CMD_START_RX_CAP,   /* Start Rx Buffer Capture */
 243        DRV_CMD_FLUSH_RX_CAP,   /* Stop the capture for now...
 244                        we will enhance this later*/
 245        DRV_CMD_GET_DRV_STAT,   /* Get Driver Internal Statistics */
 246        DRV_CMD_RST_DRV_STAT,   /* Reset Driver Internal Statistics */
 247        DRV_CMD_NOTIFY_MODE,    /* Notify the Mode to driver
 248                        in which the application is Operating*/
 249        DRV_CMD_CHANGE_CLOCK,   /* Change the core clock to either save power
 250                        or improve performance */
 251
 252        /* MUST be the last one.. */
 253        DRV_CMD_END,                    /* End of the List.. */
 254};
 255
 256#define BC_IOC_BASE             'b'
 257#define BC_IOC_VOID             _IOC_NONE
 258#define BC_IOC_IOWR(nr, type)   _IOWR(BC_IOC_BASE, nr, type)
 259#define BC_IOCTL_MB             struct BC_IOCTL_DATA
 260
 261#define BCM_IOC_GET_VERSION     BC_IOC_IOWR(DRV_CMD_VERSION, BC_IOCTL_MB)
 262#define BCM_IOC_GET_HWTYPE      BC_IOC_IOWR(DRV_CMD_GET_HWTYPE, BC_IOCTL_MB)
 263#define BCM_IOC_REG_RD          BC_IOC_IOWR(DRV_CMD_REG_RD, BC_IOCTL_MB)
 264#define BCM_IOC_REG_WR          BC_IOC_IOWR(DRV_CMD_REG_WR, BC_IOCTL_MB)
 265#define BCM_IOC_MEM_RD          BC_IOC_IOWR(DRV_CMD_MEM_RD, BC_IOCTL_MB)
 266#define BCM_IOC_MEM_WR          BC_IOC_IOWR(DRV_CMD_MEM_WR, BC_IOCTL_MB)
 267#define BCM_IOC_FPGA_RD         BC_IOC_IOWR(DRV_CMD_FPGA_RD, BC_IOCTL_MB)
 268#define BCM_IOC_FPGA_WR         BC_IOC_IOWR(DRV_CMD_FPGA_WR, BC_IOCTL_MB)
 269#define BCM_IOC_RD_PCI_CFG      BC_IOC_IOWR(DRV_CMD_RD_PCI_CFG, BC_IOCTL_MB)
 270#define BCM_IOC_WR_PCI_CFG      BC_IOC_IOWR(DRV_CMD_WR_PCI_CFG, BC_IOCTL_MB)
 271#define BCM_IOC_PROC_INPUT      BC_IOC_IOWR(DRV_CMD_PROC_INPUT, BC_IOCTL_MB)
 272#define BCM_IOC_ADD_RXBUFFS     BC_IOC_IOWR(DRV_CMD_ADD_RXBUFFS, BC_IOCTL_MB)
 273#define BCM_IOC_FETCH_RXBUFF    BC_IOC_IOWR(DRV_CMD_FETCH_RXBUFF, BC_IOCTL_MB)
 274#define BCM_IOC_FW_CMD          BC_IOC_IOWR(DRV_ISSUE_FW_CMD, BC_IOCTL_MB)
 275#define BCM_IOC_START_RX_CAP    BC_IOC_IOWR(DRV_CMD_START_RX_CAP, BC_IOCTL_MB)
 276#define BCM_IOC_FLUSH_RX_CAP    BC_IOC_IOWR(DRV_CMD_FLUSH_RX_CAP, BC_IOCTL_MB)
 277#define BCM_IOC_GET_DRV_STAT    BC_IOC_IOWR(DRV_CMD_GET_DRV_STAT, BC_IOCTL_MB)
 278#define BCM_IOC_RST_DRV_STAT    BC_IOC_IOWR(DRV_CMD_RST_DRV_STAT, BC_IOCTL_MB)
 279#define BCM_IOC_NOTIFY_MODE     BC_IOC_IOWR(DRV_CMD_NOTIFY_MODE, BC_IOCTL_MB)
 280#define BCM_IOC_FW_DOWNLOAD     BC_IOC_IOWR(DRV_CMD_FW_DOWNLOAD, BC_IOCTL_MB)
 281#define BCM_IOC_CHG_CLK         BC_IOC_IOWR(DRV_CMD_CHANGE_CLOCK, BC_IOCTL_MB)
 282#define BCM_IOC_END             BC_IOC_VOID
 283
 284/* Wrapper for main IOCTL data */
 285struct crystalhd_ioctl_data {
 286        struct BC_IOCTL_DATA    udata;          /* IOCTL from App..*/
 287        uint32_t                u_id;           /* Driver specific user ID */
 288        uint32_t                cmd;            /* Cmd ID for driver's use. */
 289        void     *add_cdata;    /* Additional command specific data..*/
 290        uint32_t add_cdata_sz;  /* Additional command specific data size */
 291        struct crystalhd_ioctl_data *next;      /* List/Fifo management */
 292};
 293
 294enum crystalhd_kmod_ver {
 295        crystalhd_kmod_major    = 0,
 296        crystalhd_kmod_minor    = 9,
 297        crystalhd_kmod_rev      = 27,
 298};
 299
 300#endif
 301