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26#include <linux/blkdev.h>
27#include <linux/kthread.h>
28#include <linux/sched.h>
29#include <linux/vmalloc.h>
30
31#include "debug.h"
32#include "trace.h"
33#include "rts51x.h"
34#include "rts51x_transport.h"
35#include "rts51x_scsi.h"
36#include "rts51x_card.h"
37#include "xd.h"
38
39static int xd_build_l2p_tbl(struct rts51x_chip *chip, int zone_no);
40static int xd_init_page(struct rts51x_chip *chip, u32 phy_blk, u16 logoff,
41 u8 start_page, u8 end_page);
42
43static inline void xd_set_err_code(struct rts51x_chip *chip, u8 err_code)
44{
45 struct xd_info *xd_card = &(chip->xd_card);
46
47 xd_card->err_code = err_code;
48}
49
50static int xd_set_init_para(struct rts51x_chip *chip)
51{
52 struct xd_info *xd_card = &(chip->xd_card);
53 int retval;
54
55 if (chip->asic_code)
56 xd_card->xd_clock = 47;
57 else
58 xd_card->xd_clock = CLK_50;
59
60 retval = switch_clock(chip, xd_card->xd_clock);
61 if (retval != STATUS_SUCCESS)
62 TRACE_RET(chip, retval);
63
64 return STATUS_SUCCESS;
65}
66
67static int xd_switch_clock(struct rts51x_chip *chip)
68{
69 struct xd_info *xd_card = &(chip->xd_card);
70 int retval;
71
72 retval = rts51x_select_card(chip, XD_CARD);
73 if (retval != STATUS_SUCCESS)
74 TRACE_RET(chip, retval);
75
76 retval = switch_clock(chip, xd_card->xd_clock);
77 if (retval != STATUS_SUCCESS)
78 TRACE_RET(chip, retval);
79
80 return STATUS_SUCCESS;
81}
82
83static int xd_read_id(struct rts51x_chip *chip, u8 id_cmd, u8 *id_buf,
84 u8 buf_len)
85{
86 int retval, i;
87
88 rts51x_init_cmd(chip);
89
90 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, id_cmd);
91 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
92 XD_TRANSFER_START | XD_READ_ID);
93 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
94 XD_TRANSFER_END);
95
96 for (i = 0; i < 4; i++) {
97 rts51x_add_cmd(chip, READ_REG_CMD, (u16) (XD_ADDRESS1 + i), 0,
98 0);
99 }
100
101 retval = rts51x_send_cmd(chip, MODE_CR, 20);
102 if (retval != STATUS_SUCCESS)
103 TRACE_RET(chip, retval);
104
105 retval = rts51x_get_rsp(chip, 5, 20);
106
107 if (retval != STATUS_SUCCESS) {
108 rts51x_clear_xd_error(chip);
109 TRACE_RET(chip, retval);
110 }
111
112 if (id_buf && buf_len) {
113 if (buf_len > 4)
114 buf_len = 4;
115 rts51x_read_rsp_buf(chip, 1, id_buf, buf_len);
116 }
117
118 return STATUS_SUCCESS;
119}
120
121static void xd_assign_phy_addr(struct rts51x_chip *chip, u32 addr, u8 mode)
122{
123 struct xd_info *xd_card = &(chip->xd_card);
124
125 switch (mode) {
126 case XD_RW_ADDR:
127 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF, 0);
128 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF,
129 (u8) addr);
130 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF,
131 (u8) (addr >> 8));
132 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS3, 0xFF,
133 (u8) (addr >> 16));
134 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
135 xd_card->addr_cycle | XD_CALC_ECC |
136 XD_BA_NO_TRANSFORM);
137 break;
138
139 case XD_ERASE_ADDR:
140 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS0, 0xFF,
141 (u8) addr);
142 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS1, 0xFF,
143 (u8) (addr >> 8));
144 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_ADDRESS2, 0xFF,
145 (u8) (addr >> 16));
146 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, 0xFF,
147 (xd_card->addr_cycle - 1) |
148 XD_CALC_ECC | XD_BA_NO_TRANSFORM);
149 break;
150
151 default:
152 break;
153 }
154}
155
156static int xd_read_redundant(struct rts51x_chip *chip, u32 page_addr, u8 *buf,
157 int buf_len)
158{
159 int retval, i;
160
161 rts51x_init_cmd(chip);
162
163 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
164
165 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
166 XD_TRANSFER_START | XD_READ_REDUNDANT);
167 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
168 XD_TRANSFER_END);
169
170 for (i = 0; i < 6; i++) {
171 rts51x_add_cmd(chip, READ_REG_CMD, (u16) (XD_PAGE_STATUS + i),
172 0, 0);
173 }
174 for (i = 0; i < 4; i++) {
175 rts51x_add_cmd(chip, READ_REG_CMD, (u16) (XD_RESERVED0 + i), 0,
176 0);
177 }
178 rts51x_add_cmd(chip, READ_REG_CMD, XD_PARITY, 0, 0);
179
180 retval = rts51x_send_cmd(chip, MODE_CR, 100);
181 if (retval != STATUS_SUCCESS)
182 TRACE_RET(chip, retval);
183
184 retval = rts51x_get_rsp(chip, 11, 500);
185
186 if (retval != STATUS_SUCCESS) {
187 rts51x_clear_xd_error(chip);
188 TRACE_RET(chip, retval);
189 }
190
191 if (buf && buf_len) {
192 if (buf_len > 11)
193 buf_len = 11;
194 rts51x_read_rsp_buf(chip, 1, buf, buf_len);
195 }
196
197 return STATUS_SUCCESS;
198}
199
200static int xd_read_data_from_ppb(struct rts51x_chip *chip, int offset, u8 *buf,
201 int buf_len)
202{
203 int retval, i;
204
205 if (!buf || (buf_len <= 0))
206 TRACE_RET(chip, STATUS_FAIL);
207
208 rts51x_init_cmd(chip);
209
210 for (i = 0; i < buf_len; i++) {
211 rts51x_add_cmd(chip, READ_REG_CMD, PPBUF_BASE2 + offset + i, 0,
212 0);
213 }
214
215 retval = rts51x_send_cmd(chip, MODE_CR, 100);
216 if (retval != STATUS_SUCCESS)
217 TRACE_RET(chip, retval);
218
219 retval = rts51x_get_rsp(chip, buf_len, 200);
220 if (retval != STATUS_SUCCESS)
221 TRACE_RET(chip, retval);
222
223 rts51x_read_rsp_buf(chip, 0, buf, buf_len);
224
225 return STATUS_SUCCESS;
226}
227
228static int xd_read_cis(struct rts51x_chip *chip, u32 page_addr, u8 *buf,
229 int buf_len)
230{
231 int retval;
232 u8 reg;
233
234 if (!buf || (buf_len < 10))
235 TRACE_RET(chip, STATUS_FAIL);
236
237 rts51x_init_cmd(chip);
238
239 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
240
241 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
242 PINGPONG_BUFFER);
243 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
244 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
245 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
246
247 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
248 XD_TRANSFER_START | XD_READ_PAGES);
249 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
250 XD_TRANSFER_END | XD_PPB_EMPTY,
251 XD_TRANSFER_END | XD_PPB_EMPTY);
252
253 retval = rts51x_send_cmd(chip, MODE_CR, 100);
254 if (retval != STATUS_SUCCESS)
255 TRACE_RET(chip, retval);
256
257 retval = rts51x_get_rsp(chip, 1, 500);
258 if (retval == STATUS_TIMEDOUT) {
259 rts51x_clear_xd_error(chip);
260 TRACE_RET(chip, retval);
261 }
262
263 RTS51X_READ_REG(chip, XD_PAGE_STATUS, ®);
264 if (reg != XD_GPG) {
265 rts51x_clear_xd_error(chip);
266 TRACE_RET(chip, STATUS_FAIL);
267 }
268
269 RTS51X_READ_REG(chip, XD_CTL, ®);
270
271 if (!(reg & XD_ECC1_ERROR) || !(reg & XD_ECC1_UNCORRECTABLE)) {
272 retval = xd_read_data_from_ppb(chip, 0, buf, buf_len);
273 if (retval != STATUS_SUCCESS)
274 TRACE_RET(chip, retval);
275 if (reg & XD_ECC1_ERROR) {
276 u8 ecc_bit, ecc_byte;
277
278 RTS51X_READ_REG(chip, XD_ECC_BIT1, &ecc_bit);
279 RTS51X_READ_REG(chip, XD_ECC_BYTE1, &ecc_byte);
280
281 RTS51X_DEBUGP("ECC_BIT1 = 0x%x, ECC_BYTE1 = 0x%x\n",
282 ecc_bit, ecc_byte);
283 if (ecc_byte < buf_len) {
284 RTS51X_DEBUGP("Before correct: 0x%x\n",
285 buf[ecc_byte]);
286 buf[ecc_byte] ^= (1 << ecc_bit);
287 RTS51X_DEBUGP("After correct: 0x%x\n",
288 buf[ecc_byte]);
289 }
290 }
291 } else if (!(reg & XD_ECC2_ERROR) || !(reg & XD_ECC2_UNCORRECTABLE)) {
292 RTS51X_WRITE_REG(chip, CARD_STOP, XD_STOP | XD_CLR_ERR,
293 XD_STOP | XD_CLR_ERR);
294
295 retval = xd_read_data_from_ppb(chip, 256, buf, buf_len);
296 if (retval != STATUS_SUCCESS)
297 TRACE_RET(chip, retval);
298 if (reg & XD_ECC2_ERROR) {
299 u8 ecc_bit, ecc_byte;
300
301 RTS51X_READ_REG(chip, XD_ECC_BIT2, &ecc_bit);
302 RTS51X_READ_REG(chip, XD_ECC_BYTE2, &ecc_byte);
303
304 RTS51X_DEBUGP("ECC_BIT2 = 0x%x, ECC_BYTE2 = 0x%x\n",
305 ecc_bit, ecc_byte);
306 if (ecc_byte < buf_len) {
307 RTS51X_DEBUGP("Before correct: 0x%x\n",
308 buf[ecc_byte]);
309 buf[ecc_byte] ^= (1 << ecc_bit);
310 RTS51X_DEBUGP("After correct: 0x%x\n",
311 buf[ecc_byte]);
312 }
313 }
314 } else {
315 rts51x_clear_xd_error(chip);
316 TRACE_RET(chip, STATUS_FAIL);
317 }
318
319 return STATUS_SUCCESS;
320}
321
322static void xd_pull_ctl_disable(struct rts51x_chip *chip)
323{
324 if (CHECK_PKG(chip, LQFP48)) {
325 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x55);
326 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
327 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
328 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
329 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
330 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
331 } else {
332 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0x65);
333 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
334 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
335 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
336 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x56);
337 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
338 }
339}
340
341static void xd_pull_ctl_enable(struct rts51x_chip *chip)
342{
343 if (CHECK_PKG(chip, LQFP48)) {
344 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xAA);
345 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x55);
346 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
347 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
348 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
349 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0xA5);
350 } else {
351 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL1, 0xFF, 0xA5);
352 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL2, 0xFF, 0x59);
353 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL3, 0xFF, 0x95);
354 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL4, 0xFF, 0x55);
355 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL5, 0xFF, 0x55);
356 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PULL_CTL6, 0xFF, 0x59);
357 }
358}
359
360static int reset_xd(struct rts51x_chip *chip)
361{
362 struct xd_info *xd_card = &(chip->xd_card);
363 int retval, i, j;
364 u8 id_buf[4], redunt[11];
365
366 retval = rts51x_select_card(chip, XD_CARD);
367 if (retval != STATUS_SUCCESS)
368 TRACE_RET(chip, STATUS_FAIL);
369
370 rts51x_init_cmd(chip);
371
372 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS, 0xFF,
373 XD_PGSTS_NOT_FF);
374 if (chip->asic_code)
375 xd_pull_ctl_disable(chip);
376 else
377 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
378 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN3));
379
380 if (!chip->option.FT2_fast_mode) {
381 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_INIT, XD_NO_AUTO_PWR_OFF,
382 0);
383 if (CHECK_PKG(chip, LQFP48) ||
384 chip->option.rts5129_D3318_off_enable) {
385 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL,
386 DV3318_AUTO_PWR_OFF,
387 DV3318_AUTO_PWR_OFF);
388 }
389 }
390 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
391 if (!chip->option.FT2_fast_mode) {
392 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
393 POWER_OFF);
394 }
395
396 retval = rts51x_send_cmd(chip, MODE_C, 100);
397 if (retval != STATUS_SUCCESS)
398 TRACE_RET(chip, retval);
399 if (!chip->option.FT2_fast_mode) {
400#ifdef SD_XD_IO_FOLLOW_PWR
401 if (CHECK_PKG(chip, LQFP48)
402 || chip->option.rts5129_D3318_off_enable) {
403 rts51x_write_register(chip, CARD_PWR_CTL,
404 LDO_OFF, LDO_OFF);
405 }
406#endif
407
408 wait_timeout(250);
409
410#ifdef SD_XD_IO_FOLLOW_PWR
411 if (CHECK_PKG(chip, LQFP48)
412 || chip->option.rts5129_D3318_off_enable) {
413 rts51x_init_cmd(chip);
414 if (chip->asic_code) {
415 xd_pull_ctl_enable(chip);
416 } else {
417 rts51x_add_cmd(chip, WRITE_REG_CMD,
418 FPGA_PULL_CTL, 0xFF,
419 (FPGA_XD_PULL_CTL_EN1 &
420 FPGA_XD_PULL_CTL_EN2));
421 }
422 retval = rts51x_send_cmd(chip, MODE_C, 100);
423 if (retval != STATUS_SUCCESS)
424 TRACE_RET(chip, STATUS_FAIL);
425 }
426#endif
427
428 retval = rts51x_card_power_on(chip, XD_CARD);
429 if (retval != STATUS_SUCCESS)
430 TRACE_RET(chip, retval);
431#ifdef SUPPORT_OCP
432 wait_timeout(50);
433 rts51x_get_card_status(chip, &(chip->card_status));
434 chip->ocp_stat = (chip->card_status >> 4) & 0x03;
435
436 if (chip->ocp_stat & (MS_OCP_NOW | MS_OCP_EVER)) {
437 RTS51X_DEBUGP("Over current, OCPSTAT is 0x%x\n",
438 chip->ocp_stat);
439 TRACE_RET(chip, STATUS_FAIL);
440 }
441#endif
442 }
443
444 rts51x_init_cmd(chip);
445
446 if (chip->asic_code)
447 xd_pull_ctl_enable(chip);
448 else
449 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF,
450 (FPGA_XD_PULL_CTL_EN1 & FPGA_XD_PULL_CTL_EN2));
451 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN,
452 XD_OUTPUT_EN);
453 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CTL, XD_CE_DISEN, XD_CE_DISEN);
454
455 retval = rts51x_send_cmd(chip, MODE_C, 100);
456 if (retval != STATUS_SUCCESS)
457 TRACE_RET(chip, STATUS_FAIL);
458
459 if (!chip->option.FT2_fast_mode)
460 wait_timeout(200);
461
462 retval = xd_set_init_para(chip);
463 if (retval != STATUS_SUCCESS)
464 TRACE_RET(chip, STATUS_FAIL);
465
466 for (i = 0; i < 4; i++) {
467 u8 xd_dat, xd_ctl;
468
469 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST)
470 TRACE_RET(chip, STATUS_FAIL);
471
472 rts51x_init_cmd(chip);
473 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_DTCTL, 0xFF,
474 XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP *
475 (2 + i + chip->option.rts51x_xd_rw_step)
476 + XD_TIME_RWN_STEP * (i + chip->option.rts51x_xd_rwn_step));
477 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CATCTL, 0xFF,
478 XD_TIME_SETUP_STEP * 3 + XD_TIME_RW_STEP * (4 +
479 i) + XD_TIME_RWN_STEP * (3 + i));
480
481 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
482 XD_TRANSFER_START | XD_RESET);
483 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
484 XD_TRANSFER_END, XD_TRANSFER_END);
485
486 rts51x_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
487 rts51x_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
488
489 retval = rts51x_send_cmd(chip, MODE_CR, 100);
490 if (retval != STATUS_SUCCESS) {
491 rts51x_clear_xd_error(chip);
492 TRACE_RET(chip, retval);
493 }
494
495 retval = rts51x_get_rsp(chip, 3, 100);
496 if (retval != STATUS_SUCCESS) {
497 rts51x_clear_xd_error(chip);
498 TRACE_RET(chip, retval);
499 }
500
501 xd_dat = chip->rsp_buf[1];
502 xd_ctl = chip->rsp_buf[2];
503 RTS51X_DEBUGP("XD_DAT: 0x%x, XD_CTL: 0x%x\n", xd_dat, xd_ctl);
504
505 if (((xd_dat & READY_FLAG) != READY_STATE)
506 || !(xd_ctl & XD_RDY))
507 continue;
508
509 retval = xd_read_id(chip, READ_ID, id_buf, 4);
510 if (retval != STATUS_SUCCESS)
511 TRACE_RET(chip, retval);
512
513 RTS51X_DEBUGP("READ_ID: 0x%x 0x%x 0x%x 0x%x\n",
514 id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
515
516 xd_card->device_code = id_buf[1];
517
518 switch (xd_card->device_code) {
519 case XD_4M_X8_512_1:
520 case XD_4M_X8_512_2:
521 xd_card->block_shift = 4;
522 xd_card->page_off = 0x0F;
523 xd_card->addr_cycle = 3;
524 xd_card->zone_cnt = 1;
525 xd_card->capacity = 8000;
526 XD_SET_4MB(xd_card);
527 break;
528 case XD_8M_X8_512:
529 xd_card->block_shift = 4;
530 xd_card->page_off = 0x0F;
531 xd_card->addr_cycle = 3;
532 xd_card->zone_cnt = 1;
533 xd_card->capacity = 16000;
534 break;
535 case XD_16M_X8_512:
536 XD_PAGE_512(xd_card);
537 xd_card->addr_cycle = 3;
538 xd_card->zone_cnt = 1;
539 xd_card->capacity = 32000;
540 break;
541 case XD_32M_X8_512:
542 XD_PAGE_512(xd_card);
543 xd_card->addr_cycle = 3;
544 xd_card->zone_cnt = 2;
545 xd_card->capacity = 64000;
546 break;
547 case XD_64M_X8_512:
548 XD_PAGE_512(xd_card);
549 xd_card->addr_cycle = 4;
550 xd_card->zone_cnt = 4;
551 xd_card->capacity = 128000;
552 break;
553 case XD_128M_X8_512:
554 XD_PAGE_512(xd_card);
555 xd_card->addr_cycle = 4;
556 xd_card->zone_cnt = 8;
557 xd_card->capacity = 256000;
558 break;
559 case XD_256M_X8_512:
560 XD_PAGE_512(xd_card);
561 xd_card->addr_cycle = 4;
562 xd_card->zone_cnt = 16;
563 xd_card->capacity = 512000;
564 break;
565 case XD_512M_X8:
566 XD_PAGE_512(xd_card);
567 xd_card->addr_cycle = 4;
568 xd_card->zone_cnt = 32;
569 xd_card->capacity = 1024000;
570 break;
571 case xD_1G_X8_512:
572 XD_PAGE_512(xd_card);
573 xd_card->addr_cycle = 4;
574 xd_card->zone_cnt = 64;
575 xd_card->capacity = 2048000;
576 break;
577 case xD_2G_X8_512:
578 XD_PAGE_512(xd_card);
579 xd_card->addr_cycle = 4;
580 xd_card->zone_cnt = 128;
581 xd_card->capacity = 4096000;
582 break;
583 default:
584 continue;
585 }
586
587
588 for (j = 0; j < 10; j++) {
589 retval = xd_read_id(chip, READ_ID, id_buf, 4);
590 if (retval != STATUS_SUCCESS)
591 TRACE_RET(chip, retval);
592
593 if (id_buf[1] != xd_card->device_code)
594 break;
595 }
596
597
598 if (j == 10)
599 break;
600 }
601
602 if (i == 4) {
603 xd_card->block_shift = 0;
604 xd_card->page_off = 0;
605 xd_card->addr_cycle = 0;
606 xd_card->capacity = 0;
607
608 TRACE_RET(chip, STATUS_FAIL);
609 }
610
611 retval = xd_read_id(chip, READ_xD_ID, id_buf, 4);
612 if (retval != STATUS_SUCCESS)
613 TRACE_RET(chip, retval);
614 RTS51X_DEBUGP("READ_xD_ID: 0x%x 0x%x 0x%x 0x%x\n",
615 id_buf[0], id_buf[1], id_buf[2], id_buf[3]);
616 if (id_buf[2] != XD_ID_CODE)
617 TRACE_RET(chip, STATUS_FAIL);
618
619
620 for (i = 0; i < 24; i++) {
621 u32 page_addr;
622
623 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST)
624 TRACE_RET(chip, STATUS_FAIL);
625
626 page_addr = (u32) i << xd_card->block_shift;
627
628 for (j = 0; j < 3; j++) {
629 retval = xd_read_redundant(chip, page_addr, redunt, 11);
630 if (retval == STATUS_SUCCESS)
631 break;
632 }
633 if (j == 3)
634 continue;
635
636 if (redunt[BLOCK_STATUS] != XD_GBLK)
637 continue;
638
639 j = 0;
640
641 if (redunt[PAGE_STATUS] != XD_GPG) {
642 for (j = 1; j <= 8; j++) {
643 retval =
644 xd_read_redundant(chip, page_addr + j,
645 redunt, 11);
646 if (retval == STATUS_SUCCESS) {
647 if (redunt[PAGE_STATUS] == XD_GPG)
648 break;
649 }
650 }
651
652 if (j == 9)
653 break;
654 }
655
656 if ((redunt[BLOCK_STATUS] == XD_GBLK)
657 && (redunt[PARITY] & XD_BA1_ALL0)) {
658 u8 buf[10];
659
660 page_addr += j;
661
662 retval = xd_read_cis(chip, page_addr, buf, 10);
663 if (retval != STATUS_SUCCESS)
664 TRACE_RET(chip, retval);
665
666 if ((buf[0] == 0x01) && (buf[1] == 0x03)
667 && (buf[2] == 0xD9)
668 && (buf[3] == 0x01) && (buf[4] == 0xFF)
669 && (buf[5] == 0x18) && (buf[6] == 0x02)
670 && (buf[7] == 0xDF) && (buf[8] == 0x01)
671 && (buf[9] == 0x20)) {
672 xd_card->cis_block = (u16) i;
673 }
674 }
675
676 break;
677 }
678
679 RTS51X_DEBUGP("CIS block: 0x%x\n", xd_card->cis_block);
680 if (xd_card->cis_block == 0xFFFF)
681 TRACE_RET(chip, STATUS_FAIL);
682
683 chip->capacity[chip->card2lun[XD_CARD]] = xd_card->capacity;
684
685 return STATUS_SUCCESS;
686}
687
688static int xd_check_data_blank(u8 *redunt)
689{
690 int i;
691
692 for (i = 0; i < 6; i++) {
693 if (redunt[PAGE_STATUS + i] != 0xFF)
694 return 0;
695 }
696
697 if ((redunt[PARITY] & (XD_ECC1_ALL1 | XD_ECC2_ALL1)) !=
698 (XD_ECC1_ALL1 | XD_ECC2_ALL1))
699 return 0;
700
701 for (i = 0; i < 4; i++) {
702 if (redunt[RESERVED0 + i] != 0xFF)
703 return 0;
704 }
705
706 return 1;
707}
708
709static u16 xd_load_log_block_addr(u8 *redunt)
710{
711 u16 addr = 0xFFFF;
712
713 if (redunt[PARITY] & XD_BA1_BA2_EQL)
714 addr =
715 ((u16) redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
716 else if (redunt[PARITY] & XD_BA1_VALID)
717 addr =
718 ((u16) redunt[BLOCK_ADDR1_H] << 8) | redunt[BLOCK_ADDR1_L];
719 else if (redunt[PARITY] & XD_BA2_VALID)
720 addr =
721 ((u16) redunt[BLOCK_ADDR2_H] << 8) | redunt[BLOCK_ADDR2_L];
722
723 return addr;
724}
725
726static int xd_init_l2p_tbl(struct rts51x_chip *chip)
727{
728 struct xd_info *xd_card = &(chip->xd_card);
729 int size, i;
730
731 RTS51X_DEBUGP("xd_init_l2p_tbl: zone_cnt = %d\n", xd_card->zone_cnt);
732
733 if (xd_card->zone_cnt < 1)
734 TRACE_RET(chip, STATUS_FAIL);
735
736 size = xd_card->zone_cnt * sizeof(struct zone_entry);
737 RTS51X_DEBUGP("Buffer size for l2p table is %d\n", size);
738
739 xd_card->zone = vmalloc(size);
740 if (!xd_card->zone)
741 TRACE_RET(chip, STATUS_NOMEM);
742
743 for (i = 0; i < xd_card->zone_cnt; i++) {
744 xd_card->zone[i].build_flag = 0;
745 xd_card->zone[i].l2p_table = NULL;
746 xd_card->zone[i].free_table = NULL;
747 xd_card->zone[i].get_index = 0;
748 xd_card->zone[i].set_index = 0;
749 xd_card->zone[i].unused_blk_cnt = 0;
750 }
751
752 return STATUS_SUCCESS;
753}
754
755static inline void free_zone(struct zone_entry *zone)
756{
757 RTS51X_DEBUGP("free_zone\n");
758 if (!zone)
759 return;
760 zone->build_flag = 0;
761 zone->set_index = 0;
762 zone->get_index = 0;
763 zone->unused_blk_cnt = 0;
764 if (zone->l2p_table) {
765 vfree(zone->l2p_table);
766 zone->l2p_table = NULL;
767 }
768 if (zone->free_table) {
769 vfree(zone->free_table);
770 zone->free_table = NULL;
771 }
772}
773
774static void xd_set_unused_block(struct rts51x_chip *chip, u32 phy_blk)
775{
776 struct xd_info *xd_card = &(chip->xd_card);
777 struct zone_entry *zone;
778 int zone_no;
779
780 zone_no = (int)phy_blk >> 10;
781 if (zone_no >= xd_card->zone_cnt) {
782 RTS51X_DEBUGP("Set unused block to invalid zone"
783 "(zone_no = %d, zone_cnt = %d)\n",
784 zone_no, xd_card->zone_cnt);
785 return;
786 }
787 zone = &(xd_card->zone[zone_no]);
788
789 if (zone->free_table == NULL) {
790 if (xd_build_l2p_tbl(chip, zone_no) != STATUS_SUCCESS)
791 return;
792 }
793
794 if ((zone->set_index >= XD_FREE_TABLE_CNT)
795 || (zone->set_index < 0)) {
796 free_zone(zone);
797 RTS51X_DEBUGP("Set unused block fail, invalid set_index\n");
798 return;
799 }
800
801 RTS51X_DEBUGP("Set unused block to index %d\n", zone->set_index);
802
803 zone->free_table[zone->set_index++] = (u16) (phy_blk & 0x3ff);
804 if (zone->set_index >= XD_FREE_TABLE_CNT)
805 zone->set_index = 0;
806 zone->unused_blk_cnt++;
807}
808
809static u32 xd_get_unused_block(struct rts51x_chip *chip, int zone_no)
810{
811 struct xd_info *xd_card = &(chip->xd_card);
812 struct zone_entry *zone;
813 u32 phy_blk;
814
815 if (zone_no >= xd_card->zone_cnt) {
816 RTS51X_DEBUGP("Get unused block from invalid zone"
817 "(zone_no = %d, zone_cnt = %d)\n",
818 zone_no, xd_card->zone_cnt);
819 TRACE_RET(chip, BLK_NOT_FOUND);
820 }
821 zone = &(xd_card->zone[zone_no]);
822
823 if ((zone->unused_blk_cnt == 0) ||
824 (zone->set_index == zone->get_index)) {
825 free_zone(zone);
826 RTS51X_DEBUGP("Get unused block fail,"
827 "no unused block available\n");
828 TRACE_RET(chip, BLK_NOT_FOUND);
829 }
830 if ((zone->get_index >= XD_FREE_TABLE_CNT) || (zone->get_index < 0)) {
831 free_zone(zone);
832 RTS51X_DEBUGP("Get unused block fail, invalid get_index\n");
833 TRACE_RET(chip, BLK_NOT_FOUND);
834 }
835
836 RTS51X_DEBUGP("Get unused block from index %d\n", zone->get_index);
837
838 phy_blk = zone->free_table[zone->get_index];
839 zone->free_table[zone->get_index++] = 0xFFFF;
840 if (zone->get_index >= XD_FREE_TABLE_CNT)
841 zone->get_index = 0;
842 zone->unused_blk_cnt--;
843
844 phy_blk += ((u32) (zone_no) << 10);
845 return phy_blk;
846}
847
848static void xd_set_l2p_tbl(struct rts51x_chip *chip, int zone_no, u16 log_off,
849 u16 phy_off)
850{
851 struct xd_info *xd_card = &(chip->xd_card);
852 struct zone_entry *zone;
853
854 zone = &(xd_card->zone[zone_no]);
855 zone->l2p_table[log_off] = phy_off;
856}
857
858static int xd_delay_write(struct rts51x_chip *chip);
859
860static u32 xd_get_l2p_tbl(struct rts51x_chip *chip, int zone_no, u16 log_off)
861{
862 struct xd_info *xd_card = &(chip->xd_card);
863 struct zone_entry *zone;
864 int retval;
865
866 zone = &(xd_card->zone[zone_no]);
867 if (zone->l2p_table[log_off] == 0xFFFF) {
868 u32 phy_blk = 0;
869 int i;
870
871 retval = xd_delay_write(chip);
872 if (retval != STATUS_SUCCESS) {
873 RTS51X_DEBUGP("In xd_get_l2p_tbl,"
874 "delay write fail!\n");
875 TRACE_RET(chip, BLK_NOT_FOUND);
876 }
877
878 if (zone->unused_blk_cnt <= 0) {
879 RTS51X_DEBUGP("No unused block!\n");
880 TRACE_RET(chip, BLK_NOT_FOUND);
881 }
882
883 for (i = 0; i < zone->unused_blk_cnt; i++) {
884 phy_blk = xd_get_unused_block(chip, zone_no);
885 if (phy_blk == BLK_NOT_FOUND) {
886 RTS51X_DEBUGP("No unused block available!\n");
887 TRACE_RET(chip, BLK_NOT_FOUND);
888 }
889
890 retval =
891 xd_init_page(chip, phy_blk, log_off, 0,
892 xd_card->page_off + 1);
893 if (retval == STATUS_SUCCESS)
894 break;
895 }
896 if (i >= zone->unused_blk_cnt) {
897 RTS51X_DEBUGP("No good unused block available!\n");
898 TRACE_RET(chip, BLK_NOT_FOUND);
899 }
900
901 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (phy_blk & 0x3FF));
902 return phy_blk;
903 }
904
905 return (u32) zone->l2p_table[log_off] + ((u32) (zone_no) << 10);
906}
907
908int rts51x_reset_xd_card(struct rts51x_chip *chip)
909{
910 struct xd_info *xd_card = &(chip->xd_card);
911 int retval;
912
913 memset(xd_card, 0, sizeof(struct xd_info));
914
915 xd_card->block_shift = 0;
916 xd_card->page_off = 0;
917 xd_card->addr_cycle = 0;
918 xd_card->capacity = 0;
919 xd_card->zone_cnt = 0;
920 xd_card->cis_block = 0xFFFF;
921 xd_card->delay_write.delay_write_flag = 0;
922
923 rts51x_enable_card_clock(chip, XD_CARD);
924
925 retval = reset_xd(chip);
926 if (retval != STATUS_SUCCESS) {
927 if (chip->option.reset_or_rw_fail_set_pad_drive) {
928 rts51x_write_register(chip, CARD_DRIVE_SEL,
929 SD20_DRIVE_MASK, DRIVE_8mA);
930 }
931 TRACE_RET(chip, retval);
932 }
933
934 retval = xd_init_l2p_tbl(chip);
935 if (retval != STATUS_SUCCESS)
936 TRACE_RET(chip, retval);
937
938 return STATUS_SUCCESS;
939}
940
941static int xd_mark_bad_block(struct rts51x_chip *chip, u32 phy_blk)
942{
943 struct xd_info *xd_card = &(chip->xd_card);
944 int retval;
945 u32 page_addr;
946 u8 reg = 0;
947
948 RTS51X_DEBUGP("mark block 0x%x as bad block\n", phy_blk);
949
950 if (phy_blk == BLK_NOT_FOUND)
951 TRACE_RET(chip, STATUS_FAIL);
952
953 rts51x_init_cmd(chip);
954
955 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
956 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF,
957 XD_LATER_BBLK);
958 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF, 0xFF);
959 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF, 0xFF);
960 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_H, 0xFF, 0xFF);
961 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR2_L, 0xFF, 0xFF);
962 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED0, 0xFF, 0xFF);
963 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED1, 0xFF, 0xFF);
964 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED2, 0xFF, 0xFF);
965 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_RESERVED3, 0xFF, 0xFF);
966
967 page_addr = phy_blk << xd_card->block_shift;
968
969 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
970
971
972 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
973 xd_card->page_off + 1);
974
975 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
976 XD_TRANSFER_START | XD_WRITE_REDUNDANT);
977 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
978 XD_TRANSFER_END);
979
980 retval = rts51x_send_cmd(chip, MODE_CR, 100);
981 if (retval != STATUS_SUCCESS)
982 TRACE_RET(chip, STATUS_FAIL);
983
984 retval = rts51x_get_rsp(chip, 1, 100);
985
986 if (retval != STATUS_SUCCESS) {
987 rts51x_clear_xd_error(chip);
988 rts51x_ep0_read_register(chip, XD_DAT, ®);
989 if (reg & PROGRAM_ERROR)
990 xd_set_err_code(chip, XD_PRG_ERROR);
991 else
992 xd_set_err_code(chip, XD_TO_ERROR);
993 TRACE_RET(chip, STATUS_FAIL);
994 }
995
996 return STATUS_SUCCESS;
997}
998
999static int xd_init_page(struct rts51x_chip *chip, u32 phy_blk, u16 logoff,
1000 u8 start_page, u8 end_page)
1001{
1002 struct xd_info *xd_card = &(chip->xd_card);
1003 int retval;
1004 u32 page_addr;
1005 u8 reg = 0;
1006
1007 RTS51X_DEBUGP("Init block 0x%x\n", phy_blk);
1008
1009 if (start_page > end_page)
1010 TRACE_RET(chip, STATUS_FAIL);
1011 if (phy_blk == BLK_NOT_FOUND)
1012 TRACE_RET(chip, STATUS_FAIL);
1013
1014 rts51x_init_cmd(chip);
1015
1016 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, 0xFF);
1017 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, 0xFF);
1018 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF,
1019 (u8) (logoff >> 8));
1020 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF,
1021 (u8) logoff);
1022
1023 page_addr = (phy_blk << xd_card->block_shift) + start_page;
1024
1025 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1026
1027 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1028 XD_BA_TRANSFORM);
1029
1030 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF,
1031 (end_page - start_page));
1032
1033 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1034 XD_TRANSFER_START | XD_WRITE_REDUNDANT);
1035 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1036 XD_TRANSFER_END);
1037
1038 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1039 if (retval != STATUS_SUCCESS)
1040 TRACE_RET(chip, STATUS_FAIL);
1041
1042 retval = rts51x_get_rsp(chip, 1, 500);
1043
1044 if (retval != STATUS_SUCCESS) {
1045 rts51x_clear_xd_error(chip);
1046 rts51x_ep0_read_register(chip, XD_DAT, ®);
1047 if (reg & PROGRAM_ERROR) {
1048 xd_mark_bad_block(chip, phy_blk);
1049 xd_set_err_code(chip, XD_PRG_ERROR);
1050 } else {
1051 xd_set_err_code(chip, XD_TO_ERROR);
1052 }
1053 TRACE_RET(chip, STATUS_FAIL);
1054 }
1055
1056 return STATUS_SUCCESS;
1057}
1058
1059static int xd_copy_page(struct rts51x_chip *chip,
1060 u32 old_blk, u32 new_blk, u8 start_page, u8 end_page)
1061{
1062 struct xd_info *xd_card = &(chip->xd_card);
1063 u32 old_page, new_page;
1064 u8 i, reg = 0;
1065 int retval;
1066
1067 RTS51X_DEBUGP("Copy page from block 0x%x to block 0x%x\n", old_blk,
1068 new_blk);
1069
1070 if (start_page > end_page)
1071 TRACE_RET(chip, STATUS_FAIL);
1072
1073 if ((old_blk == BLK_NOT_FOUND) || (new_blk == BLK_NOT_FOUND))
1074 TRACE_RET(chip, STATUS_FAIL);
1075
1076 old_page = (old_blk << xd_card->block_shift) + start_page;
1077 new_page = (new_blk << xd_card->block_shift) + start_page;
1078
1079 XD_CLR_BAD_NEWBLK(xd_card);
1080
1081 RTS51X_WRITE_REG(chip, CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER);
1082
1083 for (i = start_page; i < end_page; i++) {
1084 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1085 RTS51X_WRITE_REG(chip, CARD_STOP, XD_STOP | XD_CLR_ERR,
1086 XD_STOP | XD_CLR_ERR);
1087 xd_set_err_code(chip, XD_NO_CARD);
1088 TRACE_RET(chip, STATUS_FAIL);
1089 }
1090
1091 rts51x_init_cmd(chip);
1092
1093 xd_assign_phy_addr(chip, old_page, XD_RW_ADDR);
1094
1095
1096 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1097 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1098 XD_AUTO_CHK_DATA_STATUS, 0);
1099 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1100 XD_TRANSFER_START | XD_READ_PAGES);
1101 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1102 XD_TRANSFER_END, XD_TRANSFER_END);
1103
1104 retval = rts51x_send_cmd(chip, MODE_CR | STAGE_XD_STATUS, 100);
1105 if (retval != STATUS_SUCCESS)
1106 TRACE_RET(chip, retval);
1107
1108 retval = rts51x_get_rsp(chip, 4, 500);
1109 if ((retval != STATUS_SUCCESS) ||
1110 (chip->rsp_buf[2] & (XD_ECC1_ERROR | XD_ECC2_ERROR))) {
1111 rts51x_clear_xd_error(chip);
1112 reg = 0;
1113 rts51x_ep0_read_register(chip, XD_CTL, ®);
1114 if (reg & (XD_ECC1_ERROR | XD_ECC2_ERROR)) {
1115 wait_timeout(100);
1116
1117 if (monitor_card_cd(chip, XD_CARD) ==
1118 CD_NOT_EXIST) {
1119 xd_set_err_code(chip, XD_NO_CARD);
1120 TRACE_RET(chip, STATUS_FAIL);
1121 }
1122
1123 if (((reg &
1124 (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1125 == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1126 || ((reg & (XD_ECC2_ERROR |
1127 XD_ECC2_UNCORRECTABLE)) ==
1128 (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1129 RTS51X_WRITE_REG(chip, XD_PAGE_STATUS,
1130 0xFF, XD_BPG);
1131 RTS51X_WRITE_REG(chip, XD_BLOCK_STATUS,
1132 0xFF, XD_GBLK);
1133 XD_SET_BAD_OLDBLK(xd_card);
1134 RTS51X_DEBUGP("old block 0x%x"
1135 "ecc error\n", old_blk);
1136 }
1137 } else {
1138 xd_set_err_code(chip, XD_TO_ERROR);
1139 TRACE_RET(chip, STATUS_FAIL);
1140 }
1141 }
1142 if (XD_CHK_BAD_OLDBLK(xd_card))
1143 rts51x_clear_xd_error(chip);
1144
1145 rts51x_init_cmd(chip);
1146
1147 xd_assign_phy_addr(chip, new_page, XD_RW_ADDR);
1148 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, 1);
1149 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1150 XD_TRANSFER_START | XD_WRITE_PAGES);
1151 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1152 XD_TRANSFER_END, XD_TRANSFER_END);
1153
1154 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1155 if (retval != STATUS_SUCCESS)
1156 TRACE_RET(chip, retval);
1157
1158 retval = rts51x_get_rsp(chip, 1, 300);
1159 if (retval != STATUS_SUCCESS) {
1160 rts51x_clear_xd_error(chip);
1161 reg = 0;
1162 rts51x_ep0_read_register(chip, XD_DAT, ®);
1163 if (reg & PROGRAM_ERROR) {
1164 xd_mark_bad_block(chip, new_blk);
1165 xd_set_err_code(chip, XD_PRG_ERROR);
1166 XD_SET_BAD_NEWBLK(xd_card);
1167 } else {
1168 xd_set_err_code(chip, XD_TO_ERROR);
1169 }
1170 TRACE_RET(chip, retval);
1171 }
1172
1173 old_page++;
1174 new_page++;
1175 }
1176
1177 return STATUS_SUCCESS;
1178}
1179
1180static int xd_reset_cmd(struct rts51x_chip *chip)
1181{
1182 int retval;
1183 u8 xd_dat, xd_ctl;
1184
1185 rts51x_init_cmd(chip);
1186
1187 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1188 XD_TRANSFER_START | XD_RESET);
1189 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1190 XD_TRANSFER_END);
1191 rts51x_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1192 rts51x_add_cmd(chip, READ_REG_CMD, XD_CTL, 0, 0);
1193
1194 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1195 if (retval != STATUS_SUCCESS)
1196 TRACE_RET(chip, retval);
1197
1198 retval = rts51x_get_rsp(chip, 3, 100);
1199 if (retval != STATUS_SUCCESS) {
1200 rts51x_clear_xd_error(chip);
1201 TRACE_RET(chip, retval);
1202 }
1203
1204 xd_dat = chip->rsp_buf[1];
1205 xd_ctl = chip->rsp_buf[2];
1206 if (((xd_dat & READY_FLAG) == READY_STATE) && (xd_ctl & XD_RDY))
1207 return STATUS_SUCCESS;
1208
1209 TRACE_RET(chip, STATUS_FAIL);
1210}
1211
1212static int xd_erase_block(struct rts51x_chip *chip, u32 phy_blk)
1213{
1214 struct xd_info *xd_card = &(chip->xd_card);
1215 u32 page_addr;
1216 u8 reg = 0, xd_dat;
1217 int i, retval;
1218
1219 if (phy_blk == BLK_NOT_FOUND)
1220 TRACE_RET(chip, STATUS_FAIL);
1221
1222 page_addr = phy_blk << xd_card->block_shift;
1223
1224 for (i = 0; i < 3; i++) {
1225 rts51x_init_cmd(chip);
1226
1227 xd_assign_phy_addr(chip, page_addr, XD_ERASE_ADDR);
1228
1229 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1230 XD_TRANSFER_START | XD_ERASE);
1231 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1232 XD_TRANSFER_END, XD_TRANSFER_END);
1233 rts51x_add_cmd(chip, READ_REG_CMD, XD_DAT, 0, 0);
1234
1235 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1236 if (retval != STATUS_SUCCESS)
1237 TRACE_RET(chip, retval);
1238
1239 retval = rts51x_get_rsp(chip, 2, 300);
1240 if (retval != STATUS_SUCCESS) {
1241 rts51x_clear_xd_error(chip);
1242 rts51x_ep0_read_register(chip, XD_DAT, ®);
1243 if (reg & PROGRAM_ERROR) {
1244 xd_mark_bad_block(chip, phy_blk);
1245 xd_set_err_code(chip, XD_PRG_ERROR);
1246 TRACE_RET(chip, STATUS_FAIL);
1247 } else {
1248 xd_set_err_code(chip, XD_ERASE_FAIL);
1249 }
1250 retval = xd_reset_cmd(chip);
1251 if (retval != STATUS_SUCCESS)
1252 TRACE_RET(chip, retval);
1253 continue;
1254 }
1255 xd_dat = chip->rsp_buf[1];
1256 if (xd_dat & PROGRAM_ERROR) {
1257 xd_mark_bad_block(chip, phy_blk);
1258 xd_set_err_code(chip, XD_PRG_ERROR);
1259 TRACE_RET(chip, STATUS_FAIL);
1260 }
1261
1262 return STATUS_SUCCESS;
1263 }
1264
1265 xd_mark_bad_block(chip, phy_blk);
1266 xd_set_err_code(chip, XD_ERASE_FAIL);
1267 TRACE_RET(chip, STATUS_FAIL);
1268}
1269
1270static int xd_build_l2p_tbl(struct rts51x_chip *chip, int zone_no)
1271{
1272 struct xd_info *xd_card = &(chip->xd_card);
1273 struct zone_entry *zone;
1274 int retval;
1275 u32 start, end, i;
1276 u16 max_logoff, cur_fst_page_logoff, cur_lst_page_logoff,
1277 ent_lst_page_logoff;
1278 u8 redunt[11];
1279
1280 RTS51X_DEBUGP("xd_build_l2p_tbl: %d\n", zone_no);
1281
1282 if (xd_card->zone == NULL) {
1283 retval = xd_init_l2p_tbl(chip);
1284 if (retval != STATUS_SUCCESS)
1285 TRACE_RET(chip, retval);
1286 }
1287
1288 if (xd_card->zone[zone_no].build_flag) {
1289 RTS51X_DEBUGP("l2p table of zone %d has been built\n",
1290 zone_no);
1291 return STATUS_SUCCESS;
1292 }
1293
1294 zone = &(xd_card->zone[zone_no]);
1295
1296 if (zone->l2p_table == NULL) {
1297 zone->l2p_table = vmalloc(2000);
1298 if (zone->l2p_table == NULL)
1299 TRACE_GOTO(chip, Build_Fail);
1300 }
1301 memset((u8 *) (zone->l2p_table), 0xff, 2000);
1302
1303 if (zone->free_table == NULL) {
1304 zone->free_table = vmalloc(XD_FREE_TABLE_CNT * 2);
1305 if (zone->free_table == NULL)
1306 TRACE_GOTO(chip, Build_Fail);
1307 }
1308 memset((u8 *) (zone->free_table), 0xff, XD_FREE_TABLE_CNT * 2);
1309
1310 if (zone_no == 0) {
1311 if (xd_card->cis_block == 0xFFFF)
1312 start = 0;
1313 else
1314 start = xd_card->cis_block + 1;
1315 if (XD_CHK_4MB(xd_card)) {
1316 end = 0x200;
1317 max_logoff = 499;
1318 } else {
1319 end = 0x400;
1320 max_logoff = 999;
1321 }
1322 } else {
1323 start = (u32) (zone_no) << 10;
1324 end = (u32) (zone_no + 1) << 10;
1325 max_logoff = 999;
1326 }
1327
1328 RTS51X_DEBUGP("start block 0x%x, end block 0x%x\n", start, end);
1329
1330 zone->set_index = zone->get_index = 0;
1331 zone->unused_blk_cnt = 0;
1332
1333 for (i = start; i < end; i++) {
1334 u32 page_addr = i << xd_card->block_shift;
1335 u32 phy_block;
1336
1337 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1338 if (retval != STATUS_SUCCESS)
1339 continue;
1340
1341 if (redunt[BLOCK_STATUS] != 0xFF) {
1342 RTS51X_DEBUGP("bad block\n");
1343 continue;
1344 }
1345
1346 if (xd_check_data_blank(redunt)) {
1347 RTS51X_DEBUGP("blank block\n");
1348 xd_set_unused_block(chip, i);
1349 continue;
1350 }
1351
1352 cur_fst_page_logoff = xd_load_log_block_addr(redunt);
1353 if ((cur_fst_page_logoff == 0xFFFF)
1354 || (cur_fst_page_logoff > max_logoff)) {
1355 retval = xd_erase_block(chip, i);
1356 if (retval == STATUS_SUCCESS)
1357 xd_set_unused_block(chip, i);
1358 continue;
1359 }
1360 if ((zone_no == 0) && (cur_fst_page_logoff == 0)
1361 && (redunt[PAGE_STATUS] != XD_GPG))
1362 XD_SET_MBR_FAIL(xd_card);
1363
1364 if (zone->l2p_table[cur_fst_page_logoff] == 0xFFFF) {
1365 zone->l2p_table[cur_fst_page_logoff] =
1366 (u16) (i & 0x3FF);
1367 continue;
1368 }
1369
1370 phy_block =
1371 zone->l2p_table[cur_fst_page_logoff] +
1372 ((u32) ((zone_no) << 10));
1373
1374 page_addr = ((i + 1) << xd_card->block_shift) - 1;
1375
1376 retval = xd_read_redundant(chip, page_addr, redunt, 11);
1377 if (retval != STATUS_SUCCESS)
1378 continue;
1379
1380 cur_lst_page_logoff = xd_load_log_block_addr(redunt);
1381 if (cur_lst_page_logoff == cur_fst_page_logoff) {
1382 int m;
1383
1384 page_addr =
1385 ((phy_block + 1) << xd_card->block_shift) - 1;
1386
1387 for (m = 0; m < 3; m++) {
1388 retval =
1389 xd_read_redundant(chip, page_addr, redunt,
1390 11);
1391 if (retval == STATUS_SUCCESS)
1392 break;
1393 }
1394
1395 if (m == 3) {
1396 zone->l2p_table[cur_fst_page_logoff] =
1397 (u16) (i & 0x3FF);
1398 retval = xd_erase_block(chip, phy_block);
1399 if (retval == STATUS_SUCCESS)
1400 xd_set_unused_block(chip, phy_block);
1401 continue;
1402 }
1403
1404 ent_lst_page_logoff = xd_load_log_block_addr(redunt);
1405 if (ent_lst_page_logoff != cur_fst_page_logoff) {
1406 zone->l2p_table[cur_fst_page_logoff] =
1407 (u16) (i & 0x3FF);
1408 retval = xd_erase_block(chip, phy_block);
1409 if (retval == STATUS_SUCCESS)
1410 xd_set_unused_block(chip, phy_block);
1411 continue;
1412 } else {
1413 retval = xd_erase_block(chip, i);
1414 if (retval == STATUS_SUCCESS)
1415 xd_set_unused_block(chip, i);
1416 }
1417 } else {
1418 retval = xd_erase_block(chip, i);
1419 if (retval == STATUS_SUCCESS)
1420 xd_set_unused_block(chip, i);
1421 }
1422 }
1423
1424 if (XD_CHK_4MB(xd_card))
1425 end = 500;
1426 else
1427 end = 1000;
1428
1429 i = 0;
1430 for (start = 0; start < end; start++) {
1431 if (zone->l2p_table[start] == 0xFFFF)
1432 i++;
1433 }
1434
1435 RTS51X_DEBUGP("Block count %d, invalid L2P entry %d\n", end, i);
1436 RTS51X_DEBUGP("Total unused block: %d\n", zone->unused_blk_cnt);
1437
1438 if ((zone->unused_blk_cnt - i) < 1)
1439 chip->card_wp |= XD_CARD;
1440
1441 zone->build_flag = 1;
1442
1443 return STATUS_SUCCESS;
1444
1445Build_Fail:
1446 if (zone->l2p_table) {
1447 vfree(zone->l2p_table);
1448 zone->l2p_table = NULL;
1449 }
1450 if (zone->free_table) {
1451 vfree(zone->free_table);
1452 zone->free_table = NULL;
1453 }
1454
1455 return STATUS_FAIL;
1456}
1457
1458static int xd_send_cmd(struct rts51x_chip *chip, u8 cmd)
1459{
1460 int retval;
1461
1462 rts51x_init_cmd(chip);
1463
1464 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_DAT, 0xFF, cmd);
1465 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1466 XD_TRANSFER_START | XD_SET_CMD);
1467 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1468 XD_TRANSFER_END);
1469
1470 retval = rts51x_send_cmd(chip, MODE_CR, 100);
1471 if (retval != STATUS_SUCCESS)
1472 TRACE_RET(chip, retval);
1473
1474 retval = rts51x_get_rsp(chip, 1, 200);
1475 if (retval != STATUS_SUCCESS) {
1476 rts51x_clear_xd_error(chip);
1477 TRACE_RET(chip, retval);
1478 }
1479
1480 return STATUS_SUCCESS;
1481}
1482
1483static int xd_read_multiple_pages(struct rts51x_chip *chip, u32 phy_blk,
1484 u32 log_blk, u8 start_page, u8 end_page,
1485 u8 *buf, void **ptr, unsigned int *offset)
1486{
1487 struct xd_info *xd_card = &(chip->xd_card);
1488 u32 page_addr, new_blk;
1489 u16 log_off;
1490 u8 reg_val, page_cnt;
1491 int zone_no, retval, i;
1492
1493 if (start_page > end_page)
1494 TRACE_RET(chip, STATUS_FAIL);
1495
1496 page_cnt = end_page - start_page;
1497 zone_no = (int)(log_blk / 1000);
1498 log_off = (u16) (log_blk % 1000);
1499
1500 if ((phy_blk & 0x3FF) == 0x3FF) {
1501 for (i = 0; i < 256; i++) {
1502 page_addr = ((u32) i) << xd_card->block_shift;
1503
1504 retval = xd_read_redundant(chip, page_addr, NULL, 0);
1505 if (retval == STATUS_SUCCESS)
1506 break;
1507
1508 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1509 xd_set_err_code(chip, XD_NO_CARD);
1510 TRACE_RET(chip, STATUS_FAIL);
1511 }
1512 }
1513 }
1514
1515 page_addr = (phy_blk << xd_card->block_shift) + start_page;
1516
1517 rts51x_init_cmd(chip);
1518
1519 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1520
1521 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_PPB_TO_SIE,
1522 XD_PPB_TO_SIE);
1523 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
1524 RING_BUFFER);
1525 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1526 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CHK_DATA_STATUS,
1527 XD_AUTO_CHK_DATA_STATUS, XD_AUTO_CHK_DATA_STATUS);
1528
1529 rts51x_trans_dma_enable(chip->srb->sc_data_direction, chip, page_cnt * 512,
1530 DMA_512);
1531
1532 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1533 XD_TRANSFER_START | XD_READ_PAGES);
1534 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER,
1535 XD_TRANSFER_END | XD_PPB_EMPTY,
1536 XD_TRANSFER_END | XD_PPB_EMPTY);
1537
1538 retval = rts51x_send_cmd(chip, MODE_CDIR, 100);
1539 if (retval != STATUS_SUCCESS)
1540 TRACE_RET(chip, retval);
1541
1542 retval =
1543 rts51x_transfer_data_partial(chip, RCV_BULK_PIPE(chip), (void *)buf,
1544 ptr, offset, page_cnt * 512,
1545 scsi_sg_count(chip->srb), NULL, 2000);
1546 if (retval != STATUS_SUCCESS) {
1547 rts51x_clear_xd_error(chip);
1548
1549 if (retval == STATUS_TIMEDOUT) {
1550 xd_set_err_code(chip, XD_TO_ERROR);
1551 TRACE_RET(chip, retval);
1552 } else {
1553 TRACE_GOTO(chip, Fail);
1554 }
1555 }
1556 retval = rts51x_get_rsp(chip, 1, 200);
1557 if (retval != STATUS_SUCCESS) {
1558 rts51x_clear_xd_error(chip);
1559
1560 if (retval == STATUS_TIMEDOUT) {
1561 xd_set_err_code(chip, XD_TO_ERROR);
1562 TRACE_RET(chip, retval);
1563 } else {
1564 TRACE_GOTO(chip, Fail);
1565 }
1566 }
1567
1568 return STATUS_SUCCESS;
1569
1570Fail:
1571 rts51x_ep0_read_register(chip, XD_PAGE_STATUS, ®_val);
1572 RTS51X_DEBUGP("XD_PAGE_STATUS: 0x%x\n", reg_val);
1573
1574 if (reg_val != XD_GPG)
1575 xd_set_err_code(chip, XD_PRG_ERROR);
1576
1577 rts51x_ep0_read_register(chip, XD_CTL, ®_val);
1578 RTS51X_DEBUGP("XD_CTL: 0x%x\n", reg_val);
1579
1580
1581 if (((reg_val & (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1582 == (XD_ECC1_ERROR | XD_ECC1_UNCORRECTABLE))
1583 || ((reg_val & (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))
1584 == (XD_ECC2_ERROR | XD_ECC2_UNCORRECTABLE))) {
1585 wait_timeout(100);
1586
1587 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1588 xd_set_err_code(chip, XD_NO_CARD);
1589 TRACE_RET(chip, STATUS_FAIL);
1590 }
1591
1592 xd_set_err_code(chip, XD_ECC_ERROR);
1593
1594 new_blk = xd_get_unused_block(chip, zone_no);
1595 if (new_blk == NO_NEW_BLK) {
1596 XD_CLR_BAD_OLDBLK(xd_card);
1597 TRACE_RET(chip, STATUS_FAIL);
1598 }
1599 retval =
1600 xd_copy_page(chip, phy_blk, new_blk, 0,
1601 xd_card->page_off + 1);
1602 if (retval != STATUS_SUCCESS) {
1603 if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1604 retval = xd_erase_block(chip, new_blk);
1605 if (retval == STATUS_SUCCESS)
1606 xd_set_unused_block(chip, new_blk);
1607 } else {
1608 XD_CLR_BAD_NEWBLK(xd_card);
1609 }
1610 XD_CLR_BAD_OLDBLK(xd_card);
1611 TRACE_RET(chip, STATUS_FAIL);
1612 }
1613 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (new_blk & 0x3FF));
1614 xd_erase_block(chip, phy_blk);
1615 xd_mark_bad_block(chip, phy_blk);
1616 XD_CLR_BAD_OLDBLK(xd_card);
1617 }
1618
1619 TRACE_RET(chip, STATUS_FAIL);
1620}
1621
1622static int xd_finish_write(struct rts51x_chip *chip,
1623 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1624{
1625 struct xd_info *xd_card = &(chip->xd_card);
1626 int retval, zone_no;
1627 u16 log_off;
1628
1629 RTS51X_DEBUGP("xd_finish_write, old_blk = 0x%x, new_blk = 0x%x,"
1630 "log_blk = 0x%x\n", old_blk, new_blk, log_blk);
1631
1632 if (page_off > xd_card->page_off)
1633 TRACE_RET(chip, STATUS_FAIL);
1634
1635 zone_no = (int)(log_blk / 1000);
1636 log_off = (u16) (log_blk % 1000);
1637
1638 if (old_blk == BLK_NOT_FOUND) {
1639 retval = xd_init_page(chip, new_blk, log_off,
1640 page_off, xd_card->page_off + 1);
1641 if (retval != STATUS_SUCCESS) {
1642 retval = xd_erase_block(chip, new_blk);
1643 if (retval == STATUS_SUCCESS)
1644 xd_set_unused_block(chip, new_blk);
1645 TRACE_RET(chip, STATUS_FAIL);
1646 }
1647 } else {
1648 retval = xd_copy_page(chip, old_blk, new_blk,
1649 page_off, xd_card->page_off + 1);
1650 if (retval != STATUS_SUCCESS) {
1651 if (!XD_CHK_BAD_NEWBLK(xd_card)) {
1652 retval = xd_erase_block(chip, new_blk);
1653 if (retval == STATUS_SUCCESS)
1654 xd_set_unused_block(chip, new_blk);
1655 }
1656 XD_CLR_BAD_NEWBLK(xd_card);
1657 TRACE_RET(chip, STATUS_FAIL);
1658 }
1659
1660 retval = xd_erase_block(chip, old_blk);
1661 if (retval == STATUS_SUCCESS) {
1662 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1663 xd_mark_bad_block(chip, old_blk);
1664 XD_CLR_BAD_OLDBLK(xd_card);
1665 } else {
1666
1667 xd_set_unused_block(chip, old_blk);
1668 }
1669 } else {
1670 xd_set_err_code(chip, XD_NO_ERROR);
1671 XD_CLR_BAD_OLDBLK(xd_card);
1672 }
1673 }
1674
1675
1676 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (new_blk & 0x3FF));
1677
1678 return STATUS_SUCCESS;
1679}
1680
1681static int xd_prepare_write(struct rts51x_chip *chip,
1682 u32 old_blk, u32 new_blk, u32 log_blk, u8 page_off)
1683{
1684 int retval;
1685
1686 RTS51X_DEBUGP("xd_prepare_write, old_blk = 0x%x, new_blk = 0x%x,"
1687 "log_blk = 0x%x, page_off = %d\n",
1688 old_blk, new_blk, log_blk, (int)page_off);
1689
1690 if (page_off) {
1691 retval = xd_copy_page(chip, old_blk, new_blk, 0, page_off);
1692 if (retval != STATUS_SUCCESS)
1693 TRACE_RET(chip, retval);
1694 }
1695
1696 return STATUS_SUCCESS;
1697}
1698
1699static int xd_write_multiple_pages(struct rts51x_chip *chip, u32 old_blk,
1700 u32 new_blk, u32 log_blk, u8 start_page,
1701 u8 end_page, u8 *buf, void **ptr,
1702 unsigned int *offset)
1703{
1704 struct xd_info *xd_card = &(chip->xd_card);
1705 u32 page_addr;
1706 int zone_no, retval;
1707 u16 log_off;
1708 u8 page_cnt, reg_val;
1709
1710 RTS51X_DEBUGP("xd_write_multiple_pages, old_blk = 0x%x,"
1711 "new_blk = 0x%x, log_blk = 0x%x\n",
1712 old_blk, new_blk, log_blk);
1713
1714 if (start_page > end_page)
1715 TRACE_RET(chip, STATUS_FAIL);
1716
1717 page_cnt = end_page - start_page;
1718 zone_no = (int)(log_blk / 1000);
1719 log_off = (u16) (log_blk % 1000);
1720
1721 page_addr = (new_blk << xd_card->block_shift) + start_page;
1722
1723
1724 retval = xd_send_cmd(chip, READ1_1);
1725 if (retval != STATUS_SUCCESS)
1726 TRACE_RET(chip, retval);
1727
1728 rts51x_init_cmd(chip);
1729
1730
1731 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_H, 0xFF,
1732 (u8) (log_off >> 8));
1733 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_ADDR1_L, 0xFF,
1734 (u8) log_off);
1735 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_BLOCK_STATUS, 0xFF, XD_GBLK);
1736 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_STATUS, 0xFF, XD_GPG);
1737
1738 xd_assign_phy_addr(chip, page_addr, XD_RW_ADDR);
1739
1740
1741 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_CFG, XD_BA_TRANSFORM,
1742 XD_BA_TRANSFORM);
1743
1744 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_PAGE_CNT, 0xFF, page_cnt);
1745 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_DATA_SOURCE, 0x01,
1746 RING_BUFFER);
1747
1748 rts51x_trans_dma_enable(chip->srb->sc_data_direction, chip, page_cnt * 512,
1749 DMA_512);
1750
1751 rts51x_add_cmd(chip, WRITE_REG_CMD, XD_TRANSFER, 0xFF,
1752 XD_TRANSFER_START | XD_WRITE_PAGES);
1753 rts51x_add_cmd(chip, CHECK_REG_CMD, XD_TRANSFER, XD_TRANSFER_END,
1754 XD_TRANSFER_END);
1755
1756 retval = rts51x_send_cmd(chip, MODE_CDOR, 100);
1757 if (retval != STATUS_SUCCESS)
1758 TRACE_RET(chip, retval);
1759
1760 retval =
1761 rts51x_transfer_data_partial(chip, SND_BULK_PIPE(chip), (void *)buf,
1762 ptr, offset, page_cnt * 512,
1763 scsi_sg_count(chip->srb), NULL, 2000);
1764 if (retval != STATUS_SUCCESS) {
1765 rts51x_clear_xd_error(chip);
1766
1767 if (retval == STATUS_TIMEDOUT) {
1768 xd_set_err_code(chip, XD_TO_ERROR);
1769 TRACE_RET(chip, retval);
1770 } else {
1771 TRACE_GOTO(chip, Fail);
1772 }
1773 }
1774 retval = rts51x_get_rsp(chip, 1, 200);
1775 if (retval != STATUS_SUCCESS) {
1776 rts51x_clear_xd_error(chip);
1777
1778 if (retval == STATUS_TIMEDOUT) {
1779 xd_set_err_code(chip, XD_TO_ERROR);
1780 TRACE_RET(chip, retval);
1781 } else {
1782 TRACE_GOTO(chip, Fail);
1783 }
1784 }
1785
1786 if (end_page == (xd_card->page_off + 1)) {
1787 xd_card->delay_write.delay_write_flag = 0;
1788
1789 if (old_blk != BLK_NOT_FOUND) {
1790 retval = xd_erase_block(chip, old_blk);
1791 if (retval == STATUS_SUCCESS) {
1792 if (XD_CHK_BAD_OLDBLK(xd_card)) {
1793 xd_mark_bad_block(chip, old_blk);
1794 XD_CLR_BAD_OLDBLK(xd_card);
1795 } else {
1796 xd_set_unused_block(chip, old_blk);
1797 }
1798 } else {
1799 xd_set_err_code(chip, XD_NO_ERROR);
1800 XD_CLR_BAD_OLDBLK(xd_card);
1801 }
1802 }
1803 xd_set_l2p_tbl(chip, zone_no, log_off, (u16) (new_blk & 0x3FF));
1804 }
1805
1806 return STATUS_SUCCESS;
1807
1808Fail:
1809 rts51x_ep0_read_register(chip, XD_DAT, ®_val);
1810 RTS51X_DEBUGP("XD_DAT: 0x%x\n", reg_val);
1811
1812 if (reg_val & PROGRAM_ERROR) {
1813 xd_set_err_code(chip, XD_PRG_ERROR);
1814 xd_mark_bad_block(chip, new_blk);
1815 }
1816
1817 TRACE_RET(chip, STATUS_FAIL);
1818}
1819
1820static int xd_delay_write(struct rts51x_chip *chip)
1821{
1822 struct xd_info *xd_card = &(chip->xd_card);
1823 struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1824 int retval;
1825
1826 if (delay_write->delay_write_flag) {
1827 RTS51X_DEBUGP("xd_delay_write\n");
1828 retval = xd_switch_clock(chip);
1829 if (retval != STATUS_SUCCESS)
1830 TRACE_RET(chip, retval);
1831
1832 delay_write->delay_write_flag = 0;
1833 retval = xd_finish_write(chip,
1834 delay_write->old_phyblock,
1835 delay_write->new_phyblock,
1836 delay_write->logblock,
1837 delay_write->pageoff);
1838 if (retval != STATUS_SUCCESS)
1839 TRACE_RET(chip, retval);
1840 }
1841
1842 return STATUS_SUCCESS;
1843}
1844
1845int rts51x_xd_rw(struct scsi_cmnd *srb, struct rts51x_chip *chip, u32 start_sector,
1846 u16 sector_cnt)
1847{
1848 struct xd_info *xd_card = &(chip->xd_card);
1849 unsigned int lun = SCSI_LUN(srb);
1850 struct xd_delay_write_tag *delay_write = &(xd_card->delay_write);
1851 int retval, zone_no;
1852 u32 log_blk, old_blk = 0, new_blk = 0;
1853 u16 log_off, total_sec_cnt = sector_cnt;
1854 u8 start_page, end_page = 0, page_cnt;
1855 u8 *buf;
1856 void *ptr = NULL;
1857 unsigned int offset = 0;
1858
1859 xd_set_err_code(chip, XD_NO_ERROR);
1860
1861 xd_card->counter = 0;
1862
1863 RTS51X_DEBUGP("rts51x_xd_rw: scsi_bufflen = %d, scsi_sg_count = %d\n",
1864 scsi_bufflen(srb), scsi_sg_count(srb));
1865 RTS51X_DEBUGP("Data direction: %s\n",
1866 (srb->sc_data_direction ==
1867 DMA_TO_DEVICE) ? "write" : "read");
1868
1869 buf = (u8 *) scsi_sglist(srb);
1870
1871 retval = xd_switch_clock(chip);
1872 if (retval != STATUS_SUCCESS)
1873 TRACE_RET(chip, retval);
1874
1875 log_blk = start_sector >> xd_card->block_shift;
1876 start_page = (u8) start_sector & xd_card->page_off;
1877 zone_no = (int)(log_blk / 1000);
1878 log_off = (u16) (log_blk % 1000);
1879
1880 RTS51X_DEBUGP("log_blk = 0x%x\n", log_blk);
1881
1882 if (xd_card->zone[zone_no].build_flag == 0) {
1883 retval = xd_build_l2p_tbl(chip, zone_no);
1884 if (retval != STATUS_SUCCESS) {
1885 chip->card_fail |= XD_CARD;
1886 rts51x_set_sense_type(chip, lun, SENSE_TYPE_MEDIA_NOT_PRESENT);
1887 TRACE_RET(chip, retval);
1888 }
1889 }
1890
1891 if (srb->sc_data_direction == DMA_TO_DEVICE) {
1892 if (delay_write->delay_write_flag &&
1893 (delay_write->logblock == log_blk) &&
1894 (start_page > delay_write->pageoff)) {
1895 delay_write->delay_write_flag = 0;
1896 if (delay_write->old_phyblock != BLK_NOT_FOUND) {
1897 retval = xd_copy_page(chip,
1898 delay_write->old_phyblock,
1899 delay_write->new_phyblock,
1900 delay_write->pageoff,
1901 start_page);
1902 if (retval != STATUS_SUCCESS) {
1903 rts51x_set_sense_type(chip, lun,
1904 SENSE_TYPE_MEDIA_WRITE_ERR);
1905 TRACE_RET(chip, retval);
1906 }
1907 }
1908 old_blk = delay_write->old_phyblock;
1909 new_blk = delay_write->new_phyblock;
1910 } else if (delay_write->delay_write_flag &&
1911 (delay_write->logblock == log_blk) &&
1912 (start_page == delay_write->pageoff)) {
1913 delay_write->delay_write_flag = 0;
1914 old_blk = delay_write->old_phyblock;
1915 new_blk = delay_write->new_phyblock;
1916 } else {
1917 retval = xd_delay_write(chip);
1918 if (retval != STATUS_SUCCESS) {
1919 rts51x_set_sense_type(chip, lun,
1920 SENSE_TYPE_MEDIA_WRITE_ERR);
1921 TRACE_RET(chip, retval);
1922 }
1923 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1924 new_blk = xd_get_unused_block(chip, zone_no);
1925 if ((old_blk == BLK_NOT_FOUND)
1926 || (new_blk == BLK_NOT_FOUND)) {
1927 rts51x_set_sense_type(chip, lun,
1928 SENSE_TYPE_MEDIA_WRITE_ERR);
1929 TRACE_RET(chip, retval);
1930 }
1931
1932 retval =
1933 xd_prepare_write(chip, old_blk, new_blk, log_blk,
1934 start_page);
1935 if (retval != STATUS_SUCCESS) {
1936 if (monitor_card_cd(chip, XD_CARD) ==
1937 CD_NOT_EXIST) {
1938 rts51x_set_sense_type(chip, lun,
1939 SENSE_TYPE_MEDIA_NOT_PRESENT);
1940 TRACE_RET(chip, STATUS_FAIL);
1941 }
1942 rts51x_set_sense_type(chip, lun,
1943 SENSE_TYPE_MEDIA_WRITE_ERR);
1944 TRACE_RET(chip, retval);
1945 }
1946 }
1947 } else {
1948 retval = xd_delay_write(chip);
1949 if (retval != STATUS_SUCCESS) {
1950 if (monitor_card_cd(chip, XD_CARD) == CD_NOT_EXIST) {
1951 rts51x_set_sense_type(chip, lun,
1952 SENSE_TYPE_MEDIA_NOT_PRESENT);
1953 TRACE_RET(chip, STATUS_FAIL);
1954 }
1955 rts51x_set_sense_type(chip, lun,
1956 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1957 TRACE_RET(chip, retval);
1958 }
1959
1960 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
1961 if (old_blk == BLK_NOT_FOUND) {
1962 rts51x_set_sense_type(chip, lun,
1963 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1964 TRACE_RET(chip, STATUS_FAIL);
1965 }
1966 }
1967
1968 RTS51X_DEBUGP("old_blk = 0x%x\n", old_blk);
1969 if (srb->sc_data_direction == DMA_TO_DEVICE)
1970 RTS51X_DEBUGP("new_blk = 0x%x\n", new_blk);
1971
1972 while (total_sec_cnt) {
1973 if ((start_page + total_sec_cnt) > (xd_card->page_off + 1))
1974 end_page = xd_card->page_off + 1;
1975 else
1976 end_page = start_page + (u8) total_sec_cnt;
1977 page_cnt = end_page - start_page;
1978 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
1979 retval = xd_read_multiple_pages(chip, old_blk, log_blk,
1980 start_page, end_page,
1981 buf, &ptr, &offset);
1982 if (retval != STATUS_SUCCESS) {
1983 rts51x_set_sense_type(chip, lun,
1984 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
1985 TRACE_RET(chip, STATUS_FAIL);
1986 }
1987 } else {
1988 retval =
1989 xd_write_multiple_pages(chip, old_blk, new_blk,
1990 log_blk, start_page,
1991 end_page, buf, &ptr,
1992 &offset);
1993 if (retval != STATUS_SUCCESS) {
1994 rts51x_set_sense_type(chip, lun,
1995 SENSE_TYPE_MEDIA_WRITE_ERR);
1996 TRACE_RET(chip, STATUS_FAIL);
1997 }
1998 }
1999
2000 total_sec_cnt -= page_cnt;
2001
2002 if (total_sec_cnt == 0)
2003 break;
2004
2005 log_blk++;
2006 zone_no = (int)(log_blk / 1000);
2007 log_off = (u16) (log_blk % 1000);
2008
2009 if (xd_card->zone[zone_no].build_flag == 0) {
2010 retval = xd_build_l2p_tbl(chip, zone_no);
2011 if (retval != STATUS_SUCCESS) {
2012 chip->card_fail |= XD_CARD;
2013 rts51x_set_sense_type(chip, lun,
2014 SENSE_TYPE_MEDIA_NOT_PRESENT);
2015 TRACE_RET(chip, retval);
2016 }
2017 }
2018
2019 old_blk = xd_get_l2p_tbl(chip, zone_no, log_off);
2020 if (old_blk == BLK_NOT_FOUND) {
2021 if (srb->sc_data_direction == DMA_FROM_DEVICE) {
2022 rts51x_set_sense_type(chip, lun,
2023 SENSE_TYPE_MEDIA_UNRECOVER_READ_ERR);
2024 } else {
2025 rts51x_set_sense_type(chip, lun,
2026 SENSE_TYPE_MEDIA_WRITE_ERR);
2027 }
2028 TRACE_RET(chip, STATUS_FAIL);
2029 }
2030
2031 if (srb->sc_data_direction == DMA_TO_DEVICE) {
2032 new_blk = xd_get_unused_block(chip, zone_no);
2033 if (new_blk == BLK_NOT_FOUND) {
2034 rts51x_set_sense_type(chip, lun,
2035 SENSE_TYPE_MEDIA_WRITE_ERR);
2036 TRACE_RET(chip, STATUS_FAIL);
2037 }
2038 }
2039
2040 start_page = 0;
2041 }
2042
2043 if ((srb->sc_data_direction == DMA_TO_DEVICE) &&
2044 (end_page != (xd_card->page_off + 1))) {
2045 delay_write->delay_write_flag = 1;
2046 delay_write->old_phyblock = old_blk;
2047 delay_write->new_phyblock = new_blk;
2048 delay_write->logblock = log_blk;
2049 delay_write->pageoff = end_page;
2050 }
2051
2052 scsi_set_resid(srb, 0);
2053
2054 return STATUS_SUCCESS;
2055}
2056
2057void rts51x_xd_free_l2p_tbl(struct rts51x_chip *chip)
2058{
2059 struct xd_info *xd_card = &(chip->xd_card);
2060 int i = 0;
2061
2062 if (xd_card->zone != NULL) {
2063 for (i = 0; i < xd_card->zone_cnt; i++) {
2064 if (xd_card->zone[i].l2p_table != NULL) {
2065 vfree(xd_card->zone[i].l2p_table);
2066 xd_card->zone[i].l2p_table = NULL;
2067 }
2068 if (xd_card->zone[i].free_table != NULL) {
2069 vfree(xd_card->zone[i].free_table);
2070 xd_card->zone[i].free_table = NULL;
2071 }
2072 }
2073 vfree(xd_card->zone);
2074 xd_card->zone = NULL;
2075 }
2076}
2077
2078void rts51x_xd_cleanup_work(struct rts51x_chip *chip)
2079{
2080 struct xd_info *xd_card = &(chip->xd_card);
2081
2082 if (xd_card->delay_write.delay_write_flag) {
2083 RTS51X_DEBUGP("xD: delay write\n");
2084 xd_delay_write(chip);
2085 xd_card->counter = 0;
2086 }
2087}
2088
2089static int xd_power_off_card3v3(struct rts51x_chip *chip)
2090{
2091 int retval;
2092
2093 rts51x_init_cmd(chip);
2094
2095 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_CLK_EN, XD_CLK_EN, 0);
2096
2097 if (chip->asic_code)
2098 xd_pull_ctl_disable(chip);
2099 else
2100 rts51x_add_cmd(chip, WRITE_REG_CMD, FPGA_PULL_CTL, 0xFF, 0xDF);
2101 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_OE, XD_OUTPUT_EN, 0);
2102 if (!chip->option.FT2_fast_mode) {
2103 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL, POWER_MASK,
2104 POWER_OFF);
2105 if (CHECK_PKG(chip, LQFP48)
2106 || chip->option.rts5129_D3318_off_enable)
2107 rts51x_add_cmd(chip, WRITE_REG_CMD, CARD_PWR_CTL,
2108 DV3318_AUTO_PWR_OFF, 0);
2109 }
2110
2111 retval = rts51x_send_cmd(chip, MODE_C, 100);
2112 if (retval != STATUS_SUCCESS)
2113 TRACE_RET(chip, retval);
2114
2115 return STATUS_SUCCESS;
2116}
2117
2118int rts51x_release_xd_card(struct rts51x_chip *chip)
2119{
2120 struct xd_info *xd_card = &(chip->xd_card);
2121 int retval;
2122
2123 RTS51X_DEBUGP("rts51x_release_xd_card\n");
2124
2125 chip->card_ready &= ~XD_CARD;
2126 chip->card_fail &= ~XD_CARD;
2127 chip->card_wp &= ~XD_CARD;
2128
2129 xd_card->delay_write.delay_write_flag = 0;
2130
2131 rts51x_xd_free_l2p_tbl(chip);
2132
2133 rts51x_write_register(chip, SFSM_ED, HW_CMD_STOP, HW_CMD_STOP);
2134
2135 retval = xd_power_off_card3v3(chip);
2136 if (retval != STATUS_SUCCESS)
2137 TRACE_RET(chip, retval);
2138
2139 if (chip->asic_code && CHECK_PKG(chip, QFN24))
2140 wait_timeout(20);
2141
2142 return STATUS_SUCCESS;
2143}
2144
