1#include <linux/errno.h>
2#include <linux/signal.h>
3#include <linux/tty.h>
4#include <linux/tty_flip.h>
5#include <linux/serial.h>
6#include <linux/serial_reg.h>
7#include <linux/ioport.h>
8#include <linux/mm.h>
9#include <linux/sched.h>
10
11#include <linux/kernel.h>
12#include <linux/init.h>
13#include <linux/slab.h>
14#include <linux/wait.h>
15#include <linux/tty_driver.h>
16#include <linux/pci.h>
17#include <linux/circ_buf.h>
18
19#include <asm/uaccess.h>
20#include <asm/io.h>
21#include <asm/irq.h>
22#include <asm/serial.h>
23#include <linux/interrupt.h>
24
25
26#include <linux/parport.h>
27#include <linux/ctype.h>
28#include <linux/poll.h>
29
30
31#define MP_TERMIOS ktermios
32
33#include "sb_mp_register.h"
34#include "sb_ser_core.h"
35
36#define DRIVER_VERSION "1.1"
37#define DRIVER_DATE "2012/01/05"
38#define DRIVER_AUTHOR "SYSTEMBASE<tech@sysbas.com>"
39#define DRIVER_DESC "SystemBase PCI/PCIe Multiport Core"
40
41#define SB_TTY_MP_MAJOR 54
42#define PCI_VENDOR_ID_MULTIPORT 0x14A1
43
44#define PCI_DEVICE_ID_MP1 0x4d01
45#define PCI_DEVICE_ID_MP2 0x4d02
46#define PCI_DEVICE_ID_MP4 0x4d04
47#define PCI_DEVICE_ID_MP4A 0x4d54
48#define PCI_DEVICE_ID_MP6 0x4d06
49#define PCI_DEVICE_ID_MP6A 0x4d56
50#define PCI_DEVICE_ID_MP8 0x4d08
51#define PCI_DEVICE_ID_MP32 0x4d32
52
53#define PCI_DEVICE_ID_MP1P 0x4301
54#define PCI_DEVICE_ID_MP2S1P 0x4303
55
56#define PCIE_DEVICE_ID_MP1 0x4501
57#define PCIE_DEVICE_ID_MP2 0x4502
58#define PCIE_DEVICE_ID_MP4 0x4504
59#define PCIE_DEVICE_ID_MP8 0x4508
60#define PCIE_DEVICE_ID_MP32 0x4532
61
62#define PCIE_DEVICE_ID_MP1E 0x4e01
63#define PCIE_DEVICE_ID_MP2E 0x4e02
64#define PCIE_DEVICE_ID_MP2B 0x4b02
65#define PCIE_DEVICE_ID_MP4B 0x4b04
66#define PCIE_DEVICE_ID_MP8B 0x4b08
67
68#define PCI_DEVICE_ID_GT_MP4 0x0004
69#define PCI_DEVICE_ID_GT_MP4A 0x0054
70#define PCI_DEVICE_ID_GT_MP6 0x0006
71#define PCI_DEVICE_ID_GT_MP6A 0x0056
72#define PCI_DEVICE_ID_GT_MP8 0x0008
73#define PCI_DEVICE_ID_GT_MP32 0x0032
74
75#define PCIE_DEVICE_ID_GT_MP1 0x1501
76#define PCIE_DEVICE_ID_GT_MP2 0x1502
77#define PCIE_DEVICE_ID_GT_MP4 0x1504
78#define PCIE_DEVICE_ID_GT_MP8 0x1508
79#define PCIE_DEVICE_ID_GT_MP32 0x1532
80
81#define PCI_DEVICE_ID_MP4M 0x4604
82
83#define MAX_MP_DEV 8
84#define BD_MAX_PORT 32
85#define MAX_MP_PORT 256
86
87#define PORT_16C105XA 3
88#define PORT_16C105X 2
89#define PORT_16C55X 1
90
91#define ENABLE 1
92#define DISABLE 0
93
94
95#define TIOCGNUMOFPORT 0x545F
96#define TIOCSMULTIECHO 0x5440
97#define TIOCSPTPNOECHO 0x5441
98
99#define TIOCGOPTIONREG 0x5461
100#define TIOCGDISABLEIRQ 0x5462
101#define TIOCGENABLEIRQ 0x5463
102#define TIOCGSOFTRESET 0x5464
103#define TIOCGSOFTRESETR 0x5465
104#define TIOCGREGINFO 0x5466
105#define TIOCGGETLSR 0x5467
106#define TIOCGGETDEVID 0x5468
107#define TIOCGGETBDNO 0x5469
108#define TIOCGGETINTERFACE 0x546A
109#define TIOCGGETREV 0x546B
110#define TIOCGGETNRPORTS 0x546C
111#define TIOCGGETPORTTYPE 0x546D
112#define GETDEEPFIFO 0x54AA
113#define SETDEEPFIFO 0x54AB
114#define SETFCR 0x54BA
115#define SETTTR 0x54B1
116#define SETRTR 0x54B2
117#define GETTTR 0x54B3
118#define GETRTR 0x54B4
119
120
121#define TIOCSMULTIDROP 0x5470
122#define TIOCSMDADDR 0x5471
123#define TIOCGMDADDR 0x5472
124#define TIOCSENDADDR 0x5473
125
126
127
128#define RS232 1
129#define RS422PTP 2
130#define RS422MD 3
131#define RS485NE 4
132#define RS485ECHO 5
133
134#define serial_inp(up, offset) serial_in(up, offset)
135#define serial_outp(up, offset, value) serial_out(up, offset, value)
136
137#define PASS_LIMIT 256
138#define is_real_interrupt(irq) ((irq) != 0)
139
140#define PROBE_ANY (~0)
141
142static DEFINE_MUTEX(mp_mutex);
143#define MP_MUTEX_LOCK(x) mutex_lock(&(x))
144#define MP_MUTEX_UNLOCK(x) mutex_unlock(&(x))
145#define MP_STATE_LOCK(x) mutex_lock(&((x)->mutex))
146#define MP_STATE_UNLOCK(x) mutex_unlock(&((x)->mutex))
147
148
149#define UART_LSR_SPECIAL 0x1E
150
151#define HIGH_BITS_OFFSET ((sizeof(long)-sizeof(int))*8)
152#define uart_users(state) ((state)->count + ((state)->info ? (state)->info->blocked_open : 0))
153
154
155
156#undef MP_DEBUG
157
158#ifdef MP_DEBUG
159#define DPRINTK(x...) printk(x)
160#else
161#define DPRINTK(x...) do { } while (0)
162#endif
163
164#ifdef MP_DEBUG
165#define DEBUG_AUTOCONF(fmt...) printk(fmt)
166#else
167#define DEBUG_AUTOCONF(fmt...) do { } while (0)
168#endif
169
170#ifdef MP_DEBUG
171#define DEBUG_INTR(fmt...) printk(fmt)
172#else
173#define DEBUG_INTR(fmt...) do { } while (0)
174#endif
175
176#if defined(__i386__) && defined(CONFIG_M486)
177#define SERIAL_INLINE
178#endif
179#ifdef SERIAL_INLINE
180#define _INLINE_ inline
181#else
182#define _INLINE_
183#endif
184
185#define TYPE_POLL 1
186#define TYPE_INTERRUPT 2
187
188
189struct mp_device_t {
190 unsigned short device_id;
191 unsigned char revision;
192 char *name;
193 unsigned long uart_access_addr;
194 unsigned long option_reg_addr;
195 unsigned long reserved_addr[4];
196 int irq;
197 int nr_ports;
198 int poll_type;
199};
200
201typedef struct mppcibrd {
202 char *name;
203 unsigned short vendor_id;
204 unsigned short device_id;
205} mppcibrd_t;
206
207static mppcibrd_t mp_pciboards[] = {
208
209 { "Multi-1 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP1} ,
210 { "Multi-2 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP2} ,
211 { "Multi-4 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP4} ,
212 { "Multi-4 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP4A} ,
213 { "Multi-6 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP6} ,
214 { "Multi-6 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP6A} ,
215 { "Multi-8 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP8} ,
216 { "Multi-32 PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP32} ,
217
218 { "Multi-1P PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP1P} ,
219 { "Multi-2S1P PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP2S1P} ,
220
221 { "Multi-4(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP4} ,
222 { "Multi-4(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP4A} ,
223 { "Multi-6(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP6} ,
224 { "Multi-6(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP6A} ,
225 { "Multi-8(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP8} ,
226 { "Multi-32(GT) PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_GT_MP32} ,
227
228 { "Multi-1 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP1} ,
229 { "Multi-2 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP2} ,
230 { "Multi-4 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP4} ,
231 { "Multi-8 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP8} ,
232 { "Multi-32 PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP32} ,
233
234 { "Multi-1 PCIe E", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP1E} ,
235 { "Multi-2 PCIe E", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP2E} ,
236 { "Multi-2 PCIe B", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP2B} ,
237 { "Multi-4 PCIe B", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP4B} ,
238 { "Multi-8 PCIe B", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_MP8B} ,
239
240 { "Multi-1(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP1} ,
241 { "Multi-2(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP2} ,
242 { "Multi-4(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP4} ,
243 { "Multi-8(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP8} ,
244 { "Multi-32(GT) PCIe", PCI_VENDOR_ID_MULTIPORT , PCIE_DEVICE_ID_GT_MP32} ,
245
246 { "Multi-4M PCI", PCI_VENDOR_ID_MULTIPORT , PCI_DEVICE_ID_MP4M} ,
247};
248
249struct mp_port {
250 struct sb_uart_port port;
251
252 struct timer_list timer;
253 struct list_head list;
254 unsigned int capabilities;
255 unsigned short rev;
256 unsigned char acr;
257 unsigned char ier;
258 unsigned char lcr;
259 unsigned char mcr;
260 unsigned char mcr_mask;
261 unsigned char mcr_force;
262 unsigned char lsr_break_flag;
263
264 void (*pm)(struct sb_uart_port *port,
265 unsigned int state, unsigned int old);
266 struct mp_device_t *device;
267 unsigned long interface_config_addr;
268 unsigned long option_base_addr;
269 unsigned char interface;
270 unsigned char poll_type;
271};
272
273struct irq_info {
274 spinlock_t lock;
275 struct list_head *head;
276};
277
278struct sb105x_uart_config {
279 char *name;
280 int dfl_xmit_fifo_size;
281 int flags;
282};
283
284static const struct sb105x_uart_config uart_config[] = {
285 { "unknown", 1, 0 },
286 { "16550A", 16, UART_CLEAR_FIFO | UART_USE_FIFO },
287 { "SB16C1050", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
288 { "SB16C1050A", 128, UART_CLEAR_FIFO | UART_USE_FIFO | UART_STARTECH },
289};
290
291
292
293
