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19#if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
20#define SUPPORT_SYSRQ
21#endif
22
23#include <linux/module.h>
24#include <linux/moduleparam.h>
25#include <linux/ioport.h>
26#include <linux/init.h>
27#include <linux/console.h>
28#include <linux/sysrq.h>
29#include <linux/delay.h>
30#include <linux/platform_device.h>
31#include <linux/tty.h>
32#include <linux/ratelimit.h>
33#include <linux/tty_flip.h>
34#include <linux/serial_reg.h>
35#include <linux/serial_core.h>
36#include <linux/serial.h>
37#include <linux/serial_8250.h>
38#include <linux/nmi.h>
39#include <linux/mutex.h>
40#include <linux/slab.h>
41#ifdef CONFIG_SPARC
42#include <linux/sunserialcore.h>
43#endif
44
45#include <asm/io.h>
46#include <asm/irq.h>
47
48#include "8250.h"
49
50
51
52
53
54
55static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
56
57static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
58
59static struct uart_driver serial8250_reg;
60
61static int serial_index(struct uart_port *port)
62{
63 return (serial8250_reg.minor - 64) + port->line;
64}
65
66static unsigned int skip_txen_test;
67
68
69
70
71#if 0
72#define DEBUG_AUTOCONF(fmt...) printk(fmt)
73#else
74#define DEBUG_AUTOCONF(fmt...) do { } while (0)
75#endif
76
77#if 0
78#define DEBUG_INTR(fmt...) printk(fmt)
79#else
80#define DEBUG_INTR(fmt...) do { } while (0)
81#endif
82
83#define PASS_LIMIT 512
84
85#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
86
87
88#ifdef CONFIG_SERIAL_8250_DETECT_IRQ
89#define CONFIG_SERIAL_DETECT_IRQ 1
90#endif
91#ifdef CONFIG_SERIAL_8250_MANY_PORTS
92#define CONFIG_SERIAL_MANY_PORTS 1
93#endif
94
95
96
97
98
99#define CONFIG_HUB6 1
100
101#include <asm/serial.h>
102
103
104
105
106
107#ifndef SERIAL_PORT_DFNS
108#define SERIAL_PORT_DFNS
109#endif
110
111static const struct old_serial_port old_serial_port[] = {
112 SERIAL_PORT_DFNS
113};
114
115#define UART_NR CONFIG_SERIAL_8250_NR_UARTS
116
117#ifdef CONFIG_SERIAL_8250_RSA
118
119#define PORT_RSA_MAX 4
120static unsigned long probe_rsa[PORT_RSA_MAX];
121static unsigned int probe_rsa_count;
122#endif
123
124struct irq_info {
125 struct hlist_node node;
126 int irq;
127 spinlock_t lock;
128 struct list_head *head;
129};
130
131#define NR_IRQ_HASH 32
132static struct hlist_head irq_lists[NR_IRQ_HASH];
133static DEFINE_MUTEX(hash_mutex);
134
135
136
137
138static const struct serial8250_config uart_config[] = {
139 [PORT_UNKNOWN] = {
140 .name = "unknown",
141 .fifo_size = 1,
142 .tx_loadsz = 1,
143 },
144 [PORT_8250] = {
145 .name = "8250",
146 .fifo_size = 1,
147 .tx_loadsz = 1,
148 },
149 [PORT_16450] = {
150 .name = "16450",
151 .fifo_size = 1,
152 .tx_loadsz = 1,
153 },
154 [PORT_16550] = {
155 .name = "16550",
156 .fifo_size = 1,
157 .tx_loadsz = 1,
158 },
159 [PORT_16550A] = {
160 .name = "16550A",
161 .fifo_size = 16,
162 .tx_loadsz = 16,
163 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
164 .flags = UART_CAP_FIFO,
165 },
166 [PORT_CIRRUS] = {
167 .name = "Cirrus",
168 .fifo_size = 1,
169 .tx_loadsz = 1,
170 },
171 [PORT_16650] = {
172 .name = "ST16650",
173 .fifo_size = 1,
174 .tx_loadsz = 1,
175 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
176 },
177 [PORT_16650V2] = {
178 .name = "ST16650V2",
179 .fifo_size = 32,
180 .tx_loadsz = 16,
181 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
182 UART_FCR_T_TRIG_00,
183 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
184 },
185 [PORT_16750] = {
186 .name = "TI16750",
187 .fifo_size = 64,
188 .tx_loadsz = 64,
189 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
190 UART_FCR7_64BYTE,
191 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
192 },
193 [PORT_STARTECH] = {
194 .name = "Startech",
195 .fifo_size = 1,
196 .tx_loadsz = 1,
197 },
198 [PORT_16C950] = {
199 .name = "16C950/954",
200 .fifo_size = 128,
201 .tx_loadsz = 128,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
203
204 .flags = UART_CAP_FIFO | UART_CAP_SLEEP,
205 },
206 [PORT_16654] = {
207 .name = "ST16654",
208 .fifo_size = 64,
209 .tx_loadsz = 32,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
211 UART_FCR_T_TRIG_10,
212 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
213 },
214 [PORT_16850] = {
215 .name = "XR16850",
216 .fifo_size = 128,
217 .tx_loadsz = 128,
218 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
219 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
220 },
221 [PORT_RSA] = {
222 .name = "RSA",
223 .fifo_size = 2048,
224 .tx_loadsz = 2048,
225 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
226 .flags = UART_CAP_FIFO,
227 },
228 [PORT_NS16550A] = {
229 .name = "NS16550A",
230 .fifo_size = 16,
231 .tx_loadsz = 16,
232 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
233 .flags = UART_CAP_FIFO | UART_NATSEMI,
234 },
235 [PORT_XSCALE] = {
236 .name = "XScale",
237 .fifo_size = 32,
238 .tx_loadsz = 32,
239 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
240 .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
241 },
242 [PORT_OCTEON] = {
243 .name = "OCTEON",
244 .fifo_size = 64,
245 .tx_loadsz = 64,
246 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
247 .flags = UART_CAP_FIFO,
248 },
249 [PORT_AR7] = {
250 .name = "AR7",
251 .fifo_size = 16,
252 .tx_loadsz = 16,
253 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_00,
254 .flags = UART_CAP_FIFO | UART_CAP_AFE,
255 },
256 [PORT_U6_16550A] = {
257 .name = "U6_16550A",
258 .fifo_size = 64,
259 .tx_loadsz = 64,
260 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
261 .flags = UART_CAP_FIFO | UART_CAP_AFE,
262 },
263 [PORT_TEGRA] = {
264 .name = "Tegra",
265 .fifo_size = 32,
266 .tx_loadsz = 8,
267 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
268 UART_FCR_T_TRIG_01,
269 .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
270 },
271 [PORT_XR17D15X] = {
272 .name = "XR17D15X",
273 .fifo_size = 64,
274 .tx_loadsz = 64,
275 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
276 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
277 UART_CAP_SLEEP,
278 },
279 [PORT_XR17V35X] = {
280 .name = "XR17V35X",
281 .fifo_size = 256,
282 .tx_loadsz = 256,
283 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11 |
284 UART_FCR_T_TRIG_11,
285 .flags = UART_CAP_FIFO | UART_CAP_AFE | UART_CAP_EFR |
286 UART_CAP_SLEEP,
287 },
288 [PORT_LPC3220] = {
289 .name = "LPC3220",
290 .fifo_size = 64,
291 .tx_loadsz = 32,
292 .fcr = UART_FCR_DMA_SELECT | UART_FCR_ENABLE_FIFO |
293 UART_FCR_R_TRIG_00 | UART_FCR_T_TRIG_00,
294 .flags = UART_CAP_FIFO,
295 },
296 [PORT_BRCM_TRUMANAGE] = {
297 .name = "TruManage",
298 .fifo_size = 1,
299 .tx_loadsz = 1024,
300 .flags = UART_CAP_HFIFO,
301 },
302 [PORT_8250_CIR] = {
303 .name = "CIR port"
304 },
305 [PORT_ALTR_16550_F32] = {
306 .name = "Altera 16550 FIFO32",
307 .fifo_size = 32,
308 .tx_loadsz = 32,
309 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
310 .flags = UART_CAP_FIFO | UART_CAP_AFE,
311 },
312 [PORT_ALTR_16550_F64] = {
313 .name = "Altera 16550 FIFO64",
314 .fifo_size = 64,
315 .tx_loadsz = 64,
316 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
317 .flags = UART_CAP_FIFO | UART_CAP_AFE,
318 },
319 [PORT_ALTR_16550_F128] = {
320 .name = "Altera 16550 FIFO128",
321 .fifo_size = 128,
322 .tx_loadsz = 128,
323 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
324 .flags = UART_CAP_FIFO | UART_CAP_AFE,
325 },
326};
327
328
329static int default_serial_dl_read(struct uart_8250_port *up)
330{
331 return serial_in(up, UART_DLL) | serial_in(up, UART_DLM) << 8;
332}
333
334
335static void default_serial_dl_write(struct uart_8250_port *up, int value)
336{
337 serial_out(up, UART_DLL, value & 0xff);
338 serial_out(up, UART_DLM, value >> 8 & 0xff);
339}
340
341#if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
342
343
344static const u8 au_io_in_map[] = {
345 [UART_RX] = 0,
346 [UART_IER] = 2,
347 [UART_IIR] = 3,
348 [UART_LCR] = 5,
349 [UART_MCR] = 6,
350 [UART_LSR] = 7,
351 [UART_MSR] = 8,
352};
353
354static const u8 au_io_out_map[] = {
355 [UART_TX] = 1,
356 [UART_IER] = 2,
357 [UART_FCR] = 4,
358 [UART_LCR] = 5,
359 [UART_MCR] = 6,
360};
361
362static unsigned int au_serial_in(struct uart_port *p, int offset)
363{
364 offset = au_io_in_map[offset] << p->regshift;
365 return __raw_readl(p->membase + offset);
366}
367
368static void au_serial_out(struct uart_port *p, int offset, int value)
369{
370 offset = au_io_out_map[offset] << p->regshift;
371 __raw_writel(value, p->membase + offset);
372}
373
374
375static int au_serial_dl_read(struct uart_8250_port *up)
376{
377 return __raw_readl(up->port.membase + 0x28);
378}
379
380static void au_serial_dl_write(struct uart_8250_port *up, int value)
381{
382 __raw_writel(value, up->port.membase + 0x28);
383}
384
385#endif
386
387static unsigned int hub6_serial_in(struct uart_port *p, int offset)
388{
389 offset = offset << p->regshift;
390 outb(p->hub6 - 1 + offset, p->iobase);
391 return inb(p->iobase + 1);
392}
393
394static void hub6_serial_out(struct uart_port *p, int offset, int value)
395{
396 offset = offset << p->regshift;
397 outb(p->hub6 - 1 + offset, p->iobase);
398 outb(value, p->iobase + 1);
399}
400
401static unsigned int mem_serial_in(struct uart_port *p, int offset)
402{
403 offset = offset << p->regshift;
404 return readb(p->membase + offset);
405}
406
407static void mem_serial_out(struct uart_port *p, int offset, int value)
408{
409 offset = offset << p->regshift;
410 writeb(value, p->membase + offset);
411}
412
413static void mem32_serial_out(struct uart_port *p, int offset, int value)
414{
415 offset = offset << p->regshift;
416 writel(value, p->membase + offset);
417}
418
419static unsigned int mem32_serial_in(struct uart_port *p, int offset)
420{
421 offset = offset << p->regshift;
422 return readl(p->membase + offset);
423}
424
425static unsigned int io_serial_in(struct uart_port *p, int offset)
426{
427 offset = offset << p->regshift;
428 return inb(p->iobase + offset);
429}
430
431static void io_serial_out(struct uart_port *p, int offset, int value)
432{
433 offset = offset << p->regshift;
434 outb(value, p->iobase + offset);
435}
436
437static int serial8250_default_handle_irq(struct uart_port *port);
438static int exar_handle_irq(struct uart_port *port);
439
440static void set_io_from_upio(struct uart_port *p)
441{
442 struct uart_8250_port *up =
443 container_of(p, struct uart_8250_port, port);
444
445 up->dl_read = default_serial_dl_read;
446 up->dl_write = default_serial_dl_write;
447
448 switch (p->iotype) {
449 case UPIO_HUB6:
450 p->serial_in = hub6_serial_in;
451 p->serial_out = hub6_serial_out;
452 break;
453
454 case UPIO_MEM:
455 p->serial_in = mem_serial_in;
456 p->serial_out = mem_serial_out;
457 break;
458
459 case UPIO_MEM32:
460 p->serial_in = mem32_serial_in;
461 p->serial_out = mem32_serial_out;
462 break;
463
464#if defined(CONFIG_MIPS_ALCHEMY) || defined(CONFIG_SERIAL_8250_RT288X)
465 case UPIO_AU:
466 p->serial_in = au_serial_in;
467 p->serial_out = au_serial_out;
468 up->dl_read = au_serial_dl_read;
469 up->dl_write = au_serial_dl_write;
470 break;
471#endif
472
473 default:
474 p->serial_in = io_serial_in;
475 p->serial_out = io_serial_out;
476 break;
477 }
478
479 up->cur_iotype = p->iotype;
480 p->handle_irq = serial8250_default_handle_irq;
481}
482
483static void
484serial_port_out_sync(struct uart_port *p, int offset, int value)
485{
486 switch (p->iotype) {
487 case UPIO_MEM:
488 case UPIO_MEM32:
489 case UPIO_AU:
490 p->serial_out(p, offset, value);
491 p->serial_in(p, UART_LCR);
492 break;
493 default:
494 p->serial_out(p, offset, value);
495 }
496}
497
498
499
500
501static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
502{
503 serial_out(up, UART_SCR, offset);
504 serial_out(up, UART_ICR, value);
505}
506
507static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
508{
509 unsigned int value;
510
511 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
512 serial_out(up, UART_SCR, offset);
513 value = serial_in(up, UART_ICR);
514 serial_icr_write(up, UART_ACR, up->acr);
515
516 return value;
517}
518
519
520
521
522static void serial8250_clear_fifos(struct uart_8250_port *p)
523{
524 if (p->capabilities & UART_CAP_FIFO) {
525 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO);
526 serial_out(p, UART_FCR, UART_FCR_ENABLE_FIFO |
527 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
528 serial_out(p, UART_FCR, 0);
529 }
530}
531
532void serial8250_clear_and_reinit_fifos(struct uart_8250_port *p)
533{
534 unsigned char fcr;
535
536 serial8250_clear_fifos(p);
537 fcr = uart_config[p->port.type].fcr;
538 serial_out(p, UART_FCR, fcr);
539}
540EXPORT_SYMBOL_GPL(serial8250_clear_and_reinit_fifos);
541
542
543
544
545
546
547static void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
548{
549
550
551
552
553
554
555
556 if ((p->port.type == PORT_XR17V35X) ||
557 (p->port.type == PORT_XR17D15X)) {
558 serial_out(p, UART_EXAR_SLEEP, 0xff);
559 return;
560 }
561
562 if (p->capabilities & UART_CAP_SLEEP) {
563 if (p->capabilities & UART_CAP_EFR) {
564 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
565 serial_out(p, UART_EFR, UART_EFR_ECB);
566 serial_out(p, UART_LCR, 0);
567 }
568 serial_out(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
569 if (p->capabilities & UART_CAP_EFR) {
570 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_B);
571 serial_out(p, UART_EFR, 0);
572 serial_out(p, UART_LCR, 0);
573 }
574 }
575}
576
577#ifdef CONFIG_SERIAL_8250_RSA
578
579
580
581
582static int __enable_rsa(struct uart_8250_port *up)
583{
584 unsigned char mode;
585 int result;
586
587 mode = serial_in(up, UART_RSA_MSR);
588 result = mode & UART_RSA_MSR_FIFO;
589
590 if (!result) {
591 serial_out(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
592 mode = serial_in(up, UART_RSA_MSR);
593 result = mode & UART_RSA_MSR_FIFO;
594 }
595
596 if (result)
597 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
598
599 return result;
600}
601
602static void enable_rsa(struct uart_8250_port *up)
603{
604 if (up->port.type == PORT_RSA) {
605 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
606 spin_lock_irq(&up->port.lock);
607 __enable_rsa(up);
608 spin_unlock_irq(&up->port.lock);
609 }
610 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
611 serial_out(up, UART_RSA_FRR, 0);
612 }
613}
614
615
616
617
618
619
620
621static void disable_rsa(struct uart_8250_port *up)
622{
623 unsigned char mode;
624 int result;
625
626 if (up->port.type == PORT_RSA &&
627 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
628 spin_lock_irq(&up->port.lock);
629
630 mode = serial_in(up, UART_RSA_MSR);
631 result = !(mode & UART_RSA_MSR_FIFO);
632
633 if (!result) {
634 serial_out(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
635 mode = serial_in(up, UART_RSA_MSR);
636 result = !(mode & UART_RSA_MSR_FIFO);
637 }
638
639 if (result)
640 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
641 spin_unlock_irq(&up->port.lock);
642 }
643}
644#endif
645
646
647
648
649
650static int size_fifo(struct uart_8250_port *up)
651{
652 unsigned char old_fcr, old_mcr, old_lcr;
653 unsigned short old_dl;
654 int count;
655
656 old_lcr = serial_in(up, UART_LCR);
657 serial_out(up, UART_LCR, 0);
658 old_fcr = serial_in(up, UART_FCR);
659 old_mcr = serial_in(up, UART_MCR);
660 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
661 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
662 serial_out(up, UART_MCR, UART_MCR_LOOP);
663 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
664 old_dl = serial_dl_read(up);
665 serial_dl_write(up, 0x0001);
666 serial_out(up, UART_LCR, 0x03);
667 for (count = 0; count < 256; count++)
668 serial_out(up, UART_TX, count);
669 mdelay(20);
670 for (count = 0; (serial_in(up, UART_LSR) & UART_LSR_DR) &&
671 (count < 256); count++)
672 serial_in(up, UART_RX);
673 serial_out(up, UART_FCR, old_fcr);
674 serial_out(up, UART_MCR, old_mcr);
675 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
676 serial_dl_write(up, old_dl);
677 serial_out(up, UART_LCR, old_lcr);
678
679 return count;
680}
681
682
683
684
685
686
687static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
688{
689 unsigned char old_dll, old_dlm, old_lcr;
690 unsigned int id;
691
692 old_lcr = serial_in(p, UART_LCR);
693 serial_out(p, UART_LCR, UART_LCR_CONF_MODE_A);
694
695 old_dll = serial_in(p, UART_DLL);
696 old_dlm = serial_in(p, UART_DLM);
697
698 serial_out(p, UART_DLL, 0);
699 serial_out(p, UART_DLM, 0);
700
701 id = serial_in(p, UART_DLL) | serial_in(p, UART_DLM) << 8;
702
703 serial_out(p, UART_DLL, old_dll);
704 serial_out(p, UART_DLM, old_dlm);
705 serial_out(p, UART_LCR, old_lcr);
706
707 return id;
708}
709
710
711
712
713
714
715
716
717
718
719
720static void autoconfig_has_efr(struct uart_8250_port *up)
721{
722 unsigned int id1, id2, id3, rev;
723
724
725
726
727 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746 up->acr = 0;
747 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
748 serial_out(up, UART_EFR, UART_EFR_ECB);
749 serial_out(up, UART_LCR, 0x00);
750 id1 = serial_icr_read(up, UART_ID1);
751 id2 = serial_icr_read(up, UART_ID2);
752 id3 = serial_icr_read(up, UART_ID3);
753 rev = serial_icr_read(up, UART_REV);
754
755 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
756
757 if (id1 == 0x16 && id2 == 0xC9 &&
758 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
759 up->port.type = PORT_16C950;
760
761
762
763
764
765
766 if (id3 == 0x52 && rev == 0x01)
767 up->bugs |= UART_BUG_QUOT;
768 return;
769 }
770
771
772
773
774
775
776
777
778
779 id1 = autoconfig_read_divisor_id(up);
780 DEBUG_AUTOCONF("850id=%04x ", id1);
781
782 id2 = id1 >> 8;
783 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
784 up->port.type = PORT_16850;
785 return;
786 }
787
788
789
790
791
792
793
794
795
796
797 if (size_fifo(up) == 64)
798 up->port.type = PORT_16654;
799 else
800 up->port.type = PORT_16650V2;
801}
802
803
804
805
806
807
808static void autoconfig_8250(struct uart_8250_port *up)
809{
810 unsigned char scratch, status1, status2;
811
812 up->port.type = PORT_8250;
813
814 scratch = serial_in(up, UART_SCR);
815 serial_out(up, UART_SCR, 0xa5);
816 status1 = serial_in(up, UART_SCR);
817 serial_out(up, UART_SCR, 0x5a);
818 status2 = serial_in(up, UART_SCR);
819 serial_out(up, UART_SCR, scratch);
820
821 if (status1 == 0xa5 && status2 == 0x5a)
822 up->port.type = PORT_16450;
823}
824
825static int broken_efr(struct uart_8250_port *up)
826{
827
828
829
830
831
832 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
833 return 1;
834
835 return 0;
836}
837
838static inline int ns16550a_goto_highspeed(struct uart_8250_port *up)
839{
840 unsigned char status;
841
842 status = serial_in(up, 0x04);
843#define PRESL(x) ((x) & 0x30)
844 if (PRESL(status) == 0x10) {
845
846 return 0;
847 } else {
848 status &= ~0xB0;
849 status |= 0x10;
850 serial_out(up, 0x04, status);
851 }
852 return 1;
853}
854
855
856
857
858
859
860
861static void autoconfig_16550a(struct uart_8250_port *up)
862{
863 unsigned char status1, status2;
864 unsigned int iersave;
865
866 up->port.type = PORT_16550A;
867 up->capabilities |= UART_CAP_FIFO;
868
869
870
871
872
873
874
875
876
877 if (up->port.flags & UPF_EXAR_EFR) {
878 status1 = serial_in(up, UART_EXAR_DVID);
879 if (status1 == 0x82 || status1 == 0x84 || status1 == 0x88) {
880 DEBUG_AUTOCONF("Exar XR17V35x ");
881 up->port.type = PORT_XR17V35X;
882 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
883 UART_CAP_SLEEP;
884
885 return;
886 }
887
888 }
889
890
891
892
893
894 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
895 if (serial_in(up, UART_EFR) == 0) {
896 serial_out(up, UART_EFR, 0xA8);
897 if (serial_in(up, UART_EFR) != 0) {
898 DEBUG_AUTOCONF("EFRv1 ");
899 up->port.type = PORT_16650;
900 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
901 } else {
902 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
903 }
904 serial_out(up, UART_EFR, 0);
905 return;
906 }
907
908
909
910
911
912 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
913 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
914 DEBUG_AUTOCONF("EFRv2 ");
915 autoconfig_has_efr(up);
916 return;
917 }
918
919
920
921
922
923
924
925
926 serial_out(up, UART_LCR, 0);
927 status1 = serial_in(up, UART_MCR);
928 serial_out(up, UART_LCR, 0xE0);
929 status2 = serial_in(up, 0x02);
930
931 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
932 serial_out(up, UART_LCR, 0);
933 serial_out(up, UART_MCR, status1 ^ UART_MCR_LOOP);
934 serial_out(up, UART_LCR, 0xE0);
935 status2 = serial_in(up, 0x02);
936 serial_out(up, UART_LCR, 0);
937 serial_out(up, UART_MCR, status1);
938
939 if ((status2 ^ status1) & UART_MCR_LOOP) {
940 unsigned short quot;
941
942 serial_out(up, UART_LCR, 0xE0);
943
944 quot = serial_dl_read(up);
945 quot <<= 3;
946
947 if (ns16550a_goto_highspeed(up))
948 serial_dl_write(up, quot);
949
950 serial_out(up, UART_LCR, 0);
951
952 up->port.uartclk = 921600*16;
953 up->port.type = PORT_NS16550A;
954 up->capabilities |= UART_NATSEMI;
955 return;
956 }
957 }
958
959
960
961
962
963
964
965 serial_out(up, UART_LCR, 0);
966 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
967 status1 = serial_in(up, UART_IIR) >> 5;
968 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
969 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
970 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
971 status2 = serial_in(up, UART_IIR) >> 5;
972 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
973 serial_out(up, UART_LCR, 0);
974
975 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
976
977 if (status1 == 6 && status2 == 7) {
978 up->port.type = PORT_16750;
979 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
980 return;
981 }
982
983
984
985
986
987
988
989
990
991 iersave = serial_in(up, UART_IER);
992 serial_out(up, UART_IER, iersave & ~UART_IER_UUE);
993 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
994
995
996
997
998 serial_out(up, UART_IER, iersave | UART_IER_UUE);
999 if (serial_in(up, UART_IER) & UART_IER_UUE) {
1000
1001
1002
1003
1004 DEBUG_AUTOCONF("Xscale ");
1005 up->port.type = PORT_XSCALE;
1006 up->capabilities |= UART_CAP_UUE | UART_CAP_RTOIE;
1007 return;
1008 }
1009 } else {
1010
1011
1012
1013
1014 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
1015 }
1016 serial_out(up, UART_IER, iersave);
1017
1018
1019
1020
1021 if (up->port.flags & UPF_EXAR_EFR) {
1022 DEBUG_AUTOCONF("Exar XR17D15x ");
1023 up->port.type = PORT_XR17D15X;
1024 up->capabilities |= UART_CAP_AFE | UART_CAP_EFR |
1025 UART_CAP_SLEEP;
1026
1027 return;
1028 }
1029
1030
1031
1032
1033
1034 if (up->port.type == PORT_16550A && size_fifo(up) == 64) {
1035 up->port.type = PORT_U6_16550A;
1036 up->capabilities |= UART_CAP_AFE;
1037 }
1038}
1039
1040
1041
1042
1043
1044
1045
1046
1047static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
1048{
1049 unsigned char status1, scratch, scratch2, scratch3;
1050 unsigned char save_lcr, save_mcr;
1051 struct uart_port *port = &up->port;
1052 unsigned long flags;
1053 unsigned int old_capabilities;
1054
1055 if (!port->iobase && !port->mapbase && !port->membase)
1056 return;
1057
1058 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04lx, 0x%p): ",
1059 serial_index(port), port->iobase, port->membase);
1060
1061
1062
1063
1064
1065 spin_lock_irqsave(&port->lock, flags);
1066
1067 up->capabilities = 0;
1068 up->bugs = 0;
1069
1070 if (!(port->flags & UPF_BUGGY_UART)) {
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084 scratch = serial_in(up, UART_IER);
1085 serial_out(up, UART_IER, 0);
1086#ifdef __i386__
1087 outb(0xff, 0x080);
1088#endif
1089
1090
1091
1092
1093 scratch2 = serial_in(up, UART_IER) & 0x0f;
1094 serial_out(up, UART_IER, 0x0F);
1095#ifdef __i386__
1096 outb(0, 0x080);
1097#endif
1098 scratch3 = serial_in(up, UART_IER) & 0x0f;
1099 serial_out(up, UART_IER, scratch);
1100 if (scratch2 != 0 || scratch3 != 0x0F) {
1101
1102
1103
1104 spin_unlock_irqrestore(&port->lock, flags);
1105 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1106 scratch2, scratch3);
1107 goto out;
1108 }
1109 }
1110
1111 save_mcr = serial_in(up, UART_MCR);
1112 save_lcr = serial_in(up, UART_LCR);
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123 if (!(port->flags & UPF_SKIP_TEST)) {
1124 serial_out(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1125 status1 = serial_in(up, UART_MSR) & 0xF0;
1126 serial_out(up, UART_MCR, save_mcr);
1127 if (status1 != 0x90) {
1128 spin_unlock_irqrestore(&port->lock, flags);
1129 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1130 status1);
1131 goto out;
1132 }
1133 }
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1145 serial_out(up, UART_EFR, 0);
1146 serial_out(up, UART_LCR, 0);
1147
1148 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1149 scratch = serial_in(up, UART_IIR) >> 6;
1150
1151 switch (scratch) {
1152 case 0:
1153 autoconfig_8250(up);
1154 break;
1155 case 1:
1156 port->type = PORT_UNKNOWN;
1157 break;
1158 case 2:
1159 port->type = PORT_16550;
1160 break;
1161 case 3:
1162 autoconfig_16550a(up);
1163 break;
1164 }
1165
1166#ifdef CONFIG_SERIAL_8250_RSA
1167
1168
1169
1170 if (port->type == PORT_16550A && probeflags & PROBE_RSA) {
1171 int i;
1172
1173 for (i = 0 ; i < probe_rsa_count; ++i) {
1174 if (probe_rsa[i] == port->iobase && __enable_rsa(up)) {
1175 port->type = PORT_RSA;
1176 break;
1177 }
1178 }
1179 }
1180#endif
1181
1182 serial_out(up, UART_LCR, save_lcr);
1183
1184 port->fifosize = uart_config[up->port.type].fifo_size;
1185 old_capabilities = up->capabilities;
1186 up->capabilities = uart_config[port->type].flags;
1187 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1188
1189 if (port->type == PORT_UNKNOWN)
1190 goto out_lock;
1191
1192
1193
1194
1195#ifdef CONFIG_SERIAL_8250_RSA
1196 if (port->type == PORT_RSA)
1197 serial_out(up, UART_RSA_FRR, 0);
1198#endif
1199 serial_out(up, UART_MCR, save_mcr);
1200 serial8250_clear_fifos(up);
1201 serial_in(up, UART_RX);
1202 if (up->capabilities & UART_CAP_UUE)
1203 serial_out(up, UART_IER, UART_IER_UUE);
1204 else
1205 serial_out(up, UART_IER, 0);
1206
1207out_lock:
1208 spin_unlock_irqrestore(&port->lock, flags);
1209 if (up->capabilities != old_capabilities) {
1210 printk(KERN_WARNING
1211 "ttyS%d: detected caps %08x should be %08x\n",
1212 serial_index(port), old_capabilities,
1213 up->capabilities);
1214 }
1215out:
1216 DEBUG_AUTOCONF("iir=%d ", scratch);
1217 DEBUG_AUTOCONF("type=%s\n", uart_config[port->type].name);
1218}
1219
1220static void autoconfig_irq(struct uart_8250_port *up)
1221{
1222 struct uart_port *port = &up->port;
1223 unsigned char save_mcr, save_ier;
1224 unsigned char save_ICP = 0;
1225 unsigned int ICP = 0;
1226 unsigned long irqs;
1227 int irq;
1228
1229 if (port->flags & UPF_FOURPORT) {
1230 ICP = (port->iobase & 0xfe0) | 0x1f;
1231 save_ICP = inb_p(ICP);
1232 outb_p(0x80, ICP);
1233 inb_p(ICP);
1234 }
1235
1236
1237 probe_irq_off(probe_irq_on());
1238 save_mcr = serial_in(up, UART_MCR);
1239 save_ier = serial_in(up, UART_IER);
1240 serial_out(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1241
1242 irqs = probe_irq_on();
1243 serial_out(up, UART_MCR, 0);
1244 udelay(10);
1245 if (port->flags & UPF_FOURPORT) {
1246 serial_out(up, UART_MCR,
1247 UART_MCR_DTR | UART_MCR_RTS);
1248 } else {
1249 serial_out(up, UART_MCR,
1250 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1251 }
1252 serial_out(up, UART_IER, 0x0f);
1253 serial_in(up, UART_LSR);
1254 serial_in(up, UART_RX);
1255 serial_in(up, UART_IIR);
1256 serial_in(up, UART_MSR);
1257 serial_out(up, UART_TX, 0xFF);
1258 udelay(20);
1259 irq = probe_irq_off(irqs);
1260
1261 serial_out(up, UART_MCR, save_mcr);
1262 serial_out(up, UART_IER, save_ier);
1263
1264 if (port->flags & UPF_FOURPORT)
1265 outb_p(save_ICP, ICP);
1266
1267 port->irq = (irq > 0) ? irq : 0;
1268}
1269
1270static inline void __stop_tx(struct uart_8250_port *p)
1271{
1272 if (p->ier & UART_IER_THRI) {
1273 p->ier &= ~UART_IER_THRI;
1274 serial_out(p, UART_IER, p->ier);
1275 }
1276}
1277
1278static void serial8250_stop_tx(struct uart_port *port)
1279{
1280 struct uart_8250_port *up =
1281 container_of(port, struct uart_8250_port, port);
1282
1283 __stop_tx(up);
1284
1285
1286
1287
1288 if (port->type == PORT_16C950) {
1289 up->acr |= UART_ACR_TXDIS;
1290 serial_icr_write(up, UART_ACR, up->acr);
1291 }
1292}
1293
1294static void serial8250_start_tx(struct uart_port *port)
1295{
1296 struct uart_8250_port *up =
1297 container_of(port, struct uart_8250_port, port);
1298
1299 if (up->dma && !serial8250_tx_dma(up)) {
1300 return;
1301 } else if (!(up->ier & UART_IER_THRI)) {
1302 up->ier |= UART_IER_THRI;
1303 serial_port_out(port, UART_IER, up->ier);
1304
1305 if (up->bugs & UART_BUG_TXEN) {
1306 unsigned char lsr;
1307 lsr = serial_in(up, UART_LSR);
1308 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1309 if (lsr & UART_LSR_TEMT)
1310 serial8250_tx_chars(up);
1311 }
1312 }
1313
1314
1315
1316
1317 if (port->type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1318 up->acr &= ~UART_ACR_TXDIS;
1319 serial_icr_write(up, UART_ACR, up->acr);
1320 }
1321}
1322
1323static void serial8250_stop_rx(struct uart_port *port)
1324{
1325 struct uart_8250_port *up =
1326 container_of(port, struct uart_8250_port, port);
1327
1328 up->ier &= ~UART_IER_RLSI;
1329 up->port.read_status_mask &= ~UART_LSR_DR;
1330 serial_port_out(port, UART_IER, up->ier);
1331}
1332
1333static void serial8250_enable_ms(struct uart_port *port)
1334{
1335 struct uart_8250_port *up =
1336 container_of(port, struct uart_8250_port, port);
1337
1338
1339 if (up->bugs & UART_BUG_NOMSR)
1340 return;
1341
1342 up->ier |= UART_IER_MSI;
1343 serial_port_out(port, UART_IER, up->ier);
1344}
1345
1346
1347
1348
1349
1350
1351unsigned char
1352serial8250_rx_chars(struct uart_8250_port *up, unsigned char lsr)
1353{
1354 struct uart_port *port = &up->port;
1355 unsigned char ch;
1356 int max_count = 256;
1357 char flag;
1358
1359 do {
1360 if (likely(lsr & UART_LSR_DR))
1361 ch = serial_in(up, UART_RX);
1362 else
1363
1364
1365
1366
1367
1368
1369
1370 ch = 0;
1371
1372 flag = TTY_NORMAL;
1373 port->icount.rx++;
1374
1375 lsr |= up->lsr_saved_flags;
1376 up->lsr_saved_flags = 0;
1377
1378 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1379 if (lsr & UART_LSR_BI) {
1380 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1381 port->icount.brk++;
1382
1383
1384
1385
1386
1387
1388 if (uart_handle_break(port))
1389 goto ignore_char;
1390 } else if (lsr & UART_LSR_PE)
1391 port->icount.parity++;
1392 else if (lsr & UART_LSR_FE)
1393 port->icount.frame++;
1394 if (lsr & UART_LSR_OE)
1395 port->icount.overrun++;
1396
1397
1398
1399
1400 lsr &= port->read_status_mask;
1401
1402 if (lsr & UART_LSR_BI) {
1403 DEBUG_INTR("handling break....");
1404 flag = TTY_BREAK;
1405 } else if (lsr & UART_LSR_PE)
1406 flag = TTY_PARITY;
1407 else if (lsr & UART_LSR_FE)
1408 flag = TTY_FRAME;
1409 }
1410 if (uart_handle_sysrq_char(port, ch))
1411 goto ignore_char;
1412
1413 uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
1414
1415ignore_char:
1416 lsr = serial_in(up, UART_LSR);
1417 } while ((lsr & (UART_LSR_DR | UART_LSR_BI)) && (max_count-- > 0));
1418 spin_unlock(&port->lock);
1419 tty_flip_buffer_push(&port->state->port);
1420 spin_lock(&port->lock);
1421 return lsr;
1422}
1423EXPORT_SYMBOL_GPL(serial8250_rx_chars);
1424
1425void serial8250_tx_chars(struct uart_8250_port *up)
1426{
1427 struct uart_port *port = &up->port;
1428 struct circ_buf *xmit = &port->state->xmit;
1429 int count;
1430
1431 if (port->x_char) {
1432 serial_out(up, UART_TX, port->x_char);
1433 port->icount.tx++;
1434 port->x_char = 0;
1435 return;
1436 }
1437 if (uart_tx_stopped(port)) {
1438 serial8250_stop_tx(port);
1439 return;
1440 }
1441 if (uart_circ_empty(xmit)) {
1442 __stop_tx(up);
1443 return;
1444 }
1445
1446 count = up->tx_loadsz;
1447 do {
1448 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1449 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1450 port->icount.tx++;
1451 if (uart_circ_empty(xmit))
1452 break;
1453 if (up->capabilities & UART_CAP_HFIFO) {
1454 if ((serial_port_in(port, UART_LSR) & BOTH_EMPTY) !=
1455 BOTH_EMPTY)
1456 break;
1457 }
1458 } while (--count > 0);
1459
1460 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1461 uart_write_wakeup(port);
1462
1463 DEBUG_INTR("THRE...");
1464
1465 if (uart_circ_empty(xmit))
1466 __stop_tx(up);
1467}
1468EXPORT_SYMBOL_GPL(serial8250_tx_chars);
1469
1470unsigned int serial8250_modem_status(struct uart_8250_port *up)
1471{
1472 struct uart_port *port = &up->port;
1473 unsigned int status = serial_in(up, UART_MSR);
1474
1475 status |= up->msr_saved_flags;
1476 up->msr_saved_flags = 0;
1477 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1478 port->state != NULL) {
1479 if (status & UART_MSR_TERI)
1480 port->icount.rng++;
1481 if (status & UART_MSR_DDSR)
1482 port->icount.dsr++;
1483 if (status & UART_MSR_DDCD)
1484 uart_handle_dcd_change(port, status & UART_MSR_DCD);
1485 if (status & UART_MSR_DCTS)
1486 uart_handle_cts_change(port, status & UART_MSR_CTS);
1487
1488 wake_up_interruptible(&port->state->port.delta_msr_wait);
1489 }
1490
1491 return status;
1492}
1493EXPORT_SYMBOL_GPL(serial8250_modem_status);
1494
1495
1496
1497
1498int serial8250_handle_irq(struct uart_port *port, unsigned int iir)
1499{
1500 unsigned char status;
1501 unsigned long flags;
1502 struct uart_8250_port *up =
1503 container_of(port, struct uart_8250_port, port);
1504 int dma_err = 0;
1505
1506 if (iir & UART_IIR_NO_INT)
1507 return 0;
1508
1509 spin_lock_irqsave(&port->lock, flags);
1510
1511 status = serial_port_in(port, UART_LSR);
1512
1513 DEBUG_INTR("status = %x...", status);
1514
1515 if (status & (UART_LSR_DR | UART_LSR_BI)) {
1516 if (up->dma)
1517 dma_err = serial8250_rx_dma(up, iir);
1518
1519 if (!up->dma || dma_err)
1520 status = serial8250_rx_chars(up, status);
1521 }
1522 serial8250_modem_status(up);
1523 if (status & UART_LSR_THRE)
1524 serial8250_tx_chars(up);
1525
1526 spin_unlock_irqrestore(&port->lock, flags);
1527 return 1;
1528}
1529EXPORT_SYMBOL_GPL(serial8250_handle_irq);
1530
1531static int serial8250_default_handle_irq(struct uart_port *port)
1532{
1533 unsigned int iir = serial_port_in(port, UART_IIR);
1534
1535 return serial8250_handle_irq(port, iir);
1536}
1537
1538
1539
1540
1541
1542
1543
1544static int exar_handle_irq(struct uart_port *port)
1545{
1546 unsigned char int0, int1, int2, int3;
1547 unsigned int iir = serial_port_in(port, UART_IIR);
1548 int ret;
1549
1550 ret = serial8250_handle_irq(port, iir);
1551
1552 if ((port->type == PORT_XR17V35X) ||
1553 (port->type == PORT_XR17D15X)) {
1554 int0 = serial_port_in(port, 0x80);
1555 int1 = serial_port_in(port, 0x81);
1556 int2 = serial_port_in(port, 0x82);
1557 int3 = serial_port_in(port, 0x83);
1558 }
1559
1560 return ret;
1561}
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573
1574
1575
1576
1577static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1578{
1579 struct irq_info *i = dev_id;
1580 struct list_head *l, *end = NULL;
1581 int pass_counter = 0, handled = 0;
1582
1583 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1584
1585 spin_lock(&i->lock);
1586
1587 l = i->head;
1588 do {
1589 struct uart_8250_port *up;
1590 struct uart_port *port;
1591
1592 up = list_entry(l, struct uart_8250_port, list);
1593 port = &up->port;
1594
1595 if (port->handle_irq(port)) {
1596 handled = 1;
1597 end = NULL;
1598 } else if (end == NULL)
1599 end = l;
1600
1601 l = l->next;
1602
1603 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1604
1605 printk_ratelimited(KERN_ERR
1606 "serial8250: too much work for irq%d\n", irq);
1607 break;
1608 }
1609 } while (l != end);
1610
1611 spin_unlock(&i->lock);
1612
1613 DEBUG_INTR("end.\n");
1614
1615 return IRQ_RETVAL(handled);
1616}
1617
1618
1619
1620
1621
1622
1623
1624
1625static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1626{
1627 spin_lock_irq(&i->lock);
1628
1629 if (!list_empty(i->head)) {
1630 if (i->head == &up->list)
1631 i->head = i->head->next;
1632 list_del(&up->list);
1633 } else {
1634 BUG_ON(i->head != &up->list);
1635 i->head = NULL;
1636 }
1637 spin_unlock_irq(&i->lock);
1638
1639 if (i->head == NULL) {
1640 hlist_del(&i->node);
1641 kfree(i);
1642 }
1643}
1644
1645static int serial_link_irq_chain(struct uart_8250_port *up)
1646{
1647 struct hlist_head *h;
1648 struct hlist_node *n;
1649 struct irq_info *i;
1650 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1651
1652 mutex_lock(&hash_mutex);
1653
1654 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1655
1656 hlist_for_each(n, h) {
1657 i = hlist_entry(n, struct irq_info, node);
1658 if (i->irq == up->port.irq)
1659 break;
1660 }
1661
1662 if (n == NULL) {
1663 i = kzalloc(sizeof(struct irq_info), GFP_KERNEL);
1664 if (i == NULL) {
1665 mutex_unlock(&hash_mutex);
1666 return -ENOMEM;
1667 }
1668 spin_lock_init(&i->lock);
1669 i->irq = up->port.irq;
1670 hlist_add_head(&i->node, h);
1671 }
1672 mutex_unlock(&hash_mutex);
1673
1674 spin_lock_irq(&i->lock);
1675
1676 if (i->head) {
1677 list_add(&up->list, i->head);
1678 spin_unlock_irq(&i->lock);
1679
1680 ret = 0;
1681 } else {
1682 INIT_LIST_HEAD(&up->list);
1683 i->head = &up->list;
1684 spin_unlock_irq(&i->lock);
1685 irq_flags |= up->port.irqflags;
1686 ret = request_irq(up->port.irq, serial8250_interrupt,
1687 irq_flags, "serial", i);
1688 if (ret < 0)
1689 serial_do_unlink(i, up);
1690 }
1691
1692 return ret;
1693}
1694
1695static void serial_unlink_irq_chain(struct uart_8250_port *up)
1696{
1697 struct irq_info *i;
1698 struct hlist_node *n;
1699 struct hlist_head *h;
1700
1701 mutex_lock(&hash_mutex);
1702
1703 h = &irq_lists[up->port.irq % NR_IRQ_HASH];
1704
1705 hlist_for_each(n, h) {
1706 i = hlist_entry(n, struct irq_info, node);
1707 if (i->irq == up->port.irq)
1708 break;
1709 }
1710
1711 BUG_ON(n == NULL);
1712 BUG_ON(i->head == NULL);
1713
1714 if (list_empty(i->head))
1715 free_irq(up->port.irq, i);
1716
1717 serial_do_unlink(i, up);
1718 mutex_unlock(&hash_mutex);
1719}
1720
1721
1722
1723
1724
1725
1726
1727static void serial8250_timeout(unsigned long data)
1728{
1729 struct uart_8250_port *up = (struct uart_8250_port *)data;
1730
1731 up->port.handle_irq(&up->port);
1732 mod_timer(&up->timer, jiffies + uart_poll_timeout(&up->port));
1733}
1734
1735static void serial8250_backup_timeout(unsigned long data)
1736{
1737 struct uart_8250_port *up = (struct uart_8250_port *)data;
1738 unsigned int iir, ier = 0, lsr;
1739 unsigned long flags;
1740
1741 spin_lock_irqsave(&up->port.lock, flags);
1742
1743
1744
1745
1746
1747 if (up->port.irq) {
1748 ier = serial_in(up, UART_IER);
1749 serial_out(up, UART_IER, 0);
1750 }
1751
1752 iir = serial_in(up, UART_IIR);
1753
1754
1755
1756
1757
1758
1759
1760 lsr = serial_in(up, UART_LSR);
1761 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1762 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1763 (!uart_circ_empty(&up->port.state->xmit) || up->port.x_char) &&
1764 (lsr & UART_LSR_THRE)) {
1765 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1766 iir |= UART_IIR_THRI;
1767 }
1768
1769 if (!(iir & UART_IIR_NO_INT))
1770 serial8250_tx_chars(up);
1771
1772 if (up->port.irq)
1773 serial_out(up, UART_IER, ier);
1774
1775 spin_unlock_irqrestore(&up->port.lock, flags);
1776
1777
1778 mod_timer(&up->timer,
1779 jiffies + uart_poll_timeout(&up->port) + HZ / 5);
1780}
1781
1782static unsigned int serial8250_tx_empty(struct uart_port *port)
1783{
1784 struct uart_8250_port *up =
1785 container_of(port, struct uart_8250_port, port);
1786 unsigned long flags;
1787 unsigned int lsr;
1788
1789 spin_lock_irqsave(&port->lock, flags);
1790 lsr = serial_port_in(port, UART_LSR);
1791 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1792 spin_unlock_irqrestore(&port->lock, flags);
1793
1794 return (lsr & BOTH_EMPTY) == BOTH_EMPTY ? TIOCSER_TEMT : 0;
1795}
1796
1797static unsigned int serial8250_get_mctrl(struct uart_port *port)
1798{
1799 struct uart_8250_port *up =
1800 container_of(port, struct uart_8250_port, port);
1801 unsigned int status;
1802 unsigned int ret;
1803
1804 status = serial8250_modem_status(up);
1805
1806 ret = 0;
1807 if (status & UART_MSR_DCD)
1808 ret |= TIOCM_CAR;
1809 if (status & UART_MSR_RI)
1810 ret |= TIOCM_RNG;
1811 if (status & UART_MSR_DSR)
1812 ret |= TIOCM_DSR;
1813 if (status & UART_MSR_CTS)
1814 ret |= TIOCM_CTS;
1815 return ret;
1816}
1817
1818static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1819{
1820 struct uart_8250_port *up =
1821 container_of(port, struct uart_8250_port, port);
1822 unsigned char mcr = 0;
1823
1824 if (mctrl & TIOCM_RTS)
1825 mcr |= UART_MCR_RTS;
1826 if (mctrl & TIOCM_DTR)
1827 mcr |= UART_MCR_DTR;
1828 if (mctrl & TIOCM_OUT1)
1829 mcr |= UART_MCR_OUT1;
1830 if (mctrl & TIOCM_OUT2)
1831 mcr |= UART_MCR_OUT2;
1832 if (mctrl & TIOCM_LOOP)
1833 mcr |= UART_MCR_LOOP;
1834
1835 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1836
1837 serial_port_out(port, UART_MCR, mcr);
1838}
1839
1840static void serial8250_break_ctl(struct uart_port *port, int break_state)
1841{
1842 struct uart_8250_port *up =
1843 container_of(port, struct uart_8250_port, port);
1844 unsigned long flags;
1845
1846 spin_lock_irqsave(&port->lock, flags);
1847 if (break_state == -1)
1848 up->lcr |= UART_LCR_SBC;
1849 else
1850 up->lcr &= ~UART_LCR_SBC;
1851 serial_port_out(port, UART_LCR, up->lcr);
1852 spin_unlock_irqrestore(&port->lock, flags);
1853}
1854
1855
1856
1857
1858static void wait_for_xmitr(struct uart_8250_port *up, int bits)
1859{
1860 unsigned int status, tmout = 10000;
1861
1862
1863 for (;;) {
1864 status = serial_in(up, UART_LSR);
1865
1866 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1867
1868 if ((status & bits) == bits)
1869 break;
1870 if (--tmout == 0)
1871 break;
1872 udelay(1);
1873 }
1874
1875
1876 if (up->port.flags & UPF_CONS_FLOW) {
1877 unsigned int tmout;
1878 for (tmout = 1000000; tmout; tmout--) {
1879 unsigned int msr = serial_in(up, UART_MSR);
1880 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1881 if (msr & UART_MSR_CTS)
1882 break;
1883 udelay(1);
1884 touch_nmi_watchdog();
1885 }
1886 }
1887}
1888
1889#ifdef CONFIG_CONSOLE_POLL
1890
1891
1892
1893
1894
1895static int serial8250_get_poll_char(struct uart_port *port)
1896{
1897 unsigned char lsr = serial_port_in(port, UART_LSR);
1898
1899 if (!(lsr & UART_LSR_DR))
1900 return NO_POLL_CHAR;
1901
1902 return serial_port_in(port, UART_RX);
1903}
1904
1905
1906static void serial8250_put_poll_char(struct uart_port *port,
1907 unsigned char c)
1908{
1909 unsigned int ier;
1910 struct uart_8250_port *up =
1911 container_of(port, struct uart_8250_port, port);
1912
1913
1914
1915
1916 ier = serial_port_in(port, UART_IER);
1917 if (up->capabilities & UART_CAP_UUE)
1918 serial_port_out(port, UART_IER, UART_IER_UUE);
1919 else
1920 serial_port_out(port, UART_IER, 0);
1921
1922 wait_for_xmitr(up, BOTH_EMPTY);
1923
1924
1925
1926
1927 serial_port_out(port, UART_TX, c);
1928 if (c == 10) {
1929 wait_for_xmitr(up, BOTH_EMPTY);
1930 serial_port_out(port, UART_TX, 13);
1931 }
1932
1933
1934
1935
1936
1937 wait_for_xmitr(up, BOTH_EMPTY);
1938 serial_port_out(port, UART_IER, ier);
1939}
1940
1941#endif
1942
1943static int serial8250_startup(struct uart_port *port)
1944{
1945 struct uart_8250_port *up =
1946 container_of(port, struct uart_8250_port, port);
1947 unsigned long flags;
1948 unsigned char lsr, iir;
1949 int retval;
1950
1951 if (port->type == PORT_8250_CIR)
1952 return -ENODEV;
1953
1954 if (!port->fifosize)
1955 port->fifosize = uart_config[port->type].fifo_size;
1956 if (!up->tx_loadsz)
1957 up->tx_loadsz = uart_config[port->type].tx_loadsz;
1958 if (!up->capabilities)
1959 up->capabilities = uart_config[port->type].flags;
1960 up->mcr = 0;
1961
1962 if (port->iotype != up->cur_iotype)
1963 set_io_from_upio(port);
1964
1965 if (port->type == PORT_16C950) {
1966
1967 up->acr = 0;
1968 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1969 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1970 serial_port_out(port, UART_IER, 0);
1971 serial_port_out(port, UART_LCR, 0);
1972 serial_icr_write(up, UART_CSR, 0);
1973 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
1974 serial_port_out(port, UART_EFR, UART_EFR_ECB);
1975 serial_port_out(port, UART_LCR, 0);
1976 }
1977
1978#ifdef CONFIG_SERIAL_8250_RSA
1979
1980
1981
1982
1983 enable_rsa(up);
1984#endif
1985
1986
1987
1988
1989
1990 serial8250_clear_fifos(up);
1991
1992
1993
1994
1995 serial_port_in(port, UART_LSR);
1996 serial_port_in(port, UART_RX);
1997 serial_port_in(port, UART_IIR);
1998 serial_port_in(port, UART_MSR);
1999
2000
2001
2002
2003
2004
2005 if (!(port->flags & UPF_BUGGY_UART) &&
2006 (serial_port_in(port, UART_LSR) == 0xff)) {
2007 printk_ratelimited(KERN_INFO "ttyS%d: LSR safety check engaged!\n",
2008 serial_index(port));
2009 return -ENODEV;
2010 }
2011
2012
2013
2014
2015 if (port->type == PORT_16850) {
2016 unsigned char fctr;
2017
2018 serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
2019
2020 fctr = serial_in(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
2021 serial_port_out(port, UART_FCTR,
2022 fctr | UART_FCTR_TRGD | UART_FCTR_RX);
2023 serial_port_out(port, UART_TRG, UART_TRG_96);
2024 serial_port_out(port, UART_FCTR,
2025 fctr | UART_FCTR_TRGD | UART_FCTR_TX);
2026 serial_port_out(port, UART_TRG, UART_TRG_96);
2027
2028 serial_port_out(port, UART_LCR, 0);
2029 }
2030
2031 if (port->irq) {
2032 unsigned char iir1;
2033
2034
2035
2036
2037
2038
2039
2040
2041 spin_lock_irqsave(&port->lock, flags);
2042 if (up->port.irqflags & IRQF_SHARED)
2043 disable_irq_nosync(port->irq);
2044
2045 wait_for_xmitr(up, UART_LSR_THRE);
2046 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2047 udelay(1);
2048 iir1 = serial_port_in(port, UART_IIR);
2049 serial_port_out(port, UART_IER, 0);
2050 serial_port_out_sync(port, UART_IER, UART_IER_THRI);
2051 udelay(1);
2052 iir = serial_port_in(port, UART_IIR);
2053 serial_port_out(port, UART_IER, 0);
2054
2055 if (port->irqflags & IRQF_SHARED)
2056 enable_irq(port->irq);
2057 spin_unlock_irqrestore(&port->lock, flags);
2058
2059
2060
2061
2062
2063
2064 if ((!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) ||
2065 up->port.flags & UPF_BUG_THRE) {
2066 up->bugs |= UART_BUG_THRE;
2067 pr_debug("ttyS%d - using backup timer\n",
2068 serial_index(port));
2069 }
2070 }
2071
2072
2073
2074
2075
2076 if (up->bugs & UART_BUG_THRE) {
2077 up->timer.function = serial8250_backup_timeout;
2078 up->timer.data = (unsigned long)up;
2079 mod_timer(&up->timer, jiffies +
2080 uart_poll_timeout(port) + HZ / 5);
2081 }
2082
2083
2084
2085
2086
2087
2088 if (!port->irq) {
2089 up->timer.data = (unsigned long)up;
2090 mod_timer(&up->timer, jiffies + uart_poll_timeout(port));
2091 } else {
2092 retval = serial_link_irq_chain(up);
2093 if (retval)
2094 return retval;
2095 }
2096
2097
2098
2099
2100 serial_port_out(port, UART_LCR, UART_LCR_WLEN8);
2101
2102 spin_lock_irqsave(&port->lock, flags);
2103 if (up->port.flags & UPF_FOURPORT) {
2104 if (!up->port.irq)
2105 up->port.mctrl |= TIOCM_OUT1;
2106 } else
2107
2108
2109
2110 if (port->irq)
2111 up->port.mctrl |= TIOCM_OUT2;
2112
2113 serial8250_set_mctrl(port, port->mctrl);
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126 if (skip_txen_test || up->port.flags & UPF_NO_TXEN_TEST)
2127 goto dont_test_tx_en;
2128
2129
2130
2131
2132
2133 serial_port_out(port, UART_IER, UART_IER_THRI);
2134 lsr = serial_port_in(port, UART_LSR);
2135 iir = serial_port_in(port, UART_IIR);
2136 serial_port_out(port, UART_IER, 0);
2137
2138 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
2139 if (!(up->bugs & UART_BUG_TXEN)) {
2140 up->bugs |= UART_BUG_TXEN;
2141 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
2142 serial_index(port));
2143 }
2144 } else {
2145 up->bugs &= ~UART_BUG_TXEN;
2146 }
2147
2148dont_test_tx_en:
2149 spin_unlock_irqrestore(&port->lock, flags);
2150
2151
2152
2153
2154
2155
2156 serial_port_in(port, UART_LSR);
2157 serial_port_in(port, UART_RX);
2158 serial_port_in(port, UART_IIR);
2159 serial_port_in(port, UART_MSR);
2160 up->lsr_saved_flags = 0;
2161 up->msr_saved_flags = 0;
2162
2163
2164
2165
2166 if (up->dma) {
2167 retval = serial8250_request_dma(up);
2168 if (retval) {
2169 pr_warn_ratelimited("ttyS%d - failed to request DMA\n",
2170 serial_index(port));
2171 up->dma = NULL;
2172 }
2173 }
2174
2175
2176
2177
2178
2179
2180 up->ier = UART_IER_RLSI | UART_IER_RDI;
2181 serial_port_out(port, UART_IER, up->ier);
2182
2183 if (port->flags & UPF_FOURPORT) {
2184 unsigned int icp;
2185
2186
2187
2188 icp = (port->iobase & 0xfe0) | 0x01f;
2189 outb_p(0x80, icp);
2190 inb_p(icp);
2191 }
2192
2193 return 0;
2194}
2195
2196static void serial8250_shutdown(struct uart_port *port)
2197{
2198 struct uart_8250_port *up =
2199 container_of(port, struct uart_8250_port, port);
2200 unsigned long flags;
2201
2202
2203
2204
2205 up->ier = 0;
2206 serial_port_out(port, UART_IER, 0);
2207
2208 if (up->dma)
2209 serial8250_release_dma(up);
2210
2211 spin_lock_irqsave(&port->lock, flags);
2212 if (port->flags & UPF_FOURPORT) {
2213
2214 inb((port->iobase & 0xfe0) | 0x1f);
2215 port->mctrl |= TIOCM_OUT1;
2216 } else
2217 port->mctrl &= ~TIOCM_OUT2;
2218
2219 serial8250_set_mctrl(port, port->mctrl);
2220 spin_unlock_irqrestore(&port->lock, flags);
2221
2222
2223
2224
2225 serial_port_out(port, UART_LCR,
2226 serial_port_in(port, UART_LCR) & ~UART_LCR_SBC);
2227 serial8250_clear_fifos(up);
2228
2229#ifdef CONFIG_SERIAL_8250_RSA
2230
2231
2232
2233 disable_rsa(up);
2234#endif
2235
2236
2237
2238
2239
2240 serial_port_in(port, UART_RX);
2241
2242 del_timer_sync(&up->timer);
2243 up->timer.function = serial8250_timeout;
2244 if (port->irq)
2245 serial_unlink_irq_chain(up);
2246}
2247
2248static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2249{
2250 unsigned int quot;
2251
2252
2253
2254
2255
2256 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2257 baud == (port->uartclk/4))
2258 quot = 0x8001;
2259 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2260 baud == (port->uartclk/8))
2261 quot = 0x8002;
2262 else
2263 quot = uart_get_divisor(port, baud);
2264
2265 return quot;
2266}
2267
2268void
2269serial8250_do_set_termios(struct uart_port *port, struct ktermios *termios,
2270 struct ktermios *old)
2271{
2272 struct uart_8250_port *up =
2273 container_of(port, struct uart_8250_port, port);
2274 unsigned char cval, fcr = 0;
2275 unsigned long flags;
2276 unsigned int baud, quot;
2277 int fifo_bug = 0;
2278
2279 switch (termios->c_cflag & CSIZE) {
2280 case CS5:
2281 cval = UART_LCR_WLEN5;
2282 break;
2283 case CS6:
2284 cval = UART_LCR_WLEN6;
2285 break;
2286 case CS7:
2287 cval = UART_LCR_WLEN7;
2288 break;
2289 default:
2290 case CS8:
2291 cval = UART_LCR_WLEN8;
2292 break;
2293 }
2294
2295 if (termios->c_cflag & CSTOPB)
2296 cval |= UART_LCR_STOP;
2297 if (termios->c_cflag & PARENB) {
2298 cval |= UART_LCR_PARITY;
2299 if (up->bugs & UART_BUG_PARITY)
2300 fifo_bug = 1;
2301 }
2302 if (!(termios->c_cflag & PARODD))
2303 cval |= UART_LCR_EPAR;
2304#ifdef CMSPAR
2305 if (termios->c_cflag & CMSPAR)
2306 cval |= UART_LCR_SPAR;
2307#endif
2308
2309
2310
2311
2312 baud = uart_get_baud_rate(port, termios, old,
2313 port->uartclk / 16 / 0xffff,
2314 port->uartclk / 16);
2315 quot = serial8250_get_divisor(port, baud);
2316
2317
2318
2319
2320 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2321 quot++;
2322
2323 if (up->capabilities & UART_CAP_FIFO && port->fifosize > 1) {
2324 fcr = uart_config[port->type].fcr;
2325 if (baud < 2400 || fifo_bug) {
2326 fcr &= ~UART_FCR_TRIGGER_MASK;
2327 fcr |= UART_FCR_TRIGGER_1;
2328 }
2329 }
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339 if (up->capabilities & UART_CAP_AFE && port->fifosize >= 32) {
2340 up->mcr &= ~UART_MCR_AFE;
2341 if (termios->c_cflag & CRTSCTS)
2342 up->mcr |= UART_MCR_AFE;
2343 }
2344
2345
2346
2347
2348
2349 spin_lock_irqsave(&port->lock, flags);
2350
2351
2352
2353
2354 uart_update_timeout(port, termios->c_cflag, baud);
2355
2356 port->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2357 if (termios->c_iflag & INPCK)
2358 port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2359 if (termios->c_iflag & (BRKINT | PARMRK))
2360 port->read_status_mask |= UART_LSR_BI;
2361
2362
2363
2364
2365 port->ignore_status_mask = 0;
2366 if (termios->c_iflag & IGNPAR)
2367 port->ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2368 if (termios->c_iflag & IGNBRK) {
2369 port->ignore_status_mask |= UART_LSR_BI;
2370
2371
2372
2373
2374 if (termios->c_iflag & IGNPAR)
2375 port->ignore_status_mask |= UART_LSR_OE;
2376 }
2377
2378
2379
2380
2381 if ((termios->c_cflag & CREAD) == 0)
2382 port->ignore_status_mask |= UART_LSR_DR;
2383
2384
2385
2386
2387 up->ier &= ~UART_IER_MSI;
2388 if (!(up->bugs & UART_BUG_NOMSR) &&
2389 UART_ENABLE_MS(&up->port, termios->c_cflag))
2390 up->ier |= UART_IER_MSI;
2391 if (up->capabilities & UART_CAP_UUE)
2392 up->ier |= UART_IER_UUE;
2393 if (up->capabilities & UART_CAP_RTOIE)
2394 up->ier |= UART_IER_RTOIE;
2395
2396 serial_port_out(port, UART_IER, up->ier);
2397
2398 if (up->capabilities & UART_CAP_EFR) {
2399 unsigned char efr = 0;
2400
2401
2402
2403
2404
2405 if (termios->c_cflag & CRTSCTS)
2406 efr |= UART_EFR_CTS;
2407
2408 serial_port_out(port, UART_LCR, UART_LCR_CONF_MODE_B);
2409 if (port->flags & UPF_EXAR_EFR)
2410 serial_port_out(port, UART_XR_EFR, efr);
2411 else
2412 serial_port_out(port, UART_EFR, efr);
2413 }
2414
2415
2416 if (is_omap1510_8250(up)) {
2417 if (baud == 115200) {
2418 quot = 1;
2419 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 1);
2420 } else
2421 serial_port_out(port, UART_OMAP_OSC_12M_SEL, 0);
2422 }
2423
2424
2425
2426
2427
2428 if (up->capabilities & UART_NATSEMI)
2429 serial_port_out(port, UART_LCR, 0xe0);
2430 else
2431 serial_port_out(port, UART_LCR, cval | UART_LCR_DLAB);
2432
2433 serial_dl_write(up, quot);
2434
2435
2436
2437
2438
2439 if (port->type == PORT_16750)
2440 serial_port_out(port, UART_FCR, fcr);
2441
2442 serial_port_out(port, UART_LCR, cval);
2443 up->lcr = cval;
2444 if (port->type != PORT_16750) {
2445
2446 if (fcr & UART_FCR_ENABLE_FIFO)
2447 serial_port_out(port, UART_FCR, UART_FCR_ENABLE_FIFO);
2448 serial_port_out(port, UART_FCR, fcr);
2449 }
2450 serial8250_set_mctrl(port, port->mctrl);
2451 spin_unlock_irqrestore(&port->lock, flags);
2452
2453 if (tty_termios_baud_rate(termios))
2454 tty_termios_encode_baud_rate(termios, baud, baud);
2455}
2456EXPORT_SYMBOL(serial8250_do_set_termios);
2457
2458static void
2459serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2460 struct ktermios *old)
2461{
2462 if (port->set_termios)
2463 port->set_termios(port, termios, old);
2464 else
2465 serial8250_do_set_termios(port, termios, old);
2466}
2467
2468static void
2469serial8250_set_ldisc(struct uart_port *port, int new)
2470{
2471 if (new == N_PPS) {
2472 port->flags |= UPF_HARDPPS_CD;
2473 serial8250_enable_ms(port);
2474 } else
2475 port->flags &= ~UPF_HARDPPS_CD;
2476}
2477
2478
2479void serial8250_do_pm(struct uart_port *port, unsigned int state,
2480 unsigned int oldstate)
2481{
2482 struct uart_8250_port *p =
2483 container_of(port, struct uart_8250_port, port);
2484
2485 serial8250_set_sleep(p, state != 0);
2486}
2487EXPORT_SYMBOL(serial8250_do_pm);
2488
2489static void
2490serial8250_pm(struct uart_port *port, unsigned int state,
2491 unsigned int oldstate)
2492{
2493 if (port->pm)
2494 port->pm(port, state, oldstate);
2495 else
2496 serial8250_do_pm(port, state, oldstate);
2497}
2498
2499static unsigned int serial8250_port_size(struct uart_8250_port *pt)
2500{
2501 if (pt->port.iotype == UPIO_AU)
2502 return 0x1000;
2503 if (is_omap1_8250(pt))
2504 return 0x16 << pt->port.regshift;
2505
2506 return 8 << pt->port.regshift;
2507}
2508
2509
2510
2511
2512static int serial8250_request_std_resource(struct uart_8250_port *up)
2513{
2514 unsigned int size = serial8250_port_size(up);
2515 struct uart_port *port = &up->port;
2516 int ret = 0;
2517
2518 switch (port->iotype) {
2519 case UPIO_AU:
2520 case UPIO_TSI:
2521 case UPIO_MEM32:
2522 case UPIO_MEM:
2523 if (!port->mapbase)
2524 break;
2525
2526 if (!request_mem_region(port->mapbase, size, "serial")) {
2527 ret = -EBUSY;
2528 break;
2529 }
2530
2531 if (port->flags & UPF_IOREMAP) {
2532 port->membase = ioremap_nocache(port->mapbase, size);
2533 if (!port->membase) {
2534 release_mem_region(port->mapbase, size);
2535 ret = -ENOMEM;
2536 }
2537 }
2538 break;
2539
2540 case UPIO_HUB6:
2541 case UPIO_PORT:
2542 if (!request_region(port->iobase, size, "serial"))
2543 ret = -EBUSY;
2544 break;
2545 }
2546 return ret;
2547}
2548
2549static void serial8250_release_std_resource(struct uart_8250_port *up)
2550{
2551 unsigned int size = serial8250_port_size(up);
2552 struct uart_port *port = &up->port;
2553
2554 switch (port->iotype) {
2555 case UPIO_AU:
2556 case UPIO_TSI:
2557 case UPIO_MEM32:
2558 case UPIO_MEM:
2559 if (!port->mapbase)
2560 break;
2561
2562 if (port->flags & UPF_IOREMAP) {
2563 iounmap(port->membase);
2564 port->membase = NULL;
2565 }
2566
2567 release_mem_region(port->mapbase, size);
2568 break;
2569
2570 case UPIO_HUB6:
2571 case UPIO_PORT:
2572 release_region(port->iobase, size);
2573 break;
2574 }
2575}
2576
2577static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2578{
2579 unsigned long start = UART_RSA_BASE << up->port.regshift;
2580 unsigned int size = 8 << up->port.regshift;
2581 struct uart_port *port = &up->port;
2582 int ret = -EINVAL;
2583
2584 switch (port->iotype) {
2585 case UPIO_HUB6:
2586 case UPIO_PORT:
2587 start += port->iobase;
2588 if (request_region(start, size, "serial-rsa"))
2589 ret = 0;
2590 else
2591 ret = -EBUSY;
2592 break;
2593 }
2594
2595 return ret;
2596}
2597
2598static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2599{
2600 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2601 unsigned int size = 8 << up->port.regshift;
2602 struct uart_port *port = &up->port;
2603
2604 switch (port->iotype) {
2605 case UPIO_HUB6:
2606 case UPIO_PORT:
2607 release_region(port->iobase + offset, size);
2608 break;
2609 }
2610}
2611
2612static void serial8250_release_port(struct uart_port *port)
2613{
2614 struct uart_8250_port *up =
2615 container_of(port, struct uart_8250_port, port);
2616
2617 serial8250_release_std_resource(up);
2618 if (port->type == PORT_RSA)
2619 serial8250_release_rsa_resource(up);
2620}
2621
2622static int serial8250_request_port(struct uart_port *port)
2623{
2624 struct uart_8250_port *up =
2625 container_of(port, struct uart_8250_port, port);
2626 int ret;
2627
2628 if (port->type == PORT_8250_CIR)
2629 return -ENODEV;
2630
2631 ret = serial8250_request_std_resource(up);
2632 if (ret == 0 && port->type == PORT_RSA) {
2633 ret = serial8250_request_rsa_resource(up);
2634 if (ret < 0)
2635 serial8250_release_std_resource(up);
2636 }
2637
2638 return ret;
2639}
2640
2641static void serial8250_config_port(struct uart_port *port, int flags)
2642{
2643 struct uart_8250_port *up =
2644 container_of(port, struct uart_8250_port, port);
2645 int probeflags = PROBE_ANY;
2646 int ret;
2647
2648 if (port->type == PORT_8250_CIR)
2649 return;
2650
2651
2652
2653
2654
2655 ret = serial8250_request_std_resource(up);
2656 if (ret < 0)
2657 return;
2658
2659 ret = serial8250_request_rsa_resource(up);
2660 if (ret < 0)
2661 probeflags &= ~PROBE_RSA;
2662
2663 if (port->iotype != up->cur_iotype)
2664 set_io_from_upio(port);
2665
2666 if (flags & UART_CONFIG_TYPE)
2667 autoconfig(up, probeflags);
2668
2669
2670 if (port->type == PORT_16550A && port->iotype == UPIO_AU)
2671 up->bugs |= UART_BUG_NOMSR;
2672
2673 if (port->type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2674 autoconfig_irq(up);
2675
2676 if (port->type != PORT_RSA && probeflags & PROBE_RSA)
2677 serial8250_release_rsa_resource(up);
2678 if (port->type == PORT_UNKNOWN)
2679 serial8250_release_std_resource(up);
2680
2681
2682 if ((port->type == PORT_XR17V35X) ||
2683 (port->type == PORT_XR17D15X))
2684 port->handle_irq = exar_handle_irq;
2685}
2686
2687static int
2688serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2689{
2690 if (ser->irq >= nr_irqs || ser->irq < 0 ||
2691 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2692 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2693 ser->type == PORT_STARTECH)
2694 return -EINVAL;
2695 return 0;
2696}
2697
2698static const char *
2699serial8250_type(struct uart_port *port)
2700{
2701 int type = port->type;
2702
2703 if (type >= ARRAY_SIZE(uart_config))
2704 type = 0;
2705 return uart_config[type].name;
2706}
2707
2708static struct uart_ops serial8250_pops = {
2709 .tx_empty = serial8250_tx_empty,
2710 .set_mctrl = serial8250_set_mctrl,
2711 .get_mctrl = serial8250_get_mctrl,
2712 .stop_tx = serial8250_stop_tx,
2713 .start_tx = serial8250_start_tx,
2714 .stop_rx = serial8250_stop_rx,
2715 .enable_ms = serial8250_enable_ms,
2716 .break_ctl = serial8250_break_ctl,
2717 .startup = serial8250_startup,
2718 .shutdown = serial8250_shutdown,
2719 .set_termios = serial8250_set_termios,
2720 .set_ldisc = serial8250_set_ldisc,
2721 .pm = serial8250_pm,
2722 .type = serial8250_type,
2723 .release_port = serial8250_release_port,
2724 .request_port = serial8250_request_port,
2725 .config_port = serial8250_config_port,
2726 .verify_port = serial8250_verify_port,
2727#ifdef CONFIG_CONSOLE_POLL
2728 .poll_get_char = serial8250_get_poll_char,
2729 .poll_put_char = serial8250_put_poll_char,
2730#endif
2731};
2732
2733static struct uart_8250_port serial8250_ports[UART_NR];
2734
2735static void (*serial8250_isa_config)(int port, struct uart_port *up,
2736 unsigned short *capabilities);
2737
2738void serial8250_set_isa_configurator(
2739 void (*v)(int port, struct uart_port *up, unsigned short *capabilities))
2740{
2741 serial8250_isa_config = v;
2742}
2743EXPORT_SYMBOL(serial8250_set_isa_configurator);
2744
2745static void __init serial8250_isa_init_ports(void)
2746{
2747 struct uart_8250_port *up;
2748 static int first = 1;
2749 int i, irqflag = 0;
2750
2751 if (!first)
2752 return;
2753 first = 0;
2754
2755 if (nr_uarts > UART_NR)
2756 nr_uarts = UART_NR;
2757
2758 for (i = 0; i < nr_uarts; i++) {
2759 struct uart_8250_port *up = &serial8250_ports[i];
2760 struct uart_port *port = &up->port;
2761
2762 port->line = i;
2763 spin_lock_init(&port->lock);
2764
2765 init_timer(&up->timer);
2766 up->timer.function = serial8250_timeout;
2767 up->cur_iotype = 0xFF;
2768
2769
2770
2771
2772 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2773 up->mcr_force = ALPHA_KLUDGE_MCR;
2774
2775 port->ops = &serial8250_pops;
2776 }
2777
2778 if (share_irqs)
2779 irqflag = IRQF_SHARED;
2780
2781 for (i = 0, up = serial8250_ports;
2782 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2783 i++, up++) {
2784 struct uart_port *port = &up->port;
2785
2786 port->iobase = old_serial_port[i].port;
2787 port->irq = irq_canonicalize(old_serial_port[i].irq);
2788 port->irqflags = old_serial_port[i].irqflags;
2789 port->uartclk = old_serial_port[i].baud_base * 16;
2790 port->flags = old_serial_port[i].flags;
2791 port->hub6 = old_serial_port[i].hub6;
2792 port->membase = old_serial_port[i].iomem_base;
2793 port->iotype = old_serial_port[i].io_type;
2794 port->regshift = old_serial_port[i].iomem_reg_shift;
2795 set_io_from_upio(port);
2796 port->irqflags |= irqflag;
2797 if (serial8250_isa_config != NULL)
2798 serial8250_isa_config(i, &up->port, &up->capabilities);
2799
2800 }
2801}
2802
2803static void
2804serial8250_init_fixed_type_port(struct uart_8250_port *up, unsigned int type)
2805{
2806 up->port.type = type;
2807 if (!up->port.fifosize)
2808 up->port.fifosize = uart_config[type].fifo_size;
2809 if (!up->tx_loadsz)
2810 up->tx_loadsz = uart_config[type].tx_loadsz;
2811 if (!up->capabilities)
2812 up->capabilities = uart_config[type].flags;
2813}
2814
2815static void __init
2816serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2817{
2818 int i;
2819
2820 for (i = 0; i < nr_uarts; i++) {
2821 struct uart_8250_port *up = &serial8250_ports[i];
2822
2823 if (up->port.dev)
2824 continue;
2825
2826 up->port.dev = dev;
2827
2828 if (up->port.flags & UPF_FIXED_TYPE)
2829 serial8250_init_fixed_type_port(up, up->port.type);
2830
2831 uart_add_one_port(drv, &up->port);
2832 }
2833}
2834
2835#ifdef CONFIG_SERIAL_8250_CONSOLE
2836
2837static void serial8250_console_putchar(struct uart_port *port, int ch)
2838{
2839 struct uart_8250_port *up =
2840 container_of(port, struct uart_8250_port, port);
2841
2842 wait_for_xmitr(up, UART_LSR_THRE);
2843 serial_port_out(port, UART_TX, ch);
2844}
2845
2846
2847
2848
2849
2850
2851
2852static void
2853serial8250_console_write(struct console *co, const char *s, unsigned int count)
2854{
2855 struct uart_8250_port *up = &serial8250_ports[co->index];
2856 struct uart_port *port = &up->port;
2857 unsigned long flags;
2858 unsigned int ier;
2859 int locked = 1;
2860
2861 touch_nmi_watchdog();
2862
2863 local_irq_save(flags);
2864 if (port->sysrq) {
2865
2866 locked = 0;
2867 } else if (oops_in_progress) {
2868 locked = spin_trylock(&port->lock);
2869 } else
2870 spin_lock(&port->lock);
2871
2872
2873
2874
2875 ier = serial_port_in(port, UART_IER);
2876
2877 if (up->capabilities & UART_CAP_UUE)
2878 serial_port_out(port, UART_IER, UART_IER_UUE);
2879 else
2880 serial_port_out(port, UART_IER, 0);
2881
2882 uart_console_write(port, s, count, serial8250_console_putchar);
2883
2884
2885
2886
2887
2888 wait_for_xmitr(up, BOTH_EMPTY);
2889 serial_port_out(port, UART_IER, ier);
2890
2891
2892
2893
2894
2895
2896
2897
2898 if (up->msr_saved_flags)
2899 serial8250_modem_status(up);
2900
2901 if (locked)
2902 spin_unlock(&port->lock);
2903 local_irq_restore(flags);
2904}
2905
2906static int __init serial8250_console_setup(struct console *co, char *options)
2907{
2908 struct uart_port *port;
2909 int baud = 9600;
2910 int bits = 8;
2911 int parity = 'n';
2912 int flow = 'n';
2913
2914
2915
2916
2917
2918
2919 if (co->index >= nr_uarts)
2920 co->index = 0;
2921 port = &serial8250_ports[co->index].port;
2922 if (!port->iobase && !port->membase)
2923 return -ENODEV;
2924
2925 if (options)
2926 uart_parse_options(options, &baud, &parity, &bits, &flow);
2927
2928 return uart_set_options(port, co, baud, parity, bits, flow);
2929}
2930
2931static int serial8250_console_early_setup(void)
2932{
2933 return serial8250_find_port_for_earlycon();
2934}
2935
2936static struct console serial8250_console = {
2937 .name = "ttyS",
2938 .write = serial8250_console_write,
2939 .device = uart_console_device,
2940 .setup = serial8250_console_setup,
2941 .early_setup = serial8250_console_early_setup,
2942 .flags = CON_PRINTBUFFER | CON_ANYTIME,
2943 .index = -1,
2944 .data = &serial8250_reg,
2945};
2946
2947static int __init serial8250_console_init(void)
2948{
2949 serial8250_isa_init_ports();
2950 register_console(&serial8250_console);
2951 return 0;
2952}
2953console_initcall(serial8250_console_init);
2954
2955int serial8250_find_port(struct uart_port *p)
2956{
2957 int line;
2958 struct uart_port *port;
2959
2960 for (line = 0; line < nr_uarts; line++) {
2961 port = &serial8250_ports[line].port;
2962 if (uart_match_port(p, port))
2963 return line;
2964 }
2965 return -ENODEV;
2966}
2967
2968#define SERIAL8250_CONSOLE &serial8250_console
2969#else
2970#define SERIAL8250_CONSOLE NULL
2971#endif
2972
2973static struct uart_driver serial8250_reg = {
2974 .owner = THIS_MODULE,
2975 .driver_name = "serial",
2976 .dev_name = "ttyS",
2977 .major = TTY_MAJOR,
2978 .minor = 64,
2979 .cons = SERIAL8250_CONSOLE,
2980};
2981
2982
2983
2984
2985
2986
2987
2988int __init early_serial_setup(struct uart_port *port)
2989{
2990 struct uart_port *p;
2991
2992 if (port->line >= ARRAY_SIZE(serial8250_ports))
2993 return -ENODEV;
2994
2995 serial8250_isa_init_ports();
2996 p = &serial8250_ports[port->line].port;
2997 p->iobase = port->iobase;
2998 p->membase = port->membase;
2999 p->irq = port->irq;
3000 p->irqflags = port->irqflags;
3001 p->uartclk = port->uartclk;
3002 p->fifosize = port->fifosize;
3003 p->regshift = port->regshift;
3004 p->iotype = port->iotype;
3005 p->flags = port->flags;
3006 p->mapbase = port->mapbase;
3007 p->private_data = port->private_data;
3008 p->type = port->type;
3009 p->line = port->line;
3010
3011 set_io_from_upio(p);
3012 if (port->serial_in)
3013 p->serial_in = port->serial_in;
3014 if (port->serial_out)
3015 p->serial_out = port->serial_out;
3016 if (port->handle_irq)
3017 p->handle_irq = port->handle_irq;
3018 else
3019 p->handle_irq = serial8250_default_handle_irq;
3020
3021 return 0;
3022}
3023
3024
3025
3026
3027
3028
3029
3030void serial8250_suspend_port(int line)
3031{
3032 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
3033}
3034
3035
3036
3037
3038
3039
3040
3041void serial8250_resume_port(int line)
3042{
3043 struct uart_8250_port *up = &serial8250_ports[line];
3044 struct uart_port *port = &up->port;
3045
3046 if (up->capabilities & UART_NATSEMI) {
3047
3048 serial_port_out(port, UART_LCR, 0xE0);
3049
3050 ns16550a_goto_highspeed(up);
3051
3052 serial_port_out(port, UART_LCR, 0);
3053 port->uartclk = 921600*16;
3054 }
3055 uart_resume_port(&serial8250_reg, port);
3056}
3057
3058
3059
3060
3061
3062
3063static int serial8250_probe(struct platform_device *dev)
3064{
3065 struct plat_serial8250_port *p = dev->dev.platform_data;
3066 struct uart_8250_port uart;
3067 int ret, i, irqflag = 0;
3068
3069 memset(&uart, 0, sizeof(uart));
3070
3071 if (share_irqs)
3072 irqflag = IRQF_SHARED;
3073
3074 for (i = 0; p && p->flags != 0; p++, i++) {
3075 uart.port.iobase = p->iobase;
3076 uart.port.membase = p->membase;
3077 uart.port.irq = p->irq;
3078 uart.port.irqflags = p->irqflags;
3079 uart.port.uartclk = p->uartclk;
3080 uart.port.regshift = p->regshift;
3081 uart.port.iotype = p->iotype;
3082 uart.port.flags = p->flags;
3083 uart.port.mapbase = p->mapbase;
3084 uart.port.hub6 = p->hub6;
3085 uart.port.private_data = p->private_data;
3086 uart.port.type = p->type;
3087 uart.port.serial_in = p->serial_in;
3088 uart.port.serial_out = p->serial_out;
3089 uart.port.handle_irq = p->handle_irq;
3090 uart.port.handle_break = p->handle_break;
3091 uart.port.set_termios = p->set_termios;
3092 uart.port.pm = p->pm;
3093 uart.port.dev = &dev->dev;
3094 uart.port.irqflags |= irqflag;
3095 ret = serial8250_register_8250_port(&uart);
3096 if (ret < 0) {
3097 dev_err(&dev->dev, "unable to register port at index %d "
3098 "(IO%lx MEM%llx IRQ%d): %d\n", i,
3099 p->iobase, (unsigned long long)p->mapbase,
3100 p->irq, ret);
3101 }
3102 }
3103 return 0;
3104}
3105
3106
3107
3108
3109static int serial8250_remove(struct platform_device *dev)
3110{
3111 int i;
3112
3113 for (i = 0; i < nr_uarts; i++) {
3114 struct uart_8250_port *up = &serial8250_ports[i];
3115
3116 if (up->port.dev == &dev->dev)
3117 serial8250_unregister_port(i);
3118 }
3119 return 0;
3120}
3121
3122static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
3123{
3124 int i;
3125
3126 for (i = 0; i < UART_NR; i++) {
3127 struct uart_8250_port *up = &serial8250_ports[i];
3128
3129 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3130 uart_suspend_port(&serial8250_reg, &up->port);
3131 }
3132
3133 return 0;
3134}
3135
3136static int serial8250_resume(struct platform_device *dev)
3137{
3138 int i;
3139
3140 for (i = 0; i < UART_NR; i++) {
3141 struct uart_8250_port *up = &serial8250_ports[i];
3142
3143 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
3144 serial8250_resume_port(i);
3145 }
3146
3147 return 0;
3148}
3149
3150static struct platform_driver serial8250_isa_driver = {
3151 .probe = serial8250_probe,
3152 .remove = serial8250_remove,
3153 .suspend = serial8250_suspend,
3154 .resume = serial8250_resume,
3155 .driver = {
3156 .name = "serial8250",
3157 .owner = THIS_MODULE,
3158 },
3159};
3160
3161
3162
3163
3164
3165static struct platform_device *serial8250_isa_devs;
3166
3167
3168
3169
3170
3171
3172static DEFINE_MUTEX(serial_mutex);
3173
3174static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
3175{
3176 int i;
3177
3178
3179
3180
3181 for (i = 0; i < nr_uarts; i++)
3182 if (uart_match_port(&serial8250_ports[i].port, port))
3183 return &serial8250_ports[i];
3184
3185
3186
3187
3188
3189
3190 for (i = 0; i < nr_uarts; i++)
3191 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
3192 serial8250_ports[i].port.iobase == 0)
3193 return &serial8250_ports[i];
3194
3195
3196
3197
3198
3199 for (i = 0; i < nr_uarts; i++)
3200 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
3201 return &serial8250_ports[i];
3202
3203 return NULL;
3204}
3205
3206
3207
3208
3209
3210
3211
3212
3213
3214
3215
3216
3217
3218
3219int serial8250_register_8250_port(struct uart_8250_port *up)
3220{
3221 struct uart_8250_port *uart;
3222 int ret = -ENOSPC;
3223
3224 if (up->port.uartclk == 0)
3225 return -EINVAL;
3226
3227 mutex_lock(&serial_mutex);
3228
3229 uart = serial8250_find_match_or_unused(&up->port);
3230 if (uart && uart->port.type != PORT_8250_CIR) {
3231 if (uart->port.dev)
3232 uart_remove_one_port(&serial8250_reg, &uart->port);
3233
3234 uart->port.iobase = up->port.iobase;
3235 uart->port.membase = up->port.membase;
3236 uart->port.irq = up->port.irq;
3237 uart->port.irqflags = up->port.irqflags;
3238 uart->port.uartclk = up->port.uartclk;
3239 uart->port.fifosize = up->port.fifosize;
3240 uart->port.regshift = up->port.regshift;
3241 uart->port.iotype = up->port.iotype;
3242 uart->port.flags = up->port.flags | UPF_BOOT_AUTOCONF;
3243 uart->bugs = up->bugs;
3244 uart->port.mapbase = up->port.mapbase;
3245 uart->port.private_data = up->port.private_data;
3246 uart->port.fifosize = up->port.fifosize;
3247 uart->tx_loadsz = up->tx_loadsz;
3248 uart->capabilities = up->capabilities;
3249
3250
3251 if (uart->port.fifosize && !uart->tx_loadsz)
3252 uart->tx_loadsz = uart->port.fifosize;
3253
3254 if (up->port.dev)
3255 uart->port.dev = up->port.dev;
3256
3257 if (up->port.flags & UPF_FIXED_TYPE)
3258 serial8250_init_fixed_type_port(uart, up->port.type);
3259
3260 set_io_from_upio(&uart->port);
3261
3262 if (up->port.serial_in)
3263 uart->port.serial_in = up->port.serial_in;
3264 if (up->port.serial_out)
3265 uart->port.serial_out = up->port.serial_out;
3266 if (up->port.handle_irq)
3267 uart->port.handle_irq = up->port.handle_irq;
3268
3269 if (up->port.set_termios)
3270 uart->port.set_termios = up->port.set_termios;
3271 if (up->port.pm)
3272 uart->port.pm = up->port.pm;
3273 if (up->port.handle_break)
3274 uart->port.handle_break = up->port.handle_break;
3275 if (up->dl_read)
3276 uart->dl_read = up->dl_read;
3277 if (up->dl_write)
3278 uart->dl_write = up->dl_write;
3279 if (up->dma)
3280 uart->dma = up->dma;
3281
3282 if (serial8250_isa_config != NULL)
3283 serial8250_isa_config(0, &uart->port,
3284 &uart->capabilities);
3285
3286 ret = uart_add_one_port(&serial8250_reg, &uart->port);
3287 if (ret == 0)
3288 ret = uart->port.line;
3289 }
3290 mutex_unlock(&serial_mutex);
3291
3292 return ret;
3293}
3294EXPORT_SYMBOL(serial8250_register_8250_port);
3295
3296
3297
3298
3299
3300
3301
3302
3303void serial8250_unregister_port(int line)
3304{
3305 struct uart_8250_port *uart = &serial8250_ports[line];
3306
3307 mutex_lock(&serial_mutex);
3308 uart_remove_one_port(&serial8250_reg, &uart->port);
3309 if (serial8250_isa_devs) {
3310 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
3311 uart->port.type = PORT_UNKNOWN;
3312 uart->port.dev = &serial8250_isa_devs->dev;
3313 uart->capabilities = uart_config[uart->port.type].flags;
3314 uart_add_one_port(&serial8250_reg, &uart->port);
3315 } else {
3316 uart->port.dev = NULL;
3317 }
3318 mutex_unlock(&serial_mutex);
3319}
3320EXPORT_SYMBOL(serial8250_unregister_port);
3321
3322static int __init serial8250_init(void)
3323{
3324 int ret;
3325
3326 serial8250_isa_init_ports();
3327
3328 printk(KERN_INFO "Serial: 8250/16550 driver, "
3329 "%d ports, IRQ sharing %sabled\n", nr_uarts,
3330 share_irqs ? "en" : "dis");
3331
3332#ifdef CONFIG_SPARC
3333 ret = sunserial_register_minors(&serial8250_reg, UART_NR);
3334#else
3335 serial8250_reg.nr = UART_NR;
3336 ret = uart_register_driver(&serial8250_reg);
3337#endif
3338 if (ret)
3339 goto out;
3340
3341 ret = serial8250_pnp_init();
3342 if (ret)
3343 goto unreg_uart_drv;
3344
3345 serial8250_isa_devs = platform_device_alloc("serial8250",
3346 PLAT8250_DEV_LEGACY);
3347 if (!serial8250_isa_devs) {
3348 ret = -ENOMEM;
3349 goto unreg_pnp;
3350 }
3351
3352 ret = platform_device_add(serial8250_isa_devs);
3353 if (ret)
3354 goto put_dev;
3355
3356 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
3357
3358 ret = platform_driver_register(&serial8250_isa_driver);
3359 if (ret == 0)
3360 goto out;
3361
3362 platform_device_del(serial8250_isa_devs);
3363put_dev:
3364 platform_device_put(serial8250_isa_devs);
3365unreg_pnp:
3366 serial8250_pnp_exit();
3367unreg_uart_drv:
3368#ifdef CONFIG_SPARC
3369 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3370#else
3371 uart_unregister_driver(&serial8250_reg);
3372#endif
3373out:
3374 return ret;
3375}
3376
3377static void __exit serial8250_exit(void)
3378{
3379 struct platform_device *isa_dev = serial8250_isa_devs;
3380
3381
3382
3383
3384
3385
3386 serial8250_isa_devs = NULL;
3387
3388 platform_driver_unregister(&serial8250_isa_driver);
3389 platform_device_unregister(isa_dev);
3390
3391 serial8250_pnp_exit();
3392
3393#ifdef CONFIG_SPARC
3394 sunserial_unregister_minors(&serial8250_reg, UART_NR);
3395#else
3396 uart_unregister_driver(&serial8250_reg);
3397#endif
3398}
3399
3400module_init(serial8250_init);
3401module_exit(serial8250_exit);
3402
3403EXPORT_SYMBOL(serial8250_suspend_port);
3404EXPORT_SYMBOL(serial8250_resume_port);
3405
3406MODULE_LICENSE("GPL");
3407MODULE_DESCRIPTION("Generic 8250/16x50 serial driver");
3408
3409module_param(share_irqs, uint, 0644);
3410MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3411 " (unsafe)");
3412
3413module_param(nr_uarts, uint, 0644);
3414MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3415
3416module_param(skip_txen_test, uint, 0644);
3417MODULE_PARM_DESC(skip_txen_test, "Skip checking for the TXEN bug at init time");
3418
3419#ifdef CONFIG_SERIAL_8250_RSA
3420module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3421MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3422#endif
3423MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);
3424
3425#ifdef CONFIG_SERIAL_8250_DEPRECATED_OPTIONS
3426#ifndef MODULE
3427
3428
3429
3430
3431
3432
3433
3434
3435
3436
3437static void __used s8250_options(void)
3438{
3439#undef MODULE_PARAM_PREFIX
3440#define MODULE_PARAM_PREFIX "8250_core."
3441
3442 module_param_cb(share_irqs, ¶m_ops_uint, &share_irqs, 0644);
3443 module_param_cb(nr_uarts, ¶m_ops_uint, &nr_uarts, 0644);
3444 module_param_cb(skip_txen_test, ¶m_ops_uint, &skip_txen_test, 0644);
3445#ifdef CONFIG_SERIAL_8250_RSA
3446 __module_param_call(MODULE_PARAM_PREFIX, probe_rsa,
3447 ¶m_array_ops, .arr = &__param_arr_probe_rsa,
3448 0444, -1);
3449#endif
3450}
3451#else
3452MODULE_ALIAS("8250_core");
3453#endif
3454#endif
3455