1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19#ifndef __LINUX_EHCI_HCD_H
20#define __LINUX_EHCI_HCD_H
21
22
23
24
25
26
27
28
29
30
31
32#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33typedef __u32 __bitwise __hc32;
34typedef __u16 __bitwise __hc16;
35#else
36#define __hc32 __le32
37#define __hc16 __le16
38#endif
39
40
41#ifdef DEBUG
42#define EHCI_STATS
43#endif
44
45struct ehci_stats {
46
47 unsigned long normal;
48 unsigned long error;
49 unsigned long iaa;
50 unsigned long lost_iaa;
51
52
53 unsigned long complete;
54 unsigned long unlink;
55};
56
57
58
59
60
61
62
63
64
65
66
67#define EHCI_MAX_ROOT_PORTS 15
68
69
70
71
72
73enum ehci_rh_state {
74 EHCI_RH_HALTED,
75 EHCI_RH_SUSPENDED,
76 EHCI_RH_RUNNING,
77 EHCI_RH_STOPPING
78};
79
80
81
82
83
84
85enum ehci_hrtimer_event {
86 EHCI_HRTIMER_POLL_ASS,
87 EHCI_HRTIMER_POLL_PSS,
88 EHCI_HRTIMER_POLL_DEAD,
89 EHCI_HRTIMER_UNLINK_INTR,
90 EHCI_HRTIMER_FREE_ITDS,
91 EHCI_HRTIMER_ASYNC_UNLINKS,
92 EHCI_HRTIMER_IAA_WATCHDOG,
93 EHCI_HRTIMER_DISABLE_PERIODIC,
94 EHCI_HRTIMER_DISABLE_ASYNC,
95 EHCI_HRTIMER_IO_WATCHDOG,
96 EHCI_HRTIMER_NUM_EVENTS
97};
98#define EHCI_HRTIMER_NO_EVENT 99
99
100struct ehci_hcd {
101
102 enum ehci_hrtimer_event next_hrtimer_event;
103 unsigned enabled_hrtimer_events;
104 ktime_t hr_timeouts[EHCI_HRTIMER_NUM_EVENTS];
105 struct hrtimer hrtimer;
106
107 int PSS_poll_count;
108 int ASS_poll_count;
109 int died_poll_count;
110
111
112 struct ehci_caps __iomem *caps;
113 struct ehci_regs __iomem *regs;
114 struct ehci_dbg_port __iomem *debug;
115
116 __u32 hcs_params;
117 spinlock_t lock;
118 enum ehci_rh_state rh_state;
119
120
121 bool scanning:1;
122 bool need_rescan:1;
123 bool intr_unlinking:1;
124 bool iaa_in_progress:1;
125 bool async_unlinking:1;
126 bool shutdown:1;
127 struct ehci_qh *qh_scan_next;
128
129
130 struct ehci_qh *async;
131 struct ehci_qh *dummy;
132 struct list_head async_unlink;
133 struct list_head async_idle;
134 unsigned async_unlink_cycle;
135 unsigned async_count;
136
137
138#define DEFAULT_I_TDPS 1024
139 unsigned periodic_size;
140 __hc32 *periodic;
141 dma_addr_t periodic_dma;
142 struct list_head intr_qh_list;
143 unsigned i_thresh;
144
145 union ehci_shadow *pshadow;
146 struct list_head intr_unlink;
147 unsigned intr_unlink_cycle;
148 unsigned now_frame;
149 unsigned last_iso_frame;
150 unsigned intr_count;
151 unsigned isoc_count;
152 unsigned periodic_count;
153 unsigned uframe_periodic_max;
154
155
156
157 struct list_head cached_itd_list;
158 struct ehci_itd *last_itd_to_free;
159 struct list_head cached_sitd_list;
160 struct ehci_sitd *last_sitd_to_free;
161
162
163 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
164
165
166 unsigned long bus_suspended;
167
168 unsigned long companion_ports;
169
170 unsigned long owned_ports;
171
172 unsigned long port_c_suspend;
173
174 unsigned long suspended_ports;
175
176 unsigned long resuming_ports;
177
178
179
180 struct dma_pool *qh_pool;
181 struct dma_pool *qtd_pool;
182 struct dma_pool *itd_pool;
183 struct dma_pool *sitd_pool;
184
185 unsigned random_frame;
186 unsigned long next_statechange;
187 ktime_t last_periodic_enable;
188 u32 command;
189
190
191 unsigned no_selective_suspend:1;
192 unsigned has_fsl_port_bug:1;
193 unsigned big_endian_mmio:1;
194 unsigned big_endian_desc:1;
195 unsigned big_endian_capbase:1;
196 unsigned has_amcc_usb23:1;
197 unsigned need_io_watchdog:1;
198 unsigned amd_pll_fix:1;
199 unsigned use_dummy_qh:1;
200 unsigned has_synopsys_hc_bug:1;
201 unsigned frame_index_bug:1;
202 unsigned need_oc_pp_cycle:1;
203
204
205 #define OHCI_CTRL_HCFS (3 << 6)
206 #define OHCI_USB_OPER (2 << 6)
207 #define OHCI_USB_SUSPEND (3 << 6)
208
209 #define OHCI_HCCTRL_OFFSET 0x4
210 #define OHCI_HCCTRL_LEN 0x4
211 __hc32 *ohci_hcctrl_reg;
212 unsigned has_hostpc:1;
213 unsigned has_ppcd:1;
214 u8 sbrn;
215
216
217#ifdef EHCI_STATS
218 struct ehci_stats stats;
219# define COUNT(x) do { (x)++; } while (0)
220#else
221# define COUNT(x) do {} while (0)
222#endif
223
224
225#ifdef DEBUG
226 struct dentry *debug_dir;
227#endif
228
229
230 unsigned long priv[0] __aligned(sizeof(s64));
231};
232
233
234static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
235{
236 return (struct ehci_hcd *) (hcd->hcd_priv);
237}
238static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
239{
240 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
241}
242
243
244
245#include <linux/usb/ehci_def.h>
246
247
248
249#define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
250
251
252
253
254
255
256
257
258
259struct ehci_qtd {
260
261 __hc32 hw_next;
262 __hc32 hw_alt_next;
263 __hc32 hw_token;
264#define QTD_TOGGLE (1 << 31)
265#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
266#define QTD_IOC (1 << 15)
267#define QTD_CERR(tok) (((tok)>>10) & 0x3)
268#define QTD_PID(tok) (((tok)>>8) & 0x3)
269#define QTD_STS_ACTIVE (1 << 7)
270#define QTD_STS_HALT (1 << 6)
271#define QTD_STS_DBE (1 << 5)
272#define QTD_STS_BABBLE (1 << 4)
273#define QTD_STS_XACT (1 << 3)
274#define QTD_STS_MMF (1 << 2)
275#define QTD_STS_STS (1 << 1)
276#define QTD_STS_PING (1 << 0)
277
278#define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
279#define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
280#define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
281
282 __hc32 hw_buf [5];
283 __hc32 hw_buf_hi [5];
284
285
286 dma_addr_t qtd_dma;
287 struct list_head qtd_list;
288 struct urb *urb;
289 size_t length;
290} __attribute__ ((aligned (32)));
291
292
293#define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
294
295#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
296
297
298
299
300#define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
301
302
303
304
305
306
307
308
309
310#define Q_TYPE_ITD (0 << 1)
311#define Q_TYPE_QH (1 << 1)
312#define Q_TYPE_SITD (2 << 1)
313#define Q_TYPE_FSTN (3 << 1)
314
315
316#define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
317
318
319#define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1)
320
321
322
323
324
325
326
327
328
329union ehci_shadow {
330 struct ehci_qh *qh;
331 struct ehci_itd *itd;
332 struct ehci_sitd *sitd;
333 struct ehci_fstn *fstn;
334 __hc32 *hw_next;
335 void *ptr;
336};
337
338
339
340
341
342
343
344
345
346
347
348
349struct ehci_qh_hw {
350 __hc32 hw_next;
351 __hc32 hw_info1;
352#define QH_CONTROL_EP (1 << 27)
353#define QH_HEAD (1 << 15)
354#define QH_TOGGLE_CTL (1 << 14)
355#define QH_HIGH_SPEED (2 << 12)
356#define QH_LOW_SPEED (1 << 12)
357#define QH_FULL_SPEED (0 << 12)
358#define QH_INACTIVATE (1 << 7)
359 __hc32 hw_info2;
360#define QH_SMASK 0x000000ff
361#define QH_CMASK 0x0000ff00
362#define QH_HUBADDR 0x007f0000
363#define QH_HUBPORT 0x3f800000
364#define QH_MULT 0xc0000000
365 __hc32 hw_current;
366
367
368 __hc32 hw_qtd_next;
369 __hc32 hw_alt_next;
370 __hc32 hw_token;
371 __hc32 hw_buf [5];
372 __hc32 hw_buf_hi [5];
373} __attribute__ ((aligned(32)));
374
375struct ehci_qh {
376 struct ehci_qh_hw *hw;
377
378 dma_addr_t qh_dma;
379 union ehci_shadow qh_next;
380 struct list_head qtd_list;
381 struct list_head intr_node;
382 struct ehci_qtd *dummy;
383 struct list_head unlink_node;
384
385 unsigned unlink_cycle;
386
387 u8 qh_state;
388#define QH_STATE_LINKED 1
389#define QH_STATE_UNLINK 2
390#define QH_STATE_IDLE 3
391#define QH_STATE_UNLINK_WAIT 4
392#define QH_STATE_COMPLETING 5
393
394 u8 xacterrs;
395#define QH_XACTERR_MAX 32
396
397
398 u8 usecs;
399 u8 gap_uf;
400 u8 c_usecs;
401 u16 tt_usecs;
402 unsigned short period;
403 unsigned short start;
404#define NO_FRAME ((unsigned short)~0)
405
406 struct usb_device *dev;
407 unsigned is_out:1;
408 unsigned clearing_tt:1;
409 unsigned dequeue_during_giveback:1;
410 unsigned exception:1;
411
412};
413
414
415
416
417struct ehci_iso_packet {
418
419 u64 bufp;
420 __hc32 transaction;
421 u8 cross;
422
423 u32 buf1;
424};
425
426
427
428
429
430struct ehci_iso_sched {
431 struct list_head td_list;
432 unsigned span;
433 struct ehci_iso_packet packet [0];
434};
435
436
437
438
439
440struct ehci_iso_stream {
441
442 struct ehci_qh_hw *hw;
443
444 u8 bEndpointAddress;
445 u8 highspeed;
446 struct list_head td_list;
447 struct list_head free_list;
448 struct usb_device *udev;
449 struct usb_host_endpoint *ep;
450
451
452 int next_uframe;
453 __hc32 splits;
454
455
456
457
458
459 u8 usecs, c_usecs;
460 u16 interval;
461 u16 tt_usecs;
462 u16 maxp;
463 u16 raw_mask;
464 unsigned bandwidth;
465
466
467 __hc32 buf0;
468 __hc32 buf1;
469 __hc32 buf2;
470
471
472 __hc32 address;
473};
474
475
476
477
478
479
480
481
482
483struct ehci_itd {
484
485 __hc32 hw_next;
486 __hc32 hw_transaction [8];
487#define EHCI_ISOC_ACTIVE (1<<31)
488#define EHCI_ISOC_BUF_ERR (1<<30)
489#define EHCI_ISOC_BABBLE (1<<29)
490#define EHCI_ISOC_XACTERR (1<<28)
491#define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
492#define EHCI_ITD_IOC (1 << 15)
493
494#define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
495
496 __hc32 hw_bufp [7];
497 __hc32 hw_bufp_hi [7];
498
499
500 dma_addr_t itd_dma;
501 union ehci_shadow itd_next;
502
503 struct urb *urb;
504 struct ehci_iso_stream *stream;
505 struct list_head itd_list;
506
507
508 unsigned frame;
509 unsigned pg;
510 unsigned index[8];
511} __attribute__ ((aligned (32)));
512
513
514
515
516
517
518
519
520
521struct ehci_sitd {
522
523 __hc32 hw_next;
524
525 __hc32 hw_fullspeed_ep;
526 __hc32 hw_uframe;
527 __hc32 hw_results;
528#define SITD_IOC (1 << 31)
529#define SITD_PAGE (1 << 30)
530#define SITD_LENGTH(x) (0x3ff & ((x)>>16))
531#define SITD_STS_ACTIVE (1 << 7)
532#define SITD_STS_ERR (1 << 6)
533#define SITD_STS_DBE (1 << 5)
534#define SITD_STS_BABBLE (1 << 4)
535#define SITD_STS_XACT (1 << 3)
536#define SITD_STS_MMF (1 << 2)
537#define SITD_STS_STS (1 << 1)
538
539#define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
540
541 __hc32 hw_buf [2];
542 __hc32 hw_backpointer;
543 __hc32 hw_buf_hi [2];
544
545
546 dma_addr_t sitd_dma;
547 union ehci_shadow sitd_next;
548
549 struct urb *urb;
550 struct ehci_iso_stream *stream;
551 struct list_head sitd_list;
552 unsigned frame;
553 unsigned index;
554} __attribute__ ((aligned (32)));
555
556
557
558
559
560
561
562
563
564
565
566
567struct ehci_fstn {
568 __hc32 hw_next;
569 __hc32 hw_prev;
570
571
572 dma_addr_t fstn_dma;
573 union ehci_shadow fstn_next;
574} __attribute__ ((aligned (32)));
575
576
577
578
579
580#define ehci_prepare_ports_for_controller_suspend(ehci, do_wakeup) \
581 ehci_adjust_port_wakeup_flags(ehci, true, do_wakeup);
582
583#define ehci_prepare_ports_for_controller_resume(ehci) \
584 ehci_adjust_port_wakeup_flags(ehci, false, false);
585
586
587
588#ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
589
590
591
592
593
594
595
596
597#define ehci_is_TDI(e) (ehci_to_hcd(e)->has_tt)
598
599
600static inline unsigned int
601ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
602{
603 if (ehci_is_TDI(ehci)) {
604 switch ((portsc >> (ehci->has_hostpc ? 25 : 26)) & 3) {
605 case 0:
606 return 0;
607 case 1:
608 return USB_PORT_STAT_LOW_SPEED;
609 case 2:
610 default:
611 return USB_PORT_STAT_HIGH_SPEED;
612 }
613 }
614 return USB_PORT_STAT_HIGH_SPEED;
615}
616
617#else
618
619#define ehci_is_TDI(e) (0)
620
621#define ehci_port_speed(ehci, portsc) USB_PORT_STAT_HIGH_SPEED
622#endif
623
624
625
626#ifdef CONFIG_PPC_83xx
627
628
629
630#define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
631#else
632#define ehci_has_fsl_portno_bug(e) (0)
633#endif
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
650#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
651#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
652#else
653#define ehci_big_endian_mmio(e) 0
654#define ehci_big_endian_capbase(e) 0
655#endif
656
657
658
659
660
661#if defined(CONFIG_ARM) && defined(CONFIG_ARCH_IXP4XX)
662#define readl_be(addr) __raw_readl((__force unsigned *)addr)
663#define writel_be(val, addr) __raw_writel(val, (__force unsigned *)addr)
664#endif
665
666static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
667 __u32 __iomem * regs)
668{
669#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
670 return ehci_big_endian_mmio(ehci) ?
671 readl_be(regs) :
672 readl(regs);
673#else
674 return readl(regs);
675#endif
676}
677
678static inline void ehci_writel(const struct ehci_hcd *ehci,
679 const unsigned int val, __u32 __iomem *regs)
680{
681#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
682 ehci_big_endian_mmio(ehci) ?
683 writel_be(val, regs) :
684 writel(val, regs);
685#else
686 writel(val, regs);
687#endif
688}
689
690
691
692
693
694
695#ifdef CONFIG_44x
696static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
697{
698 u32 hc_control;
699
700 hc_control = (readl_be(ehci->ohci_hcctrl_reg) & ~OHCI_CTRL_HCFS);
701 if (operational)
702 hc_control |= OHCI_USB_OPER;
703 else
704 hc_control |= OHCI_USB_SUSPEND;
705
706 writel_be(hc_control, ehci->ohci_hcctrl_reg);
707 (void) readl_be(ehci->ohci_hcctrl_reg);
708}
709#else
710static inline void set_ohci_hcfs(struct ehci_hcd *ehci, int operational)
711{ }
712#endif
713
714
715
716
717
718
719
720
721
722
723#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
724#define ehci_big_endian_desc(e) ((e)->big_endian_desc)
725
726
727static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
728{
729 return ehci_big_endian_desc(ehci)
730 ? (__force __hc32)cpu_to_be32(x)
731 : (__force __hc32)cpu_to_le32(x);
732}
733
734
735static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
736{
737 return ehci_big_endian_desc(ehci)
738 ? be32_to_cpu((__force __be32)x)
739 : le32_to_cpu((__force __le32)x);
740}
741
742static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
743{
744 return ehci_big_endian_desc(ehci)
745 ? be32_to_cpup((__force __be32 *)x)
746 : le32_to_cpup((__force __le32 *)x);
747}
748
749#else
750
751
752static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
753{
754 return cpu_to_le32(x);
755}
756
757
758static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
759{
760 return le32_to_cpu(x);
761}
762
763static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
764{
765 return le32_to_cpup(x);
766}
767
768#endif
769
770
771
772#define ehci_dbg(ehci, fmt, args...) \
773 dev_dbg(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
774#define ehci_err(ehci, fmt, args...) \
775 dev_err(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
776#define ehci_info(ehci, fmt, args...) \
777 dev_info(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
778#define ehci_warn(ehci, fmt, args...) \
779 dev_warn(ehci_to_hcd(ehci)->self.controller , fmt , ## args)
780
781#ifdef VERBOSE_DEBUG
782# define ehci_vdbg ehci_dbg
783#else
784 static inline void ehci_vdbg(struct ehci_hcd *ehci, ...) {}
785#endif
786
787#ifndef DEBUG
788#define STUB_DEBUG_FILES
789#endif
790
791
792
793
794
795struct ehci_driver_overrides {
796 size_t extra_priv_size;
797 int (*reset)(struct usb_hcd *hcd);
798};
799
800extern void ehci_init_driver(struct hc_driver *drv,
801 const struct ehci_driver_overrides *over);
802extern int ehci_setup(struct usb_hcd *hcd);
803extern int ehci_handshake(struct ehci_hcd *ehci, void __iomem *ptr,
804 u32 mask, u32 done, int usec);
805
806#ifdef CONFIG_PM
807extern int ehci_suspend(struct usb_hcd *hcd, bool do_wakeup);
808extern int ehci_resume(struct usb_hcd *hcd, bool hibernated);
809#endif
810
811#endif
812