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9
10#include <linux/irq.h>
11#include <linux/slab.h>
12
13static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
14{
15 int last = urb_priv->length - 1;
16
17 if (last >= 0) {
18 int i;
19 struct td *td;
20
21 for (i = 0; i <= last; i++) {
22 td = urb_priv->td [i];
23 if (td)
24 td_free (hc, td);
25 }
26 }
27
28 list_del (&urb_priv->pending);
29 kfree (urb_priv);
30}
31
32
33
34
35
36
37
38
39static void
40finish_urb(struct ohci_hcd *ohci, struct urb *urb, int status)
41__releases(ohci->lock)
42__acquires(ohci->lock)
43{
44 struct device *dev = ohci_to_hcd(ohci)->self.controller;
45
46
47 urb_free_priv (ohci, urb->hcpriv);
48 urb->hcpriv = NULL;
49 if (likely(status == -EINPROGRESS))
50 status = 0;
51
52 switch (usb_pipetype (urb->pipe)) {
53 case PIPE_ISOCHRONOUS:
54 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
55 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
56 if (quirk_amdiso(ohci))
57 usb_amd_quirk_pll_enable();
58 if (quirk_amdprefetch(ohci))
59 sb800_prefetch(dev, 0);
60 }
61 break;
62 case PIPE_INTERRUPT:
63 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
64 break;
65 }
66
67#ifdef OHCI_VERBOSE_DEBUG
68 urb_print(urb, "RET", usb_pipeout (urb->pipe), status);
69#endif
70
71
72 usb_hcd_unlink_urb_from_ep(ohci_to_hcd(ohci), urb);
73 spin_unlock (&ohci->lock);
74 usb_hcd_giveback_urb(ohci_to_hcd(ohci), urb, status);
75 spin_lock (&ohci->lock);
76
77
78 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
79 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
80 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
81 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
82 }
83}
84
85
86
87
88
89
90
91
92
93static int balance (struct ohci_hcd *ohci, int interval, int load)
94{
95 int i, branch = -ENOSPC;
96
97
98 if (interval > NUM_INTS)
99 interval = NUM_INTS;
100
101
102
103
104 for (i = 0; i < interval ; i++) {
105 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
106 int j;
107
108
109 for (j = i; j < NUM_INTS; j += interval) {
110 if ((ohci->load [j] + load) > 900)
111 break;
112 }
113 if (j < NUM_INTS)
114 continue;
115 branch = i;
116 }
117 }
118 return branch;
119}
120
121
122
123
124
125
126
127static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
128{
129 unsigned i;
130
131 ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
132 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
133 ed, ed->branch, ed->load, ed->interval);
134
135 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
136 struct ed **prev = &ohci->periodic [i];
137 __hc32 *prev_p = &ohci->hcca->int_table [i];
138 struct ed *here = *prev;
139
140
141
142
143
144 while (here && ed != here) {
145 if (ed->interval > here->interval)
146 break;
147 prev = &here->ed_next;
148 prev_p = &here->hwNextED;
149 here = *prev;
150 }
151 if (ed != here) {
152 ed->ed_next = here;
153 if (here)
154 ed->hwNextED = *prev_p;
155 wmb ();
156 *prev = ed;
157 *prev_p = cpu_to_hc32(ohci, ed->dma);
158 wmb();
159 }
160 ohci->load [i] += ed->load;
161 }
162 ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
163}
164
165
166
167static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
168{
169 int branch;
170
171 ed->state = ED_OPER;
172 ed->ed_prev = NULL;
173 ed->ed_next = NULL;
174 ed->hwNextED = 0;
175 if (quirk_zfmicro(ohci)
176 && (ed->type == PIPE_INTERRUPT)
177 && !(ohci->eds_scheduled++))
178 mod_timer(&ohci->unlink_watchdog, round_jiffies(jiffies + HZ));
179 wmb ();
180
181
182
183
184
185
186
187
188
189
190
191 switch (ed->type) {
192 case PIPE_CONTROL:
193 if (ohci->ed_controltail == NULL) {
194 WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
195 ohci_writel (ohci, ed->dma,
196 &ohci->regs->ed_controlhead);
197 } else {
198 ohci->ed_controltail->ed_next = ed;
199 ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
200 ed->dma);
201 }
202 ed->ed_prev = ohci->ed_controltail;
203 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
204 wmb();
205 ohci->hc_control |= OHCI_CTRL_CLE;
206 ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
207 ohci_writel (ohci, ohci->hc_control,
208 &ohci->regs->control);
209 }
210 ohci->ed_controltail = ed;
211 break;
212
213 case PIPE_BULK:
214 if (ohci->ed_bulktail == NULL) {
215 WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
216 ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
217 } else {
218 ohci->ed_bulktail->ed_next = ed;
219 ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
220 ed->dma);
221 }
222 ed->ed_prev = ohci->ed_bulktail;
223 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
224 wmb();
225 ohci->hc_control |= OHCI_CTRL_BLE;
226 ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
227 ohci_writel (ohci, ohci->hc_control,
228 &ohci->regs->control);
229 }
230 ohci->ed_bulktail = ed;
231 break;
232
233
234
235 default:
236 branch = balance (ohci, ed->interval, ed->load);
237 if (branch < 0) {
238 ohci_dbg (ohci,
239 "ERR %d, interval %d msecs, load %d\n",
240 branch, ed->interval, ed->load);
241
242 return branch;
243 }
244 ed->branch = branch;
245 periodic_link (ohci, ed);
246 }
247
248
249
250
251 return 0;
252}
253
254
255
256
257static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
258{
259 int i;
260
261 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
262 struct ed *temp;
263 struct ed **prev = &ohci->periodic [i];
264 __hc32 *prev_p = &ohci->hcca->int_table [i];
265
266 while (*prev && (temp = *prev) != ed) {
267 prev_p = &temp->hwNextED;
268 prev = &temp->ed_next;
269 }
270 if (*prev) {
271 *prev_p = ed->hwNextED;
272 *prev = ed->ed_next;
273 }
274 ohci->load [i] -= ed->load;
275 }
276 ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
277
278 ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
279 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
280 ed, ed->branch, ed->load, ed->interval);
281}
282
283
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285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
306{
307 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
308 wmb ();
309 ed->state = ED_UNLINK;
310
311
312
313
314
315
316
317
318
319
320
321 switch (ed->type) {
322 case PIPE_CONTROL:
323
324 if (ed->ed_prev == NULL) {
325 if (!ed->hwNextED) {
326 ohci->hc_control &= ~OHCI_CTRL_CLE;
327 ohci_writel (ohci, ohci->hc_control,
328 &ohci->regs->control);
329
330 } else
331 ohci_writel (ohci,
332 hc32_to_cpup (ohci, &ed->hwNextED),
333 &ohci->regs->ed_controlhead);
334 } else {
335 ed->ed_prev->ed_next = ed->ed_next;
336 ed->ed_prev->hwNextED = ed->hwNextED;
337 }
338
339 if (ohci->ed_controltail == ed) {
340 ohci->ed_controltail = ed->ed_prev;
341 if (ohci->ed_controltail)
342 ohci->ed_controltail->ed_next = NULL;
343 } else if (ed->ed_next) {
344 ed->ed_next->ed_prev = ed->ed_prev;
345 }
346 break;
347
348 case PIPE_BULK:
349
350 if (ed->ed_prev == NULL) {
351 if (!ed->hwNextED) {
352 ohci->hc_control &= ~OHCI_CTRL_BLE;
353 ohci_writel (ohci, ohci->hc_control,
354 &ohci->regs->control);
355
356 } else
357 ohci_writel (ohci,
358 hc32_to_cpup (ohci, &ed->hwNextED),
359 &ohci->regs->ed_bulkhead);
360 } else {
361 ed->ed_prev->ed_next = ed->ed_next;
362 ed->ed_prev->hwNextED = ed->hwNextED;
363 }
364
365 if (ohci->ed_bulktail == ed) {
366 ohci->ed_bulktail = ed->ed_prev;
367 if (ohci->ed_bulktail)
368 ohci->ed_bulktail->ed_next = NULL;
369 } else if (ed->ed_next) {
370 ed->ed_next->ed_prev = ed->ed_prev;
371 }
372 break;
373
374
375
376 default:
377 periodic_unlink (ohci, ed);
378 break;
379 }
380}
381
382
383
384
385
386
387
388static struct ed *ed_get (
389 struct ohci_hcd *ohci,
390 struct usb_host_endpoint *ep,
391 struct usb_device *udev,
392 unsigned int pipe,
393 int interval
394) {
395 struct ed *ed;
396 unsigned long flags;
397
398 spin_lock_irqsave (&ohci->lock, flags);
399
400 if (!(ed = ep->hcpriv)) {
401 struct td *td;
402 int is_out;
403 u32 info;
404
405 ed = ed_alloc (ohci, GFP_ATOMIC);
406 if (!ed) {
407
408 goto done;
409 }
410
411
412 td = td_alloc (ohci, GFP_ATOMIC);
413 if (!td) {
414
415 ed_free (ohci, ed);
416 ed = NULL;
417 goto done;
418 }
419 ed->dummy = td;
420 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
421 ed->hwHeadP = ed->hwTailP;
422 ed->state = ED_IDLE;
423
424 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
425
426
427
428
429 info = usb_pipedevice (pipe);
430 ed->type = usb_pipetype(pipe);
431
432 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
433 info |= usb_endpoint_maxp(&ep->desc) << 16;
434 if (udev->speed == USB_SPEED_LOW)
435 info |= ED_LOWSPEED;
436
437 if (ed->type != PIPE_CONTROL) {
438 info |= is_out ? ED_OUT : ED_IN;
439 if (ed->type != PIPE_BULK) {
440
441 if (ed->type == PIPE_ISOCHRONOUS)
442 info |= ED_ISO;
443 else if (interval > 32)
444 interval = 32;
445 ed->interval = interval;
446 ed->load = usb_calc_bus_time (
447 udev->speed, !is_out,
448 ed->type == PIPE_ISOCHRONOUS,
449 usb_endpoint_maxp(&ep->desc))
450 / 1000;
451 }
452 }
453 ed->hwINFO = cpu_to_hc32(ohci, info);
454
455 ep->hcpriv = ed;
456 }
457
458done:
459 spin_unlock_irqrestore (&ohci->lock, flags);
460 return ed;
461}
462
463
464
465
466
467
468
469
470
471static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
472{
473 ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
474 ed_deschedule (ohci, ed);
475
476
477 ed->ed_next = ohci->ed_rm_list;
478 ed->ed_prev = NULL;
479 ohci->ed_rm_list = ed;
480
481
482 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
483 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
484
485 (void) ohci_readl (ohci, &ohci->regs->control);
486
487
488
489
490
491
492 ed->tick = ohci_frame_no(ohci) + 1;
493
494}
495
496
497
498
499
500
501
502static void
503td_fill (struct ohci_hcd *ohci, u32 info,
504 dma_addr_t data, int len,
505 struct urb *urb, int index)
506{
507 struct td *td, *td_pt;
508 struct urb_priv *urb_priv = urb->hcpriv;
509 int is_iso = info & TD_ISO;
510 int hash;
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525 if (index != (urb_priv->length - 1)
526 || (urb->transfer_flags & URB_NO_INTERRUPT))
527 info |= TD_DI_SET (6);
528
529
530 td_pt = urb_priv->td [index];
531
532
533 td = urb_priv->td [index] = urb_priv->ed->dummy;
534 urb_priv->ed->dummy = td_pt;
535
536 td->ed = urb_priv->ed;
537 td->next_dl_td = NULL;
538 td->index = index;
539 td->urb = urb;
540 td->data_dma = data;
541 if (!len)
542 data = 0;
543
544 td->hwINFO = cpu_to_hc32 (ohci, info);
545 if (is_iso) {
546 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
547 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
548 (data & 0x0FFF) | 0xE000);
549 td->ed->last_iso = info & 0xffff;
550 } else {
551 td->hwCBP = cpu_to_hc32 (ohci, data);
552 }
553 if (data)
554 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
555 else
556 td->hwBE = 0;
557 td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
558
559
560 list_add_tail (&td->td_list, &td->ed->td_list);
561
562
563 hash = TD_HASH_FUNC (td->td_dma);
564 td->td_hash = ohci->td_hash [hash];
565 ohci->td_hash [hash] = td;
566
567
568 wmb ();
569 td->ed->hwTailP = td->hwNextTD;
570}
571
572
573
574
575
576
577
578
579static void td_submit_urb (
580 struct ohci_hcd *ohci,
581 struct urb *urb
582) {
583 struct urb_priv *urb_priv = urb->hcpriv;
584 struct device *dev = ohci_to_hcd(ohci)->self.controller;
585 dma_addr_t data;
586 int data_len = urb->transfer_buffer_length;
587 int cnt = 0;
588 u32 info = 0;
589 int is_out = usb_pipeout (urb->pipe);
590 int periodic = 0;
591
592
593
594
595
596 if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
597 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
598 is_out, 1);
599 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
600 }
601
602 list_add (&urb_priv->pending, &ohci->pending);
603
604 if (data_len)
605 data = urb->transfer_dma;
606 else
607 data = 0;
608
609
610
611
612
613 switch (urb_priv->ed->type) {
614
615
616
617
618 case PIPE_INTERRUPT:
619
620 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
621 && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
622
623 case PIPE_BULK:
624 info = is_out
625 ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
626 : TD_T_TOGGLE | TD_CC | TD_DP_IN;
627
628 while (data_len > 4096) {
629 td_fill (ohci, info, data, 4096, urb, cnt);
630 data += 4096;
631 data_len -= 4096;
632 cnt++;
633 }
634
635 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
636 info |= TD_R;
637 td_fill (ohci, info, data, data_len, urb, cnt);
638 cnt++;
639 if ((urb->transfer_flags & URB_ZERO_PACKET)
640 && cnt < urb_priv->length) {
641 td_fill (ohci, info, 0, 0, urb, cnt);
642 cnt++;
643 }
644
645 if (urb_priv->ed->type == PIPE_BULK) {
646 wmb ();
647 ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
648 }
649 break;
650
651
652
653
654 case PIPE_CONTROL:
655 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
656 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
657 if (data_len > 0) {
658 info = TD_CC | TD_R | TD_T_DATA1;
659 info |= is_out ? TD_DP_OUT : TD_DP_IN;
660
661 td_fill (ohci, info, data, data_len, urb, cnt++);
662 }
663 info = (is_out || data_len == 0)
664 ? TD_CC | TD_DP_IN | TD_T_DATA1
665 : TD_CC | TD_DP_OUT | TD_T_DATA1;
666 td_fill (ohci, info, data, 0, urb, cnt++);
667
668 wmb ();
669 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
670 break;
671
672
673
674
675
676 case PIPE_ISOCHRONOUS:
677 for (cnt = urb_priv->td_cnt; cnt < urb->number_of_packets;
678 cnt++) {
679 int frame = urb->start_frame;
680
681
682
683
684 frame += cnt * urb->interval;
685 frame &= 0xffff;
686 td_fill (ohci, TD_CC | TD_ISO | frame,
687 data + urb->iso_frame_desc [cnt].offset,
688 urb->iso_frame_desc [cnt].length, urb, cnt);
689 }
690 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0) {
691 if (quirk_amdiso(ohci))
692 usb_amd_quirk_pll_disable();
693 if (quirk_amdprefetch(ohci))
694 sb800_prefetch(dev, 1);
695 }
696 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
697 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
698 break;
699 }
700
701
702 if (periodic) {
703 wmb ();
704 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
705 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
706 }
707
708
709}
710
711
712
713
714
715
716static int td_done(struct ohci_hcd *ohci, struct urb *urb, struct td *td)
717{
718 u32 tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
719 int cc = 0;
720 int status = -EINPROGRESS;
721
722 list_del (&td->td_list);
723
724
725 if (tdINFO & TD_ISO) {
726 u16 tdPSW = ohci_hwPSW(ohci, td, 0);
727 int dlen = 0;
728
729
730
731
732
733 cc = (tdPSW >> 12) & 0xF;
734 if (tdINFO & TD_CC)
735 return status;
736
737 if (usb_pipeout (urb->pipe))
738 dlen = urb->iso_frame_desc [td->index].length;
739 else {
740
741 if (cc == TD_DATAUNDERRUN)
742 cc = TD_CC_NOERROR;
743 dlen = tdPSW & 0x3ff;
744 }
745 urb->actual_length += dlen;
746 urb->iso_frame_desc [td->index].actual_length = dlen;
747 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
748
749 if (cc != TD_CC_NOERROR)
750 ohci_vdbg (ohci,
751 "urb %p iso td %p (%d) len %d cc %d\n",
752 urb, td, 1 + td->index, dlen, cc);
753
754
755
756
757
758 } else {
759 int type = usb_pipetype (urb->pipe);
760 u32 tdBE = hc32_to_cpup (ohci, &td->hwBE);
761
762 cc = TD_CC_GET (tdINFO);
763
764
765 if (cc == TD_DATAUNDERRUN
766 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
767 cc = TD_CC_NOERROR;
768 if (cc != TD_CC_NOERROR && cc < 0x0E)
769 status = cc_to_error[cc];
770
771
772 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
773 if (td->hwCBP == 0)
774 urb->actual_length += tdBE - td->data_dma + 1;
775 else
776 urb->actual_length +=
777 hc32_to_cpup (ohci, &td->hwCBP)
778 - td->data_dma;
779 }
780
781 if (cc != TD_CC_NOERROR && cc < 0x0E)
782 ohci_vdbg (ohci,
783 "urb %p td %p (%d) cc %d, len=%d/%d\n",
784 urb, td, 1 + td->index, cc,
785 urb->actual_length,
786 urb->transfer_buffer_length);
787 }
788 return status;
789}
790
791
792
793static void ed_halted(struct ohci_hcd *ohci, struct td *td, int cc)
794{
795 struct urb *urb = td->urb;
796 urb_priv_t *urb_priv = urb->hcpriv;
797 struct ed *ed = td->ed;
798 struct list_head *tmp = td->td_list.next;
799 __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
800
801
802
803
804 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
805 wmb ();
806 ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
807
808
809
810
811
812 while (tmp != &ed->td_list) {
813 struct td *next;
814
815 next = list_entry (tmp, struct td, td_list);
816 tmp = next->td_list.next;
817
818 if (next->urb != urb)
819 break;
820
821
822
823
824
825
826
827
828
829 list_del(&next->td_list);
830 urb_priv->td_cnt++;
831 ed->hwHeadP = next->hwNextTD | toggle;
832 }
833
834
835
836
837
838 switch (cc) {
839 case TD_DATAUNDERRUN:
840 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
841 break;
842
843 case TD_CC_STALL:
844 if (usb_pipecontrol (urb->pipe))
845 break;
846
847 default:
848 ohci_dbg (ohci,
849 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
850 urb, urb->dev->devpath,
851 usb_pipeendpoint (urb->pipe),
852 usb_pipein (urb->pipe) ? "in" : "out",
853 hc32_to_cpu (ohci, td->hwINFO),
854 cc, cc_to_error [cc]);
855 }
856}
857
858
859
860
861static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
862{
863 u32 td_dma;
864 struct td *td_rev = NULL;
865 struct td *td = NULL;
866
867 td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
868 ohci->hcca->done_head = 0;
869 wmb();
870
871
872
873
874 while (td_dma) {
875 int cc;
876
877 td = dma_to_td (ohci, td_dma);
878 if (!td) {
879 ohci_err (ohci, "bad entry %8x\n", td_dma);
880 break;
881 }
882
883 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
884 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
885
886
887
888
889
890 if (cc != TD_CC_NOERROR
891 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
892 ed_halted(ohci, td, cc);
893
894 td->next_dl_td = td_rev;
895 td_rev = td;
896 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
897 }
898 return td_rev;
899}
900
901
902
903
904static void
905finish_unlinks (struct ohci_hcd *ohci, u16 tick)
906{
907 struct ed *ed, **last;
908
909rescan_all:
910 for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
911 struct list_head *entry, *tmp;
912 int completed, modified;
913 __hc32 *prev;
914
915
916
917
918 if (likely(ohci->rh_state == OHCI_RH_RUNNING)) {
919 if (tick_before (tick, ed->tick)) {
920skip_ed:
921 last = &ed->ed_next;
922 continue;
923 }
924
925 if (!list_empty (&ed->td_list)) {
926 struct td *td;
927 u32 head;
928
929 td = list_entry (ed->td_list.next, struct td,
930 td_list);
931 head = hc32_to_cpu (ohci, ed->hwHeadP) &
932 TD_MASK;
933
934
935 if (td->td_dma != head) {
936 if (ed == ohci->ed_to_check)
937 ohci->ed_to_check = NULL;
938 else
939 goto skip_ed;
940 }
941 }
942 }
943
944
945
946
947
948 *last = ed->ed_next;
949 ed->ed_next = NULL;
950 modified = 0;
951
952
953
954
955
956
957
958
959
960rescan_this:
961 completed = 0;
962 prev = &ed->hwHeadP;
963 list_for_each_safe (entry, tmp, &ed->td_list) {
964 struct td *td;
965 struct urb *urb;
966 urb_priv_t *urb_priv;
967 __hc32 savebits;
968 u32 tdINFO;
969
970 td = list_entry (entry, struct td, td_list);
971 urb = td->urb;
972 urb_priv = td->urb->hcpriv;
973
974 if (!urb->unlinked) {
975 prev = &td->hwNextTD;
976 continue;
977 }
978
979
980 savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
981 *prev = td->hwNextTD | savebits;
982
983
984
985
986
987
988 tdINFO = hc32_to_cpup(ohci, &td->hwINFO);
989 if ((tdINFO & TD_T) == TD_T_DATA0)
990 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_C);
991 else if ((tdINFO & TD_T) == TD_T_DATA1)
992 ed->hwHeadP |= cpu_to_hc32(ohci, ED_C);
993
994
995 td_done (ohci, urb, td);
996 urb_priv->td_cnt++;
997
998
999 if (urb_priv->td_cnt == urb_priv->length) {
1000 modified = completed = 1;
1001 finish_urb(ohci, urb, 0);
1002 }
1003 }
1004 if (completed && !list_empty (&ed->td_list))
1005 goto rescan_this;
1006
1007
1008 ed->state = ED_IDLE;
1009 if (quirk_zfmicro(ohci) && ed->type == PIPE_INTERRUPT)
1010 ohci->eds_scheduled--;
1011 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1012 ed->hwNextED = 0;
1013 wmb ();
1014 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
1015
1016
1017 if (!list_empty (&ed->td_list)) {
1018 if (ohci->rh_state == OHCI_RH_RUNNING)
1019 ed_schedule (ohci, ed);
1020 }
1021
1022 if (modified)
1023 goto rescan_all;
1024 }
1025
1026
1027 if (ohci->rh_state == OHCI_RH_RUNNING && !ohci->ed_rm_list) {
1028 u32 command = 0, control = 0;
1029
1030 if (ohci->ed_controltail) {
1031 command |= OHCI_CLF;
1032 if (quirk_zfmicro(ohci))
1033 mdelay(1);
1034 if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1035 control |= OHCI_CTRL_CLE;
1036 ohci_writel (ohci, 0,
1037 &ohci->regs->ed_controlcurrent);
1038 }
1039 }
1040 if (ohci->ed_bulktail) {
1041 command |= OHCI_BLF;
1042 if (quirk_zfmicro(ohci))
1043 mdelay(1);
1044 if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1045 control |= OHCI_CTRL_BLE;
1046 ohci_writel (ohci, 0,
1047 &ohci->regs->ed_bulkcurrent);
1048 }
1049 }
1050
1051
1052 if (control) {
1053 ohci->hc_control |= control;
1054 if (quirk_zfmicro(ohci))
1055 mdelay(1);
1056 ohci_writel (ohci, ohci->hc_control,
1057 &ohci->regs->control);
1058 }
1059 if (command) {
1060 if (quirk_zfmicro(ohci))
1061 mdelay(1);
1062 ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1063 }
1064 }
1065}
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077static void takeback_td(struct ohci_hcd *ohci, struct td *td)
1078{
1079 struct urb *urb = td->urb;
1080 urb_priv_t *urb_priv = urb->hcpriv;
1081 struct ed *ed = td->ed;
1082 int status;
1083
1084
1085 status = td_done(ohci, urb, td);
1086 urb_priv->td_cnt++;
1087
1088
1089 if (urb_priv->td_cnt == urb_priv->length)
1090 finish_urb(ohci, urb, status);
1091
1092
1093 if (list_empty(&ed->td_list)) {
1094 if (ed->state == ED_OPER)
1095 start_ed_unlink(ohci, ed);
1096
1097
1098 } else if ((ed->hwINFO & cpu_to_hc32(ohci, ED_SKIP | ED_DEQUEUE))
1099 == cpu_to_hc32(ohci, ED_SKIP)) {
1100 td = list_entry(ed->td_list.next, struct td, td_list);
1101 if (!(td->hwINFO & cpu_to_hc32(ohci, TD_DONE))) {
1102 ed->hwINFO &= ~cpu_to_hc32(ohci, ED_SKIP);
1103
1104 switch (ed->type) {
1105 case PIPE_CONTROL:
1106 ohci_writel(ohci, OHCI_CLF,
1107 &ohci->regs->cmdstatus);
1108 break;
1109 case PIPE_BULK:
1110 ohci_writel(ohci, OHCI_BLF,
1111 &ohci->regs->cmdstatus);
1112 break;
1113 }
1114 }
1115 }
1116}
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127static void
1128dl_done_list (struct ohci_hcd *ohci)
1129{
1130 struct td *td = dl_reverse_done_list (ohci);
1131
1132 while (td) {
1133 struct td *td_next = td->next_dl_td;
1134 struct ed *ed = td->ed;
1135
1136
1137
1138
1139
1140
1141
1142
1143 for (;;) {
1144 struct td *td2;
1145
1146 td2 = list_first_entry(&ed->td_list, struct td,
1147 td_list);
1148 if (td2 == td)
1149 break;
1150 takeback_td(ohci, td2);
1151 }
1152
1153 takeback_td(ohci, td);
1154 td = td_next;
1155 }
1156}
1157