1/* 2 * Wireless Host Controller (WHC) data structures. 3 * 4 * Copyright (C) 2007 Cambridge Silicon Radio Ltd. 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License version 8 * 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 18 * 02110-1301, USA. 19 */ 20#ifndef _WHCI_WHCI_HC_H 21#define _WHCI_WHCI_HC_H 22 23#include <linux/list.h> 24 25/** 26 * WHCI_PAGE_SIZE - page size use by WHCI 27 * 28 * WHCI assumes that host system uses pages of 4096 octets. 29 */ 30#define WHCI_PAGE_SIZE 4096 31 32 33/** 34 * QTD_MAX_TXFER_SIZE - max number of bytes to transfer with a single 35 * qtd. 36 * 37 * This is 2^20 - 1. 38 */ 39#define QTD_MAX_XFER_SIZE 1048575 40 41 42/** 43 * struct whc_qtd - Queue Element Transfer Descriptors (qTD) 44 * 45 * This describes the data for a bulk, control or interrupt transfer. 46 * 47 * [WHCI] section 3.2.4 48 */ 49struct whc_qtd { 50 __le32 status; /*< remaining transfer len and transfer status */ 51 __le32 options; 52 __le64 page_list_ptr; /*< physical pointer to data buffer page list*/ 53 __u8 setup[8]; /*< setup data for control transfers */ 54} __attribute__((packed)); 55 56#define QTD_STS_ACTIVE (1 << 31) /* enable execution of transaction */ 57#define QTD_STS_HALTED (1 << 30) /* transfer halted */ 58#define QTD_STS_DBE (1 << 29) /* data buffer error */ 59#define QTD_STS_BABBLE (1 << 28) /* babble detected */ 60#define QTD_STS_RCE (1 << 27) /* retry count exceeded */ 61#define QTD_STS_LAST_PKT (1 << 26) /* set Last Packet Flag in WUSB header */ 62#define QTD_STS_INACTIVE (1 << 25) /* queue set is marked inactive */ 63#define QTD_STS_IALT_VALID (1 << 23) /* iAlt field is valid */ 64#define QTD_STS_IALT(i) (QTD_STS_IALT_VALID | ((i) << 20)) /* iAlt field */ 65#define QTD_STS_LEN(l) ((l) << 0) /* transfer length */ 66#define QTD_STS_TO_LEN(s) ((s) & 0x000fffff) 67 68#define QTD_OPT_IOC (1 << 1) /* page_list_ptr points to buffer directly */ 69#define QTD_OPT_SMALL (1 << 0) /* interrupt on complete */ 70 71/** 72 * struct whc_itd - Isochronous Queue Element Transfer Descriptors (iTD) 73 * 74 * This describes the data and other parameters for an isochronous 75 * transfer. 76 * 77 * [WHCI] section 3.2.5 78 */ 79struct whc_itd { 80 __le16 presentation_time; /*< presentation time for OUT transfers */ 81 __u8 num_segments; /*< number of data segments in segment list */ 82 __u8 status; /*< command execution status */ 83 __le32 options; /*< misc transfer options */ 84 __le64 page_list_ptr; /*< physical pointer to data buffer page list */ 85 __le64 seg_list_ptr; /*< physical pointer to segment list */ 86} __attribute__((packed)); 87 88#define ITD_STS_ACTIVE (1 << 7) /* enable execution of transaction */ 89#define ITD_STS_DBE (1 << 5) /* data buffer error */ 90#define ITD_STS_BABBLE (1 << 4) /* babble detected */ 91#define ITD_STS_INACTIVE (1 << 1) /* queue set is marked inactive */ 92 93#define ITD_OPT_IOC (1 << 1) /* interrupt on complete */ 94#define ITD_OPT_SMALL (1 << 0) /* page_list_ptr points to buffer directly */ 95 96/** 97 * Page list entry. 98 * 99 * A TD's page list must contain sufficient page list entries for the 100 * total data length in the TD. 101 * 102 * [WHCI] section 3.2.4.3 103 */ 104struct whc_page_list_entry { 105 __le64 buf_ptr; /*< physical pointer to buffer */ 106} __attribute__((packed)); 107 108/** 109 * struct whc_seg_list_entry - Segment list entry. 110 * 111 * Describes a portion of the data buffer described in the containing 112 * qTD's page list. 113 * 114 * seg_ptr = qtd->page_list_ptr[qtd->seg_list_ptr[seg].idx].buf_ptr 115 * + qtd->seg_list_ptr[seg].offset; 116 * 117 * Segments can't cross page boundries. 118 * 119 * [WHCI] section 3.2.5.5 120 */ 121struct whc_seg_list_entry { 122 __le16 len; /*< segment length */ 123 __u8 idx; /*< index into page list */ 124 __u8 status; /*< segment status */ 125 __le16 offset; /*< 12 bit offset into page */ 126} __attribute__((packed)); 127 128/** 129 * struct whc_qhead - endpoint and status information for a qset. 130 * 131 * [WHCI] section 3.2.6 132 */ 133struct whc_qhead { 134 __le64 link; /*< next qset in list */ 135 __le32 info1; 136 __le32 info2; 137 __le32 info3; 138 __le16 status; 139 __le16 err_count; /*< transaction error count */ 140 __le32 cur_window; 141 __le32 scratch[3]; /*< h/w scratch area */ 142 union { 143 struct whc_qtd qtd; 144 struct whc_itd itd; 145 } overlay; 146} __attribute__((packed)); 147 148#define QH_LINK_PTR_MASK (~0x03Full) 149#define QH_LINK_PTR(ptr) ((ptr) & QH_LINK_PTR_MASK) 150#define QH_LINK_IQS (1 << 4) /* isochronous queue set */ 151#define QH_LINK_NTDS(n) (((n) - 1) << 1) /* number of TDs in queue set */ 152#define QH_LINK_T (1 << 0) /* last queue set in periodic schedule list */ 153 154#define QH_INFO1_EP(e) ((e) << 0) /* endpoint number */ 155#define QH_INFO1_DIR_IN (1 << 4) /* IN transfer */ 156#define QH_INFO1_DIR_OUT (0 << 4) /* OUT transfer */ 157#define QH_INFO1_TR_TYPE_CTRL (0x0 << 5) /* control transfer */ 158#define QH_INFO1_TR_TYPE_ISOC (0x1 << 5) /* isochronous transfer */ 159#define QH_INFO1_TR_TYPE_BULK (0x2 << 5) /* bulk transfer */ 160#define QH_INFO1_TR_TYPE_INT (0x3 << 5) /* interrupt */ 161#define QH_INFO1_TR_TYPE_LP_INT (0x7 << 5) /* low power interrupt */ 162#define QH_INFO1_DEV_INFO_IDX(i) ((i) << 8) /* index into device info buffer */ 163#define QH_INFO1_SET_INACTIVE (1 << 15) /* set inactive after transfer */ 164#define QH_INFO1_MAX_PKT_LEN(l) ((l) << 16) /* maximum packet length */ 165 166#define QH_INFO2_BURST(b) ((b) << 0) /* maximum burst length */ 167#define QH_INFO2_DBP(p) ((p) << 5) /* data burst policy (see [WUSB] table 5-7) */ 168#define QH_INFO2_MAX_COUNT(c) ((c) << 8) /* max isoc/int pkts per zone */ 169#define QH_INFO2_RQS (1 << 15) /* reactivate queue set */ 170#define QH_INFO2_MAX_RETRY(r) ((r) << 16) /* maximum transaction retries */ 171#define QH_INFO2_MAX_SEQ(s) ((s) << 20) /* maximum sequence number */ 172#define QH_INFO3_MAX_DELAY(d) ((d) << 0) /* maximum stream delay in 125 us units (isoc only) */ 173#define QH_INFO3_INTERVAL(i) ((i) << 16) /* segment interval in 125 us units (isoc only) */ 174 175#define QH_INFO3_TX_RATE(r) ((r) << 24) /* PHY rate (see [ECMA-368] section 10.3.1.1) */ 176#define QH_INFO3_TX_PWR(p) ((p) << 29) /* transmit power (see [WUSB] section 5.2.1.2) */ 177 178#define QH_STATUS_FLOW_CTRL (1 << 15) 179#define QH_STATUS_ICUR(i) ((i) << 5) 180#define QH_STATUS_TO_ICUR(s) (((s) >> 5) & 0x7) 181#define QH_STATUS_SEQ_MASK 0x1f 182 183/** 184 * usb_pipe_to_qh_type - USB core pipe type to QH transfer type 185 * 186 * Returns the QH type field for a USB core pipe type. 187 */ 188static inline unsigned usb_pipe_to_qh_type(unsigned pipe) 189{ 190 static const unsigned type[] = { 191 [PIPE_ISOCHRONOUS] = QH_INFO1_TR_TYPE_ISOC, 192 [PIPE_INTERRUPT] = QH_INFO1_TR_TYPE_INT, 193 [PIPE_CONTROL] = QH_INFO1_TR_TYPE_CTRL, 194 [PIPE_BULK] = QH_INFO1_TR_TYPE_BULK, 195 }; 196 return type[usb_pipetype(pipe)]; 197} 198 199/** 200 * Maxiumum number of TDs in a qset. 201 */ 202#define WHCI_QSET_TD_MAX 8 203 204/** 205 * struct whc_qset - WUSB data transfers to a specific endpoint 206 * @qh: the QHead of this qset 207 * @qtd: up to 8 qTDs (for qsets for control, bulk and interrupt 208 * transfers) 209 * @itd: up to 8 iTDs (for qsets for isochronous transfers) 210 * @qset_dma: DMA address for this qset 211 * @whc: WHCI HC this qset is for 212 * @ep: endpoint 213 * @stds: list of sTDs queued to this qset 214 * @ntds: number of qTDs queued (not necessarily the same as nTDs 215 * field in the QH) 216 * @td_start: index of the first qTD in the list 217 * @td_end: index of next free qTD in the list (provided 218 * ntds < WHCI_QSET_TD_MAX) 219 * 220 * Queue Sets (qsets) are added to the asynchronous schedule list 221 * (ASL) or the periodic zone list (PZL). 222 * 223 * qsets may contain up to 8 TDs (either qTDs or iTDs as appropriate). 224 * Each TD may refer to at most 1 MiB of data. If a single transfer 225 * has > 8MiB of data, TDs can be reused as they are completed since 226 * the TD list is used as a circular buffer. Similarly, several 227 * (smaller) transfers may be queued in a qset. 228 * 229 * WHCI controllers may cache portions of the qsets in the ASL and 230 * PZL, requiring the WHCD to inform the WHC that the lists have been 231 * updated (fields changed or qsets inserted or removed). For safe 232 * insertion and removal of qsets from the lists the schedule must be 233 * stopped to avoid races in updating the QH link pointers. 234 * 235 * Since the HC is free to execute qsets in any order, all transfers 236 * to an endpoint should use the same qset to ensure transfers are 237 * executed in the order they're submitted. 238 * 239 * [WHCI] section 3.2.3 240 */ 241struct whc_qset { 242 struct whc_qhead qh; 243 union { 244 struct whc_qtd qtd[WHCI_QSET_TD_MAX]; 245 struct whc_itd itd[WHCI_QSET_TD_MAX]; 246 }; 247 248 /* private data for WHCD */ 249 dma_addr_t qset_dma; 250 struct whc *whc; 251 struct usb_host_endpoint *ep; 252 struct list_head stds; 253 int ntds; 254 int td_start; 255 int td_end; 256 struct list_head list_node; 257 unsigned in_sw_list:1; 258 unsigned in_hw_list:1; 259 unsigned remove:1; 260 unsigned reset:1; 261 struct urb *pause_after_urb; 262 struct completion remove_complete; 263 uint16_t max_packet; 264 uint8_t max_burst; 265 uint8_t max_seq; 266}; 267 268static inline void whc_qset_set_link_ptr(u64 *ptr, u64 target) 269{ 270 if (target) 271 *ptr = (*ptr & ~(QH_LINK_PTR_MASK | QH_LINK_T)) | QH_LINK_PTR(target); 272 else 273 *ptr = QH_LINK_T; 274} 275 276/** 277 * struct di_buf_entry - Device Information (DI) buffer entry. 278 * 279 * There's one of these per connected device. 280 */ 281struct di_buf_entry { 282 __le32 availability_info[8]; /*< MAS availability information, one MAS per bit */ 283 __le32 addr_sec_info; /*< addressing and security info */ 284 __le32 reserved[7]; 285} __attribute__((packed)); 286 287#define WHC_DI_SECURE (1 << 31) 288#define WHC_DI_DISABLE (1 << 30) 289#define WHC_DI_KEY_IDX(k) ((k) << 8) 290#define WHC_DI_KEY_IDX_MASK 0x0000ff00 291#define WHC_DI_DEV_ADDR(a) ((a) << 0) 292#define WHC_DI_DEV_ADDR_MASK 0x000000ff 293 294/** 295 * struct dn_buf_entry - Device Notification (DN) buffer entry. 296 * 297 * [WHCI] section 3.2.8 298 */ 299struct dn_buf_entry { 300 __u8 msg_size; /*< number of octets of valid DN data */ 301 __u8 reserved1; 302 __u8 src_addr; /*< source address */ 303 __u8 status; /*< buffer entry status */ 304 __le32 tkid; /*< TKID for source device, valid if secure bit is set */ 305 __u8 dn_data[56]; /*< up to 56 octets of DN data */ 306} __attribute__((packed)); 307 308#define WHC_DN_STATUS_VALID (1 << 7) /* buffer entry is valid */ 309#define WHC_DN_STATUS_SECURE (1 << 6) /* notification received using secure frame */ 310 311#define WHC_N_DN_ENTRIES (4096 / sizeof(struct dn_buf_entry)) 312 313/* The Add MMC IE WUSB Generic Command may take up to 256 bytes of 314 data. [WHCI] section 2.4.7. */ 315#define WHC_GEN_CMD_DATA_LEN 256 316 317/* 318 * HC registers. 319 * 320 * [WHCI] section 2.4 321 */ 322 323#define WHCIVERSION 0x00 324 325#define WHCSPARAMS 0x04 326# define WHCSPARAMS_TO_N_MMC_IES(p) (((p) >> 16) & 0xff) 327# define WHCSPARAMS_TO_N_KEYS(p) (((p) >> 8) & 0xff) 328# define WHCSPARAMS_TO_N_DEVICES(p) (((p) >> 0) & 0x7f) 329 330#define WUSBCMD 0x08 331# define WUSBCMD_BCID(b) ((b) << 16) 332# define WUSBCMD_BCID_MASK (0xff << 16) 333# define WUSBCMD_ASYNC_QSET_RM (1 << 12) 334# define WUSBCMD_PERIODIC_QSET_RM (1 << 11) 335# define WUSBCMD_WUSBSI(s) ((s) << 8) 336# define WUSBCMD_WUSBSI_MASK (0x7 << 8) 337# define WUSBCMD_ASYNC_SYNCED_DB (1 << 7) 338# define WUSBCMD_PERIODIC_SYNCED_DB (1 << 6) 339# define WUSBCMD_ASYNC_UPDATED (1 << 5) 340# define WUSBCMD_PERIODIC_UPDATED (1 << 4) 341# define WUSBCMD_ASYNC_EN (1 << 3) 342# define WUSBCMD_PERIODIC_EN (1 << 2) 343# define WUSBCMD_WHCRESET (1 << 1) 344# define WUSBCMD_RUN (1 << 0) 345 346#define WUSBSTS 0x0c 347# define WUSBSTS_ASYNC_SCHED (1 << 15) 348# define WUSBSTS_PERIODIC_SCHED (1 << 14) 349# define WUSBSTS_DNTS_SCHED (1 << 13) 350# define WUSBSTS_HCHALTED (1 << 12) 351# define WUSBSTS_GEN_CMD_DONE (1 << 9) 352# define WUSBSTS_CHAN_TIME_ROLLOVER (1 << 8) 353# define WUSBSTS_DNTS_OVERFLOW (1 << 7) 354# define WUSBSTS_BPST_ADJUSTMENT_CHANGED (1 << 6) 355# define WUSBSTS_HOST_ERR (1 << 5) 356# define WUSBSTS_ASYNC_SCHED_SYNCED (1 << 4) 357# define WUSBSTS_PERIODIC_SCHED_SYNCED (1 << 3) 358# define WUSBSTS_DNTS_INT (1 << 2) 359# define WUSBSTS_ERR_INT (1 << 1) 360# define WUSBSTS_INT (1 << 0) 361# define WUSBSTS_INT_MASK 0x3ff 362 363#define WUSBINTR 0x10 364# define WUSBINTR_GEN_CMD_DONE (1 << 9) 365# define WUSBINTR_CHAN_TIME_ROLLOVER (1 << 8) 366# define WUSBINTR_DNTS_OVERFLOW (1 << 7) 367# define WUSBINTR_BPST_ADJUSTMENT_CHANGED (1 << 6) 368# define WUSBINTR_HOST_ERR (1 << 5) 369# define WUSBINTR_ASYNC_SCHED_SYNCED (1 << 4) 370# define WUSBINTR_PERIODIC_SCHED_SYNCED (1 << 3) 371# define WUSBINTR_DNTS_INT (1 << 2) 372# define WUSBINTR_ERR_INT (1 << 1) 373# define WUSBINTR_INT (1 << 0) 374# define WUSBINTR_ALL 0x3ff 375 376#define WUSBGENCMDSTS 0x14 377# define WUSBGENCMDSTS_ACTIVE (1 << 31) 378# define WUSBGENCMDSTS_ERROR (1 << 24) 379# define WUSBGENCMDSTS_IOC (1 << 23) 380# define WUSBGENCMDSTS_MMCIE_ADD 0x01 381# define WUSBGENCMDSTS_MMCIE_RM 0x02 382# define WUSBGENCMDSTS_SET_MAS 0x03 383# define WUSBGENCMDSTS_CHAN_STOP 0x04 384# define WUSBGENCMDSTS_RWP_EN 0x05 385 386#define WUSBGENCMDPARAMS 0x18 387#define WUSBGENADDR 0x20 388#define WUSBASYNCLISTADDR 0x28 389#define WUSBDNTSBUFADDR 0x30 390#define WUSBDEVICEINFOADDR 0x38 391 392#define WUSBSETSECKEYCMD 0x40 393# define WUSBSETSECKEYCMD_SET (1 << 31) 394# define WUSBSETSECKEYCMD_ERASE (1 << 30) 395# define WUSBSETSECKEYCMD_GTK (1 << 8) 396# define WUSBSETSECKEYCMD_IDX(i) ((i) << 0) 397 398#define WUSBTKID 0x44 399#define WUSBSECKEY 0x48 400#define WUSBPERIODICLISTBASE 0x58 401#define WUSBMASINDEX 0x60 402 403#define WUSBDNTSCTRL 0x64 404# define WUSBDNTSCTRL_ACTIVE (1 << 31) 405# define WUSBDNTSCTRL_INTERVAL(i) ((i) << 8) 406# define WUSBDNTSCTRL_SLOTS(s) ((s) << 0) 407 408#define WUSBTIME 0x68 409# define WUSBTIME_CHANNEL_TIME_MASK 0x00ffffff 410 411#define WUSBBPST 0x6c 412#define WUSBDIBUPDATED 0x70 413 414#endif /* #ifndef _WHCI_WHCI_HC_H */ 415