linux/drivers/usb/host/xhci-ring.c
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   1/*
   2 * xHCI host controller driver
   3 *
   4 * Copyright (C) 2008 Intel Corp.
   5 *
   6 * Author: Sarah Sharp
   7 * Some code borrowed from the Linux EHCI driver.
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12 *
  13 * This program is distributed in the hope that it will be useful, but
  14 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  15 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 * for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software Foundation,
  20 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21 */
  22
  23/*
  24 * Ring initialization rules:
  25 * 1. Each segment is initialized to zero, except for link TRBs.
  26 * 2. Ring cycle state = 0.  This represents Producer Cycle State (PCS) or
  27 *    Consumer Cycle State (CCS), depending on ring function.
  28 * 3. Enqueue pointer = dequeue pointer = address of first TRB in the segment.
  29 *
  30 * Ring behavior rules:
  31 * 1. A ring is empty if enqueue == dequeue.  This means there will always be at
  32 *    least one free TRB in the ring.  This is useful if you want to turn that
  33 *    into a link TRB and expand the ring.
  34 * 2. When incrementing an enqueue or dequeue pointer, if the next TRB is a
  35 *    link TRB, then load the pointer with the address in the link TRB.  If the
  36 *    link TRB had its toggle bit set, you may need to update the ring cycle
  37 *    state (see cycle bit rules).  You may have to do this multiple times
  38 *    until you reach a non-link TRB.
  39 * 3. A ring is full if enqueue++ (for the definition of increment above)
  40 *    equals the dequeue pointer.
  41 *
  42 * Cycle bit rules:
  43 * 1. When a consumer increments a dequeue pointer and encounters a toggle bit
  44 *    in a link TRB, it must toggle the ring cycle state.
  45 * 2. When a producer increments an enqueue pointer and encounters a toggle bit
  46 *    in a link TRB, it must toggle the ring cycle state.
  47 *
  48 * Producer rules:
  49 * 1. Check if ring is full before you enqueue.
  50 * 2. Write the ring cycle state to the cycle bit in the TRB you're enqueuing.
  51 *    Update enqueue pointer between each write (which may update the ring
  52 *    cycle state).
  53 * 3. Notify consumer.  If SW is producer, it rings the doorbell for command
  54 *    and endpoint rings.  If HC is the producer for the event ring,
  55 *    and it generates an interrupt according to interrupt modulation rules.
  56 *
  57 * Consumer rules:
  58 * 1. Check if TRB belongs to you.  If the cycle bit == your ring cycle state,
  59 *    the TRB is owned by the consumer.
  60 * 2. Update dequeue pointer (which may update the ring cycle state) and
  61 *    continue processing TRBs until you reach a TRB which is not owned by you.
  62 * 3. Notify the producer.  SW is the consumer for the event ring, and it
  63 *   updates event ring dequeue pointer.  HC is the consumer for the command and
  64 *   endpoint rings; it generates events on the event ring for these.
  65 */
  66
  67#include <linux/scatterlist.h>
  68#include <linux/slab.h>
  69#include "xhci.h"
  70
  71static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
  72                struct xhci_virt_device *virt_dev,
  73                struct xhci_event_cmd *event);
  74
  75/*
  76 * Returns zero if the TRB isn't in this segment, otherwise it returns the DMA
  77 * address of the TRB.
  78 */
  79dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg,
  80                union xhci_trb *trb)
  81{
  82        unsigned long segment_offset;
  83
  84        if (!seg || !trb || trb < seg->trbs)
  85                return 0;
  86        /* offset in TRBs */
  87        segment_offset = trb - seg->trbs;
  88        if (segment_offset > TRBS_PER_SEGMENT)
  89                return 0;
  90        return seg->dma + (segment_offset * sizeof(*trb));
  91}
  92
  93/* Does this link TRB point to the first segment in a ring,
  94 * or was the previous TRB the last TRB on the last segment in the ERST?
  95 */
  96static bool last_trb_on_last_seg(struct xhci_hcd *xhci, struct xhci_ring *ring,
  97                struct xhci_segment *seg, union xhci_trb *trb)
  98{
  99        if (ring == xhci->event_ring)
 100                return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
 101                        (seg->next == xhci->event_ring->first_seg);
 102        else
 103                return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
 104}
 105
 106/* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
 107 * segment?  I.e. would the updated event TRB pointer step off the end of the
 108 * event seg?
 109 */
 110static int last_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
 111                struct xhci_segment *seg, union xhci_trb *trb)
 112{
 113        if (ring == xhci->event_ring)
 114                return trb == &seg->trbs[TRBS_PER_SEGMENT];
 115        else
 116                return TRB_TYPE_LINK_LE32(trb->link.control);
 117}
 118
 119static int enqueue_is_link_trb(struct xhci_ring *ring)
 120{
 121        struct xhci_link_trb *link = &ring->enqueue->link;
 122        return TRB_TYPE_LINK_LE32(link->control);
 123}
 124
 125/* Updates trb to point to the next TRB in the ring, and updates seg if the next
 126 * TRB is in a new segment.  This does not skip over link TRBs, and it does not
 127 * effect the ring dequeue or enqueue pointers.
 128 */
 129static void next_trb(struct xhci_hcd *xhci,
 130                struct xhci_ring *ring,
 131                struct xhci_segment **seg,
 132                union xhci_trb **trb)
 133{
 134        if (last_trb(xhci, ring, *seg, *trb)) {
 135                *seg = (*seg)->next;
 136                *trb = ((*seg)->trbs);
 137        } else {
 138                (*trb)++;
 139        }
 140}
 141
 142/*
 143 * See Cycle bit rules. SW is the consumer for the event ring only.
 144 * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 145 */
 146static void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring)
 147{
 148        unsigned long long addr;
 149
 150        ring->deq_updates++;
 151
 152        /*
 153         * If this is not event ring, and the dequeue pointer
 154         * is not on a link TRB, there is one more usable TRB
 155         */
 156        if (ring->type != TYPE_EVENT &&
 157                        !last_trb(xhci, ring, ring->deq_seg, ring->dequeue))
 158                ring->num_trbs_free++;
 159
 160        do {
 161                /*
 162                 * Update the dequeue pointer further if that was a link TRB or
 163                 * we're at the end of an event ring segment (which doesn't have
 164                 * link TRBS)
 165                 */
 166                if (last_trb(xhci, ring, ring->deq_seg, ring->dequeue)) {
 167                        if (ring->type == TYPE_EVENT &&
 168                                        last_trb_on_last_seg(xhci, ring,
 169                                                ring->deq_seg, ring->dequeue)) {
 170                                ring->cycle_state = (ring->cycle_state ? 0 : 1);
 171                        }
 172                        ring->deq_seg = ring->deq_seg->next;
 173                        ring->dequeue = ring->deq_seg->trbs;
 174                } else {
 175                        ring->dequeue++;
 176                }
 177        } while (last_trb(xhci, ring, ring->deq_seg, ring->dequeue));
 178
 179        addr = (unsigned long long) xhci_trb_virt_to_dma(ring->deq_seg, ring->dequeue);
 180}
 181
 182/*
 183 * See Cycle bit rules. SW is the consumer for the event ring only.
 184 * Don't make a ring full of link TRBs.  That would be dumb and this would loop.
 185 *
 186 * If we've just enqueued a TRB that is in the middle of a TD (meaning the
 187 * chain bit is set), then set the chain bit in all the following link TRBs.
 188 * If we've enqueued the last TRB in a TD, make sure the following link TRBs
 189 * have their chain bit cleared (so that each Link TRB is a separate TD).
 190 *
 191 * Section 6.4.4.1 of the 0.95 spec says link TRBs cannot have the chain bit
 192 * set, but other sections talk about dealing with the chain bit set.  This was
 193 * fixed in the 0.96 specification errata, but we have to assume that all 0.95
 194 * xHCI hardware can't handle the chain bit being cleared on a link TRB.
 195 *
 196 * @more_trbs_coming:   Will you enqueue more TRBs before calling
 197 *                      prepare_transfer()?
 198 */
 199static void inc_enq(struct xhci_hcd *xhci, struct xhci_ring *ring,
 200                        bool more_trbs_coming)
 201{
 202        u32 chain;
 203        union xhci_trb *next;
 204        unsigned long long addr;
 205
 206        chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
 207        /* If this is not event ring, there is one less usable TRB */
 208        if (ring->type != TYPE_EVENT &&
 209                        !last_trb(xhci, ring, ring->enq_seg, ring->enqueue))
 210                ring->num_trbs_free--;
 211        next = ++(ring->enqueue);
 212
 213        ring->enq_updates++;
 214        /* Update the dequeue pointer further if that was a link TRB or we're at
 215         * the end of an event ring segment (which doesn't have link TRBS)
 216         */
 217        while (last_trb(xhci, ring, ring->enq_seg, next)) {
 218                if (ring->type != TYPE_EVENT) {
 219                        /*
 220                         * If the caller doesn't plan on enqueueing more
 221                         * TDs before ringing the doorbell, then we
 222                         * don't want to give the link TRB to the
 223                         * hardware just yet.  We'll give the link TRB
 224                         * back in prepare_ring() just before we enqueue
 225                         * the TD at the top of the ring.
 226                         */
 227                        if (!chain && !more_trbs_coming)
 228                                break;
 229
 230                        /* If we're not dealing with 0.95 hardware or
 231                         * isoc rings on AMD 0.96 host,
 232                         * carry over the chain bit of the previous TRB
 233                         * (which may mean the chain bit is cleared).
 234                         */
 235                        if (!(ring->type == TYPE_ISOC &&
 236                                        (xhci->quirks & XHCI_AMD_0x96_HOST))
 237                                                && !xhci_link_trb_quirk(xhci)) {
 238                                next->link.control &=
 239                                        cpu_to_le32(~TRB_CHAIN);
 240                                next->link.control |=
 241                                        cpu_to_le32(chain);
 242                        }
 243                        /* Give this link TRB to the hardware */
 244                        wmb();
 245                        next->link.control ^= cpu_to_le32(TRB_CYCLE);
 246
 247                        /* Toggle the cycle bit after the last ring segment. */
 248                        if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
 249                                ring->cycle_state = (ring->cycle_state ? 0 : 1);
 250                        }
 251                }
 252                ring->enq_seg = ring->enq_seg->next;
 253                ring->enqueue = ring->enq_seg->trbs;
 254                next = ring->enqueue;
 255        }
 256        addr = (unsigned long long) xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
 257}
 258
 259/*
 260 * Check to see if there's room to enqueue num_trbs on the ring and make sure
 261 * enqueue pointer will not advance into dequeue segment. See rules above.
 262 */
 263static inline int room_on_ring(struct xhci_hcd *xhci, struct xhci_ring *ring,
 264                unsigned int num_trbs)
 265{
 266        int num_trbs_in_deq_seg;
 267
 268        if (ring->num_trbs_free < num_trbs)
 269                return 0;
 270
 271        if (ring->type != TYPE_COMMAND && ring->type != TYPE_EVENT) {
 272                num_trbs_in_deq_seg = ring->dequeue - ring->deq_seg->trbs;
 273                if (ring->num_trbs_free < num_trbs + num_trbs_in_deq_seg)
 274                        return 0;
 275        }
 276
 277        return 1;
 278}
 279
 280/* Ring the host controller doorbell after placing a command on the ring */
 281void xhci_ring_cmd_db(struct xhci_hcd *xhci)
 282{
 283        if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING))
 284                return;
 285
 286        xhci_dbg(xhci, "// Ding dong!\n");
 287        xhci_writel(xhci, DB_VALUE_HOST, &xhci->dba->doorbell[0]);
 288        /* Flush PCI posted writes */
 289        xhci_readl(xhci, &xhci->dba->doorbell[0]);
 290}
 291
 292static int xhci_abort_cmd_ring(struct xhci_hcd *xhci)
 293{
 294        u64 temp_64;
 295        int ret;
 296
 297        xhci_dbg(xhci, "Abort command ring\n");
 298
 299        if (!(xhci->cmd_ring_state & CMD_RING_STATE_RUNNING)) {
 300                xhci_dbg(xhci, "The command ring isn't running, "
 301                                "Have the command ring been stopped?\n");
 302                return 0;
 303        }
 304
 305        temp_64 = xhci_read_64(xhci, &xhci->op_regs->cmd_ring);
 306        if (!(temp_64 & CMD_RING_RUNNING)) {
 307                xhci_dbg(xhci, "Command ring had been stopped\n");
 308                return 0;
 309        }
 310        xhci->cmd_ring_state = CMD_RING_STATE_ABORTED;
 311        xhci_write_64(xhci, temp_64 | CMD_RING_ABORT,
 312                        &xhci->op_regs->cmd_ring);
 313
 314        /* Section 4.6.1.2 of xHCI 1.0 spec says software should
 315         * time the completion od all xHCI commands, including
 316         * the Command Abort operation. If software doesn't see
 317         * CRR negated in a timely manner (e.g. longer than 5
 318         * seconds), then it should assume that the there are
 319         * larger problems with the xHC and assert HCRST.
 320         */
 321        ret = xhci_handshake(xhci, &xhci->op_regs->cmd_ring,
 322                        CMD_RING_RUNNING, 0, 5 * 1000 * 1000);
 323        if (ret < 0) {
 324                xhci_err(xhci, "Stopped the command ring failed, "
 325                                "maybe the host is dead\n");
 326                xhci->xhc_state |= XHCI_STATE_DYING;
 327                xhci_quiesce(xhci);
 328                xhci_halt(xhci);
 329                return -ESHUTDOWN;
 330        }
 331
 332        return 0;
 333}
 334
 335static int xhci_queue_cd(struct xhci_hcd *xhci,
 336                struct xhci_command *command,
 337                union xhci_trb *cmd_trb)
 338{
 339        struct xhci_cd *cd;
 340        cd = kzalloc(sizeof(struct xhci_cd), GFP_ATOMIC);
 341        if (!cd)
 342                return -ENOMEM;
 343        INIT_LIST_HEAD(&cd->cancel_cmd_list);
 344
 345        cd->command = command;
 346        cd->cmd_trb = cmd_trb;
 347        list_add_tail(&cd->cancel_cmd_list, &xhci->cancel_cmd_list);
 348
 349        return 0;
 350}
 351
 352/*
 353 * Cancel the command which has issue.
 354 *
 355 * Some commands may hang due to waiting for acknowledgement from
 356 * usb device. It is outside of the xHC's ability to control and
 357 * will cause the command ring is blocked. When it occurs software
 358 * should intervene to recover the command ring.
 359 * See Section 4.6.1.1 and 4.6.1.2
 360 */
 361int xhci_cancel_cmd(struct xhci_hcd *xhci, struct xhci_command *command,
 362                union xhci_trb *cmd_trb)
 363{
 364        int retval = 0;
 365        unsigned long flags;
 366
 367        spin_lock_irqsave(&xhci->lock, flags);
 368
 369        if (xhci->xhc_state & XHCI_STATE_DYING) {
 370                xhci_warn(xhci, "Abort the command ring,"
 371                                " but the xHCI is dead.\n");
 372                retval = -ESHUTDOWN;
 373                goto fail;
 374        }
 375
 376        /* queue the cmd desriptor to cancel_cmd_list */
 377        retval = xhci_queue_cd(xhci, command, cmd_trb);
 378        if (retval) {
 379                xhci_warn(xhci, "Queuing command descriptor failed.\n");
 380                goto fail;
 381        }
 382
 383        /* abort command ring */
 384        retval = xhci_abort_cmd_ring(xhci);
 385        if (retval) {
 386                xhci_err(xhci, "Abort command ring failed\n");
 387                if (unlikely(retval == -ESHUTDOWN)) {
 388                        spin_unlock_irqrestore(&xhci->lock, flags);
 389                        usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 390                        xhci_dbg(xhci, "xHCI host controller is dead.\n");
 391                        return retval;
 392                }
 393        }
 394
 395fail:
 396        spin_unlock_irqrestore(&xhci->lock, flags);
 397        return retval;
 398}
 399
 400void xhci_ring_ep_doorbell(struct xhci_hcd *xhci,
 401                unsigned int slot_id,
 402                unsigned int ep_index,
 403                unsigned int stream_id)
 404{
 405        __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
 406        struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 407        unsigned int ep_state = ep->ep_state;
 408
 409        /* Don't ring the doorbell for this endpoint if there are pending
 410         * cancellations because we don't want to interrupt processing.
 411         * We don't want to restart any stream rings if there's a set dequeue
 412         * pointer command pending because the device can choose to start any
 413         * stream once the endpoint is on the HW schedule.
 414         * FIXME - check all the stream rings for pending cancellations.
 415         */
 416        if ((ep_state & EP_HALT_PENDING) || (ep_state & SET_DEQ_PENDING) ||
 417            (ep_state & EP_HALTED))
 418                return;
 419        xhci_writel(xhci, DB_VALUE(ep_index, stream_id), db_addr);
 420        /* The CPU has better things to do at this point than wait for a
 421         * write-posting flush.  It'll get there soon enough.
 422         */
 423}
 424
 425/* Ring the doorbell for any rings with pending URBs */
 426static void ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
 427                unsigned int slot_id,
 428                unsigned int ep_index)
 429{
 430        unsigned int stream_id;
 431        struct xhci_virt_ep *ep;
 432
 433        ep = &xhci->devs[slot_id]->eps[ep_index];
 434
 435        /* A ring has pending URBs if its TD list is not empty */
 436        if (!(ep->ep_state & EP_HAS_STREAMS)) {
 437                if (ep->ring && !(list_empty(&ep->ring->td_list)))
 438                        xhci_ring_ep_doorbell(xhci, slot_id, ep_index, 0);
 439                return;
 440        }
 441
 442        for (stream_id = 1; stream_id < ep->stream_info->num_streams;
 443                        stream_id++) {
 444                struct xhci_stream_info *stream_info = ep->stream_info;
 445                if (!list_empty(&stream_info->stream_rings[stream_id]->td_list))
 446                        xhci_ring_ep_doorbell(xhci, slot_id, ep_index,
 447                                                stream_id);
 448        }
 449}
 450
 451/*
 452 * Find the segment that trb is in.  Start searching in start_seg.
 453 * If we must move past a segment that has a link TRB with a toggle cycle state
 454 * bit set, then we will toggle the value pointed at by cycle_state.
 455 */
 456static struct xhci_segment *find_trb_seg(
 457                struct xhci_segment *start_seg,
 458                union xhci_trb  *trb, int *cycle_state)
 459{
 460        struct xhci_segment *cur_seg = start_seg;
 461        struct xhci_generic_trb *generic_trb;
 462
 463        while (cur_seg->trbs > trb ||
 464                        &cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
 465                generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
 466                if (generic_trb->field[3] & cpu_to_le32(LINK_TOGGLE))
 467                        *cycle_state ^= 0x1;
 468                cur_seg = cur_seg->next;
 469                if (cur_seg == start_seg)
 470                        /* Looped over the entire list.  Oops! */
 471                        return NULL;
 472        }
 473        return cur_seg;
 474}
 475
 476
 477static struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
 478                unsigned int slot_id, unsigned int ep_index,
 479                unsigned int stream_id)
 480{
 481        struct xhci_virt_ep *ep;
 482
 483        ep = &xhci->devs[slot_id]->eps[ep_index];
 484        /* Common case: no streams */
 485        if (!(ep->ep_state & EP_HAS_STREAMS))
 486                return ep->ring;
 487
 488        if (stream_id == 0) {
 489                xhci_warn(xhci,
 490                                "WARN: Slot ID %u, ep index %u has streams, "
 491                                "but URB has no stream ID.\n",
 492                                slot_id, ep_index);
 493                return NULL;
 494        }
 495
 496        if (stream_id < ep->stream_info->num_streams)
 497                return ep->stream_info->stream_rings[stream_id];
 498
 499        xhci_warn(xhci,
 500                        "WARN: Slot ID %u, ep index %u has "
 501                        "stream IDs 1 to %u allocated, "
 502                        "but stream ID %u is requested.\n",
 503                        slot_id, ep_index,
 504                        ep->stream_info->num_streams - 1,
 505                        stream_id);
 506        return NULL;
 507}
 508
 509/* Get the right ring for the given URB.
 510 * If the endpoint supports streams, boundary check the URB's stream ID.
 511 * If the endpoint doesn't support streams, return the singular endpoint ring.
 512 */
 513static struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
 514                struct urb *urb)
 515{
 516        return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
 517                xhci_get_endpoint_index(&urb->ep->desc), urb->stream_id);
 518}
 519
 520/*
 521 * Move the xHC's endpoint ring dequeue pointer past cur_td.
 522 * Record the new state of the xHC's endpoint ring dequeue segment,
 523 * dequeue pointer, and new consumer cycle state in state.
 524 * Update our internal representation of the ring's dequeue pointer.
 525 *
 526 * We do this in three jumps:
 527 *  - First we update our new ring state to be the same as when the xHC stopped.
 528 *  - Then we traverse the ring to find the segment that contains
 529 *    the last TRB in the TD.  We toggle the xHC's new cycle state when we pass
 530 *    any link TRBs with the toggle cycle bit set.
 531 *  - Finally we move the dequeue state one TRB further, toggling the cycle bit
 532 *    if we've moved it past a link TRB with the toggle cycle bit set.
 533 *
 534 * Some of the uses of xhci_generic_trb are grotty, but if they're done
 535 * with correct __le32 accesses they should work fine.  Only users of this are
 536 * in here.
 537 */
 538void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
 539                unsigned int slot_id, unsigned int ep_index,
 540                unsigned int stream_id, struct xhci_td *cur_td,
 541                struct xhci_dequeue_state *state)
 542{
 543        struct xhci_virt_device *dev = xhci->devs[slot_id];
 544        struct xhci_ring *ep_ring;
 545        struct xhci_generic_trb *trb;
 546        struct xhci_ep_ctx *ep_ctx;
 547        dma_addr_t addr;
 548
 549        ep_ring = xhci_triad_to_transfer_ring(xhci, slot_id,
 550                        ep_index, stream_id);
 551        if (!ep_ring) {
 552                xhci_warn(xhci, "WARN can't find new dequeue state "
 553                                "for invalid stream ID %u.\n",
 554                                stream_id);
 555                return;
 556        }
 557        state->new_cycle_state = 0;
 558        xhci_dbg(xhci, "Finding segment containing stopped TRB.\n");
 559        state->new_deq_seg = find_trb_seg(cur_td->start_seg,
 560                        dev->eps[ep_index].stopped_trb,
 561                        &state->new_cycle_state);
 562        if (!state->new_deq_seg) {
 563                WARN_ON(1);
 564                return;
 565        }
 566
 567        /* Dig out the cycle state saved by the xHC during the stop ep cmd */
 568        xhci_dbg(xhci, "Finding endpoint context\n");
 569        ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
 570        state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
 571
 572        state->new_deq_ptr = cur_td->last_trb;
 573        xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
 574        state->new_deq_seg = find_trb_seg(state->new_deq_seg,
 575                        state->new_deq_ptr,
 576                        &state->new_cycle_state);
 577        if (!state->new_deq_seg) {
 578                WARN_ON(1);
 579                return;
 580        }
 581
 582        trb = &state->new_deq_ptr->generic;
 583        if (TRB_TYPE_LINK_LE32(trb->field[3]) &&
 584            (trb->field[3] & cpu_to_le32(LINK_TOGGLE)))
 585                state->new_cycle_state ^= 0x1;
 586        next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
 587
 588        /*
 589         * If there is only one segment in a ring, find_trb_seg()'s while loop
 590         * will not run, and it will return before it has a chance to see if it
 591         * needs to toggle the cycle bit.  It can't tell if the stalled transfer
 592         * ended just before the link TRB on a one-segment ring, or if the TD
 593         * wrapped around the top of the ring, because it doesn't have the TD in
 594         * question.  Look for the one-segment case where stalled TRB's address
 595         * is greater than the new dequeue pointer address.
 596         */
 597        if (ep_ring->first_seg == ep_ring->first_seg->next &&
 598                        state->new_deq_ptr < dev->eps[ep_index].stopped_trb)
 599                state->new_cycle_state ^= 0x1;
 600        xhci_dbg(xhci, "Cycle state = 0x%x\n", state->new_cycle_state);
 601
 602        /* Don't update the ring cycle state for the producer (us). */
 603        xhci_dbg(xhci, "New dequeue segment = %p (virtual)\n",
 604                        state->new_deq_seg);
 605        addr = xhci_trb_virt_to_dma(state->new_deq_seg, state->new_deq_ptr);
 606        xhci_dbg(xhci, "New dequeue pointer = 0x%llx (DMA)\n",
 607                        (unsigned long long) addr);
 608}
 609
 610/* flip_cycle means flip the cycle bit of all but the first and last TRB.
 611 * (The last TRB actually points to the ring enqueue pointer, which is not part
 612 * of this TD.)  This is used to remove partially enqueued isoc TDs from a ring.
 613 */
 614static void td_to_noop(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
 615                struct xhci_td *cur_td, bool flip_cycle)
 616{
 617        struct xhci_segment *cur_seg;
 618        union xhci_trb *cur_trb;
 619
 620        for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
 621                        true;
 622                        next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
 623                if (TRB_TYPE_LINK_LE32(cur_trb->generic.field[3])) {
 624                        /* Unchain any chained Link TRBs, but
 625                         * leave the pointers intact.
 626                         */
 627                        cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
 628                        /* Flip the cycle bit (link TRBs can't be the first
 629                         * or last TRB).
 630                         */
 631                        if (flip_cycle)
 632                                cur_trb->generic.field[3] ^=
 633                                        cpu_to_le32(TRB_CYCLE);
 634                        xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
 635                        xhci_dbg(xhci, "Address = %p (0x%llx dma); "
 636                                        "in seg %p (0x%llx dma)\n",
 637                                        cur_trb,
 638                                        (unsigned long long)xhci_trb_virt_to_dma(cur_seg, cur_trb),
 639                                        cur_seg,
 640                                        (unsigned long long)cur_seg->dma);
 641                } else {
 642                        cur_trb->generic.field[0] = 0;
 643                        cur_trb->generic.field[1] = 0;
 644                        cur_trb->generic.field[2] = 0;
 645                        /* Preserve only the cycle bit of this TRB */
 646                        cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
 647                        /* Flip the cycle bit except on the first or last TRB */
 648                        if (flip_cycle && cur_trb != cur_td->first_trb &&
 649                                        cur_trb != cur_td->last_trb)
 650                                cur_trb->generic.field[3] ^=
 651                                        cpu_to_le32(TRB_CYCLE);
 652                        cur_trb->generic.field[3] |= cpu_to_le32(
 653                                TRB_TYPE(TRB_TR_NOOP));
 654                        xhci_dbg(xhci, "TRB to noop at offset 0x%llx\n",
 655                                        (unsigned long long)
 656                                        xhci_trb_virt_to_dma(cur_seg, cur_trb));
 657                }
 658                if (cur_trb == cur_td->last_trb)
 659                        break;
 660        }
 661}
 662
 663static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
 664                unsigned int ep_index, unsigned int stream_id,
 665                struct xhci_segment *deq_seg,
 666                union xhci_trb *deq_ptr, u32 cycle_state);
 667
 668void xhci_queue_new_dequeue_state(struct xhci_hcd *xhci,
 669                unsigned int slot_id, unsigned int ep_index,
 670                unsigned int stream_id,
 671                struct xhci_dequeue_state *deq_state)
 672{
 673        struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
 674
 675        xhci_dbg(xhci, "Set TR Deq Ptr cmd, new deq seg = %p (0x%llx dma), "
 676                        "new deq ptr = %p (0x%llx dma), new cycle = %u\n",
 677                        deq_state->new_deq_seg,
 678                        (unsigned long long)deq_state->new_deq_seg->dma,
 679                        deq_state->new_deq_ptr,
 680                        (unsigned long long)xhci_trb_virt_to_dma(deq_state->new_deq_seg, deq_state->new_deq_ptr),
 681                        deq_state->new_cycle_state);
 682        queue_set_tr_deq(xhci, slot_id, ep_index, stream_id,
 683                        deq_state->new_deq_seg,
 684                        deq_state->new_deq_ptr,
 685                        (u32) deq_state->new_cycle_state);
 686        /* Stop the TD queueing code from ringing the doorbell until
 687         * this command completes.  The HC won't set the dequeue pointer
 688         * if the ring is running, and ringing the doorbell starts the
 689         * ring running.
 690         */
 691        ep->ep_state |= SET_DEQ_PENDING;
 692}
 693
 694static void xhci_stop_watchdog_timer_in_irq(struct xhci_hcd *xhci,
 695                struct xhci_virt_ep *ep)
 696{
 697        ep->ep_state &= ~EP_HALT_PENDING;
 698        /* Can't del_timer_sync in interrupt, so we attempt to cancel.  If the
 699         * timer is running on another CPU, we don't decrement stop_cmds_pending
 700         * (since we didn't successfully stop the watchdog timer).
 701         */
 702        if (del_timer(&ep->stop_cmd_timer))
 703                ep->stop_cmds_pending--;
 704}
 705
 706/* Must be called with xhci->lock held in interrupt context */
 707static void xhci_giveback_urb_in_irq(struct xhci_hcd *xhci,
 708                struct xhci_td *cur_td, int status, char *adjective)
 709{
 710        struct usb_hcd *hcd;
 711        struct urb      *urb;
 712        struct urb_priv *urb_priv;
 713
 714        urb = cur_td->urb;
 715        urb_priv = urb->hcpriv;
 716        urb_priv->td_cnt++;
 717        hcd = bus_to_hcd(urb->dev->bus);
 718
 719        /* Only giveback urb when this is the last td in urb */
 720        if (urb_priv->td_cnt == urb_priv->length) {
 721                if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
 722                        xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
 723                        if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
 724                                if (xhci->quirks & XHCI_AMD_PLL_FIX)
 725                                        usb_amd_quirk_pll_enable();
 726                        }
 727                }
 728                usb_hcd_unlink_urb_from_ep(hcd, urb);
 729
 730                spin_unlock(&xhci->lock);
 731                usb_hcd_giveback_urb(hcd, urb, status);
 732                xhci_urb_free_priv(xhci, urb_priv);
 733                spin_lock(&xhci->lock);
 734        }
 735}
 736
 737/*
 738 * When we get a command completion for a Stop Endpoint Command, we need to
 739 * unlink any cancelled TDs from the ring.  There are two ways to do that:
 740 *
 741 *  1. If the HW was in the middle of processing the TD that needs to be
 742 *     cancelled, then we must move the ring's dequeue pointer past the last TRB
 743 *     in the TD with a Set Dequeue Pointer Command.
 744 *  2. Otherwise, we turn all the TRBs in the TD into No-op TRBs (with the chain
 745 *     bit cleared) so that the HW will skip over them.
 746 */
 747static void handle_stopped_endpoint(struct xhci_hcd *xhci,
 748                union xhci_trb *trb, struct xhci_event_cmd *event)
 749{
 750        unsigned int slot_id;
 751        unsigned int ep_index;
 752        struct xhci_virt_device *virt_dev;
 753        struct xhci_ring *ep_ring;
 754        struct xhci_virt_ep *ep;
 755        struct list_head *entry;
 756        struct xhci_td *cur_td = NULL;
 757        struct xhci_td *last_unlinked_td;
 758
 759        struct xhci_dequeue_state deq_state;
 760
 761        if (unlikely(TRB_TO_SUSPEND_PORT(
 762                             le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
 763                slot_id = TRB_TO_SLOT_ID(
 764                        le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
 765                virt_dev = xhci->devs[slot_id];
 766                if (virt_dev)
 767                        handle_cmd_in_cmd_wait_list(xhci, virt_dev,
 768                                event);
 769                else
 770                        xhci_warn(xhci, "Stop endpoint command "
 771                                "completion for disabled slot %u\n",
 772                                slot_id);
 773                return;
 774        }
 775
 776        memset(&deq_state, 0, sizeof(deq_state));
 777        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
 778        ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
 779        ep = &xhci->devs[slot_id]->eps[ep_index];
 780
 781        if (list_empty(&ep->cancelled_td_list)) {
 782                xhci_stop_watchdog_timer_in_irq(xhci, ep);
 783                ep->stopped_td = NULL;
 784                ep->stopped_trb = NULL;
 785                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 786                return;
 787        }
 788
 789        /* Fix up the ep ring first, so HW stops executing cancelled TDs.
 790         * We have the xHCI lock, so nothing can modify this list until we drop
 791         * it.  We're also in the event handler, so we can't get re-interrupted
 792         * if another Stop Endpoint command completes
 793         */
 794        list_for_each(entry, &ep->cancelled_td_list) {
 795                cur_td = list_entry(entry, struct xhci_td, cancelled_td_list);
 796                xhci_dbg(xhci, "Removing canceled TD starting at 0x%llx (dma).\n",
 797                                (unsigned long long)xhci_trb_virt_to_dma(
 798                                        cur_td->start_seg, cur_td->first_trb));
 799                ep_ring = xhci_urb_to_transfer_ring(xhci, cur_td->urb);
 800                if (!ep_ring) {
 801                        /* This shouldn't happen unless a driver is mucking
 802                         * with the stream ID after submission.  This will
 803                         * leave the TD on the hardware ring, and the hardware
 804                         * will try to execute it, and may access a buffer
 805                         * that has already been freed.  In the best case, the
 806                         * hardware will execute it, and the event handler will
 807                         * ignore the completion event for that TD, since it was
 808                         * removed from the td_list for that endpoint.  In
 809                         * short, don't muck with the stream ID after
 810                         * submission.
 811                         */
 812                        xhci_warn(xhci, "WARN Cancelled URB %p "
 813                                        "has invalid stream ID %u.\n",
 814                                        cur_td->urb,
 815                                        cur_td->urb->stream_id);
 816                        goto remove_finished_td;
 817                }
 818                /*
 819                 * If we stopped on the TD we need to cancel, then we have to
 820                 * move the xHC endpoint ring dequeue pointer past this TD.
 821                 */
 822                if (cur_td == ep->stopped_td)
 823                        xhci_find_new_dequeue_state(xhci, slot_id, ep_index,
 824                                        cur_td->urb->stream_id,
 825                                        cur_td, &deq_state);
 826                else
 827                        td_to_noop(xhci, ep_ring, cur_td, false);
 828remove_finished_td:
 829                /*
 830                 * The event handler won't see a completion for this TD anymore,
 831                 * so remove it from the endpoint ring's TD list.  Keep it in
 832                 * the cancelled TD list for URB completion later.
 833                 */
 834                list_del_init(&cur_td->td_list);
 835        }
 836        last_unlinked_td = cur_td;
 837        xhci_stop_watchdog_timer_in_irq(xhci, ep);
 838
 839        /* If necessary, queue a Set Transfer Ring Dequeue Pointer command */
 840        if (deq_state.new_deq_ptr && deq_state.new_deq_seg) {
 841                xhci_queue_new_dequeue_state(xhci,
 842                                slot_id, ep_index,
 843                                ep->stopped_td->urb->stream_id,
 844                                &deq_state);
 845                xhci_ring_cmd_db(xhci);
 846        } else {
 847                /* Otherwise ring the doorbell(s) to restart queued transfers */
 848                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
 849        }
 850        ep->stopped_td = NULL;
 851        ep->stopped_trb = NULL;
 852
 853        /*
 854         * Drop the lock and complete the URBs in the cancelled TD list.
 855         * New TDs to be cancelled might be added to the end of the list before
 856         * we can complete all the URBs for the TDs we already unlinked.
 857         * So stop when we've completed the URB for the last TD we unlinked.
 858         */
 859        do {
 860                cur_td = list_entry(ep->cancelled_td_list.next,
 861                                struct xhci_td, cancelled_td_list);
 862                list_del_init(&cur_td->cancelled_td_list);
 863
 864                /* Clean up the cancelled URB */
 865                /* Doesn't matter what we pass for status, since the core will
 866                 * just overwrite it (because the URB has been unlinked).
 867                 */
 868                xhci_giveback_urb_in_irq(xhci, cur_td, 0, "cancelled");
 869
 870                /* Stop processing the cancelled list if the watchdog timer is
 871                 * running.
 872                 */
 873                if (xhci->xhc_state & XHCI_STATE_DYING)
 874                        return;
 875        } while (cur_td != last_unlinked_td);
 876
 877        /* Return to the event handler with xhci->lock re-acquired */
 878}
 879
 880/* Watchdog timer function for when a stop endpoint command fails to complete.
 881 * In this case, we assume the host controller is broken or dying or dead.  The
 882 * host may still be completing some other events, so we have to be careful to
 883 * let the event ring handler and the URB dequeueing/enqueueing functions know
 884 * through xhci->state.
 885 *
 886 * The timer may also fire if the host takes a very long time to respond to the
 887 * command, and the stop endpoint command completion handler cannot delete the
 888 * timer before the timer function is called.  Another endpoint cancellation may
 889 * sneak in before the timer function can grab the lock, and that may queue
 890 * another stop endpoint command and add the timer back.  So we cannot use a
 891 * simple flag to say whether there is a pending stop endpoint command for a
 892 * particular endpoint.
 893 *
 894 * Instead we use a combination of that flag and a counter for the number of
 895 * pending stop endpoint commands.  If the timer is the tail end of the last
 896 * stop endpoint command, and the endpoint's command is still pending, we assume
 897 * the host is dying.
 898 */
 899void xhci_stop_endpoint_command_watchdog(unsigned long arg)
 900{
 901        struct xhci_hcd *xhci;
 902        struct xhci_virt_ep *ep;
 903        struct xhci_virt_ep *temp_ep;
 904        struct xhci_ring *ring;
 905        struct xhci_td *cur_td;
 906        int ret, i, j;
 907        unsigned long flags;
 908
 909        ep = (struct xhci_virt_ep *) arg;
 910        xhci = ep->xhci;
 911
 912        spin_lock_irqsave(&xhci->lock, flags);
 913
 914        ep->stop_cmds_pending--;
 915        if (xhci->xhc_state & XHCI_STATE_DYING) {
 916                xhci_dbg(xhci, "Stop EP timer ran, but another timer marked "
 917                                "xHCI as DYING, exiting.\n");
 918                spin_unlock_irqrestore(&xhci->lock, flags);
 919                return;
 920        }
 921        if (!(ep->stop_cmds_pending == 0 && (ep->ep_state & EP_HALT_PENDING))) {
 922                xhci_dbg(xhci, "Stop EP timer ran, but no command pending, "
 923                                "exiting.\n");
 924                spin_unlock_irqrestore(&xhci->lock, flags);
 925                return;
 926        }
 927
 928        xhci_warn(xhci, "xHCI host not responding to stop endpoint command.\n");
 929        xhci_warn(xhci, "Assuming host is dying, halting host.\n");
 930        /* Oops, HC is dead or dying or at least not responding to the stop
 931         * endpoint command.
 932         */
 933        xhci->xhc_state |= XHCI_STATE_DYING;
 934        /* Disable interrupts from the host controller and start halting it */
 935        xhci_quiesce(xhci);
 936        spin_unlock_irqrestore(&xhci->lock, flags);
 937
 938        ret = xhci_halt(xhci);
 939
 940        spin_lock_irqsave(&xhci->lock, flags);
 941        if (ret < 0) {
 942                /* This is bad; the host is not responding to commands and it's
 943                 * not allowing itself to be halted.  At least interrupts are
 944                 * disabled. If we call usb_hc_died(), it will attempt to
 945                 * disconnect all device drivers under this host.  Those
 946                 * disconnect() methods will wait for all URBs to be unlinked,
 947                 * so we must complete them.
 948                 */
 949                xhci_warn(xhci, "Non-responsive xHCI host is not halting.\n");
 950                xhci_warn(xhci, "Completing active URBs anyway.\n");
 951                /* We could turn all TDs on the rings to no-ops.  This won't
 952                 * help if the host has cached part of the ring, and is slow if
 953                 * we want to preserve the cycle bit.  Skip it and hope the host
 954                 * doesn't touch the memory.
 955                 */
 956        }
 957        for (i = 0; i < MAX_HC_SLOTS; i++) {
 958                if (!xhci->devs[i])
 959                        continue;
 960                for (j = 0; j < 31; j++) {
 961                        temp_ep = &xhci->devs[i]->eps[j];
 962                        ring = temp_ep->ring;
 963                        if (!ring)
 964                                continue;
 965                        xhci_dbg(xhci, "Killing URBs for slot ID %u, "
 966                                        "ep index %u\n", i, j);
 967                        while (!list_empty(&ring->td_list)) {
 968                                cur_td = list_first_entry(&ring->td_list,
 969                                                struct xhci_td,
 970                                                td_list);
 971                                list_del_init(&cur_td->td_list);
 972                                if (!list_empty(&cur_td->cancelled_td_list))
 973                                        list_del_init(&cur_td->cancelled_td_list);
 974                                xhci_giveback_urb_in_irq(xhci, cur_td,
 975                                                -ESHUTDOWN, "killed");
 976                        }
 977                        while (!list_empty(&temp_ep->cancelled_td_list)) {
 978                                cur_td = list_first_entry(
 979                                                &temp_ep->cancelled_td_list,
 980                                                struct xhci_td,
 981                                                cancelled_td_list);
 982                                list_del_init(&cur_td->cancelled_td_list);
 983                                xhci_giveback_urb_in_irq(xhci, cur_td,
 984                                                -ESHUTDOWN, "killed");
 985                        }
 986                }
 987        }
 988        spin_unlock_irqrestore(&xhci->lock, flags);
 989        xhci_dbg(xhci, "Calling usb_hc_died()\n");
 990        usb_hc_died(xhci_to_hcd(xhci)->primary_hcd);
 991        xhci_dbg(xhci, "xHCI host controller is dead.\n");
 992}
 993
 994
 995static void update_ring_for_set_deq_completion(struct xhci_hcd *xhci,
 996                struct xhci_virt_device *dev,
 997                struct xhci_ring *ep_ring,
 998                unsigned int ep_index)
 999{
1000        union xhci_trb *dequeue_temp;
1001        int num_trbs_free_temp;
1002        bool revert = false;
1003
1004        num_trbs_free_temp = ep_ring->num_trbs_free;
1005        dequeue_temp = ep_ring->dequeue;
1006
1007        /* If we get two back-to-back stalls, and the first stalled transfer
1008         * ends just before a link TRB, the dequeue pointer will be left on
1009         * the link TRB by the code in the while loop.  So we have to update
1010         * the dequeue pointer one segment further, or we'll jump off
1011         * the segment into la-la-land.
1012         */
1013        if (last_trb(xhci, ep_ring, ep_ring->deq_seg, ep_ring->dequeue)) {
1014                ep_ring->deq_seg = ep_ring->deq_seg->next;
1015                ep_ring->dequeue = ep_ring->deq_seg->trbs;
1016        }
1017
1018        while (ep_ring->dequeue != dev->eps[ep_index].queued_deq_ptr) {
1019                /* We have more usable TRBs */
1020                ep_ring->num_trbs_free++;
1021                ep_ring->dequeue++;
1022                if (last_trb(xhci, ep_ring, ep_ring->deq_seg,
1023                                ep_ring->dequeue)) {
1024                        if (ep_ring->dequeue ==
1025                                        dev->eps[ep_index].queued_deq_ptr)
1026                                break;
1027                        ep_ring->deq_seg = ep_ring->deq_seg->next;
1028                        ep_ring->dequeue = ep_ring->deq_seg->trbs;
1029                }
1030                if (ep_ring->dequeue == dequeue_temp) {
1031                        revert = true;
1032                        break;
1033                }
1034        }
1035
1036        if (revert) {
1037                xhci_dbg(xhci, "Unable to find new dequeue pointer\n");
1038                ep_ring->num_trbs_free = num_trbs_free_temp;
1039        }
1040}
1041
1042/*
1043 * When we get a completion for a Set Transfer Ring Dequeue Pointer command,
1044 * we need to clear the set deq pending flag in the endpoint ring state, so that
1045 * the TD queueing code can ring the doorbell again.  We also need to ring the
1046 * endpoint doorbell to restart the ring, but only if there aren't more
1047 * cancellations pending.
1048 */
1049static void handle_set_deq_completion(struct xhci_hcd *xhci,
1050                struct xhci_event_cmd *event,
1051                union xhci_trb *trb)
1052{
1053        unsigned int slot_id;
1054        unsigned int ep_index;
1055        unsigned int stream_id;
1056        struct xhci_ring *ep_ring;
1057        struct xhci_virt_device *dev;
1058        struct xhci_ep_ctx *ep_ctx;
1059        struct xhci_slot_ctx *slot_ctx;
1060
1061        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1062        ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1063        stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
1064        dev = xhci->devs[slot_id];
1065
1066        ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
1067        if (!ep_ring) {
1068                xhci_warn(xhci, "WARN Set TR deq ptr command for "
1069                                "freed stream ID %u\n",
1070                                stream_id);
1071                /* XXX: Harmless??? */
1072                dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1073                return;
1074        }
1075
1076        ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
1077        slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
1078
1079        if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
1080                unsigned int ep_state;
1081                unsigned int slot_state;
1082
1083                switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
1084                case COMP_TRB_ERR:
1085                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
1086                                        "of stream ID configuration\n");
1087                        break;
1088                case COMP_CTX_STATE:
1089                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
1090                                        "to incorrect slot or ep state.\n");
1091                        ep_state = le32_to_cpu(ep_ctx->ep_info);
1092                        ep_state &= EP_STATE_MASK;
1093                        slot_state = le32_to_cpu(slot_ctx->dev_state);
1094                        slot_state = GET_SLOT_STATE(slot_state);
1095                        xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
1096                                        slot_state, ep_state);
1097                        break;
1098                case COMP_EBADSLT:
1099                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed because "
1100                                        "slot %u was not enabled.\n", slot_id);
1101                        break;
1102                default:
1103                        xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
1104                                        "completion code of %u.\n",
1105                                  GET_COMP_CODE(le32_to_cpu(event->status)));
1106                        break;
1107                }
1108                /* OK what do we do now?  The endpoint state is hosed, and we
1109                 * should never get to this point if the synchronization between
1110                 * queueing, and endpoint state are correct.  This might happen
1111                 * if the device gets disconnected after we've finished
1112                 * cancelling URBs, which might not be an error...
1113                 */
1114        } else {
1115                xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
1116                         le64_to_cpu(ep_ctx->deq));
1117                if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
1118                                         dev->eps[ep_index].queued_deq_ptr) ==
1119                    (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
1120                        /* Update the ring's dequeue segment and dequeue pointer
1121                         * to reflect the new position.
1122                         */
1123                        update_ring_for_set_deq_completion(xhci, dev,
1124                                ep_ring, ep_index);
1125                } else {
1126                        xhci_warn(xhci, "Mismatch between completed Set TR Deq "
1127                                        "Ptr command & xHCI internal state.\n");
1128                        xhci_warn(xhci, "ep deq seg = %p, deq ptr = %p\n",
1129                                        dev->eps[ep_index].queued_deq_seg,
1130                                        dev->eps[ep_index].queued_deq_ptr);
1131                }
1132        }
1133
1134        dev->eps[ep_index].ep_state &= ~SET_DEQ_PENDING;
1135        dev->eps[ep_index].queued_deq_seg = NULL;
1136        dev->eps[ep_index].queued_deq_ptr = NULL;
1137        /* Restart any rings with pending URBs */
1138        ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1139}
1140
1141static void handle_reset_ep_completion(struct xhci_hcd *xhci,
1142                struct xhci_event_cmd *event,
1143                union xhci_trb *trb)
1144{
1145        int slot_id;
1146        unsigned int ep_index;
1147
1148        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
1149        ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
1150        /* This command will only fail if the endpoint wasn't halted,
1151         * but we don't care.
1152         */
1153        xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
1154                 GET_COMP_CODE(le32_to_cpu(event->status)));
1155
1156        /* HW with the reset endpoint quirk needs to have a configure endpoint
1157         * command complete before the endpoint can be used.  Queue that here
1158         * because the HW can't handle two commands being queued in a row.
1159         */
1160        if (xhci->quirks & XHCI_RESET_EP_QUIRK) {
1161                xhci_dbg(xhci, "Queueing configure endpoint command\n");
1162                xhci_queue_configure_endpoint(xhci,
1163                                xhci->devs[slot_id]->in_ctx->dma, slot_id,
1164                                false);
1165                xhci_ring_cmd_db(xhci);
1166        } else {
1167                /* Clear our internal halted state and restart the ring(s) */
1168                xhci->devs[slot_id]->eps[ep_index].ep_state &= ~EP_HALTED;
1169                ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1170        }
1171}
1172
1173/* Complete the command and detele it from the devcie's command queue.
1174 */
1175static void xhci_complete_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1176                struct xhci_command *command, u32 status)
1177{
1178        command->status = status;
1179        list_del(&command->cmd_list);
1180        if (command->completion)
1181                complete(command->completion);
1182        else
1183                xhci_free_command(xhci, command);
1184}
1185
1186
1187/* Check to see if a command in the device's command queue matches this one.
1188 * Signal the completion or free the command, and return 1.  Return 0 if the
1189 * completed command isn't at the head of the command list.
1190 */
1191static int handle_cmd_in_cmd_wait_list(struct xhci_hcd *xhci,
1192                struct xhci_virt_device *virt_dev,
1193                struct xhci_event_cmd *event)
1194{
1195        struct xhci_command *command;
1196
1197        if (list_empty(&virt_dev->cmd_list))
1198                return 0;
1199
1200        command = list_entry(virt_dev->cmd_list.next,
1201                        struct xhci_command, cmd_list);
1202        if (xhci->cmd_ring->dequeue != command->command_trb)
1203                return 0;
1204
1205        xhci_complete_cmd_in_cmd_wait_list(xhci, command,
1206                        GET_COMP_CODE(le32_to_cpu(event->status)));
1207        return 1;
1208}
1209
1210/*
1211 * Finding the command trb need to be cancelled and modifying it to
1212 * NO OP command. And if the command is in device's command wait
1213 * list, finishing and freeing it.
1214 *
1215 * If we can't find the command trb, we think it had already been
1216 * executed.
1217 */
1218static void xhci_cmd_to_noop(struct xhci_hcd *xhci, struct xhci_cd *cur_cd)
1219{
1220        struct xhci_segment *cur_seg;
1221        union xhci_trb *cmd_trb;
1222        u32 cycle_state;
1223
1224        if (xhci->cmd_ring->dequeue == xhci->cmd_ring->enqueue)
1225                return;
1226
1227        /* find the current segment of command ring */
1228        cur_seg = find_trb_seg(xhci->cmd_ring->first_seg,
1229                        xhci->cmd_ring->dequeue, &cycle_state);
1230
1231        if (!cur_seg) {
1232                xhci_warn(xhci, "Command ring mismatch, dequeue = %p %llx (dma)\n",
1233                                xhci->cmd_ring->dequeue,
1234                                (unsigned long long)
1235                                xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1236                                        xhci->cmd_ring->dequeue));
1237                xhci_debug_ring(xhci, xhci->cmd_ring);
1238                xhci_dbg_ring_ptrs(xhci, xhci->cmd_ring);
1239                return;
1240        }
1241
1242        /* find the command trb matched by cd from command ring */
1243        for (cmd_trb = xhci->cmd_ring->dequeue;
1244                        cmd_trb != xhci->cmd_ring->enqueue;
1245                        next_trb(xhci, xhci->cmd_ring, &cur_seg, &cmd_trb)) {
1246                /* If the trb is link trb, continue */
1247                if (TRB_TYPE_LINK_LE32(cmd_trb->generic.field[3]))
1248                        continue;
1249
1250                if (cur_cd->cmd_trb == cmd_trb) {
1251
1252                        /* If the command in device's command list, we should
1253                         * finish it and free the command structure.
1254                         */
1255                        if (cur_cd->command)
1256                                xhci_complete_cmd_in_cmd_wait_list(xhci,
1257                                        cur_cd->command, COMP_CMD_STOP);
1258
1259                        /* get cycle state from the origin command trb */
1260                        cycle_state = le32_to_cpu(cmd_trb->generic.field[3])
1261                                & TRB_CYCLE;
1262
1263                        /* modify the command trb to NO OP command */
1264                        cmd_trb->generic.field[0] = 0;
1265                        cmd_trb->generic.field[1] = 0;
1266                        cmd_trb->generic.field[2] = 0;
1267                        cmd_trb->generic.field[3] = cpu_to_le32(
1268                                        TRB_TYPE(TRB_CMD_NOOP) | cycle_state);
1269                        break;
1270                }
1271        }
1272}
1273
1274static void xhci_cancel_cmd_in_cd_list(struct xhci_hcd *xhci)
1275{
1276        struct xhci_cd *cur_cd, *next_cd;
1277
1278        if (list_empty(&xhci->cancel_cmd_list))
1279                return;
1280
1281        list_for_each_entry_safe(cur_cd, next_cd,
1282                        &xhci->cancel_cmd_list, cancel_cmd_list) {
1283                xhci_cmd_to_noop(xhci, cur_cd);
1284                list_del(&cur_cd->cancel_cmd_list);
1285                kfree(cur_cd);
1286        }
1287}
1288
1289/*
1290 * traversing the cancel_cmd_list. If the command descriptor according
1291 * to cmd_trb is found, the function free it and return 1, otherwise
1292 * return 0.
1293 */
1294static int xhci_search_cmd_trb_in_cd_list(struct xhci_hcd *xhci,
1295                union xhci_trb *cmd_trb)
1296{
1297        struct xhci_cd *cur_cd, *next_cd;
1298
1299        if (list_empty(&xhci->cancel_cmd_list))
1300                return 0;
1301
1302        list_for_each_entry_safe(cur_cd, next_cd,
1303                        &xhci->cancel_cmd_list, cancel_cmd_list) {
1304                if (cur_cd->cmd_trb == cmd_trb) {
1305                        if (cur_cd->command)
1306                                xhci_complete_cmd_in_cmd_wait_list(xhci,
1307                                        cur_cd->command, COMP_CMD_STOP);
1308                        list_del(&cur_cd->cancel_cmd_list);
1309                        kfree(cur_cd);
1310                        return 1;
1311                }
1312        }
1313
1314        return 0;
1315}
1316
1317/*
1318 * If the cmd_trb_comp_code is COMP_CMD_ABORT, we just check whether the
1319 * trb pointed by the command ring dequeue pointer is the trb we want to
1320 * cancel or not. And if the cmd_trb_comp_code is COMP_CMD_STOP, we will
1321 * traverse the cancel_cmd_list to trun the all of the commands according
1322 * to command descriptor to NO-OP trb.
1323 */
1324static int handle_stopped_cmd_ring(struct xhci_hcd *xhci,
1325                int cmd_trb_comp_code)
1326{
1327        int cur_trb_is_good = 0;
1328
1329        /* Searching the cmd trb pointed by the command ring dequeue
1330         * pointer in command descriptor list. If it is found, free it.
1331         */
1332        cur_trb_is_good = xhci_search_cmd_trb_in_cd_list(xhci,
1333                        xhci->cmd_ring->dequeue);
1334
1335        if (cmd_trb_comp_code == COMP_CMD_ABORT)
1336                xhci->cmd_ring_state = CMD_RING_STATE_STOPPED;
1337        else if (cmd_trb_comp_code == COMP_CMD_STOP) {
1338                /* traversing the cancel_cmd_list and canceling
1339                 * the command according to command descriptor
1340                 */
1341                xhci_cancel_cmd_in_cd_list(xhci);
1342
1343                xhci->cmd_ring_state = CMD_RING_STATE_RUNNING;
1344                /*
1345                 * ring command ring doorbell again to restart the
1346                 * command ring
1347                 */
1348                if (xhci->cmd_ring->dequeue != xhci->cmd_ring->enqueue)
1349                        xhci_ring_cmd_db(xhci);
1350        }
1351        return cur_trb_is_good;
1352}
1353
1354static void handle_cmd_completion(struct xhci_hcd *xhci,
1355                struct xhci_event_cmd *event)
1356{
1357        int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1358        u64 cmd_dma;
1359        dma_addr_t cmd_dequeue_dma;
1360        struct xhci_input_control_ctx *ctrl_ctx;
1361        struct xhci_virt_device *virt_dev;
1362        unsigned int ep_index;
1363        struct xhci_ring *ep_ring;
1364        unsigned int ep_state;
1365
1366        cmd_dma = le64_to_cpu(event->cmd_trb);
1367        cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
1368                        xhci->cmd_ring->dequeue);
1369        /* Is the command ring deq ptr out of sync with the deq seg ptr? */
1370        if (cmd_dequeue_dma == 0) {
1371                xhci->error_bitmask |= 1 << 4;
1372                return;
1373        }
1374        /* Does the DMA address match our internal dequeue pointer address? */
1375        if (cmd_dma != (u64) cmd_dequeue_dma) {
1376                xhci->error_bitmask |= 1 << 5;
1377                return;
1378        }
1379
1380        if ((GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_ABORT) ||
1381                (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_CMD_STOP)) {
1382                /* If the return value is 0, we think the trb pointed by
1383                 * command ring dequeue pointer is a good trb. The good
1384                 * trb means we don't want to cancel the trb, but it have
1385                 * been stopped by host. So we should handle it normally.
1386                 * Otherwise, driver should invoke inc_deq() and return.
1387                 */
1388                if (handle_stopped_cmd_ring(xhci,
1389                                GET_COMP_CODE(le32_to_cpu(event->status)))) {
1390                        inc_deq(xhci, xhci->cmd_ring);
1391                        return;
1392                }
1393        }
1394
1395        switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
1396                & TRB_TYPE_BITMASK) {
1397        case TRB_TYPE(TRB_ENABLE_SLOT):
1398                if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
1399                        xhci->slot_id = slot_id;
1400                else
1401                        xhci->slot_id = 0;
1402                complete(&xhci->addr_dev);
1403                break;
1404        case TRB_TYPE(TRB_DISABLE_SLOT):
1405                if (xhci->devs[slot_id]) {
1406                        if (xhci->quirks & XHCI_EP_LIMIT_QUIRK)
1407                                /* Delete default control endpoint resources */
1408                                xhci_free_device_endpoint_resources(xhci,
1409                                                xhci->devs[slot_id], true);
1410                        xhci_free_virt_device(xhci, slot_id);
1411                }
1412                break;
1413        case TRB_TYPE(TRB_CONFIG_EP):
1414                virt_dev = xhci->devs[slot_id];
1415                if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1416                        break;
1417                /*
1418                 * Configure endpoint commands can come from the USB core
1419                 * configuration or alt setting changes, or because the HW
1420                 * needed an extra configure endpoint command after a reset
1421                 * endpoint command or streams were being configured.
1422                 * If the command was for a halted endpoint, the xHCI driver
1423                 * is not waiting on the configure endpoint command.
1424                 */
1425                ctrl_ctx = xhci_get_input_control_ctx(xhci,
1426                                virt_dev->in_ctx);
1427                if (!ctrl_ctx) {
1428                        xhci_warn(xhci, "Could not get input context, bad type.\n");
1429                        break;
1430                }
1431                /* Input ctx add_flags are the endpoint index plus one */
1432                ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
1433                /* A usb_set_interface() call directly after clearing a halted
1434                 * condition may race on this quirky hardware.  Not worth
1435                 * worrying about, since this is prototype hardware.  Not sure
1436                 * if this will work for streams, but streams support was
1437                 * untested on this prototype.
1438                 */
1439                if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
1440                                ep_index != (unsigned int) -1 &&
1441                    le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
1442                    le32_to_cpu(ctrl_ctx->drop_flags)) {
1443                        ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
1444                        ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
1445                        if (!(ep_state & EP_HALTED))
1446                                goto bandwidth_change;
1447                        xhci_dbg(xhci, "Completed config ep cmd - "
1448                                        "last ep index = %d, state = %d\n",
1449                                        ep_index, ep_state);
1450                        /* Clear internal halted state and restart ring(s) */
1451                        xhci->devs[slot_id]->eps[ep_index].ep_state &=
1452                                ~EP_HALTED;
1453                        ring_doorbell_for_active_rings(xhci, slot_id, ep_index);
1454                        break;
1455                }
1456bandwidth_change:
1457                xhci_dbg(xhci, "Completed config ep cmd\n");
1458                xhci->devs[slot_id]->cmd_status =
1459                        GET_COMP_CODE(le32_to_cpu(event->status));
1460                complete(&xhci->devs[slot_id]->cmd_completion);
1461                break;
1462        case TRB_TYPE(TRB_EVAL_CONTEXT):
1463                virt_dev = xhci->devs[slot_id];
1464                if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
1465                        break;
1466                xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1467                complete(&xhci->devs[slot_id]->cmd_completion);
1468                break;
1469        case TRB_TYPE(TRB_ADDR_DEV):
1470                xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
1471                complete(&xhci->addr_dev);
1472                break;
1473        case TRB_TYPE(TRB_STOP_RING):
1474                handle_stopped_endpoint(xhci, xhci->cmd_ring->dequeue, event);
1475                break;
1476        case TRB_TYPE(TRB_SET_DEQ):
1477                handle_set_deq_completion(xhci, event, xhci->cmd_ring->dequeue);
1478                break;
1479        case TRB_TYPE(TRB_CMD_NOOP):
1480                break;
1481        case TRB_TYPE(TRB_RESET_EP):
1482                handle_reset_ep_completion(xhci, event, xhci->cmd_ring->dequeue);
1483                break;
1484        case TRB_TYPE(TRB_RESET_DEV):
1485                xhci_dbg(xhci, "Completed reset device command.\n");
1486                slot_id = TRB_TO_SLOT_ID(
1487                        le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
1488                virt_dev = xhci->devs[slot_id];
1489                if (virt_dev)
1490                        handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
1491                else
1492                        xhci_warn(xhci, "Reset device command completion "
1493                                        "for disabled slot %u\n", slot_id);
1494                break;
1495        case TRB_TYPE(TRB_NEC_GET_FW):
1496                if (!(xhci->quirks & XHCI_NEC_HOST)) {
1497                        xhci->error_bitmask |= 1 << 6;
1498                        break;
1499                }
1500                xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
1501                         NEC_FW_MAJOR(le32_to_cpu(event->status)),
1502                         NEC_FW_MINOR(le32_to_cpu(event->status)));
1503                break;
1504        default:
1505                /* Skip over unknown commands on the event ring */
1506                xhci->error_bitmask |= 1 << 6;
1507                break;
1508        }
1509        inc_deq(xhci, xhci->cmd_ring);
1510}
1511
1512static void handle_vendor_event(struct xhci_hcd *xhci,
1513                union xhci_trb *event)
1514{
1515        u32 trb_type;
1516
1517        trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
1518        xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
1519        if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
1520                handle_cmd_completion(xhci, &event->event_cmd);
1521}
1522
1523/* @port_id: the one-based port ID from the hardware (indexed from array of all
1524 * port registers -- USB 3.0 and USB 2.0).
1525 *
1526 * Returns a zero-based port number, which is suitable for indexing into each of
1527 * the split roothubs' port arrays and bus state arrays.
1528 * Add one to it in order to call xhci_find_slot_id_by_port.
1529 */
1530static unsigned int find_faked_portnum_from_hw_portnum(struct usb_hcd *hcd,
1531                struct xhci_hcd *xhci, u32 port_id)
1532{
1533        unsigned int i;
1534        unsigned int num_similar_speed_ports = 0;
1535
1536        /* port_id from the hardware is 1-based, but port_array[], usb3_ports[],
1537         * and usb2_ports are 0-based indexes.  Count the number of similar
1538         * speed ports, up to 1 port before this port.
1539         */
1540        for (i = 0; i < (port_id - 1); i++) {
1541                u8 port_speed = xhci->port_array[i];
1542
1543                /*
1544                 * Skip ports that don't have known speeds, or have duplicate
1545                 * Extended Capabilities port speed entries.
1546                 */
1547                if (port_speed == 0 || port_speed == DUPLICATE_ENTRY)
1548                        continue;
1549
1550                /*
1551                 * USB 3.0 ports are always under a USB 3.0 hub.  USB 2.0 and
1552                 * 1.1 ports are under the USB 2.0 hub.  If the port speed
1553                 * matches the device speed, it's a similar speed port.
1554                 */
1555                if ((port_speed == 0x03) == (hcd->speed == HCD_USB3))
1556                        num_similar_speed_ports++;
1557        }
1558        return num_similar_speed_ports;
1559}
1560
1561static void handle_device_notification(struct xhci_hcd *xhci,
1562                union xhci_trb *event)
1563{
1564        u32 slot_id;
1565        struct usb_device *udev;
1566
1567        slot_id = TRB_TO_SLOT_ID(event->generic.field[3]);
1568        if (!xhci->devs[slot_id]) {
1569                xhci_warn(xhci, "Device Notification event for "
1570                                "unused slot %u\n", slot_id);
1571                return;
1572        }
1573
1574        xhci_dbg(xhci, "Device Wake Notification event for slot ID %u\n",
1575                        slot_id);
1576        udev = xhci->devs[slot_id]->udev;
1577        if (udev && udev->parent)
1578                usb_wakeup_notification(udev->parent, udev->portnum);
1579}
1580
1581static void handle_port_status(struct xhci_hcd *xhci,
1582                union xhci_trb *event)
1583{
1584        struct usb_hcd *hcd;
1585        u32 port_id;
1586        u32 temp, temp1;
1587        int max_ports;
1588        int slot_id;
1589        unsigned int faked_port_index;
1590        u8 major_revision;
1591        struct xhci_bus_state *bus_state;
1592        __le32 __iomem **port_array;
1593        bool bogus_port_status = false;
1594
1595        /* Port status change events always have a successful completion code */
1596        if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
1597                xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
1598                xhci->error_bitmask |= 1 << 8;
1599        }
1600        port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
1601        xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
1602
1603        max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
1604        if ((port_id <= 0) || (port_id > max_ports)) {
1605                xhci_warn(xhci, "Invalid port id %d\n", port_id);
1606                inc_deq(xhci, xhci->event_ring);
1607                return;
1608        }
1609
1610        /* Figure out which usb_hcd this port is attached to:
1611         * is it a USB 3.0 port or a USB 2.0/1.1 port?
1612         */
1613        major_revision = xhci->port_array[port_id - 1];
1614
1615        /* Find the right roothub. */
1616        hcd = xhci_to_hcd(xhci);
1617        if ((major_revision == 0x03) != (hcd->speed == HCD_USB3))
1618                hcd = xhci->shared_hcd;
1619
1620        if (major_revision == 0) {
1621                xhci_warn(xhci, "Event for port %u not in "
1622                                "Extended Capabilities, ignoring.\n",
1623                                port_id);
1624                bogus_port_status = true;
1625                goto cleanup;
1626        }
1627        if (major_revision == DUPLICATE_ENTRY) {
1628                xhci_warn(xhci, "Event for port %u duplicated in"
1629                                "Extended Capabilities, ignoring.\n",
1630                                port_id);
1631                bogus_port_status = true;
1632                goto cleanup;
1633        }
1634
1635        /*
1636         * Hardware port IDs reported by a Port Status Change Event include USB
1637         * 3.0 and USB 2.0 ports.  We want to check if the port has reported a
1638         * resume event, but we first need to translate the hardware port ID
1639         * into the index into the ports on the correct split roothub, and the
1640         * correct bus_state structure.
1641         */
1642        bus_state = &xhci->bus_state[hcd_index(hcd)];
1643        if (hcd->speed == HCD_USB3)
1644                port_array = xhci->usb3_ports;
1645        else
1646                port_array = xhci->usb2_ports;
1647        /* Find the faked port hub number */
1648        faked_port_index = find_faked_portnum_from_hw_portnum(hcd, xhci,
1649                        port_id);
1650
1651        temp = xhci_readl(xhci, port_array[faked_port_index]);
1652        if (hcd->state == HC_STATE_SUSPENDED) {
1653                xhci_dbg(xhci, "resume root hub\n");
1654                usb_hcd_resume_root_hub(hcd);
1655        }
1656
1657        if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_RESUME) {
1658                xhci_dbg(xhci, "port resume event for port %d\n", port_id);
1659
1660                temp1 = xhci_readl(xhci, &xhci->op_regs->command);
1661                if (!(temp1 & CMD_RUN)) {
1662                        xhci_warn(xhci, "xHC is not running.\n");
1663                        goto cleanup;
1664                }
1665
1666                if (DEV_SUPERSPEED(temp)) {
1667                        xhci_dbg(xhci, "remote wake SS port %d\n", port_id);
1668                        /* Set a flag to say the port signaled remote wakeup,
1669                         * so we can tell the difference between the end of
1670                         * device and host initiated resume.
1671                         */
1672                        bus_state->port_remote_wakeup |= 1 << faked_port_index;
1673                        xhci_test_and_clear_bit(xhci, port_array,
1674                                        faked_port_index, PORT_PLC);
1675                        xhci_set_link_state(xhci, port_array, faked_port_index,
1676                                                XDEV_U0);
1677                        /* Need to wait until the next link state change
1678                         * indicates the device is actually in U0.
1679                         */
1680                        bogus_port_status = true;
1681                        goto cleanup;
1682                } else {
1683                        xhci_dbg(xhci, "resume HS port %d\n", port_id);
1684                        bus_state->resume_done[faked_port_index] = jiffies +
1685                                msecs_to_jiffies(20);
1686                        set_bit(faked_port_index, &bus_state->resuming_ports);
1687                        mod_timer(&hcd->rh_timer,
1688                                  bus_state->resume_done[faked_port_index]);
1689                        /* Do the rest in GetPortStatus */
1690                }
1691        }
1692
1693        if ((temp & PORT_PLC) && (temp & PORT_PLS_MASK) == XDEV_U0 &&
1694                        DEV_SUPERSPEED(temp)) {
1695                xhci_dbg(xhci, "resume SS port %d finished\n", port_id);
1696                /* We've just brought the device into U0 through either the
1697                 * Resume state after a device remote wakeup, or through the
1698                 * U3Exit state after a host-initiated resume.  If it's a device
1699                 * initiated remote wake, don't pass up the link state change,
1700                 * so the roothub behavior is consistent with external
1701                 * USB 3.0 hub behavior.
1702                 */
1703                slot_id = xhci_find_slot_id_by_port(hcd, xhci,
1704                                faked_port_index + 1);
1705                if (slot_id && xhci->devs[slot_id])
1706                        xhci_ring_device(xhci, slot_id);
1707                if (bus_state->port_remote_wakeup & (1 << faked_port_index)) {
1708                        bus_state->port_remote_wakeup &=
1709                                ~(1 << faked_port_index);
1710                        xhci_test_and_clear_bit(xhci, port_array,
1711                                        faked_port_index, PORT_PLC);
1712                        usb_wakeup_notification(hcd->self.root_hub,
1713                                        faked_port_index + 1);
1714                        bogus_port_status = true;
1715                        goto cleanup;
1716                }
1717        }
1718
1719        if (hcd->speed != HCD_USB3)
1720                xhci_test_and_clear_bit(xhci, port_array, faked_port_index,
1721                                        PORT_PLC);
1722
1723cleanup:
1724        /* Update event ring dequeue pointer before dropping the lock */
1725        inc_deq(xhci, xhci->event_ring);
1726
1727        /* Don't make the USB core poll the roothub if we got a bad port status
1728         * change event.  Besides, at that point we can't tell which roothub
1729         * (USB 2.0 or USB 3.0) to kick.
1730         */
1731        if (bogus_port_status)
1732                return;
1733
1734        /*
1735         * xHCI port-status-change events occur when the "or" of all the
1736         * status-change bits in the portsc register changes from 0 to 1.
1737         * New status changes won't cause an event if any other change
1738         * bits are still set.  When an event occurs, switch over to
1739         * polling to avoid losing status changes.
1740         */
1741        xhci_dbg(xhci, "%s: starting port polling.\n", __func__);
1742        set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
1743        spin_unlock(&xhci->lock);
1744        /* Pass this up to the core */
1745        usb_hcd_poll_rh_status(hcd);
1746        spin_lock(&xhci->lock);
1747}
1748
1749/*
1750 * This TD is defined by the TRBs starting at start_trb in start_seg and ending
1751 * at end_trb, which may be in another segment.  If the suspect DMA address is a
1752 * TRB in this TD, this function returns that TRB's segment.  Otherwise it
1753 * returns 0.
1754 */
1755struct xhci_segment *trb_in_td(struct xhci_segment *start_seg,
1756                union xhci_trb  *start_trb,
1757                union xhci_trb  *end_trb,
1758                dma_addr_t      suspect_dma)
1759{
1760        dma_addr_t start_dma;
1761        dma_addr_t end_seg_dma;
1762        dma_addr_t end_trb_dma;
1763        struct xhci_segment *cur_seg;
1764
1765        start_dma = xhci_trb_virt_to_dma(start_seg, start_trb);
1766        cur_seg = start_seg;
1767
1768        do {
1769                if (start_dma == 0)
1770                        return NULL;
1771                /* We may get an event for a Link TRB in the middle of a TD */
1772                end_seg_dma = xhci_trb_virt_to_dma(cur_seg,
1773                                &cur_seg->trbs[TRBS_PER_SEGMENT - 1]);
1774                /* If the end TRB isn't in this segment, this is set to 0 */
1775                end_trb_dma = xhci_trb_virt_to_dma(cur_seg, end_trb);
1776
1777                if (end_trb_dma > 0) {
1778                        /* The end TRB is in this segment, so suspect should be here */
1779                        if (start_dma <= end_trb_dma) {
1780                                if (suspect_dma >= start_dma && suspect_dma <= end_trb_dma)
1781                                        return cur_seg;
1782                        } else {
1783                                /* Case for one segment with
1784                                 * a TD wrapped around to the top
1785                                 */
1786                                if ((suspect_dma >= start_dma &&
1787                                                        suspect_dma <= end_seg_dma) ||
1788                                                (suspect_dma >= cur_seg->dma &&
1789                                                 suspect_dma <= end_trb_dma))
1790                                        return cur_seg;
1791                        }
1792                        return NULL;
1793                } else {
1794                        /* Might still be somewhere in this segment */
1795                        if (suspect_dma >= start_dma && suspect_dma <= end_seg_dma)
1796                                return cur_seg;
1797                }
1798                cur_seg = cur_seg->next;
1799                start_dma = xhci_trb_virt_to_dma(cur_seg, &cur_seg->trbs[0]);
1800        } while (cur_seg != start_seg);
1801
1802        return NULL;
1803}
1804
1805static void xhci_cleanup_halted_endpoint(struct xhci_hcd *xhci,
1806                unsigned int slot_id, unsigned int ep_index,
1807                unsigned int stream_id,
1808                struct xhci_td *td, union xhci_trb *event_trb)
1809{
1810        struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
1811        ep->ep_state |= EP_HALTED;
1812        ep->stopped_td = td;
1813        ep->stopped_trb = event_trb;
1814        ep->stopped_stream = stream_id;
1815
1816        xhci_queue_reset_ep(xhci, slot_id, ep_index);
1817        xhci_cleanup_stalled_ring(xhci, td->urb->dev, ep_index);
1818
1819        ep->stopped_td = NULL;
1820        ep->stopped_trb = NULL;
1821        ep->stopped_stream = 0;
1822
1823        xhci_ring_cmd_db(xhci);
1824}
1825
1826/* Check if an error has halted the endpoint ring.  The class driver will
1827 * cleanup the halt for a non-default control endpoint if we indicate a stall.
1828 * However, a babble and other errors also halt the endpoint ring, and the class
1829 * driver won't clear the halt in that case, so we need to issue a Set Transfer
1830 * Ring Dequeue Pointer command manually.
1831 */
1832static int xhci_requires_manual_halt_cleanup(struct xhci_hcd *xhci,
1833                struct xhci_ep_ctx *ep_ctx,
1834                unsigned int trb_comp_code)
1835{
1836        /* TRB completion codes that may require a manual halt cleanup */
1837        if (trb_comp_code == COMP_TX_ERR ||
1838                        trb_comp_code == COMP_BABBLE ||
1839                        trb_comp_code == COMP_SPLIT_ERR)
1840                /* The 0.96 spec says a babbling control endpoint
1841                 * is not halted. The 0.96 spec says it is.  Some HW
1842                 * claims to be 0.95 compliant, but it halts the control
1843                 * endpoint anyway.  Check if a babble halted the
1844                 * endpoint.
1845                 */
1846                if ((ep_ctx->ep_info & cpu_to_le32(EP_STATE_MASK)) ==
1847                    cpu_to_le32(EP_STATE_HALTED))
1848                        return 1;
1849
1850        return 0;
1851}
1852
1853int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code)
1854{
1855        if (trb_comp_code >= 224 && trb_comp_code <= 255) {
1856                /* Vendor defined "informational" completion code,
1857                 * treat as not-an-error.
1858                 */
1859                xhci_dbg(xhci, "Vendor defined info completion code %u\n",
1860                                trb_comp_code);
1861                xhci_dbg(xhci, "Treating code as success.\n");
1862                return 1;
1863        }
1864        return 0;
1865}
1866
1867/*
1868 * Finish the td processing, remove the td from td list;
1869 * Return 1 if the urb can be given back.
1870 */
1871static int finish_td(struct xhci_hcd *xhci, struct xhci_td *td,
1872        union xhci_trb *event_trb, struct xhci_transfer_event *event,
1873        struct xhci_virt_ep *ep, int *status, bool skip)
1874{
1875        struct xhci_virt_device *xdev;
1876        struct xhci_ring *ep_ring;
1877        unsigned int slot_id;
1878        int ep_index;
1879        struct urb *urb = NULL;
1880        struct xhci_ep_ctx *ep_ctx;
1881        int ret = 0;
1882        struct urb_priv *urb_priv;
1883        u32 trb_comp_code;
1884
1885        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1886        xdev = xhci->devs[slot_id];
1887        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1888        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1889        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1890        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1891
1892        if (skip)
1893                goto td_cleanup;
1894
1895        if (trb_comp_code == COMP_STOP_INVAL ||
1896                        trb_comp_code == COMP_STOP) {
1897                /* The Endpoint Stop Command completion will take care of any
1898                 * stopped TDs.  A stopped TD may be restarted, so don't update
1899                 * the ring dequeue pointer or take this TD off any lists yet.
1900                 */
1901                ep->stopped_td = td;
1902                ep->stopped_trb = event_trb;
1903                return 0;
1904        } else {
1905                if (trb_comp_code == COMP_STALL) {
1906                        /* The transfer is completed from the driver's
1907                         * perspective, but we need to issue a set dequeue
1908                         * command for this stalled endpoint to move the dequeue
1909                         * pointer past the TD.  We can't do that here because
1910                         * the halt condition must be cleared first.  Let the
1911                         * USB class driver clear the stall later.
1912                         */
1913                        ep->stopped_td = td;
1914                        ep->stopped_trb = event_trb;
1915                        ep->stopped_stream = ep_ring->stream_id;
1916                } else if (xhci_requires_manual_halt_cleanup(xhci,
1917                                        ep_ctx, trb_comp_code)) {
1918                        /* Other types of errors halt the endpoint, but the
1919                         * class driver doesn't call usb_reset_endpoint() unless
1920                         * the error is -EPIPE.  Clear the halted status in the
1921                         * xHCI hardware manually.
1922                         */
1923                        xhci_cleanup_halted_endpoint(xhci,
1924                                        slot_id, ep_index, ep_ring->stream_id,
1925                                        td, event_trb);
1926                } else {
1927                        /* Update ring dequeue pointer */
1928                        while (ep_ring->dequeue != td->last_trb)
1929                                inc_deq(xhci, ep_ring);
1930                        inc_deq(xhci, ep_ring);
1931                }
1932
1933td_cleanup:
1934                /* Clean up the endpoint's TD list */
1935                urb = td->urb;
1936                urb_priv = urb->hcpriv;
1937
1938                /* Do one last check of the actual transfer length.
1939                 * If the host controller said we transferred more data than
1940                 * the buffer length, urb->actual_length will be a very big
1941                 * number (since it's unsigned).  Play it safe and say we didn't
1942                 * transfer anything.
1943                 */
1944                if (urb->actual_length > urb->transfer_buffer_length) {
1945                        xhci_warn(xhci, "URB transfer length is wrong, "
1946                                        "xHC issue? req. len = %u, "
1947                                        "act. len = %u\n",
1948                                        urb->transfer_buffer_length,
1949                                        urb->actual_length);
1950                        urb->actual_length = 0;
1951                        if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
1952                                *status = -EREMOTEIO;
1953                        else
1954                                *status = 0;
1955                }
1956                list_del_init(&td->td_list);
1957                /* Was this TD slated to be cancelled but completed anyway? */
1958                if (!list_empty(&td->cancelled_td_list))
1959                        list_del_init(&td->cancelled_td_list);
1960
1961                urb_priv->td_cnt++;
1962                /* Giveback the urb when all the tds are completed */
1963                if (urb_priv->td_cnt == urb_priv->length) {
1964                        ret = 1;
1965                        if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
1966                                xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs--;
1967                                if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs
1968                                        == 0) {
1969                                        if (xhci->quirks & XHCI_AMD_PLL_FIX)
1970                                                usb_amd_quirk_pll_enable();
1971                                }
1972                        }
1973                }
1974        }
1975
1976        return ret;
1977}
1978
1979/*
1980 * Process control tds, update urb status and actual_length.
1981 */
1982static int process_ctrl_td(struct xhci_hcd *xhci, struct xhci_td *td,
1983        union xhci_trb *event_trb, struct xhci_transfer_event *event,
1984        struct xhci_virt_ep *ep, int *status)
1985{
1986        struct xhci_virt_device *xdev;
1987        struct xhci_ring *ep_ring;
1988        unsigned int slot_id;
1989        int ep_index;
1990        struct xhci_ep_ctx *ep_ctx;
1991        u32 trb_comp_code;
1992
1993        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
1994        xdev = xhci->devs[slot_id];
1995        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
1996        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
1997        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
1998        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
1999
2000        switch (trb_comp_code) {
2001        case COMP_SUCCESS:
2002                if (event_trb == ep_ring->dequeue) {
2003                        xhci_warn(xhci, "WARN: Success on ctrl setup TRB "
2004                                        "without IOC set??\n");
2005                        *status = -ESHUTDOWN;
2006                } else if (event_trb != td->last_trb) {
2007                        xhci_warn(xhci, "WARN: Success on ctrl data TRB "
2008                                        "without IOC set??\n");
2009                        *status = -ESHUTDOWN;
2010                } else {
2011                        *status = 0;
2012                }
2013                break;
2014        case COMP_SHORT_TX:
2015                if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2016                        *status = -EREMOTEIO;
2017                else
2018                        *status = 0;
2019                break;
2020        case COMP_STOP_INVAL:
2021        case COMP_STOP:
2022                return finish_td(xhci, td, event_trb, event, ep, status, false);
2023        default:
2024                if (!xhci_requires_manual_halt_cleanup(xhci,
2025                                        ep_ctx, trb_comp_code))
2026                        break;
2027                xhci_dbg(xhci, "TRB error code %u, "
2028                                "halted endpoint index = %u\n",
2029                                trb_comp_code, ep_index);
2030                /* else fall through */
2031        case COMP_STALL:
2032                /* Did we transfer part of the data (middle) phase? */
2033                if (event_trb != ep_ring->dequeue &&
2034                                event_trb != td->last_trb)
2035                        td->urb->actual_length =
2036                                td->urb->transfer_buffer_length -
2037                                EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2038                else
2039                        td->urb->actual_length = 0;
2040
2041                xhci_cleanup_halted_endpoint(xhci,
2042                        slot_id, ep_index, 0, td, event_trb);
2043                return finish_td(xhci, td, event_trb, event, ep, status, true);
2044        }
2045        /*
2046         * Did we transfer any data, despite the errors that might have
2047         * happened?  I.e. did we get past the setup stage?
2048         */
2049        if (event_trb != ep_ring->dequeue) {
2050                /* The event was for the status stage */
2051                if (event_trb == td->last_trb) {
2052                        if (td->urb->actual_length != 0) {
2053                                /* Don't overwrite a previously set error code
2054                                 */
2055                                if ((*status == -EINPROGRESS || *status == 0) &&
2056                                                (td->urb->transfer_flags
2057                                                 & URB_SHORT_NOT_OK))
2058                                        /* Did we already see a short data
2059                                         * stage? */
2060                                        *status = -EREMOTEIO;
2061                        } else {
2062                                td->urb->actual_length =
2063                                        td->urb->transfer_buffer_length;
2064                        }
2065                } else {
2066                /* Maybe the event was for the data stage? */
2067                        td->urb->actual_length =
2068                                td->urb->transfer_buffer_length -
2069                                EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2070                        xhci_dbg(xhci, "Waiting for status "
2071                                        "stage event\n");
2072                        return 0;
2073                }
2074        }
2075
2076        return finish_td(xhci, td, event_trb, event, ep, status, false);
2077}
2078
2079/*
2080 * Process isochronous tds, update urb packet status and actual_length.
2081 */
2082static int process_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2083        union xhci_trb *event_trb, struct xhci_transfer_event *event,
2084        struct xhci_virt_ep *ep, int *status)
2085{
2086        struct xhci_ring *ep_ring;
2087        struct urb_priv *urb_priv;
2088        int idx;
2089        int len = 0;
2090        union xhci_trb *cur_trb;
2091        struct xhci_segment *cur_seg;
2092        struct usb_iso_packet_descriptor *frame;
2093        u32 trb_comp_code;
2094        bool skip_td = false;
2095
2096        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2097        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2098        urb_priv = td->urb->hcpriv;
2099        idx = urb_priv->td_cnt;
2100        frame = &td->urb->iso_frame_desc[idx];
2101
2102        /* handle completion code */
2103        switch (trb_comp_code) {
2104        case COMP_SUCCESS:
2105                if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0) {
2106                        frame->status = 0;
2107                        break;
2108                }
2109                if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2110                        trb_comp_code = COMP_SHORT_TX;
2111        case COMP_SHORT_TX:
2112                frame->status = td->urb->transfer_flags & URB_SHORT_NOT_OK ?
2113                                -EREMOTEIO : 0;
2114                break;
2115        case COMP_BW_OVER:
2116                frame->status = -ECOMM;
2117                skip_td = true;
2118                break;
2119        case COMP_BUFF_OVER:
2120        case COMP_BABBLE:
2121                frame->status = -EOVERFLOW;
2122                skip_td = true;
2123                break;
2124        case COMP_DEV_ERR:
2125        case COMP_STALL:
2126        case COMP_TX_ERR:
2127                frame->status = -EPROTO;
2128                skip_td = true;
2129                break;
2130        case COMP_STOP:
2131        case COMP_STOP_INVAL:
2132                break;
2133        default:
2134                frame->status = -1;
2135                break;
2136        }
2137
2138        if (trb_comp_code == COMP_SUCCESS || skip_td) {
2139                frame->actual_length = frame->length;
2140                td->urb->actual_length += frame->length;
2141        } else {
2142                for (cur_trb = ep_ring->dequeue,
2143                     cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
2144                     next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2145                        if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2146                            !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2147                                len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2148                }
2149                len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2150                        EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2151
2152                if (trb_comp_code != COMP_STOP_INVAL) {
2153                        frame->actual_length = len;
2154                        td->urb->actual_length += len;
2155                }
2156        }
2157
2158        return finish_td(xhci, td, event_trb, event, ep, status, false);
2159}
2160
2161static int skip_isoc_td(struct xhci_hcd *xhci, struct xhci_td *td,
2162                        struct xhci_transfer_event *event,
2163                        struct xhci_virt_ep *ep, int *status)
2164{
2165        struct xhci_ring *ep_ring;
2166        struct urb_priv *urb_priv;
2167        struct usb_iso_packet_descriptor *frame;
2168        int idx;
2169
2170        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2171        urb_priv = td->urb->hcpriv;
2172        idx = urb_priv->td_cnt;
2173        frame = &td->urb->iso_frame_desc[idx];
2174
2175        /* The transfer is partly done. */
2176        frame->status = -EXDEV;
2177
2178        /* calc actual length */
2179        frame->actual_length = 0;
2180
2181        /* Update ring dequeue pointer */
2182        while (ep_ring->dequeue != td->last_trb)
2183                inc_deq(xhci, ep_ring);
2184        inc_deq(xhci, ep_ring);
2185
2186        return finish_td(xhci, td, NULL, event, ep, status, true);
2187}
2188
2189/*
2190 * Process bulk and interrupt tds, update urb status and actual_length.
2191 */
2192static int process_bulk_intr_td(struct xhci_hcd *xhci, struct xhci_td *td,
2193        union xhci_trb *event_trb, struct xhci_transfer_event *event,
2194        struct xhci_virt_ep *ep, int *status)
2195{
2196        struct xhci_ring *ep_ring;
2197        union xhci_trb *cur_trb;
2198        struct xhci_segment *cur_seg;
2199        u32 trb_comp_code;
2200
2201        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2202        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2203
2204        switch (trb_comp_code) {
2205        case COMP_SUCCESS:
2206                /* Double check that the HW transferred everything. */
2207                if (event_trb != td->last_trb ||
2208                    EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2209                        xhci_warn(xhci, "WARN Successful completion "
2210                                        "on short TX\n");
2211                        if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2212                                *status = -EREMOTEIO;
2213                        else
2214                                *status = 0;
2215                        if ((xhci->quirks & XHCI_TRUST_TX_LENGTH))
2216                                trb_comp_code = COMP_SHORT_TX;
2217                } else {
2218                        *status = 0;
2219                }
2220                break;
2221        case COMP_SHORT_TX:
2222                if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2223                        *status = -EREMOTEIO;
2224                else
2225                        *status = 0;
2226                break;
2227        default:
2228                /* Others already handled above */
2229                break;
2230        }
2231        if (trb_comp_code == COMP_SHORT_TX)
2232                xhci_dbg(xhci, "ep %#x - asked for %d bytes, "
2233                                "%d bytes untransferred\n",
2234                                td->urb->ep->desc.bEndpointAddress,
2235                                td->urb->transfer_buffer_length,
2236                                EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2237        /* Fast path - was this the last TRB in the TD for this URB? */
2238        if (event_trb == td->last_trb) {
2239                if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
2240                        td->urb->actual_length =
2241                                td->urb->transfer_buffer_length -
2242                                EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2243                        if (td->urb->transfer_buffer_length <
2244                                        td->urb->actual_length) {
2245                                xhci_warn(xhci, "HC gave bad length "
2246                                                "of %d bytes left\n",
2247                                          EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)));
2248                                td->urb->actual_length = 0;
2249                                if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2250                                        *status = -EREMOTEIO;
2251                                else
2252                                        *status = 0;
2253                        }
2254                        /* Don't overwrite a previously set error code */
2255                        if (*status == -EINPROGRESS) {
2256                                if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
2257                                        *status = -EREMOTEIO;
2258                                else
2259                                        *status = 0;
2260                        }
2261                } else {
2262                        td->urb->actual_length =
2263                                td->urb->transfer_buffer_length;
2264                        /* Ignore a short packet completion if the
2265                         * untransferred length was zero.
2266                         */
2267                        if (*status == -EREMOTEIO)
2268                                *status = 0;
2269                }
2270        } else {
2271                /* Slow path - walk the list, starting from the dequeue
2272                 * pointer, to get the actual length transferred.
2273                 */
2274                td->urb->actual_length = 0;
2275                for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
2276                                cur_trb != event_trb;
2277                                next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
2278                        if (!TRB_TYPE_NOOP_LE32(cur_trb->generic.field[3]) &&
2279                            !TRB_TYPE_LINK_LE32(cur_trb->generic.field[3]))
2280                                td->urb->actual_length +=
2281                                        TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
2282                }
2283                /* If the ring didn't stop on a Link or No-op TRB, add
2284                 * in the actual bytes transferred from the Normal TRB
2285                 */
2286                if (trb_comp_code != COMP_STOP_INVAL)
2287                        td->urb->actual_length +=
2288                                TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
2289                                EVENT_TRB_LEN(le32_to_cpu(event->transfer_len));
2290        }
2291
2292        return finish_td(xhci, td, event_trb, event, ep, status, false);
2293}
2294
2295/*
2296 * If this function returns an error condition, it means it got a Transfer
2297 * event with a corrupted Slot ID, Endpoint ID, or TRB DMA address.
2298 * At this point, the host controller is probably hosed and should be reset.
2299 */
2300static int handle_tx_event(struct xhci_hcd *xhci,
2301                struct xhci_transfer_event *event)
2302        __releases(&xhci->lock)
2303        __acquires(&xhci->lock)
2304{
2305        struct xhci_virt_device *xdev;
2306        struct xhci_virt_ep *ep;
2307        struct xhci_ring *ep_ring;
2308        unsigned int slot_id;
2309        int ep_index;
2310        struct xhci_td *td = NULL;
2311        dma_addr_t event_dma;
2312        struct xhci_segment *event_seg;
2313        union xhci_trb *event_trb;
2314        struct urb *urb = NULL;
2315        int status = -EINPROGRESS;
2316        struct urb_priv *urb_priv;
2317        struct xhci_ep_ctx *ep_ctx;
2318        struct list_head *tmp;
2319        u32 trb_comp_code;
2320        int ret = 0;
2321        int td_num = 0;
2322
2323        slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
2324        xdev = xhci->devs[slot_id];
2325        if (!xdev) {
2326                xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
2327                xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2328                         (unsigned long long) xhci_trb_virt_to_dma(
2329                                 xhci->event_ring->deq_seg,
2330                                 xhci->event_ring->dequeue),
2331                         lower_32_bits(le64_to_cpu(event->buffer)),
2332                         upper_32_bits(le64_to_cpu(event->buffer)),
2333                         le32_to_cpu(event->transfer_len),
2334                         le32_to_cpu(event->flags));
2335                xhci_dbg(xhci, "Event ring:\n");
2336                xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2337                return -ENODEV;
2338        }
2339
2340        /* Endpoint ID is 1 based, our index is zero based */
2341        ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
2342        ep = &xdev->eps[ep_index];
2343        ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
2344        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2345        if (!ep_ring ||
2346            (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
2347            EP_STATE_DISABLED) {
2348                xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
2349                                "or incorrect stream ring\n");
2350                xhci_err(xhci, "@%016llx %08x %08x %08x %08x\n",
2351                         (unsigned long long) xhci_trb_virt_to_dma(
2352                                 xhci->event_ring->deq_seg,
2353                                 xhci->event_ring->dequeue),
2354                         lower_32_bits(le64_to_cpu(event->buffer)),
2355                         upper_32_bits(le64_to_cpu(event->buffer)),
2356                         le32_to_cpu(event->transfer_len),
2357                         le32_to_cpu(event->flags));
2358                xhci_dbg(xhci, "Event ring:\n");
2359                xhci_debug_segment(xhci, xhci->event_ring->deq_seg);
2360                return -ENODEV;
2361        }
2362
2363        /* Count current td numbers if ep->skip is set */
2364        if (ep->skip) {
2365                list_for_each(tmp, &ep_ring->td_list)
2366                        td_num++;
2367        }
2368
2369        event_dma = le64_to_cpu(event->buffer);
2370        trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
2371        /* Look for common error cases */
2372        switch (trb_comp_code) {
2373        /* Skip codes that require special handling depending on
2374         * transfer type
2375         */
2376        case COMP_SUCCESS:
2377                if (EVENT_TRB_LEN(le32_to_cpu(event->transfer_len)) == 0)
2378                        break;
2379                if (xhci->quirks & XHCI_TRUST_TX_LENGTH)
2380                        trb_comp_code = COMP_SHORT_TX;
2381                else
2382                        xhci_warn_ratelimited(xhci,
2383                                        "WARN Successful completion on short TX: needs XHCI_TRUST_TX_LENGTH quirk?\n");
2384        case COMP_SHORT_TX:
2385                break;
2386        case COMP_STOP:
2387                xhci_dbg(xhci, "Stopped on Transfer TRB\n");
2388                break;
2389        case COMP_STOP_INVAL:
2390                xhci_dbg(xhci, "Stopped on No-op or Link TRB\n");
2391                break;
2392        case COMP_STALL:
2393                xhci_dbg(xhci, "Stalled endpoint\n");
2394                ep->ep_state |= EP_HALTED;
2395                status = -EPIPE;
2396                break;
2397        case COMP_TRB_ERR:
2398                xhci_warn(xhci, "WARN: TRB error on endpoint\n");
2399                status = -EILSEQ;
2400                break;
2401        case COMP_SPLIT_ERR:
2402        case COMP_TX_ERR:
2403                xhci_dbg(xhci, "Transfer error on endpoint\n");
2404                status = -EPROTO;
2405                break;
2406        case COMP_BABBLE:
2407                xhci_dbg(xhci, "Babble error on endpoint\n");
2408                status = -EOVERFLOW;
2409                break;
2410        case COMP_DB_ERR:
2411                xhci_warn(xhci, "WARN: HC couldn't access mem fast enough\n");
2412                status = -ENOSR;
2413                break;
2414        case COMP_BW_OVER:
2415                xhci_warn(xhci, "WARN: bandwidth overrun event on endpoint\n");
2416                break;
2417        case COMP_BUFF_OVER:
2418                xhci_warn(xhci, "WARN: buffer overrun event on endpoint\n");
2419                break;
2420        case COMP_UNDERRUN:
2421                /*
2422                 * When the Isoch ring is empty, the xHC will generate
2423                 * a Ring Overrun Event for IN Isoch endpoint or Ring
2424                 * Underrun Event for OUT Isoch endpoint.
2425                 */
2426                xhci_dbg(xhci, "underrun event on endpoint\n");
2427                if (!list_empty(&ep_ring->td_list))
2428                        xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
2429                                        "still with TDs queued?\n",
2430                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2431                                 ep_index);
2432                goto cleanup;
2433        case COMP_OVERRUN:
2434                xhci_dbg(xhci, "overrun event on endpoint\n");
2435                if (!list_empty(&ep_ring->td_list))
2436                        xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
2437                                        "still with TDs queued?\n",
2438                                 TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2439                                 ep_index);
2440                goto cleanup;
2441        case COMP_DEV_ERR:
2442                xhci_warn(xhci, "WARN: detect an incompatible device");
2443                status = -EPROTO;
2444                break;
2445        case COMP_MISSED_INT:
2446                /*
2447                 * When encounter missed service error, one or more isoc tds
2448                 * may be missed by xHC.
2449                 * Set skip flag of the ep_ring; Complete the missed tds as
2450                 * short transfer when process the ep_ring next time.
2451                 */
2452                ep->skip = true;
2453                xhci_dbg(xhci, "Miss service interval error, set skip flag\n");
2454                goto cleanup;
2455        default:
2456                if (xhci_is_vendor_info_code(xhci, trb_comp_code)) {
2457                        status = 0;
2458                        break;
2459                }
2460                xhci_warn(xhci, "ERROR Unknown event condition, HC probably "
2461                                "busted\n");
2462                goto cleanup;
2463        }
2464
2465        do {
2466                /* This TRB should be in the TD at the head of this ring's
2467                 * TD list.
2468                 */
2469                if (list_empty(&ep_ring->td_list)) {
2470                        /*
2471                         * A stopped endpoint may generate an extra completion
2472                         * event if the device was suspended.  Don't print
2473                         * warnings.
2474                         */
2475                        if (!(trb_comp_code == COMP_STOP ||
2476                                                trb_comp_code == COMP_STOP_INVAL)) {
2477                                xhci_warn(xhci, "WARN Event TRB for slot %d ep %d with no TDs queued?\n",
2478                                                TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
2479                                                ep_index);
2480                                xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
2481                                                (le32_to_cpu(event->flags) &
2482                                                 TRB_TYPE_BITMASK)>>10);
2483                                xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
2484                        }
2485                        if (ep->skip) {
2486                                ep->skip = false;
2487                                xhci_dbg(xhci, "td_list is empty while skip "
2488                                                "flag set. Clear skip flag.\n");
2489                        }
2490                        ret = 0;
2491                        goto cleanup;
2492                }
2493
2494                /* We've skipped all the TDs on the ep ring when ep->skip set */
2495                if (ep->skip && td_num == 0) {
2496                        ep->skip = false;
2497                        xhci_dbg(xhci, "All tds on the ep_ring skipped. "
2498                                                "Clear skip flag.\n");
2499                        ret = 0;
2500                        goto cleanup;
2501                }
2502
2503                td = list_entry(ep_ring->td_list.next, struct xhci_td, td_list);
2504                if (ep->skip)
2505                        td_num--;
2506
2507                /* Is this a TRB in the currently executing TD? */
2508                event_seg = trb_in_td(ep_ring->deq_seg, ep_ring->dequeue,
2509                                td->last_trb, event_dma);
2510
2511                /*
2512                 * Skip the Force Stopped Event. The event_trb(event_dma) of FSE
2513                 * is not in the current TD pointed by ep_ring->dequeue because
2514                 * that the hardware dequeue pointer still at the previous TRB
2515                 * of the current TD. The previous TRB maybe a Link TD or the
2516                 * last TRB of the previous TD. The command completion handle
2517                 * will take care the rest.
2518                 */
2519                if (!event_seg && trb_comp_code == COMP_STOP_INVAL) {
2520                        ret = 0;
2521                        goto cleanup;
2522                }
2523
2524                if (!event_seg) {
2525                        if (!ep->skip ||
2526                            !usb_endpoint_xfer_isoc(&td->urb->ep->desc)) {
2527                                /* Some host controllers give a spurious
2528                                 * successful event after a short transfer.
2529                                 * Ignore it.
2530                                 */
2531                                if ((xhci->quirks & XHCI_SPURIOUS_SUCCESS) && 
2532                                                ep_ring->last_td_was_short) {
2533                                        ep_ring->last_td_was_short = false;
2534                                        ret = 0;
2535                                        goto cleanup;
2536                                }
2537                                /* HC is busted, give up! */
2538                                xhci_err(xhci,
2539                                        "ERROR Transfer event TRB DMA ptr not "
2540                                        "part of current TD\n");
2541                                return -ESHUTDOWN;
2542                        }
2543
2544                        ret = skip_isoc_td(xhci, td, event, ep, &status);
2545                        goto cleanup;
2546                }
2547                if (trb_comp_code == COMP_SHORT_TX)
2548                        ep_ring->last_td_was_short = true;
2549                else
2550                        ep_ring->last_td_was_short = false;
2551
2552                if (ep->skip) {
2553                        xhci_dbg(xhci, "Found td. Clear skip flag.\n");
2554                        ep->skip = false;
2555                }
2556
2557                event_trb = &event_seg->trbs[(event_dma - event_seg->dma) /
2558                                                sizeof(*event_trb)];
2559                /*
2560                 * No-op TRB should not trigger interrupts.
2561                 * If event_trb is a no-op TRB, it means the
2562                 * corresponding TD has been cancelled. Just ignore
2563                 * the TD.
2564                 */
2565                if (TRB_TYPE_NOOP_LE32(event_trb->generic.field[3])) {
2566                        xhci_dbg(xhci,
2567                                 "event_trb is a no-op TRB. Skip it\n");
2568                        goto cleanup;
2569                }
2570
2571                /* Now update the urb's actual_length and give back to
2572                 * the core
2573                 */
2574                if (usb_endpoint_xfer_control(&td->urb->ep->desc))
2575                        ret = process_ctrl_td(xhci, td, event_trb, event, ep,
2576                                                 &status);
2577                else if (usb_endpoint_xfer_isoc(&td->urb->ep->desc))
2578                        ret = process_isoc_td(xhci, td, event_trb, event, ep,
2579                                                 &status);
2580                else
2581                        ret = process_bulk_intr_td(xhci, td, event_trb, event,
2582                                                 ep, &status);
2583
2584cleanup:
2585                /*
2586                 * Do not update event ring dequeue pointer if ep->skip is set.
2587                 * Will roll back to continue process missed tds.
2588                 */
2589                if (trb_comp_code == COMP_MISSED_INT || !ep->skip) {
2590                        inc_deq(xhci, xhci->event_ring);
2591                }
2592
2593                if (ret) {
2594                        urb = td->urb;
2595                        urb_priv = urb->hcpriv;
2596                        /* Leave the TD around for the reset endpoint function
2597                         * to use(but only if it's not a control endpoint,
2598                         * since we already queued the Set TR dequeue pointer
2599                         * command for stalled control endpoints).
2600                         */
2601                        if (usb_endpoint_xfer_control(&urb->ep->desc) ||
2602                                (trb_comp_code != COMP_STALL &&
2603                                        trb_comp_code != COMP_BABBLE))
2604                                xhci_urb_free_priv(xhci, urb_priv);
2605                        else
2606                                kfree(urb_priv);
2607
2608                        usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
2609                        if ((urb->actual_length != urb->transfer_buffer_length &&
2610                                                (urb->transfer_flags &
2611                                                 URB_SHORT_NOT_OK)) ||
2612                                        (status != 0 &&
2613                                         !usb_endpoint_xfer_isoc(&urb->ep->desc)))
2614                                xhci_dbg(xhci, "Giveback URB %p, len = %d, "
2615                                                "expected = %d, status = %d\n",
2616                                                urb, urb->actual_length,
2617                                                urb->transfer_buffer_length,
2618                                                status);
2619                        spin_unlock(&xhci->lock);
2620                        /* EHCI, UHCI, and OHCI always unconditionally set the
2621                         * urb->status of an isochronous endpoint to 0.
2622                         */
2623                        if (usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS)
2624                                status = 0;
2625                        usb_hcd_giveback_urb(bus_to_hcd(urb->dev->bus), urb, status);
2626                        spin_lock(&xhci->lock);
2627                }
2628
2629        /*
2630         * If ep->skip is set, it means there are missed tds on the
2631         * endpoint ring need to take care of.
2632         * Process them as short transfer until reach the td pointed by
2633         * the event.
2634         */
2635        } while (ep->skip && trb_comp_code != COMP_MISSED_INT);
2636
2637        return 0;
2638}
2639
2640/*
2641 * This function handles all OS-owned events on the event ring.  It may drop
2642 * xhci->lock between event processing (e.g. to pass up port status changes).
2643 * Returns >0 for "possibly more events to process" (caller should call again),
2644 * otherwise 0 if done.  In future, <0 returns should indicate error code.
2645 */
2646static int xhci_handle_event(struct xhci_hcd *xhci)
2647{
2648        union xhci_trb *event;
2649        int update_ptrs = 1;
2650        int ret;
2651
2652        if (!xhci->event_ring || !xhci->event_ring->dequeue) {
2653                xhci->error_bitmask |= 1 << 1;
2654                return 0;
2655        }
2656
2657        event = xhci->event_ring->dequeue;
2658        /* Does the HC or OS own the TRB? */
2659        if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
2660            xhci->event_ring->cycle_state) {
2661                xhci->error_bitmask |= 1 << 2;
2662                return 0;
2663        }
2664
2665        /*
2666         * Barrier between reading the TRB_CYCLE (valid) flag above and any
2667         * speculative reads of the event's flags/data below.
2668         */
2669        rmb();
2670        /* FIXME: Handle more event types. */
2671        switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
2672        case TRB_TYPE(TRB_COMPLETION):
2673                handle_cmd_completion(xhci, &event->event_cmd);
2674                break;
2675        case TRB_TYPE(TRB_PORT_STATUS):
2676                handle_port_status(xhci, event);
2677                update_ptrs = 0;
2678                break;
2679        case TRB_TYPE(TRB_TRANSFER):
2680                ret = handle_tx_event(xhci, &event->trans_event);
2681                if (ret < 0)
2682                        xhci->error_bitmask |= 1 << 9;
2683                else
2684                        update_ptrs = 0;
2685                break;
2686        case TRB_TYPE(TRB_DEV_NOTE):
2687                handle_device_notification(xhci, event);
2688                break;
2689        default:
2690                if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
2691                    TRB_TYPE(48))
2692                        handle_vendor_event(xhci, event);
2693                else
2694                        xhci->error_bitmask |= 1 << 3;
2695        }
2696        /* Any of the above functions may drop and re-acquire the lock, so check
2697         * to make sure a watchdog timer didn't mark the host as non-responsive.
2698         */
2699        if (xhci->xhc_state & XHCI_STATE_DYING) {
2700                xhci_dbg(xhci, "xHCI host dying, returning from "
2701                                "event handler.\n");
2702                return 0;
2703        }
2704
2705        if (update_ptrs)
2706                /* Update SW event ring dequeue pointer */
2707                inc_deq(xhci, xhci->event_ring);
2708
2709        /* Are there more items on the event ring?  Caller will call us again to
2710         * check.
2711         */
2712        return 1;
2713}
2714
2715/*
2716 * xHCI spec says we can get an interrupt, and if the HC has an error condition,
2717 * we might get bad data out of the event ring.  Section 4.10.2.7 has a list of
2718 * indicators of an event TRB error, but we check the status *first* to be safe.
2719 */
2720irqreturn_t xhci_irq(struct usb_hcd *hcd)
2721{
2722        struct xhci_hcd *xhci = hcd_to_xhci(hcd);
2723        u32 status;
2724        u64 temp_64;
2725        union xhci_trb *event_ring_deq;
2726        dma_addr_t deq;
2727
2728        spin_lock(&xhci->lock);
2729        /* Check if the xHC generated the interrupt, or the irq is shared */
2730        status = xhci_readl(xhci, &xhci->op_regs->status);
2731        if (status == 0xffffffff)
2732                goto hw_died;
2733
2734        if (!(status & STS_EINT)) {
2735                spin_unlock(&xhci->lock);
2736                return IRQ_NONE;
2737        }
2738        if (status & STS_FATAL) {
2739                xhci_warn(xhci, "WARNING: Host System Error\n");
2740                xhci_halt(xhci);
2741hw_died:
2742                spin_unlock(&xhci->lock);
2743                return -ESHUTDOWN;
2744        }
2745
2746        /*
2747         * Clear the op reg interrupt status first,
2748         * so we can receive interrupts from other MSI-X interrupters.
2749         * Write 1 to clear the interrupt status.
2750         */
2751        status |= STS_EINT;
2752        xhci_writel(xhci, status, &xhci->op_regs->status);
2753        /* FIXME when MSI-X is supported and there are multiple vectors */
2754        /* Clear the MSI-X event interrupt status */
2755
2756        if (hcd->irq) {
2757                u32 irq_pending;
2758                /* Acknowledge the PCI interrupt */
2759                irq_pending = xhci_readl(xhci, &xhci->ir_set->irq_pending);
2760                irq_pending |= IMAN_IP;
2761                xhci_writel(xhci, irq_pending, &xhci->ir_set->irq_pending);
2762        }
2763
2764        if (xhci->xhc_state & XHCI_STATE_DYING) {
2765                xhci_dbg(xhci, "xHCI dying, ignoring interrupt. "
2766                                "Shouldn't IRQs be disabled?\n");
2767                /* Clear the event handler busy flag (RW1C);
2768                 * the event ring should be empty.
2769                 */
2770                temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2771                xhci_write_64(xhci, temp_64 | ERST_EHB,
2772                                &xhci->ir_set->erst_dequeue);
2773                spin_unlock(&xhci->lock);
2774
2775                return IRQ_HANDLED;
2776        }
2777
2778        event_ring_deq = xhci->event_ring->dequeue;
2779        /* FIXME this should be a delayed service routine
2780         * that clears the EHB.
2781         */
2782        while (xhci_handle_event(xhci) > 0) {}
2783
2784        temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
2785        /* If necessary, update the HW's version of the event ring deq ptr. */
2786        if (event_ring_deq != xhci->event_ring->dequeue) {
2787                deq = xhci_trb_virt_to_dma(xhci->event_ring->deq_seg,
2788                                xhci->event_ring->dequeue);
2789                if (deq == 0)
2790                        xhci_warn(xhci, "WARN something wrong with SW event "
2791                                        "ring dequeue ptr.\n");
2792                /* Update HC event ring dequeue pointer */
2793                temp_64 &= ERST_PTR_MASK;
2794                temp_64 |= ((u64) deq & (u64) ~ERST_PTR_MASK);
2795        }
2796
2797        /* Clear the event handler busy flag (RW1C); event ring is empty. */
2798        temp_64 |= ERST_EHB;
2799        xhci_write_64(xhci, temp_64, &xhci->ir_set->erst_dequeue);
2800
2801        spin_unlock(&xhci->lock);
2802
2803        return IRQ_HANDLED;
2804}
2805
2806irqreturn_t xhci_msi_irq(int irq, void *hcd)
2807{
2808        return xhci_irq(hcd);
2809}
2810
2811/****           Endpoint Ring Operations        ****/
2812
2813/*
2814 * Generic function for queueing a TRB on a ring.
2815 * The caller must have checked to make sure there's room on the ring.
2816 *
2817 * @more_trbs_coming:   Will you enqueue more TRBs before calling
2818 *                      prepare_transfer()?
2819 */
2820static void queue_trb(struct xhci_hcd *xhci, struct xhci_ring *ring,
2821                bool more_trbs_coming,
2822                u32 field1, u32 field2, u32 field3, u32 field4)
2823{
2824        struct xhci_generic_trb *trb;
2825
2826        trb = &ring->enqueue->generic;
2827        trb->field[0] = cpu_to_le32(field1);
2828        trb->field[1] = cpu_to_le32(field2);
2829        trb->field[2] = cpu_to_le32(field3);
2830        trb->field[3] = cpu_to_le32(field4);
2831        inc_enq(xhci, ring, more_trbs_coming);
2832}
2833
2834/*
2835 * Does various checks on the endpoint ring, and makes it ready to queue num_trbs.
2836 * FIXME allocate segments if the ring is full.
2837 */
2838static int prepare_ring(struct xhci_hcd *xhci, struct xhci_ring *ep_ring,
2839                u32 ep_state, unsigned int num_trbs, gfp_t mem_flags)
2840{
2841        unsigned int num_trbs_needed;
2842
2843        /* Make sure the endpoint has been added to xHC schedule */
2844        switch (ep_state) {
2845        case EP_STATE_DISABLED:
2846                /*
2847                 * USB core changed config/interfaces without notifying us,
2848                 * or hardware is reporting the wrong state.
2849                 */
2850                xhci_warn(xhci, "WARN urb submitted to disabled ep\n");
2851                return -ENOENT;
2852        case EP_STATE_ERROR:
2853                xhci_warn(xhci, "WARN waiting for error on ep to be cleared\n");
2854                /* FIXME event handling code for error needs to clear it */
2855                /* XXX not sure if this should be -ENOENT or not */
2856                return -EINVAL;
2857        case EP_STATE_HALTED:
2858                xhci_dbg(xhci, "WARN halted endpoint, queueing URB anyway.\n");
2859        case EP_STATE_STOPPED:
2860        case EP_STATE_RUNNING:
2861                break;
2862        default:
2863                xhci_err(xhci, "ERROR unknown endpoint state for ep\n");
2864                /*
2865                 * FIXME issue Configure Endpoint command to try to get the HC
2866                 * back into a known state.
2867                 */
2868                return -EINVAL;
2869        }
2870
2871        while (1) {
2872                if (room_on_ring(xhci, ep_ring, num_trbs))
2873                        break;
2874
2875                if (ep_ring == xhci->cmd_ring) {
2876                        xhci_err(xhci, "Do not support expand command ring\n");
2877                        return -ENOMEM;
2878                }
2879
2880                xhci_dbg(xhci, "ERROR no room on ep ring, "
2881                                        "try ring expansion\n");
2882                num_trbs_needed = num_trbs - ep_ring->num_trbs_free;
2883                if (xhci_ring_expansion(xhci, ep_ring, num_trbs_needed,
2884                                        mem_flags)) {
2885                        xhci_err(xhci, "Ring expansion failed\n");
2886                        return -ENOMEM;
2887                }
2888        }
2889
2890        if (enqueue_is_link_trb(ep_ring)) {
2891                struct xhci_ring *ring = ep_ring;
2892                union xhci_trb *next;
2893
2894                next = ring->enqueue;
2895
2896                while (last_trb(xhci, ring, ring->enq_seg, next)) {
2897                        /* If we're not dealing with 0.95 hardware or isoc rings
2898                         * on AMD 0.96 host, clear the chain bit.
2899                         */
2900                        if (!xhci_link_trb_quirk(xhci) &&
2901                                        !(ring->type == TYPE_ISOC &&
2902                                         (xhci->quirks & XHCI_AMD_0x96_HOST)))
2903                                next->link.control &= cpu_to_le32(~TRB_CHAIN);
2904                        else
2905                                next->link.control |= cpu_to_le32(TRB_CHAIN);
2906
2907                        wmb();
2908                        next->link.control ^= cpu_to_le32(TRB_CYCLE);
2909
2910                        /* Toggle the cycle bit after the last ring segment. */
2911                        if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
2912                                ring->cycle_state = (ring->cycle_state ? 0 : 1);
2913                        }
2914                        ring->enq_seg = ring->enq_seg->next;
2915                        ring->enqueue = ring->enq_seg->trbs;
2916                        next = ring->enqueue;
2917                }
2918        }
2919
2920        return 0;
2921}
2922
2923static int prepare_transfer(struct xhci_hcd *xhci,
2924                struct xhci_virt_device *xdev,
2925                unsigned int ep_index,
2926                unsigned int stream_id,
2927                unsigned int num_trbs,
2928                struct urb *urb,
2929                unsigned int td_index,
2930                gfp_t mem_flags)
2931{
2932        int ret;
2933        struct urb_priv *urb_priv;
2934        struct xhci_td  *td;
2935        struct xhci_ring *ep_ring;
2936        struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
2937
2938        ep_ring = xhci_stream_id_to_ring(xdev, ep_index, stream_id);
2939        if (!ep_ring) {
2940                xhci_dbg(xhci, "Can't prepare ring for bad stream ID %u\n",
2941                                stream_id);
2942                return -EINVAL;
2943        }
2944
2945        ret = prepare_ring(xhci, ep_ring,
2946                           le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
2947                           num_trbs, mem_flags);
2948        if (ret)
2949                return ret;
2950
2951        urb_priv = urb->hcpriv;
2952        td = urb_priv->td[td_index];
2953
2954        INIT_LIST_HEAD(&td->td_list);
2955        INIT_LIST_HEAD(&td->cancelled_td_list);
2956
2957        if (td_index == 0) {
2958                ret = usb_hcd_link_urb_to_ep(bus_to_hcd(urb->dev->bus), urb);
2959                if (unlikely(ret))
2960                        return ret;
2961        }
2962
2963        td->urb = urb;
2964        /* Add this TD to the tail of the endpoint ring's TD list */
2965        list_add_tail(&td->td_list, &ep_ring->td_list);
2966        td->start_seg = ep_ring->enq_seg;
2967        td->first_trb = ep_ring->enqueue;
2968
2969        urb_priv->td[td_index] = td;
2970
2971        return 0;
2972}
2973
2974static unsigned int count_sg_trbs_needed(struct xhci_hcd *xhci, struct urb *urb)
2975{
2976        int num_sgs, num_trbs, running_total, temp, i;
2977        struct scatterlist *sg;
2978
2979        sg = NULL;
2980        num_sgs = urb->num_mapped_sgs;
2981        temp = urb->transfer_buffer_length;
2982
2983        num_trbs = 0;
2984        for_each_sg(urb->sg, sg, num_sgs, i) {
2985                unsigned int len = sg_dma_len(sg);
2986
2987                /* Scatter gather list entries may cross 64KB boundaries */
2988                running_total = TRB_MAX_BUFF_SIZE -
2989                        (sg_dma_address(sg) & (TRB_MAX_BUFF_SIZE - 1));
2990                running_total &= TRB_MAX_BUFF_SIZE - 1;
2991                if (running_total != 0)
2992                        num_trbs++;
2993
2994                /* How many more 64KB chunks to transfer, how many more TRBs? */
2995                while (running_total < sg_dma_len(sg) && running_total < temp) {
2996                        num_trbs++;
2997                        running_total += TRB_MAX_BUFF_SIZE;
2998                }
2999                len = min_t(int, len, temp);
3000                temp -= len;
3001                if (temp == 0)
3002                        break;
3003        }
3004        return num_trbs;
3005}
3006
3007static void check_trb_math(struct urb *urb, int num_trbs, int running_total)
3008{
3009        if (num_trbs != 0)
3010                dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated number of "
3011                                "TRBs, %d left\n", __func__,
3012                                urb->ep->desc.bEndpointAddress, num_trbs);
3013        if (running_total != urb->transfer_buffer_length)
3014                dev_err(&urb->dev->dev, "%s - ep %#x - Miscalculated tx length, "
3015                                "queued %#x (%d), asked for %#x (%d)\n",
3016                                __func__,
3017                                urb->ep->desc.bEndpointAddress,
3018                                running_total, running_total,
3019                                urb->transfer_buffer_length,
3020                                urb->transfer_buffer_length);
3021}
3022
3023static void giveback_first_trb(struct xhci_hcd *xhci, int slot_id,
3024                unsigned int ep_index, unsigned int stream_id, int start_cycle,
3025                struct xhci_generic_trb *start_trb)
3026{
3027        /*
3028         * Pass all the TRBs to the hardware at once and make sure this write
3029         * isn't reordered.
3030         */
3031        wmb();
3032        if (start_cycle)
3033                start_trb->field[3] |= cpu_to_le32(start_cycle);
3034        else
3035                start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
3036        xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
3037}
3038
3039/*
3040 * xHCI uses normal TRBs for both bulk and interrupt.  When the interrupt
3041 * endpoint is to be serviced, the xHC will consume (at most) one TD.  A TD
3042 * (comprised of sg list entries) can take several service intervals to
3043 * transmit.
3044 */
3045int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3046                struct urb *urb, int slot_id, unsigned int ep_index)
3047{
3048        struct xhci_ep_ctx *ep_ctx = xhci_get_ep_ctx(xhci,
3049                        xhci->devs[slot_id]->out_ctx, ep_index);
3050        int xhci_interval;
3051        int ep_interval;
3052
3053        xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3054        ep_interval = urb->interval;
3055        /* Convert to microframes */
3056        if (urb->dev->speed == USB_SPEED_LOW ||
3057                        urb->dev->speed == USB_SPEED_FULL)
3058                ep_interval *= 8;
3059        /* FIXME change this to a warning and a suggestion to use the new API
3060         * to set the polling interval (once the API is added).
3061         */
3062        if (xhci_interval != ep_interval) {
3063                if (printk_ratelimit())
3064                        dev_dbg(&urb->dev->dev, "Driver uses different interval"
3065                                        " (%d microframe%s) than xHCI "
3066                                        "(%d microframe%s)\n",
3067                                        ep_interval,
3068                                        ep_interval == 1 ? "" : "s",
3069                                        xhci_interval,
3070                                        xhci_interval == 1 ? "" : "s");
3071                urb->interval = xhci_interval;
3072                /* Convert back to frames for LS/FS devices */
3073                if (urb->dev->speed == USB_SPEED_LOW ||
3074                                urb->dev->speed == USB_SPEED_FULL)
3075                        urb->interval /= 8;
3076        }
3077        return xhci_queue_bulk_tx(xhci, mem_flags, urb, slot_id, ep_index);
3078}
3079
3080/*
3081 * The TD size is the number of bytes remaining in the TD (including this TRB),
3082 * right shifted by 10.
3083 * It must fit in bits 21:17, so it can't be bigger than 31.
3084 */
3085static u32 xhci_td_remainder(unsigned int remainder)
3086{
3087        u32 max = (1 << (21 - 17 + 1)) - 1;
3088
3089        if ((remainder >> 10) >= max)
3090                return max << 17;
3091        else
3092                return (remainder >> 10) << 17;
3093}
3094
3095/*
3096 * For xHCI 1.0 host controllers, TD size is the number of max packet sized
3097 * packets remaining in the TD (*not* including this TRB).
3098 *
3099 * Total TD packet count = total_packet_count =
3100 *     DIV_ROUND_UP(TD size in bytes / wMaxPacketSize)
3101 *
3102 * Packets transferred up to and including this TRB = packets_transferred =
3103 *     rounddown(total bytes transferred including this TRB / wMaxPacketSize)
3104 *
3105 * TD size = total_packet_count - packets_transferred
3106 *
3107 * It must fit in bits 21:17, so it can't be bigger than 31.
3108 * The last TRB in a TD must have the TD size set to zero.
3109 */
3110static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
3111                unsigned int total_packet_count, struct urb *urb,
3112                unsigned int num_trbs_left)
3113{
3114        int packets_transferred;
3115
3116        /* One TRB with a zero-length data packet. */
3117        if (num_trbs_left == 0 || (running_total == 0 && trb_buff_len == 0))
3118                return 0;
3119
3120        /* All the TRB queueing functions don't count the current TRB in
3121         * running_total.
3122         */
3123        packets_transferred = (running_total + trb_buff_len) /
3124                GET_MAX_PACKET(usb_endpoint_maxp(&urb->ep->desc));
3125
3126        if ((total_packet_count - packets_transferred) > 31)
3127                return 31 << 17;
3128        return (total_packet_count - packets_transferred) << 17;
3129}
3130
3131static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3132                struct urb *urb, int slot_id, unsigned int ep_index)
3133{
3134        struct xhci_ring *ep_ring;
3135        unsigned int num_trbs;
3136        struct urb_priv *urb_priv;
3137        struct xhci_td *td;
3138        struct scatterlist *sg;
3139        int num_sgs;
3140        int trb_buff_len, this_sg_len, running_total;
3141        unsigned int total_packet_count;
3142        bool first_trb;
3143        u64 addr;
3144        bool more_trbs_coming;
3145
3146        struct xhci_generic_trb *start_trb;
3147        int start_cycle;
3148
3149        ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3150        if (!ep_ring)
3151                return -EINVAL;
3152
3153        num_trbs = count_sg_trbs_needed(xhci, urb);
3154        num_sgs = urb->num_mapped_sgs;
3155        total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3156                        usb_endpoint_maxp(&urb->ep->desc));
3157
3158        trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
3159                        ep_index, urb->stream_id,
3160                        num_trbs, urb, 0, mem_flags);
3161        if (trb_buff_len < 0)
3162                return trb_buff_len;
3163
3164        urb_priv = urb->hcpriv;
3165        td = urb_priv->td[0];
3166
3167        /*
3168         * Don't give the first TRB to the hardware (by toggling the cycle bit)
3169         * until we've finished creating all the other TRBs.  The ring's cycle
3170         * state may change as we enqueue the other TRBs, so save it too.
3171         */
3172        start_trb = &ep_ring->enqueue->generic;
3173        start_cycle = ep_ring->cycle_state;
3174
3175        running_total = 0;
3176        /*
3177         * How much data is in the first TRB?
3178         *
3179         * There are three forces at work for TRB buffer pointers and lengths:
3180         * 1. We don't want to walk off the end of this sg-list entry buffer.
3181         * 2. The transfer length that the driver requested may be smaller than
3182         *    the amount of memory allocated for this scatter-gather list.
3183         * 3. TRBs buffers can't cross 64KB boundaries.
3184         */
3185        sg = urb->sg;
3186        addr = (u64) sg_dma_address(sg);
3187        this_sg_len = sg_dma_len(sg);
3188        trb_buff_len = TRB_MAX_BUFF_SIZE - (addr & (TRB_MAX_BUFF_SIZE - 1));
3189        trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3190        if (trb_buff_len > urb->transfer_buffer_length)
3191                trb_buff_len = urb->transfer_buffer_length;
3192
3193        first_trb = true;
3194        /* Queue the first TRB, even if it's zero-length */
3195        do {
3196                u32 field = 0;
3197                u32 length_field = 0;
3198                u32 remainder = 0;
3199
3200                /* Don't change the cycle bit of the first TRB until later */
3201                if (first_trb) {
3202                        first_trb = false;
3203                        if (start_cycle == 0)
3204                                field |= 0x1;
3205                } else
3206                        field |= ep_ring->cycle_state;
3207
3208                /* Chain all the TRBs together; clear the chain bit in the last
3209                 * TRB to indicate it's the last TRB in the chain.
3210                 */
3211                if (num_trbs > 1) {
3212                        field |= TRB_CHAIN;
3213                } else {
3214                        /* FIXME - add check for ZERO_PACKET flag before this */
3215                        td->last_trb = ep_ring->enqueue;
3216                        field |= TRB_IOC;
3217                }
3218
3219                /* Only set interrupt on short packet for IN endpoints */
3220                if (usb_urb_dir_in(urb))
3221                        field |= TRB_ISP;
3222
3223                if (TRB_MAX_BUFF_SIZE -
3224                                (addr & (TRB_MAX_BUFF_SIZE - 1)) < trb_buff_len) {
3225                        xhci_warn(xhci, "WARN: sg dma xfer crosses 64KB boundaries!\n");
3226                        xhci_dbg(xhci, "Next boundary at %#x, end dma = %#x\n",
3227                                        (unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
3228                                        (unsigned int) addr + trb_buff_len);
3229                }
3230
3231                /* Set the TRB length, TD size, and interrupter fields. */
3232                if (xhci->hci_version < 0x100) {
3233                        remainder = xhci_td_remainder(
3234                                        urb->transfer_buffer_length -
3235                                        running_total);
3236                } else {
3237                        remainder = xhci_v1_0_td_remainder(running_total,
3238                                        trb_buff_len, total_packet_count, urb,
3239                                        num_trbs - 1);
3240                }
3241                length_field = TRB_LEN(trb_buff_len) |
3242                        remainder |
3243                        TRB_INTR_TARGET(0);
3244
3245                if (num_trbs > 1)
3246                        more_trbs_coming = true;
3247                else
3248                        more_trbs_coming = false;
3249                queue_trb(xhci, ep_ring, more_trbs_coming,
3250                                lower_32_bits(addr),
3251                                upper_32_bits(addr),
3252                                length_field,
3253                                field | TRB_TYPE(TRB_NORMAL));
3254                --num_trbs;
3255                running_total += trb_buff_len;
3256
3257                /* Calculate length for next transfer --
3258                 * Are we done queueing all the TRBs for this sg entry?
3259                 */
3260                this_sg_len -= trb_buff_len;
3261                if (this_sg_len == 0) {
3262                        --num_sgs;
3263                        if (num_sgs == 0)
3264                                break;
3265                        sg = sg_next(sg);
3266                        addr = (u64) sg_dma_address(sg);
3267                        this_sg_len = sg_dma_len(sg);
3268                } else {
3269                        addr += trb_buff_len;
3270                }
3271
3272                trb_buff_len = TRB_MAX_BUFF_SIZE -
3273                        (addr & (TRB_MAX_BUFF_SIZE - 1));
3274                trb_buff_len = min_t(int, trb_buff_len, this_sg_len);
3275                if (running_total + trb_buff_len > urb->transfer_buffer_length)
3276                        trb_buff_len =
3277                                urb->transfer_buffer_length - running_total;
3278        } while (running_total < urb->transfer_buffer_length);
3279
3280        check_trb_math(urb, num_trbs, running_total);
3281        giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3282                        start_cycle, start_trb);
3283        return 0;
3284}
3285
3286/* This is very similar to what ehci-q.c qtd_fill() does */
3287int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3288                struct urb *urb, int slot_id, unsigned int ep_index)
3289{
3290        struct xhci_ring *ep_ring;
3291        struct urb_priv *urb_priv;
3292        struct xhci_td *td;
3293        int num_trbs;
3294        struct xhci_generic_trb *start_trb;
3295        bool first_trb;
3296        bool more_trbs_coming;
3297        int start_cycle;
3298        u32 field, length_field;
3299
3300        int running_total, trb_buff_len, ret;
3301        unsigned int total_packet_count;
3302        u64 addr;
3303
3304        if (urb->num_sgs)
3305                return queue_bulk_sg_tx(xhci, mem_flags, urb, slot_id, ep_index);
3306
3307        ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3308        if (!ep_ring)
3309                return -EINVAL;
3310
3311        num_trbs = 0;
3312        /* How much data is (potentially) left before the 64KB boundary? */
3313        running_total = TRB_MAX_BUFF_SIZE -
3314                (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3315        running_total &= TRB_MAX_BUFF_SIZE - 1;
3316
3317        /* If there's some data on this 64KB chunk, or we have to send a
3318         * zero-length transfer, we need at least one TRB
3319         */
3320        if (running_total != 0 || urb->transfer_buffer_length == 0)
3321                num_trbs++;
3322        /* How many more 64KB chunks to transfer, how many more TRBs? */
3323        while (running_total < urb->transfer_buffer_length) {
3324                num_trbs++;
3325                running_total += TRB_MAX_BUFF_SIZE;
3326        }
3327        /* FIXME: this doesn't deal with URB_ZERO_PACKET - need one more */
3328
3329        ret = prepare_transfer(xhci, xhci->devs[slot_id],
3330                        ep_index, urb->stream_id,
3331                        num_trbs, urb, 0, mem_flags);
3332        if (ret < 0)
3333                return ret;
3334
3335        urb_priv = urb->hcpriv;
3336        td = urb_priv->td[0];
3337
3338        /*
3339         * Don't give the first TRB to the hardware (by toggling the cycle bit)
3340         * until we've finished creating all the other TRBs.  The ring's cycle
3341         * state may change as we enqueue the other TRBs, so save it too.
3342         */
3343        start_trb = &ep_ring->enqueue->generic;
3344        start_cycle = ep_ring->cycle_state;
3345
3346        running_total = 0;
3347        total_packet_count = DIV_ROUND_UP(urb->transfer_buffer_length,
3348                        usb_endpoint_maxp(&urb->ep->desc));
3349        /* How much data is in the first TRB? */
3350        addr = (u64) urb->transfer_dma;
3351        trb_buff_len = TRB_MAX_BUFF_SIZE -
3352                (urb->transfer_dma & (TRB_MAX_BUFF_SIZE - 1));
3353        if (trb_buff_len > urb->transfer_buffer_length)
3354                trb_buff_len = urb->transfer_buffer_length;
3355
3356        first_trb = true;
3357
3358        /* Queue the first TRB, even if it's zero-length */
3359        do {
3360                u32 remainder = 0;
3361                field = 0;
3362
3363                /* Don't change the cycle bit of the first TRB until later */
3364                if (first_trb) {
3365                        first_trb = false;
3366                        if (start_cycle == 0)
3367                                field |= 0x1;
3368                } else
3369                        field |= ep_ring->cycle_state;
3370
3371                /* Chain all the TRBs together; clear the chain bit in the last
3372                 * TRB to indicate it's the last TRB in the chain.
3373                 */
3374                if (num_trbs > 1) {
3375                        field |= TRB_CHAIN;
3376                } else {
3377                        /* FIXME - add check for ZERO_PACKET flag before this */
3378                        td->last_trb = ep_ring->enqueue;
3379                        field |= TRB_IOC;
3380                }
3381
3382                /* Only set interrupt on short packet for IN endpoints */
3383                if (usb_urb_dir_in(urb))
3384                        field |= TRB_ISP;
3385
3386                /* Set the TRB length, TD size, and interrupter fields. */
3387                if (xhci->hci_version < 0x100) {
3388                        remainder = xhci_td_remainder(
3389                                        urb->transfer_buffer_length -
3390                                        running_total);
3391                } else {
3392                        remainder = xhci_v1_0_td_remainder(running_total,
3393                                        trb_buff_len, total_packet_count, urb,
3394                                        num_trbs - 1);
3395                }
3396                length_field = TRB_LEN(trb_buff_len) |
3397                        remainder |
3398                        TRB_INTR_TARGET(0);
3399
3400                if (num_trbs > 1)
3401                        more_trbs_coming = true;
3402                else
3403                        more_trbs_coming = false;
3404                queue_trb(xhci, ep_ring, more_trbs_coming,
3405                                lower_32_bits(addr),
3406                                upper_32_bits(addr),
3407                                length_field,
3408                                field | TRB_TYPE(TRB_NORMAL));
3409                --num_trbs;
3410                running_total += trb_buff_len;
3411
3412                /* Calculate length for next transfer */
3413                addr += trb_buff_len;
3414                trb_buff_len = urb->transfer_buffer_length - running_total;
3415                if (trb_buff_len > TRB_MAX_BUFF_SIZE)
3416                        trb_buff_len = TRB_MAX_BUFF_SIZE;
3417        } while (running_total < urb->transfer_buffer_length);
3418
3419        check_trb_math(urb, num_trbs, running_total);
3420        giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3421                        start_cycle, start_trb);
3422        return 0;
3423}
3424
3425/* Caller must have locked xhci->lock */
3426int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3427                struct urb *urb, int slot_id, unsigned int ep_index)
3428{
3429        struct xhci_ring *ep_ring;
3430        int num_trbs;
3431        int ret;
3432        struct usb_ctrlrequest *setup;
3433        struct xhci_generic_trb *start_trb;
3434        int start_cycle;
3435        u32 field, length_field;
3436        struct urb_priv *urb_priv;
3437        struct xhci_td *td;
3438
3439        ep_ring = xhci_urb_to_transfer_ring(xhci, urb);
3440        if (!ep_ring)
3441                return -EINVAL;
3442
3443        /*
3444         * Need to copy setup packet into setup TRB, so we can't use the setup
3445         * DMA address.
3446         */
3447        if (!urb->setup_packet)
3448                return -EINVAL;
3449
3450        /* 1 TRB for setup, 1 for status */
3451        num_trbs = 2;
3452        /*
3453         * Don't need to check if we need additional event data and normal TRBs,
3454         * since data in control transfers will never get bigger than 16MB
3455         * XXX: can we get a buffer that crosses 64KB boundaries?
3456         */
3457        if (urb->transfer_buffer_length > 0)
3458                num_trbs++;
3459        ret = prepare_transfer(xhci, xhci->devs[slot_id],
3460                        ep_index, urb->stream_id,
3461                        num_trbs, urb, 0, mem_flags);
3462        if (ret < 0)
3463                return ret;
3464
3465        urb_priv = urb->hcpriv;
3466        td = urb_priv->td[0];
3467
3468        /*
3469         * Don't give the first TRB to the hardware (by toggling the cycle bit)
3470         * until we've finished creating all the other TRBs.  The ring's cycle
3471         * state may change as we enqueue the other TRBs, so save it too.
3472         */
3473        start_trb = &ep_ring->enqueue->generic;
3474        start_cycle = ep_ring->cycle_state;
3475
3476        /* Queue setup TRB - see section 6.4.1.2.1 */
3477        /* FIXME better way to translate setup_packet into two u32 fields? */
3478        setup = (struct usb_ctrlrequest *) urb->setup_packet;
3479        field = 0;
3480        field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
3481        if (start_cycle == 0)
3482                field |= 0x1;
3483
3484        /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
3485        if (xhci->hci_version == 0x100) {
3486                if (urb->transfer_buffer_length > 0) {
3487                        if (setup->bRequestType & USB_DIR_IN)
3488                                field |= TRB_TX_TYPE(TRB_DATA_IN);
3489                        else
3490                                field |= TRB_TX_TYPE(TRB_DATA_OUT);
3491                }
3492        }
3493
3494        queue_trb(xhci, ep_ring, true,
3495                  setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
3496                  le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
3497                  TRB_LEN(8) | TRB_INTR_TARGET(0),
3498                  /* Immediate data in pointer */
3499                  field);
3500
3501        /* If there's data, queue data TRBs */
3502        /* Only set interrupt on short packet for IN endpoints */
3503        if (usb_urb_dir_in(urb))
3504                field = TRB_ISP | TRB_TYPE(TRB_DATA);
3505        else
3506                field = TRB_TYPE(TRB_DATA);
3507
3508        length_field = TRB_LEN(urb->transfer_buffer_length) |
3509                xhci_td_remainder(urb->transfer_buffer_length) |
3510                TRB_INTR_TARGET(0);
3511        if (urb->transfer_buffer_length > 0) {
3512                if (setup->bRequestType & USB_DIR_IN)
3513                        field |= TRB_DIR_IN;
3514                queue_trb(xhci, ep_ring, true,
3515                                lower_32_bits(urb->transfer_dma),
3516                                upper_32_bits(urb->transfer_dma),
3517                                length_field,
3518                                field | ep_ring->cycle_state);
3519        }
3520
3521        /* Save the DMA address of the last TRB in the TD */
3522        td->last_trb = ep_ring->enqueue;
3523
3524        /* Queue status TRB - see Table 7 and sections 4.11.2.2 and 6.4.1.2.3 */
3525        /* If the device sent data, the status stage is an OUT transfer */
3526        if (urb->transfer_buffer_length > 0 && setup->bRequestType & USB_DIR_IN)
3527                field = 0;
3528        else
3529                field = TRB_DIR_IN;
3530        queue_trb(xhci, ep_ring, false,
3531                        0,
3532                        0,
3533                        TRB_INTR_TARGET(0),
3534                        /* Event on completion */
3535                        field | TRB_IOC | TRB_TYPE(TRB_STATUS) | ep_ring->cycle_state);
3536
3537        giveback_first_trb(xhci, slot_id, ep_index, 0,
3538                        start_cycle, start_trb);
3539        return 0;
3540}
3541
3542static int count_isoc_trbs_needed(struct xhci_hcd *xhci,
3543                struct urb *urb, int i)
3544{
3545        int num_trbs = 0;
3546        u64 addr, td_len;
3547
3548        addr = (u64) (urb->transfer_dma + urb->iso_frame_desc[i].offset);
3549        td_len = urb->iso_frame_desc[i].length;
3550
3551        num_trbs = DIV_ROUND_UP(td_len + (addr & (TRB_MAX_BUFF_SIZE - 1)),
3552                        TRB_MAX_BUFF_SIZE);
3553        if (num_trbs == 0)
3554                num_trbs++;
3555
3556        return num_trbs;
3557}
3558
3559/*
3560 * The transfer burst count field of the isochronous TRB defines the number of
3561 * bursts that are required to move all packets in this TD.  Only SuperSpeed
3562 * devices can burst up to bMaxBurst number of packets per service interval.
3563 * This field is zero based, meaning a value of zero in the field means one
3564 * burst.  Basically, for everything but SuperSpeed devices, this field will be
3565 * zero.  Only xHCI 1.0 host controllers support this field.
3566 */
3567static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
3568                struct usb_device *udev,
3569                struct urb *urb, unsigned int total_packet_count)
3570{
3571        unsigned int max_burst;
3572
3573        if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
3574                return 0;
3575
3576        max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3577        return roundup(total_packet_count, max_burst + 1) - 1;
3578}
3579
3580/*
3581 * Returns the number of packets in the last "burst" of packets.  This field is
3582 * valid for all speeds of devices.  USB 2.0 devices can only do one "burst", so
3583 * the last burst packet count is equal to the total number of packets in the
3584 * TD.  SuperSpeed endpoints can have up to 3 bursts.  All but the last burst
3585 * must contain (bMaxBurst + 1) number of packets, but the last burst can
3586 * contain 1 to (bMaxBurst + 1) packets.
3587 */
3588static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
3589                struct usb_device *udev,
3590                struct urb *urb, unsigned int total_packet_count)
3591{
3592        unsigned int max_burst;
3593        unsigned int residue;
3594
3595        if (xhci->hci_version < 0x100)
3596                return 0;
3597
3598        switch (udev->speed) {
3599        case USB_SPEED_SUPER:
3600                /* bMaxBurst is zero based: 0 means 1 packet per burst */
3601                max_burst = urb->ep->ss_ep_comp.bMaxBurst;
3602                residue = total_packet_count % (max_burst + 1);
3603                /* If residue is zero, the last burst contains (max_burst + 1)
3604                 * number of packets, but the TLBPC field is zero-based.
3605                 */
3606                if (residue == 0)
3607                        return max_burst;
3608                return residue - 1;
3609        default:
3610                if (total_packet_count == 0)
3611                        return 0;
3612                return total_packet_count - 1;
3613        }
3614}
3615
3616/* This is for isoc transfer */
3617static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
3618                struct urb *urb, int slot_id, unsigned int ep_index)
3619{
3620        struct xhci_ring *ep_ring;
3621        struct urb_priv *urb_priv;
3622        struct xhci_td *td;
3623        int num_tds, trbs_per_td;
3624        struct xhci_generic_trb *start_trb;
3625        bool first_trb;
3626        int start_cycle;
3627        u32 field, length_field;
3628        int running_total, trb_buff_len, td_len, td_remain_len, ret;
3629        u64 start_addr, addr;
3630        int i, j;
3631        bool more_trbs_coming;
3632
3633        ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
3634
3635        num_tds = urb->number_of_packets;
3636        if (num_tds < 1) {
3637                xhci_dbg(xhci, "Isoc URB with zero packets?\n");
3638                return -EINVAL;
3639        }
3640
3641        start_addr = (u64) urb->transfer_dma;
3642        start_trb = &ep_ring->enqueue->generic;
3643        start_cycle = ep_ring->cycle_state;
3644
3645        urb_priv = urb->hcpriv;
3646        /* Queue the first TRB, even if it's zero-length */
3647        for (i = 0; i < num_tds; i++) {
3648                unsigned int total_packet_count;
3649                unsigned int burst_count;
3650                unsigned int residue;
3651
3652                first_trb = true;
3653                running_total = 0;
3654                addr = start_addr + urb->iso_frame_desc[i].offset;
3655                td_len = urb->iso_frame_desc[i].length;
3656                td_remain_len = td_len;
3657                total_packet_count = DIV_ROUND_UP(td_len,
3658                                GET_MAX_PACKET(
3659                                        usb_endpoint_maxp(&urb->ep->desc)));
3660                /* A zero-length transfer still involves at least one packet. */
3661                if (total_packet_count == 0)
3662                        total_packet_count++;
3663                burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
3664                                total_packet_count);
3665                residue = xhci_get_last_burst_packet_count(xhci,
3666                                urb->dev, urb, total_packet_count);
3667
3668                trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
3669
3670                ret = prepare_transfer(xhci, xhci->devs[slot_id], ep_index,
3671                                urb->stream_id, trbs_per_td, urb, i, mem_flags);
3672                if (ret < 0) {
3673                        if (i == 0)
3674                                return ret;
3675                        goto cleanup;
3676                }
3677
3678                td = urb_priv->td[i];
3679                for (j = 0; j < trbs_per_td; j++) {
3680                        u32 remainder = 0;
3681                        field = 0;
3682
3683                        if (first_trb) {
3684                                field = TRB_TBC(burst_count) |
3685                                        TRB_TLBPC(residue);
3686                                /* Queue the isoc TRB */
3687                                field |= TRB_TYPE(TRB_ISOC);
3688                                /* Assume URB_ISO_ASAP is set */
3689                                field |= TRB_SIA;
3690                                if (i == 0) {
3691                                        if (start_cycle == 0)
3692                                                field |= 0x1;
3693                                } else
3694                                        field |= ep_ring->cycle_state;
3695                                first_trb = false;
3696                        } else {
3697                                /* Queue other normal TRBs */
3698                                field |= TRB_TYPE(TRB_NORMAL);
3699                                field |= ep_ring->cycle_state;
3700                        }
3701
3702                        /* Only set interrupt on short packet for IN EPs */
3703                        if (usb_urb_dir_in(urb))
3704                                field |= TRB_ISP;
3705
3706                        /* Chain all the TRBs together; clear the chain bit in
3707                         * the last TRB to indicate it's the last TRB in the
3708                         * chain.
3709                         */
3710                        if (j < trbs_per_td - 1) {
3711                                field |= TRB_CHAIN;
3712                                more_trbs_coming = true;
3713                        } else {
3714                                td->last_trb = ep_ring->enqueue;
3715                                field |= TRB_IOC;
3716                                if (xhci->hci_version == 0x100 &&
3717                                                !(xhci->quirks &
3718                                                        XHCI_AVOID_BEI)) {
3719                                        /* Set BEI bit except for the last td */
3720                                        if (i < num_tds - 1)
3721                                                field |= TRB_BEI;
3722                                }
3723                                more_trbs_coming = false;
3724                        }
3725
3726                        /* Calculate TRB length */
3727                        trb_buff_len = TRB_MAX_BUFF_SIZE -
3728                                (addr & ((1 << TRB_MAX_BUFF_SHIFT) - 1));
3729                        if (trb_buff_len > td_remain_len)
3730                                trb_buff_len = td_remain_len;
3731
3732                        /* Set the TRB length, TD size, & interrupter fields. */
3733                        if (xhci->hci_version < 0x100) {
3734                                remainder = xhci_td_remainder(
3735                                                td_len - running_total);
3736                        } else {
3737                                remainder = xhci_v1_0_td_remainder(
3738                                                running_total, trb_buff_len,
3739                                                total_packet_count, urb,
3740                                                (trbs_per_td - j - 1));
3741                        }
3742                        length_field = TRB_LEN(trb_buff_len) |
3743                                remainder |
3744                                TRB_INTR_TARGET(0);
3745
3746                        queue_trb(xhci, ep_ring, more_trbs_coming,
3747                                lower_32_bits(addr),
3748                                upper_32_bits(addr),
3749                                length_field,
3750                                field);
3751                        running_total += trb_buff_len;
3752
3753                        addr += trb_buff_len;
3754                        td_remain_len -= trb_buff_len;
3755                }
3756
3757                /* Check TD length */
3758                if (running_total != td_len) {
3759                        xhci_err(xhci, "ISOC TD length unmatch\n");
3760                        ret = -EINVAL;
3761                        goto cleanup;
3762                }
3763        }
3764
3765        if (xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs == 0) {
3766                if (xhci->quirks & XHCI_AMD_PLL_FIX)
3767                        usb_amd_quirk_pll_disable();
3768        }
3769        xhci_to_hcd(xhci)->self.bandwidth_isoc_reqs++;
3770
3771        giveback_first_trb(xhci, slot_id, ep_index, urb->stream_id,
3772                        start_cycle, start_trb);
3773        return 0;
3774cleanup:
3775        /* Clean up a partially enqueued isoc transfer. */
3776
3777        for (i--; i >= 0; i--)
3778                list_del_init(&urb_priv->td[i]->td_list);
3779
3780        /* Use the first TD as a temporary variable to turn the TDs we've queued
3781         * into No-ops with a software-owned cycle bit. That way the hardware
3782         * won't accidentally start executing bogus TDs when we partially
3783         * overwrite them.  td->first_trb and td->start_seg are already set.
3784         */
3785        urb_priv->td[0]->last_trb = ep_ring->enqueue;
3786        /* Every TRB except the first & last will have its cycle bit flipped. */
3787        td_to_noop(xhci, ep_ring, urb_priv->td[0], true);
3788
3789        /* Reset the ring enqueue back to the first TRB and its cycle bit. */
3790        ep_ring->enqueue = urb_priv->td[0]->first_trb;
3791        ep_ring->enq_seg = urb_priv->td[0]->start_seg;
3792        ep_ring->cycle_state = start_cycle;
3793        ep_ring->num_trbs_free = ep_ring->num_trbs_free_temp;
3794        usb_hcd_unlink_urb_from_ep(bus_to_hcd(urb->dev->bus), urb);
3795        return ret;
3796}
3797
3798/*
3799 * Check transfer ring to guarantee there is enough room for the urb.
3800 * Update ISO URB start_frame and interval.
3801 * Update interval as xhci_queue_intr_tx does. Just use xhci frame_index to
3802 * update the urb->start_frame by now.
3803 * Always assume URB_ISO_ASAP set, and NEVER use urb->start_frame as input.
3804 */
3805int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
3806                struct urb *urb, int slot_id, unsigned int ep_index)
3807{
3808        struct xhci_virt_device *xdev;
3809        struct xhci_ring *ep_ring;
3810        struct xhci_ep_ctx *ep_ctx;
3811        int start_frame;
3812        int xhci_interval;
3813        int ep_interval;
3814        int num_tds, num_trbs, i;
3815        int ret;
3816
3817        xdev = xhci->devs[slot_id];
3818        ep_ring = xdev->eps[ep_index].ring;
3819        ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
3820
3821        num_trbs = 0;
3822        num_tds = urb->number_of_packets;
3823        for (i = 0; i < num_tds; i++)
3824                num_trbs += count_isoc_trbs_needed(xhci, urb, i);
3825
3826        /* Check the ring to guarantee there is enough room for the whole urb.
3827         * Do not insert any td of the urb to the ring if the check failed.
3828         */
3829        ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
3830                           num_trbs, mem_flags);
3831        if (ret)
3832                return ret;
3833
3834        start_frame = xhci_readl(xhci, &xhci->run_regs->microframe_index);
3835        start_frame &= 0x3fff;
3836
3837        urb->start_frame = start_frame;
3838        if (urb->dev->speed == USB_SPEED_LOW ||
3839                        urb->dev->speed == USB_SPEED_FULL)
3840                urb->start_frame >>= 3;
3841
3842        xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
3843        ep_interval = urb->interval;
3844        /* Convert to microframes */
3845        if (urb->dev->speed == USB_SPEED_LOW ||
3846                        urb->dev->speed == USB_SPEED_FULL)
3847                ep_interval *= 8;
3848        /* FIXME change this to a warning and a suggestion to use the new API
3849         * to set the polling interval (once the API is added).
3850         */
3851        if (xhci_interval != ep_interval) {
3852                if (printk_ratelimit())
3853                        dev_dbg(&urb->dev->dev, "Driver uses different interval"
3854                                        " (%d microframe%s) than xHCI "
3855                                        "(%d microframe%s)\n",
3856                                        ep_interval,
3857                                        ep_interval == 1 ? "" : "s",
3858                                        xhci_interval,
3859                                        xhci_interval == 1 ? "" : "s");
3860                urb->interval = xhci_interval;
3861                /* Convert back to frames for LS/FS devices */
3862                if (urb->dev->speed == USB_SPEED_LOW ||
3863                                urb->dev->speed == USB_SPEED_FULL)
3864                        urb->interval /= 8;
3865        }
3866        ep_ring->num_trbs_free_temp = ep_ring->num_trbs_free;
3867
3868        return xhci_queue_isoc_tx(xhci, mem_flags, urb, slot_id, ep_index);
3869}
3870
3871/****           Command Ring Operations         ****/
3872
3873/* Generic function for queueing a command TRB on the command ring.
3874 * Check to make sure there's room on the command ring for one command TRB.
3875 * Also check that there's room reserved for commands that must not fail.
3876 * If this is a command that must not fail, meaning command_must_succeed = TRUE,
3877 * then only check for the number of reserved spots.
3878 * Don't decrement xhci->cmd_ring_reserved_trbs after we've queued the TRB
3879 * because the command event handler may want to resubmit a failed command.
3880 */
3881static int queue_command(struct xhci_hcd *xhci, u32 field1, u32 field2,
3882                u32 field3, u32 field4, bool command_must_succeed)
3883{
3884        int reserved_trbs = xhci->cmd_ring_reserved_trbs;
3885        int ret;
3886
3887        if (!command_must_succeed)
3888                reserved_trbs++;
3889
3890        ret = prepare_ring(xhci, xhci->cmd_ring, EP_STATE_RUNNING,
3891                        reserved_trbs, GFP_ATOMIC);
3892        if (ret < 0) {
3893                xhci_err(xhci, "ERR: No room for command on command ring\n");
3894                if (command_must_succeed)
3895                        xhci_err(xhci, "ERR: Reserved TRB counting for "
3896                                        "unfailable commands failed.\n");
3897                return ret;
3898        }
3899        queue_trb(xhci, xhci->cmd_ring, false, field1, field2, field3,
3900                        field4 | xhci->cmd_ring->cycle_state);
3901        return 0;
3902}
3903
3904/* Queue a slot enable or disable request on the command ring */
3905int xhci_queue_slot_control(struct xhci_hcd *xhci, u32 trb_type, u32 slot_id)
3906{
3907        return queue_command(xhci, 0, 0, 0,
3908                        TRB_TYPE(trb_type) | SLOT_ID_FOR_TRB(slot_id), false);
3909}
3910
3911/* Queue an address device command TRB */
3912int xhci_queue_address_device(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3913                u32 slot_id)
3914{
3915        return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3916                        upper_32_bits(in_ctx_ptr), 0,
3917                        TRB_TYPE(TRB_ADDR_DEV) | SLOT_ID_FOR_TRB(slot_id),
3918                        false);
3919}
3920
3921int xhci_queue_vendor_command(struct xhci_hcd *xhci,
3922                u32 field1, u32 field2, u32 field3, u32 field4)
3923{
3924        return queue_command(xhci, field1, field2, field3, field4, false);
3925}
3926
3927/* Queue a reset device command TRB */
3928int xhci_queue_reset_device(struct xhci_hcd *xhci, u32 slot_id)
3929{
3930        return queue_command(xhci, 0, 0, 0,
3931                        TRB_TYPE(TRB_RESET_DEV) | SLOT_ID_FOR_TRB(slot_id),
3932                        false);
3933}
3934
3935/* Queue a configure endpoint command TRB */
3936int xhci_queue_configure_endpoint(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3937                u32 slot_id, bool command_must_succeed)
3938{
3939        return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3940                        upper_32_bits(in_ctx_ptr), 0,
3941                        TRB_TYPE(TRB_CONFIG_EP) | SLOT_ID_FOR_TRB(slot_id),
3942                        command_must_succeed);
3943}
3944
3945/* Queue an evaluate context command TRB */
3946int xhci_queue_evaluate_context(struct xhci_hcd *xhci, dma_addr_t in_ctx_ptr,
3947                u32 slot_id, bool command_must_succeed)
3948{
3949        return queue_command(xhci, lower_32_bits(in_ctx_ptr),
3950                        upper_32_bits(in_ctx_ptr), 0,
3951                        TRB_TYPE(TRB_EVAL_CONTEXT) | SLOT_ID_FOR_TRB(slot_id),
3952                        command_must_succeed);
3953}
3954
3955/*
3956 * Suspend is set to indicate "Stop Endpoint Command" is being issued to stop
3957 * activity on an endpoint that is about to be suspended.
3958 */
3959int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, int slot_id,
3960                unsigned int ep_index, int suspend)
3961{
3962        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3963        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3964        u32 type = TRB_TYPE(TRB_STOP_RING);
3965        u32 trb_suspend = SUSPEND_PORT_FOR_TRB(suspend);
3966
3967        return queue_command(xhci, 0, 0, 0,
3968                        trb_slot_id | trb_ep_index | type | trb_suspend, false);
3969}
3970
3971/* Set Transfer Ring Dequeue Pointer command.
3972 * This should not be used for endpoints that have streams enabled.
3973 */
3974static int queue_set_tr_deq(struct xhci_hcd *xhci, int slot_id,
3975                unsigned int ep_index, unsigned int stream_id,
3976                struct xhci_segment *deq_seg,
3977                union xhci_trb *deq_ptr, u32 cycle_state)
3978{
3979        dma_addr_t addr;
3980        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
3981        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
3982        u32 trb_stream_id = STREAM_ID_FOR_TRB(stream_id);
3983        u32 type = TRB_TYPE(TRB_SET_DEQ);
3984        struct xhci_virt_ep *ep;
3985
3986        addr = xhci_trb_virt_to_dma(deq_seg, deq_ptr);
3987        if (addr == 0) {
3988                xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3989                xhci_warn(xhci, "WARN deq seg = %p, deq pt = %p\n",
3990                                deq_seg, deq_ptr);
3991                return 0;
3992        }
3993        ep = &xhci->devs[slot_id]->eps[ep_index];
3994        if ((ep->ep_state & SET_DEQ_PENDING)) {
3995                xhci_warn(xhci, "WARN Cannot submit Set TR Deq Ptr\n");
3996                xhci_warn(xhci, "A Set TR Deq Ptr command is pending.\n");
3997                return 0;
3998        }
3999        ep->queued_deq_seg = deq_seg;
4000        ep->queued_deq_ptr = deq_ptr;
4001        return queue_command(xhci, lower_32_bits(addr) | cycle_state,
4002                        upper_32_bits(addr), trb_stream_id,
4003                        trb_slot_id | trb_ep_index | type, false);
4004}
4005
4006int xhci_queue_reset_ep(struct xhci_hcd *xhci, int slot_id,
4007                unsigned int ep_index)
4008{
4009        u32 trb_slot_id = SLOT_ID_FOR_TRB(slot_id);
4010        u32 trb_ep_index = EP_ID_FOR_TRB(ep_index);
4011        u32 type = TRB_TYPE(TRB_RESET_EP);
4012
4013        return queue_command(xhci, 0, 0, 0, trb_slot_id | trb_ep_index | type,
4014                        false);
4015}
4016