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29#include <linux/init.h>
30#include <linux/module.h>
31#include <linux/clk.h>
32#include <linux/err.h>
33#include <linux/io.h>
34#include <linux/platform_device.h>
35#include <linux/dma-mapping.h>
36#include <linux/usb/nop-usb-xceiv.h>
37#include <linux/platform_data/usb-omap.h>
38
39#include "musb_core.h"
40
41
42
43
44
45#define USB_REVISION_REG 0x00
46#define USB_CTRL_REG 0x04
47#define USB_STAT_REG 0x08
48#define USB_EMULATION_REG 0x0c
49
50#define USB_AUTOREQ_REG 0x14
51#define USB_SRP_FIX_TIME_REG 0x18
52#define USB_TEARDOWN_REG 0x1c
53#define EP_INTR_SRC_REG 0x20
54#define EP_INTR_SRC_SET_REG 0x24
55#define EP_INTR_SRC_CLEAR_REG 0x28
56#define EP_INTR_MASK_REG 0x2c
57#define EP_INTR_MASK_SET_REG 0x30
58#define EP_INTR_MASK_CLEAR_REG 0x34
59#define EP_INTR_SRC_MASKED_REG 0x38
60#define CORE_INTR_SRC_REG 0x40
61#define CORE_INTR_SRC_SET_REG 0x44
62#define CORE_INTR_SRC_CLEAR_REG 0x48
63#define CORE_INTR_MASK_REG 0x4c
64#define CORE_INTR_MASK_SET_REG 0x50
65#define CORE_INTR_MASK_CLEAR_REG 0x54
66#define CORE_INTR_SRC_MASKED_REG 0x58
67
68#define USB_END_OF_INTR_REG 0x60
69
70
71#define AM35X_SOFT_RESET_MASK 1
72
73
74#define AM35X_INTR_USB_SHIFT 16
75#define AM35X_INTR_USB_MASK (0x1ff << AM35X_INTR_USB_SHIFT)
76#define AM35X_INTR_DRVVBUS 0x100
77#define AM35X_INTR_RX_SHIFT 16
78#define AM35X_INTR_TX_SHIFT 0
79#define AM35X_TX_EP_MASK 0xffff
80#define AM35X_RX_EP_MASK 0xfffe
81#define AM35X_TX_INTR_MASK (AM35X_TX_EP_MASK << AM35X_INTR_TX_SHIFT)
82#define AM35X_RX_INTR_MASK (AM35X_RX_EP_MASK << AM35X_INTR_RX_SHIFT)
83
84#define USB_MENTOR_CORE_OFFSET 0x400
85
86struct am35x_glue {
87 struct device *dev;
88 struct platform_device *musb;
89 struct clk *phy_clk;
90 struct clk *clk;
91};
92#define glue_to_musb(g) platform_get_drvdata(g->musb)
93
94
95
96
97static void am35x_musb_enable(struct musb *musb)
98{
99 void __iomem *reg_base = musb->ctrl_base;
100 u32 epmask;
101
102
103 epmask = ((musb->epmask & AM35X_TX_EP_MASK) << AM35X_INTR_TX_SHIFT) |
104 ((musb->epmask & AM35X_RX_EP_MASK) << AM35X_INTR_RX_SHIFT);
105
106 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
107 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
108
109
110 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
111 AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT);
112}
113
114
115
116
117static void am35x_musb_disable(struct musb *musb)
118{
119 void __iomem *reg_base = musb->ctrl_base;
120
121 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
122 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
123 AM35X_TX_INTR_MASK | AM35X_RX_INTR_MASK);
124 musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
125 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
126}
127
128#define portstate(stmt) stmt
129
130static void am35x_musb_set_vbus(struct musb *musb, int is_on)
131{
132 WARN_ON(is_on && is_peripheral_active(musb));
133}
134
135#define POLL_SECONDS 2
136
137static struct timer_list otg_workaround;
138
139static void otg_timer(unsigned long _musb)
140{
141 struct musb *musb = (void *)_musb;
142 void __iomem *mregs = musb->mregs;
143 u8 devctl;
144 unsigned long flags;
145
146
147
148
149
150 devctl = musb_readb(mregs, MUSB_DEVCTL);
151 dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
152 usb_otg_state_string(musb->xceiv->state));
153
154 spin_lock_irqsave(&musb->lock, flags);
155 switch (musb->xceiv->state) {
156 case OTG_STATE_A_WAIT_BCON:
157 devctl &= ~MUSB_DEVCTL_SESSION;
158 musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
159
160 devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
161 if (devctl & MUSB_DEVCTL_BDEVICE) {
162 musb->xceiv->state = OTG_STATE_B_IDLE;
163 MUSB_DEV_MODE(musb);
164 } else {
165 musb->xceiv->state = OTG_STATE_A_IDLE;
166 MUSB_HST_MODE(musb);
167 }
168 break;
169 case OTG_STATE_A_WAIT_VFALL:
170 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
171 musb_writel(musb->ctrl_base, CORE_INTR_SRC_SET_REG,
172 MUSB_INTR_VBUSERROR << AM35X_INTR_USB_SHIFT);
173 break;
174 case OTG_STATE_B_IDLE:
175 devctl = musb_readb(mregs, MUSB_DEVCTL);
176 if (devctl & MUSB_DEVCTL_BDEVICE)
177 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
178 else
179 musb->xceiv->state = OTG_STATE_A_IDLE;
180 break;
181 default:
182 break;
183 }
184 spin_unlock_irqrestore(&musb->lock, flags);
185}
186
187static void am35x_musb_try_idle(struct musb *musb, unsigned long timeout)
188{
189 static unsigned long last_timer;
190
191 if (timeout == 0)
192 timeout = jiffies + msecs_to_jiffies(3);
193
194
195 if (musb->is_active || (musb->a_wait_bcon == 0 &&
196 musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
197 dev_dbg(musb->controller, "%s active, deleting timer\n",
198 usb_otg_state_string(musb->xceiv->state));
199 del_timer(&otg_workaround);
200 last_timer = jiffies;
201 return;
202 }
203
204 if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
205 dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
206 return;
207 }
208 last_timer = timeout;
209
210 dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
211 usb_otg_state_string(musb->xceiv->state),
212 jiffies_to_msecs(timeout - jiffies));
213 mod_timer(&otg_workaround, timeout);
214}
215
216static irqreturn_t am35x_musb_interrupt(int irq, void *hci)
217{
218 struct musb *musb = hci;
219 void __iomem *reg_base = musb->ctrl_base;
220 struct device *dev = musb->controller;
221 struct musb_hdrc_platform_data *plat = dev->platform_data;
222 struct omap_musb_board_data *data = plat->board_data;
223 struct usb_otg *otg = musb->xceiv->otg;
224 unsigned long flags;
225 irqreturn_t ret = IRQ_NONE;
226 u32 epintr, usbintr;
227
228 spin_lock_irqsave(&musb->lock, flags);
229
230
231 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_REG);
232
233 if (epintr) {
234 musb_writel(reg_base, EP_INTR_SRC_CLEAR_REG, epintr);
235
236 musb->int_rx =
237 (epintr & AM35X_RX_INTR_MASK) >> AM35X_INTR_RX_SHIFT;
238 musb->int_tx =
239 (epintr & AM35X_TX_INTR_MASK) >> AM35X_INTR_TX_SHIFT;
240 }
241
242
243 usbintr = musb_readl(reg_base, CORE_INTR_SRC_MASKED_REG);
244 if (!usbintr && !epintr)
245 goto eoi;
246
247 if (usbintr) {
248 musb_writel(reg_base, CORE_INTR_SRC_CLEAR_REG, usbintr);
249
250 musb->int_usb =
251 (usbintr & AM35X_INTR_USB_MASK) >> AM35X_INTR_USB_SHIFT;
252 }
253
254
255
256
257
258
259
260
261 if (usbintr & (AM35X_INTR_DRVVBUS << AM35X_INTR_USB_SHIFT)) {
262 int drvvbus = musb_readl(reg_base, USB_STAT_REG);
263 void __iomem *mregs = musb->mregs;
264 u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
265 int err;
266
267 err = musb->int_usb & MUSB_INTR_VBUSERROR;
268 if (err) {
269
270
271
272
273
274
275
276
277
278
279
280 musb->int_usb &= ~MUSB_INTR_VBUSERROR;
281 musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
282 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
283 WARNING("VBUS error workaround (delay coming)\n");
284 } else if (drvvbus) {
285 MUSB_HST_MODE(musb);
286 otg->default_a = 1;
287 musb->xceiv->state = OTG_STATE_A_WAIT_VRISE;
288 portstate(musb->port1_status |= USB_PORT_STAT_POWER);
289 del_timer(&otg_workaround);
290 } else {
291 musb->is_active = 0;
292 MUSB_DEV_MODE(musb);
293 otg->default_a = 0;
294 musb->xceiv->state = OTG_STATE_B_IDLE;
295 portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
296 }
297
298
299 dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
300 drvvbus ? "on" : "off",
301 usb_otg_state_string(musb->xceiv->state),
302 err ? " ERROR" : "",
303 devctl);
304 ret = IRQ_HANDLED;
305 }
306
307
308 if (musb->int_usb & MUSB_INTR_DISCONNECT) {
309 musb->int_tx = 0;
310 musb->int_rx = 0;
311 }
312
313 if (musb->int_tx || musb->int_rx || musb->int_usb)
314 ret |= musb_interrupt(musb);
315
316eoi:
317
318 if (ret == IRQ_HANDLED || epintr || usbintr) {
319
320 if (data->clear_irq)
321 data->clear_irq();
322
323 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
324 }
325
326
327 if (musb->xceiv->state == OTG_STATE_B_IDLE)
328 mod_timer(&otg_workaround, jiffies + POLL_SECONDS * HZ);
329
330 spin_unlock_irqrestore(&musb->lock, flags);
331
332 return ret;
333}
334
335static int am35x_musb_set_mode(struct musb *musb, u8 musb_mode)
336{
337 struct device *dev = musb->controller;
338 struct musb_hdrc_platform_data *plat = dev->platform_data;
339 struct omap_musb_board_data *data = plat->board_data;
340 int retval = 0;
341
342 if (data->set_mode)
343 data->set_mode(musb_mode);
344 else
345 retval = -EIO;
346
347 return retval;
348}
349
350static int am35x_musb_init(struct musb *musb)
351{
352 struct device *dev = musb->controller;
353 struct musb_hdrc_platform_data *plat = dev->platform_data;
354 struct omap_musb_board_data *data = plat->board_data;
355 void __iomem *reg_base = musb->ctrl_base;
356 u32 rev;
357
358 musb->mregs += USB_MENTOR_CORE_OFFSET;
359
360
361 rev = musb_readl(reg_base, USB_REVISION_REG);
362 if (!rev)
363 return -ENODEV;
364
365 usb_nop_xceiv_register();
366 musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
367 if (IS_ERR_OR_NULL(musb->xceiv))
368 return -EPROBE_DEFER;
369
370 setup_timer(&otg_workaround, otg_timer, (unsigned long) musb);
371
372
373 if (data->reset)
374 data->reset();
375
376
377 musb_writel(reg_base, USB_CTRL_REG, AM35X_SOFT_RESET_MASK);
378
379
380 if (data->set_phy_power)
381 data->set_phy_power(1);
382
383 msleep(5);
384
385 musb->isr = am35x_musb_interrupt;
386
387
388 if (data->clear_irq)
389 data->clear_irq();
390
391 return 0;
392}
393
394static int am35x_musb_exit(struct musb *musb)
395{
396 struct device *dev = musb->controller;
397 struct musb_hdrc_platform_data *plat = dev->platform_data;
398 struct omap_musb_board_data *data = plat->board_data;
399
400 del_timer_sync(&otg_workaround);
401
402
403 if (data->set_phy_power)
404 data->set_phy_power(0);
405
406 usb_put_phy(musb->xceiv);
407 usb_nop_xceiv_unregister();
408
409 return 0;
410}
411
412
413void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
414{
415 void __iomem *fifo = hw_ep->fifo;
416 u32 val;
417 int i;
418
419
420 if (likely((0x03 & (unsigned long) dst) == 0) && len >= 4) {
421 readsl(fifo, dst, len >> 2);
422 dst += len & ~0x03;
423 len &= 0x03;
424 }
425
426
427
428
429 if (len > 4) {
430 for (i = 0; i < (len >> 2); i++) {
431 *(u32 *) dst = musb_readl(fifo, 0);
432 dst += 4;
433 }
434 len &= 0x03;
435 }
436 if (len > 0) {
437 val = musb_readl(fifo, 0);
438 memcpy(dst, &val, len);
439 }
440}
441
442static const struct musb_platform_ops am35x_ops = {
443 .init = am35x_musb_init,
444 .exit = am35x_musb_exit,
445
446 .enable = am35x_musb_enable,
447 .disable = am35x_musb_disable,
448
449 .set_mode = am35x_musb_set_mode,
450 .try_idle = am35x_musb_try_idle,
451
452 .set_vbus = am35x_musb_set_vbus,
453};
454
455static u64 am35x_dmamask = DMA_BIT_MASK(32);
456
457static int am35x_probe(struct platform_device *pdev)
458{
459 struct musb_hdrc_platform_data *pdata = pdev->dev.platform_data;
460 struct platform_device *musb;
461 struct am35x_glue *glue;
462
463 struct clk *phy_clk;
464 struct clk *clk;
465
466 int ret = -ENOMEM;
467
468 glue = kzalloc(sizeof(*glue), GFP_KERNEL);
469 if (!glue) {
470 dev_err(&pdev->dev, "failed to allocate glue context\n");
471 goto err0;
472 }
473
474 musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
475 if (!musb) {
476 dev_err(&pdev->dev, "failed to allocate musb device\n");
477 goto err1;
478 }
479
480 phy_clk = clk_get(&pdev->dev, "fck");
481 if (IS_ERR(phy_clk)) {
482 dev_err(&pdev->dev, "failed to get PHY clock\n");
483 ret = PTR_ERR(phy_clk);
484 goto err3;
485 }
486
487 clk = clk_get(&pdev->dev, "ick");
488 if (IS_ERR(clk)) {
489 dev_err(&pdev->dev, "failed to get clock\n");
490 ret = PTR_ERR(clk);
491 goto err4;
492 }
493
494 ret = clk_enable(phy_clk);
495 if (ret) {
496 dev_err(&pdev->dev, "failed to enable PHY clock\n");
497 goto err5;
498 }
499
500 ret = clk_enable(clk);
501 if (ret) {
502 dev_err(&pdev->dev, "failed to enable clock\n");
503 goto err6;
504 }
505
506 musb->dev.parent = &pdev->dev;
507 musb->dev.dma_mask = &am35x_dmamask;
508 musb->dev.coherent_dma_mask = am35x_dmamask;
509
510 glue->dev = &pdev->dev;
511 glue->musb = musb;
512 glue->phy_clk = phy_clk;
513 glue->clk = clk;
514
515 pdata->platform_ops = &am35x_ops;
516
517 platform_set_drvdata(pdev, glue);
518
519 ret = platform_device_add_resources(musb, pdev->resource,
520 pdev->num_resources);
521 if (ret) {
522 dev_err(&pdev->dev, "failed to add resources\n");
523 goto err7;
524 }
525
526 ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
527 if (ret) {
528 dev_err(&pdev->dev, "failed to add platform_data\n");
529 goto err7;
530 }
531
532 ret = platform_device_add(musb);
533 if (ret) {
534 dev_err(&pdev->dev, "failed to register musb device\n");
535 goto err7;
536 }
537
538 return 0;
539
540err7:
541 clk_disable(clk);
542
543err6:
544 clk_disable(phy_clk);
545
546err5:
547 clk_put(clk);
548
549err4:
550 clk_put(phy_clk);
551
552err3:
553 platform_device_put(musb);
554
555err1:
556 kfree(glue);
557
558err0:
559 return ret;
560}
561
562static int am35x_remove(struct platform_device *pdev)
563{
564 struct am35x_glue *glue = platform_get_drvdata(pdev);
565
566 platform_device_unregister(glue->musb);
567 clk_disable(glue->clk);
568 clk_disable(glue->phy_clk);
569 clk_put(glue->clk);
570 clk_put(glue->phy_clk);
571 kfree(glue);
572
573 return 0;
574}
575
576#ifdef CONFIG_PM
577static int am35x_suspend(struct device *dev)
578{
579 struct am35x_glue *glue = dev_get_drvdata(dev);
580 struct musb_hdrc_platform_data *plat = dev->platform_data;
581 struct omap_musb_board_data *data = plat->board_data;
582
583
584 if (data->set_phy_power)
585 data->set_phy_power(0);
586
587 clk_disable(glue->phy_clk);
588 clk_disable(glue->clk);
589
590 return 0;
591}
592
593static int am35x_resume(struct device *dev)
594{
595 struct am35x_glue *glue = dev_get_drvdata(dev);
596 struct musb_hdrc_platform_data *plat = dev->platform_data;
597 struct omap_musb_board_data *data = plat->board_data;
598 int ret;
599
600
601 if (data->set_phy_power)
602 data->set_phy_power(1);
603
604 ret = clk_enable(glue->phy_clk);
605 if (ret) {
606 dev_err(dev, "failed to enable PHY clock\n");
607 return ret;
608 }
609
610 ret = clk_enable(glue->clk);
611 if (ret) {
612 dev_err(dev, "failed to enable clock\n");
613 return ret;
614 }
615
616 return 0;
617}
618
619static struct dev_pm_ops am35x_pm_ops = {
620 .suspend = am35x_suspend,
621 .resume = am35x_resume,
622};
623
624#define DEV_PM_OPS &am35x_pm_ops
625#else
626#define DEV_PM_OPS NULL
627#endif
628
629static struct platform_driver am35x_driver = {
630 .probe = am35x_probe,
631 .remove = am35x_remove,
632 .driver = {
633 .name = "musb-am35x",
634 .pm = DEV_PM_OPS,
635 },
636};
637
638MODULE_DESCRIPTION("AM35x MUSB Glue Layer");
639MODULE_AUTHOR("Ajay Kumar Gupta <ajay.gupta@ti.com>");
640MODULE_LICENSE("GPL v2");
641module_platform_driver(am35x_driver);
642