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23#include <linux/device.h>
24#include <linux/module.h>
25#include <linux/kernel.h>
26#include <linux/errno.h>
27#include <linux/string.h>
28#include <linux/mm.h>
29#include <linux/fb.h>
30#include <linux/init.h>
31#include <linux/dma-mapping.h>
32#include <linux/of_device.h>
33#include <linux/of_platform.h>
34#include <linux/of_address.h>
35#include <linux/io.h>
36#include <linux/xilinxfb.h>
37#include <linux/slab.h>
38
39#ifdef CONFIG_PPC_DCR
40#include <asm/dcr.h>
41#endif
42
43#define DRIVER_NAME "xilinxfb"
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63#define NUM_REGS 2
64#define REG_FB_ADDR 0
65#define REG_CTRL 1
66#define REG_CTRL_ENABLE 0x0001
67#define REG_CTRL_ROTATE 0x0002
68
69
70
71
72
73
74
75
76
77
78#define BYTES_PER_PIXEL 4
79#define BITS_PER_PIXEL (BYTES_PER_PIXEL * 8)
80
81#define RED_SHIFT 16
82#define GREEN_SHIFT 8
83#define BLUE_SHIFT 0
84
85#define PALETTE_ENTRIES_NO 16
86
87
88
89
90static struct xilinxfb_platform_data xilinx_fb_default_pdata = {
91 .xres = 640,
92 .yres = 480,
93 .xvirt = 1024,
94 .yvirt = 480,
95};
96
97
98
99
100static struct fb_fix_screeninfo xilinx_fb_fix = {
101 .id = "Xilinx",
102 .type = FB_TYPE_PACKED_PIXELS,
103 .visual = FB_VISUAL_TRUECOLOR,
104 .accel = FB_ACCEL_NONE
105};
106
107static struct fb_var_screeninfo xilinx_fb_var = {
108 .bits_per_pixel = BITS_PER_PIXEL,
109
110 .red = { RED_SHIFT, 8, 0 },
111 .green = { GREEN_SHIFT, 8, 0 },
112 .blue = { BLUE_SHIFT, 8, 0 },
113 .transp = { 0, 0, 0 },
114
115 .activate = FB_ACTIVATE_NOW
116};
117
118
119#define BUS_ACCESS_FLAG 0x1
120#define LITTLE_ENDIAN_ACCESS 0x2
121
122struct xilinxfb_drvdata {
123
124 struct fb_info info;
125
126 phys_addr_t regs_phys;
127
128 void __iomem *regs;
129
130#ifdef CONFIG_PPC_DCR
131 dcr_host_t dcr_host;
132 unsigned int dcr_len;
133#endif
134 void *fb_virt;
135 dma_addr_t fb_phys;
136 int fb_alloced;
137
138 u8 flags;
139
140 u32 reg_ctrl_default;
141
142 u32 pseudo_palette[PALETTE_ENTRIES_NO];
143
144};
145
146#define to_xilinxfb_drvdata(_info) \
147 container_of(_info, struct xilinxfb_drvdata, info)
148
149
150
151
152
153
154static void xilinx_fb_out32(struct xilinxfb_drvdata *drvdata, u32 offset,
155 u32 val)
156{
157 if (drvdata->flags & BUS_ACCESS_FLAG) {
158 if (drvdata->flags & LITTLE_ENDIAN_ACCESS)
159 iowrite32(val, drvdata->regs + (offset << 2));
160 else
161 iowrite32be(val, drvdata->regs + (offset << 2));
162 }
163#ifdef CONFIG_PPC_DCR
164 else
165 dcr_write(drvdata->dcr_host, offset, val);
166#endif
167}
168
169static u32 xilinx_fb_in32(struct xilinxfb_drvdata *drvdata, u32 offset)
170{
171 if (drvdata->flags & BUS_ACCESS_FLAG) {
172 if (drvdata->flags & LITTLE_ENDIAN_ACCESS)
173 return ioread32(drvdata->regs + (offset << 2));
174 else
175 return ioread32be(drvdata->regs + (offset << 2));
176 }
177#ifdef CONFIG_PPC_DCR
178 else
179 return dcr_read(drvdata->dcr_host, offset);
180#endif
181 return 0;
182}
183
184static int
185xilinx_fb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
186 unsigned transp, struct fb_info *fbi)
187{
188 u32 *palette = fbi->pseudo_palette;
189
190 if (regno >= PALETTE_ENTRIES_NO)
191 return -EINVAL;
192
193 if (fbi->var.grayscale) {
194
195
196 red = green = blue =
197 (red * 77 + green * 151 + blue * 28 + 127) >> 8;
198 }
199
200
201
202
203 red >>= 8;
204 green >>= 8;
205 blue >>= 8;
206 palette[regno] = (red << RED_SHIFT) | (green << GREEN_SHIFT) |
207 (blue << BLUE_SHIFT);
208
209 return 0;
210}
211
212static int
213xilinx_fb_blank(int blank_mode, struct fb_info *fbi)
214{
215 struct xilinxfb_drvdata *drvdata = to_xilinxfb_drvdata(fbi);
216
217 switch (blank_mode) {
218 case FB_BLANK_UNBLANK:
219
220 xilinx_fb_out32(drvdata, REG_CTRL, drvdata->reg_ctrl_default);
221 break;
222
223 case FB_BLANK_NORMAL:
224 case FB_BLANK_VSYNC_SUSPEND:
225 case FB_BLANK_HSYNC_SUSPEND:
226 case FB_BLANK_POWERDOWN:
227
228 xilinx_fb_out32(drvdata, REG_CTRL, 0);
229 default:
230 break;
231
232 }
233 return 0;
234}
235
236static struct fb_ops xilinxfb_ops =
237{
238 .owner = THIS_MODULE,
239 .fb_setcolreg = xilinx_fb_setcolreg,
240 .fb_blank = xilinx_fb_blank,
241 .fb_fillrect = cfb_fillrect,
242 .fb_copyarea = cfb_copyarea,
243 .fb_imageblit = cfb_imageblit,
244};
245
246
247
248
249
250static int xilinxfb_assign(struct platform_device *pdev,
251 struct xilinxfb_drvdata *drvdata,
252 struct xilinxfb_platform_data *pdata)
253{
254 int rc;
255 struct device *dev = &pdev->dev;
256 int fbsize = pdata->xvirt * pdata->yvirt * BYTES_PER_PIXEL;
257
258 if (drvdata->flags & BUS_ACCESS_FLAG) {
259 struct resource *res;
260
261 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
262 drvdata->regs_phys = res->start;
263 drvdata->regs = devm_request_and_ioremap(&pdev->dev, res);
264 if (!drvdata->regs) {
265 rc = -EADDRNOTAVAIL;
266 goto err_region;
267 }
268 }
269
270
271 if (pdata->fb_phys) {
272 drvdata->fb_phys = pdata->fb_phys;
273 drvdata->fb_virt = ioremap(pdata->fb_phys, fbsize);
274 } else {
275 drvdata->fb_alloced = 1;
276 drvdata->fb_virt = dma_alloc_coherent(dev, PAGE_ALIGN(fbsize),
277 &drvdata->fb_phys, GFP_KERNEL);
278 }
279
280 if (!drvdata->fb_virt) {
281 dev_err(dev, "Could not allocate frame buffer memory\n");
282 rc = -ENOMEM;
283 if (drvdata->flags & BUS_ACCESS_FLAG)
284 goto err_fbmem;
285 else
286 goto err_region;
287 }
288
289
290 memset_io((void __iomem *)drvdata->fb_virt, 0, fbsize);
291
292
293 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
294 rc = xilinx_fb_in32(drvdata, REG_FB_ADDR);
295
296 if (rc != drvdata->fb_phys) {
297 drvdata->flags |= LITTLE_ENDIAN_ACCESS;
298 xilinx_fb_out32(drvdata, REG_FB_ADDR, drvdata->fb_phys);
299 }
300
301
302 drvdata->reg_ctrl_default = REG_CTRL_ENABLE;
303 if (pdata->rotate_screen)
304 drvdata->reg_ctrl_default |= REG_CTRL_ROTATE;
305 xilinx_fb_out32(drvdata, REG_CTRL,
306 drvdata->reg_ctrl_default);
307
308
309 drvdata->info.device = dev;
310 drvdata->info.screen_base = (void __iomem *)drvdata->fb_virt;
311 drvdata->info.fbops = &xilinxfb_ops;
312 drvdata->info.fix = xilinx_fb_fix;
313 drvdata->info.fix.smem_start = drvdata->fb_phys;
314 drvdata->info.fix.smem_len = fbsize;
315 drvdata->info.fix.line_length = pdata->xvirt * BYTES_PER_PIXEL;
316
317 drvdata->info.pseudo_palette = drvdata->pseudo_palette;
318 drvdata->info.flags = FBINFO_DEFAULT;
319 drvdata->info.var = xilinx_fb_var;
320 drvdata->info.var.height = pdata->screen_height_mm;
321 drvdata->info.var.width = pdata->screen_width_mm;
322 drvdata->info.var.xres = pdata->xres;
323 drvdata->info.var.yres = pdata->yres;
324 drvdata->info.var.xres_virtual = pdata->xvirt;
325 drvdata->info.var.yres_virtual = pdata->yvirt;
326
327
328 rc = fb_alloc_cmap(&drvdata->info.cmap, PALETTE_ENTRIES_NO, 0);
329 if (rc) {
330 dev_err(dev, "Fail to allocate colormap (%d entries)\n",
331 PALETTE_ENTRIES_NO);
332 goto err_cmap;
333 }
334
335
336 rc = register_framebuffer(&drvdata->info);
337 if (rc) {
338 dev_err(dev, "Could not register frame buffer\n");
339 goto err_regfb;
340 }
341
342 if (drvdata->flags & BUS_ACCESS_FLAG) {
343
344 dev_dbg(dev, "regs: phys=%pa, virt=%p\n",
345 &drvdata->regs_phys, drvdata->regs);
346 }
347
348 dev_dbg(dev, "fb: phys=%llx, virt=%p, size=%x\n",
349 (unsigned long long)drvdata->fb_phys, drvdata->fb_virt, fbsize);
350
351 return 0;
352
353err_regfb:
354 fb_dealloc_cmap(&drvdata->info.cmap);
355
356err_cmap:
357 if (drvdata->fb_alloced)
358 dma_free_coherent(dev, PAGE_ALIGN(fbsize), drvdata->fb_virt,
359 drvdata->fb_phys);
360 else
361 iounmap(drvdata->fb_virt);
362
363
364 xilinx_fb_out32(drvdata, REG_CTRL, 0);
365
366err_fbmem:
367 if (drvdata->flags & BUS_ACCESS_FLAG)
368 devm_iounmap(dev, drvdata->regs);
369
370err_region:
371 kfree(drvdata);
372 dev_set_drvdata(dev, NULL);
373
374 return rc;
375}
376
377static int xilinxfb_release(struct device *dev)
378{
379 struct xilinxfb_drvdata *drvdata = dev_get_drvdata(dev);
380
381#if !defined(CONFIG_FRAMEBUFFER_CONSOLE) && defined(CONFIG_LOGO)
382 xilinx_fb_blank(VESA_POWERDOWN, &drvdata->info);
383#endif
384
385 unregister_framebuffer(&drvdata->info);
386
387 fb_dealloc_cmap(&drvdata->info.cmap);
388
389 if (drvdata->fb_alloced)
390 dma_free_coherent(dev, PAGE_ALIGN(drvdata->info.fix.smem_len),
391 drvdata->fb_virt, drvdata->fb_phys);
392 else
393 iounmap(drvdata->fb_virt);
394
395
396 xilinx_fb_out32(drvdata, REG_CTRL, 0);
397
398
399 if (drvdata->flags & BUS_ACCESS_FLAG)
400 devm_iounmap(dev, drvdata->regs);
401#ifdef CONFIG_PPC_DCR
402 else
403 dcr_unmap(drvdata->dcr_host, drvdata->dcr_len);
404#endif
405
406 kfree(drvdata);
407 dev_set_drvdata(dev, NULL);
408
409 return 0;
410}
411
412
413
414
415
416static int xilinxfb_of_probe(struct platform_device *op)
417{
418 const u32 *prop;
419 u32 tft_access = 0;
420 struct xilinxfb_platform_data pdata;
421 int size;
422 struct xilinxfb_drvdata *drvdata;
423
424
425 pdata = xilinx_fb_default_pdata;
426
427
428 drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
429 if (!drvdata) {
430 dev_err(&op->dev, "Couldn't allocate device private record\n");
431 return -ENOMEM;
432 }
433
434
435
436
437
438 of_property_read_u32(op->dev.of_node, "xlnx,dcr-splb-slave-if",
439 &tft_access);
440
441
442
443
444
445 if (tft_access) {
446 drvdata->flags |= BUS_ACCESS_FLAG;
447 }
448#ifdef CONFIG_PPC_DCR
449 else {
450 int start;
451 start = dcr_resource_start(op->dev.of_node, 0);
452 drvdata->dcr_len = dcr_resource_len(op->dev.of_node, 0);
453 drvdata->dcr_host = dcr_map(op->dev.of_node, start, drvdata->dcr_len);
454 if (!DCR_MAP_OK(drvdata->dcr_host)) {
455 dev_err(&op->dev, "invalid DCR address\n");
456 kfree(drvdata);
457 return -ENODEV;
458 }
459 }
460#endif
461
462 prop = of_get_property(op->dev.of_node, "phys-size", &size);
463 if ((prop) && (size >= sizeof(u32)*2)) {
464 pdata.screen_width_mm = prop[0];
465 pdata.screen_height_mm = prop[1];
466 }
467
468 prop = of_get_property(op->dev.of_node, "resolution", &size);
469 if ((prop) && (size >= sizeof(u32)*2)) {
470 pdata.xres = prop[0];
471 pdata.yres = prop[1];
472 }
473
474 prop = of_get_property(op->dev.of_node, "virtual-resolution", &size);
475 if ((prop) && (size >= sizeof(u32)*2)) {
476 pdata.xvirt = prop[0];
477 pdata.yvirt = prop[1];
478 }
479
480 if (of_find_property(op->dev.of_node, "rotate-display", NULL))
481 pdata.rotate_screen = 1;
482
483 dev_set_drvdata(&op->dev, drvdata);
484 return xilinxfb_assign(op, drvdata, &pdata);
485}
486
487static int xilinxfb_of_remove(struct platform_device *op)
488{
489 return xilinxfb_release(&op->dev);
490}
491
492
493static struct of_device_id xilinxfb_of_match[] = {
494 { .compatible = "xlnx,xps-tft-1.00.a", },
495 { .compatible = "xlnx,xps-tft-2.00.a", },
496 { .compatible = "xlnx,xps-tft-2.01.a", },
497 { .compatible = "xlnx,plb-tft-cntlr-ref-1.00.a", },
498 { .compatible = "xlnx,plb-dvi-cntlr-ref-1.00.c", },
499 {},
500};
501MODULE_DEVICE_TABLE(of, xilinxfb_of_match);
502
503static struct platform_driver xilinxfb_of_driver = {
504 .probe = xilinxfb_of_probe,
505 .remove = xilinxfb_of_remove,
506 .driver = {
507 .name = DRIVER_NAME,
508 .owner = THIS_MODULE,
509 .of_match_table = xilinxfb_of_match,
510 },
511};
512
513module_platform_driver(xilinxfb_of_driver);
514
515MODULE_AUTHOR("MontaVista Software, Inc. <source@mvista.com>");
516MODULE_DESCRIPTION("Xilinx TFT frame buffer driver");
517MODULE_LICENSE("GPL");
518