LXR linux/include/linux/mfd/ti_am335x

   1#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
   2#define __LINUX_TI_AM335X_TSCADC_MFD_H
   3
   4/*
   5 * TI Touch Screen / ADC MFD driver
   6 *
   7 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
   8 *
   9 * This program is free software; you can redistribute it and/or
  10 * modify it under the terms of the GNU General Public License as
  11 * published by the Free Software Foundation version 2.
  12 *
  13 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  14 * kind, whether express or implied; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 */
  18
  19#include <linux/mfd/core.h>
  20
  21#define REG_RAWIRQSTATUS        0x024
  22#define REG_IRQSTATUS           0x028
  23#define REG_IRQENABLE           0x02C
  24#define REG_IRQCLR              0x030
  25#define REG_IRQWAKEUP           0x034
  26#define REG_CTRL                0x040
  27#define REG_ADCFSM              0x044
  28#define REG_CLKDIV              0x04C
  29#define REG_SE                  0x054
  30#define REG_IDLECONFIG          0x058
  31#define REG_CHARGECONFIG        0x05C
  32#define REG_CHARGEDELAY         0x060
  33#define REG_STEPCONFIG(n)       (0x64 + ((n) * 8))
  34#define REG_STEPDELAY(n)        (0x68 + ((n) * 8))
  35#define REG_FIFO0CNT            0xE4
  36#define REG_FIFO0THR            0xE8
  37#define REG_FIFO1CNT            0xF0
  38#define REG_FIFO1THR            0xF4
  39#define REG_FIFO0               0x100
  40#define REG_FIFO1               0x200
  41
  42/*      Register Bitfields      */
  43/* IRQ wakeup enable */
  44#define IRQWKUP_ENB             BIT(0)
  45
  46/* Step Enable */
  47#define STEPENB_MASK            (0x1FFFF << 0)
  48#define STEPENB(val)            ((val) << 0)
  49
  50/* IRQ enable */
  51#define IRQENB_HW_PEN           BIT(0)
  52#define IRQENB_FIFO0THRES       BIT(2)
  53#define IRQENB_FIFO1THRES       BIT(5)
  54#define IRQENB_PENUP            BIT(9)
  55
  56/* Step Configuration */
  57#define STEPCONFIG_MODE_MASK    (3 << 0)
  58#define STEPCONFIG_MODE(val)    ((val) << 0)
  59#define STEPCONFIG_MODE_HWSYNC  STEPCONFIG_MODE(2)
  60#define STEPCONFIG_AVG_MASK     (7 << 2)
  61#define STEPCONFIG_AVG(val)     ((val) << 2)
  62#define STEPCONFIG_AVG_16       STEPCONFIG_AVG(4)
  63#define STEPCONFIG_XPP          BIT(5)
  64#define STEPCONFIG_XNN          BIT(6)
  65#define STEPCONFIG_YPP          BIT(7)
  66#define STEPCONFIG_YNN          BIT(8)
  67#define STEPCONFIG_XNP          BIT(9)
  68#define STEPCONFIG_YPN          BIT(10)
  69#define STEPCONFIG_INM_MASK     (0xF << 15)
  70#define STEPCONFIG_INM(val)     ((val) << 15)
  71#define STEPCONFIG_INM_ADCREFM  STEPCONFIG_INM(8)
  72#define STEPCONFIG_INP_MASK     (0xF << 19)
  73#define STEPCONFIG_INP(val)     ((val) << 19)
  74#define STEPCONFIG_INP_AN4      STEPCONFIG_INP(4)
  75#define STEPCONFIG_INP_ADCREFM  STEPCONFIG_INP(8)
  76#define STEPCONFIG_FIFO1        BIT(26)
  77
  78/* Delay register */
  79#define STEPDELAY_OPEN_MASK     (0x3FFFF << 0)
  80#define STEPDELAY_OPEN(val)     ((val) << 0)
  81#define STEPCONFIG_OPENDLY      STEPDELAY_OPEN(0x098)
  82#define STEPDELAY_SAMPLE_MASK   (0xFF << 24)
  83#define STEPDELAY_SAMPLE(val)   ((val) << 24)
  84#define STEPCONFIG_SAMPLEDLY    STEPDELAY_SAMPLE(0)
  85
  86/* Charge Config */
  87#define STEPCHARGE_RFP_MASK     (7 << 12)
  88#define STEPCHARGE_RFP(val)     ((val) << 12)
  89#define STEPCHARGE_RFP_XPUL     STEPCHARGE_RFP(1)
  90#define STEPCHARGE_INM_MASK     (0xF << 15)
  91#define STEPCHARGE_INM(val)     ((val) << 15)
  92#define STEPCHARGE_INM_AN1      STEPCHARGE_INM(1)
  93#define STEPCHARGE_INP_MASK     (0xF << 19)
  94#define STEPCHARGE_INP(val)     ((val) << 19)
  95#define STEPCHARGE_RFM_MASK     (3 << 23)
  96#define STEPCHARGE_RFM(val)     ((val) << 23)
  97#define STEPCHARGE_RFM_XNUR     STEPCHARGE_RFM(1)
  98
  99/* Charge delay */
 100#define CHARGEDLY_OPEN_MASK     (0x3FFFF << 0)
 101#define CHARGEDLY_OPEN(val)     ((val) << 0)
 102#define CHARGEDLY_OPENDLY       CHARGEDLY_OPEN(1)
 103
 104/* Control register */
 105#define CNTRLREG_TSCSSENB       BIT(0)
 106#define CNTRLREG_STEPID         BIT(1)
 107#define CNTRLREG_STEPCONFIGWRT  BIT(2)
 108#define CNTRLREG_POWERDOWN      BIT(4)
 109#define CNTRLREG_AFE_CTRL_MASK  (3 << 5)
 110#define CNTRLREG_AFE_CTRL(val)  ((val) << 5)
 111#define CNTRLREG_4WIRE          CNTRLREG_AFE_CTRL(1)
 112#define CNTRLREG_5WIRE          CNTRLREG_AFE_CTRL(2)
 113#define CNTRLREG_8WIRE          CNTRLREG_AFE_CTRL(3)
 114#define CNTRLREG_TSCENB         BIT(7)
 115
 116/* FIFO READ Register */
 117#define FIFOREAD_DATA_MASK (0xfff << 0)
 118#define FIFOREAD_CHNLID_MASK (0xf << 16)
 119
 120/* Sequencer Status */
 121#define SEQ_STATUS BIT(5)
 122
 123#define ADC_CLK                 3000000
 124#define MAX_CLK_DIV             7
 125#define TOTAL_STEPS             16
 126#define TOTAL_CHANNELS          8
 127
 128/*
 129* ADC runs at 3MHz, and it takes
 130* 15 cycles to latch one data output.
 131* Hence the idle time for ADC to
 132* process one sample data would be
 133* around 5 micro seconds.
 134*/
 135#define IDLE_TIMEOUT 5 /* microsec */
 136
 137#define TSCADC_CELLS            2
 138
 139struct ti_tscadc_dev {
 140        struct device *dev;
 141        struct regmap *regmap_tscadc;
 142        void __iomem *tscadc_base;
 143        int irq;
 144        int used_cells; /* 1-2 */
 145        int tsc_cell;   /* -1 if not used */
 146        int adc_cell;   /* -1 if not used */
 147        struct mfd_cell cells[TSCADC_CELLS];
 148        u32 reg_se_cache;
 149        spinlock_t reg_lock;
 150
 151        /* tsc device */
 152        struct titsc *tsc;
 153
 154        /* adc device */
 155        struct adc_device *adc;
 156};
 157
 158static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p)
 159{
 160        struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data;
 161
 162        return *tscadc_dev;
 163}
 164
 165void am335x_tsc_se_update(struct ti_tscadc_dev *tsadc);
 166void am335x_tsc_se_set(struct ti_tscadc_dev *tsadc, u32 val);
 167void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
 168
 169#endif
 170