LXR linux/include/linux/mfd/twl6040.h

   1/*
   2 * MFD driver for twl6040
   3 *
   4 * Authors:     Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
   5 *              Misael Lopez Cruz <misael.lopez@ti.com>
   6 *
   7 * Copyright:   (C) 2011 Texas Instruments, Inc.
   8 *
   9 * This program is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License version 2 as
  11 * published by the Free Software Foundation.
  12 *
  13 * This program is distributed in the hope that it will be useful, but
  14 * WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16 * General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21 * 02110-1301 USA
  22 *
  23 */
  24
  25#ifndef __TWL6040_CODEC_H__
  26#define __TWL6040_CODEC_H__
  27
  28#include <linux/interrupt.h>
  29#include <linux/mfd/core.h>
  30#include <linux/regulator/consumer.h>
  31
  32#define TWL6040_REG_ASICID              0x01
  33#define TWL6040_REG_ASICREV             0x02
  34#define TWL6040_REG_INTID               0x03
  35#define TWL6040_REG_INTMR               0x04
  36#define TWL6040_REG_NCPCTL              0x05
  37#define TWL6040_REG_LDOCTL              0x06
  38#define TWL6040_REG_HPPLLCTL            0x07
  39#define TWL6040_REG_LPPLLCTL            0x08
  40#define TWL6040_REG_LPPLLDIV            0x09
  41#define TWL6040_REG_AMICBCTL            0x0A
  42#define TWL6040_REG_DMICBCTL            0x0B
  43#define TWL6040_REG_MICLCTL             0x0C
  44#define TWL6040_REG_MICRCTL             0x0D
  45#define TWL6040_REG_MICGAIN             0x0E
  46#define TWL6040_REG_LINEGAIN            0x0F
  47#define TWL6040_REG_HSLCTL              0x10
  48#define TWL6040_REG_HSRCTL              0x11
  49#define TWL6040_REG_HSGAIN              0x12
  50#define TWL6040_REG_EARCTL              0x13
  51#define TWL6040_REG_HFLCTL              0x14
  52#define TWL6040_REG_HFLGAIN             0x15
  53#define TWL6040_REG_HFRCTL              0x16
  54#define TWL6040_REG_HFRGAIN             0x17
  55#define TWL6040_REG_VIBCTLL             0x18
  56#define TWL6040_REG_VIBDATL             0x19
  57#define TWL6040_REG_VIBCTLR             0x1A
  58#define TWL6040_REG_VIBDATR             0x1B
  59#define TWL6040_REG_HKCTL1              0x1C
  60#define TWL6040_REG_HKCTL2              0x1D
  61#define TWL6040_REG_GPOCTL              0x1E
  62#define TWL6040_REG_ALB                 0x1F
  63#define TWL6040_REG_DLB                 0x20
  64#define TWL6040_REG_TRIM1               0x28
  65#define TWL6040_REG_TRIM2               0x29
  66#define TWL6040_REG_TRIM3               0x2A
  67#define TWL6040_REG_HSOTRIM             0x2B
  68#define TWL6040_REG_HFOTRIM             0x2C
  69#define TWL6040_REG_ACCCTL              0x2D
  70#define TWL6040_REG_STATUS              0x2E
  71
  72/* INTID (0x03) fields */
  73
  74#define TWL6040_THINT                   0x01
  75#define TWL6040_PLUGINT                 0x02
  76#define TWL6040_UNPLUGINT               0x04
  77#define TWL6040_HOOKINT                 0x08
  78#define TWL6040_HFINT                   0x10
  79#define TWL6040_VIBINT                  0x20
  80#define TWL6040_READYINT                0x40
  81
  82/* INTMR (0x04) fields */
  83
  84#define TWL6040_THMSK                   0x01
  85#define TWL6040_PLUGMSK                 0x02
  86#define TWL6040_HOOKMSK                 0x08
  87#define TWL6040_HFMSK                   0x10
  88#define TWL6040_VIBMSK                  0x20
  89#define TWL6040_READYMSK                0x40
  90#define TWL6040_ALLINT_MSK              0x7B
  91
  92/* NCPCTL (0x05) fields */
  93
  94#define TWL6040_NCPENA                  0x01
  95#define TWL6040_NCPOPEN                 0x40
  96
  97/* LDOCTL (0x06) fields */
  98
  99#define TWL6040_LSLDOENA                0x01
 100#define TWL6040_HSLDOENA                0x04
 101#define TWL6040_REFENA                  0x40
 102#define TWL6040_OSCENA                  0x80
 103
 104/* HPPLLCTL (0x07) fields */
 105
 106#define TWL6040_HPLLENA                 0x01
 107#define TWL6040_HPLLRST                 0x02
 108#define TWL6040_HPLLBP                  0x04
 109#define TWL6040_HPLLSQRENA              0x08
 110#define TWL6040_MCLK_12000KHZ           (0 << 5)
 111#define TWL6040_MCLK_19200KHZ           (1 << 5)
 112#define TWL6040_MCLK_26000KHZ           (2 << 5)
 113#define TWL6040_MCLK_38400KHZ           (3 << 5)
 114#define TWL6040_MCLK_MSK                0x60
 115
 116/* LPPLLCTL (0x08) fields */
 117
 118#define TWL6040_LPLLENA                 0x01
 119#define TWL6040_LPLLRST                 0x02
 120#define TWL6040_LPLLSEL                 0x04
 121#define TWL6040_LPLLFIN                 0x08
 122#define TWL6040_HPLLSEL                 0x10
 123
 124/* HSLCTL/R (0x10/0x11) fields */
 125
 126#define TWL6040_HSDACENA                (1 << 0)
 127#define TWL6040_HSDACMODE               (1 << 1)
 128#define TWL6040_HSDRVENA                (1 << 2)
 129#define TWL6040_HSDRVMODE               (1 << 3)
 130
 131/* HFLCTL/R (0x14/0x16) fields */
 132
 133#define TWL6040_HFDACENA                (1 << 0)
 134#define TWL6040_HFPGAENA                (1 << 1)
 135#define TWL6040_HFDRVENA                (1 << 4)
 136
 137/* VIBCTLL/R (0x18/0x1A) fields */
 138
 139#define TWL6040_VIBENA                  (1 << 0)
 140#define TWL6040_VIBSEL                  (1 << 1)
 141#define TWL6040_VIBCTRL                 (1 << 2)
 142#define TWL6040_VIBCTRL_P               (1 << 3)
 143#define TWL6040_VIBCTRL_N               (1 << 4)
 144
 145/* VIBDATL/R (0x19/0x1B) fields */
 146
 147#define TWL6040_VIBDAT_MAX              0x64
 148
 149/* GPOCTL (0x1E) fields */
 150
 151#define TWL6040_GPO1                    0x01
 152#define TWL6040_GPO2                    0x02
 153#define TWL6040_GPO3                    0x04
 154
 155/* ACCCTL (0x2D) fields */
 156
 157#define TWL6040_I2CSEL                  0x01
 158#define TWL6040_RESETSPLIT              0x04
 159#define TWL6040_INTCLRMODE              0x08
 160
 161/* STATUS (0x2E) fields */
 162
 163#define TWL6040_PLUGCOMP                0x02
 164#define TWL6040_VIBLOCDET               0x10
 165#define TWL6040_VIBROCDET               0x20
 166#define TWL6040_TSHUTDET                0x40
 167
 168#define TWL6040_CELLS                   3
 169
 170#define TWL6040_REV_ES1_0               0x00
 171#define TWL6040_REV_ES1_1               0x01 /* Rev ES1.1 and ES1.2 */
 172#define TWL6040_REV_ES1_3               0x02
 173#define TWL6041_REV_ES2_0               0x10
 174
 175#define TWL6040_IRQ_TH                  0
 176#define TWL6040_IRQ_PLUG                1
 177#define TWL6040_IRQ_HOOK                2
 178#define TWL6040_IRQ_HF                  3
 179#define TWL6040_IRQ_VIB                 4
 180#define TWL6040_IRQ_READY               5
 181
 182/* PLL selection */
 183#define TWL6040_SYSCLK_SEL_LPPLL        0
 184#define TWL6040_SYSCLK_SEL_HPPLL        1
 185
 186#define TWL6040_GPO_MAX 3
 187
 188struct twl6040_codec_data {
 189        u16 hs_left_step;
 190        u16 hs_right_step;
 191        u16 hf_left_step;
 192        u16 hf_right_step;
 193};
 194
 195struct twl6040_vibra_data {
 196        unsigned int vibldrv_res;       /* left driver resistance */
 197        unsigned int vibrdrv_res;       /* right driver resistance */
 198        unsigned int viblmotor_res;     /* left motor resistance */
 199        unsigned int vibrmotor_res;     /* right motor resistance */
 200        int vddvibl_uV;                 /* VDDVIBL volt, set 0 for fixed reg */
 201        int vddvibr_uV;                 /* VDDVIBR volt, set 0 for fixed reg */
 202};
 203
 204struct twl6040_gpo_data {
 205        int gpio_base;
 206};
 207
 208struct twl6040_platform_data {
 209        int audpwron_gpio;      /* audio power-on gpio */
 210
 211        struct twl6040_codec_data *codec;
 212        struct twl6040_vibra_data *vibra;
 213        struct twl6040_gpo_data *gpo;
 214};
 215
 216struct regmap;
 217struct regmap_irq_chips_data;
 218
 219struct twl6040 {
 220        struct device *dev;
 221        struct regmap *regmap;
 222        struct regmap_irq_chip_data *irq_data;
 223        struct regulator_bulk_data supplies[2]; /* supplies for vio, v2v1 */
 224        struct mutex mutex;
 225        struct mutex irq_mutex;
 226        struct mfd_cell cells[TWL6040_CELLS];
 227        struct completion ready;
 228
 229        int audpwron;
 230        int power_count;
 231        int rev;
 232        u8 vibra_ctrl_cache[2];
 233
 234        /* PLL configuration */
 235        int pll;
 236        unsigned int sysclk;
 237        unsigned int mclk;
 238
 239        unsigned int irq;
 240        unsigned int irq_ready;
 241        unsigned int irq_th;
 242};
 243
 244int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
 245int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg,
 246                      u8 val);
 247int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg,
 248                     u8 mask);
 249int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg,
 250                       u8 mask);
 251int twl6040_power(struct twl6040 *twl6040, int on);
 252int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
 253                    unsigned int freq_in, unsigned int freq_out);
 254int twl6040_get_pll(struct twl6040 *twl6040);
 255unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
 256
 257/* Get the combined status of the vibra control register */
 258int twl6040_get_vibralr_status(struct twl6040 *twl6040);
 259
 260static inline int twl6040_get_revid(struct twl6040 *twl6040)
 261{
 262        return twl6040->rev;
 263}
 264
 265
 266#endif  /* End of __TWL6040_CODEC_H__ */
 267