LXR linux/include/linux/sh

   1/*
   2 * Header for the new SH dmaengine driver
   3 *
   4 * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 */
  10#ifndef SH_DMA_H
  11#define SH_DMA_H
  12
  13#include <linux/dmaengine.h>
  14#include <linux/list.h>
  15#include <linux/shdma-base.h>
  16#include <linux/types.h>
  17
  18struct device;
  19
  20/* Used by slave DMA clients to request DMA to/from a specific peripheral */
  21struct sh_dmae_slave {
  22        struct shdma_slave              shdma_slave;    /* Set by the platform */
  23};
  24
  25/*
  26 * Supplied by platforms to specify, how a DMA channel has to be configured for
  27 * a certain peripheral
  28 */
  29struct sh_dmae_slave_config {
  30        int             slave_id;
  31        dma_addr_t      addr;
  32        u32             chcr;
  33        char            mid_rid;
  34};
  35
  36struct sh_dmae_channel {
  37        unsigned int    offset;
  38        unsigned int    dmars;
  39        unsigned int    dmars_bit;
  40        unsigned int    chclr_offset;
  41};
  42
  43struct sh_dmae_pdata {
  44        const struct sh_dmae_slave_config *slave;
  45        int slave_num;
  46        const struct sh_dmae_channel *channel;
  47        int channel_num;
  48        unsigned int ts_low_shift;
  49        unsigned int ts_low_mask;
  50        unsigned int ts_high_shift;
  51        unsigned int ts_high_mask;
  52        const unsigned int *ts_shift;
  53        int ts_shift_num;
  54        u16 dmaor_init;
  55        unsigned int chcr_offset;
  56        u32 chcr_ie_bit;
  57
  58        unsigned int dmaor_is_32bit:1;
  59        unsigned int needs_tend_set:1;
  60        unsigned int no_dmars:1;
  61        unsigned int chclr_present:1;
  62        unsigned int slave_only:1;
  63};
  64
  65/* DMA register */
  66#define SAR     0x00
  67#define DAR     0x04
  68#define TCR     0x08
  69#define CHCR    0x0C
  70#define DMAOR   0x40
  71
  72#define TEND    0x18 /* USB-DMAC */
  73
  74/* DMAOR definitions */
  75#define DMAOR_AE        0x00000004
  76#define DMAOR_NMIF      0x00000002
  77#define DMAOR_DME       0x00000001
  78
  79/* Definitions for the SuperH DMAC */
  80#define REQ_L   0x00000000
  81#define REQ_E   0x00080000
  82#define RACK_H  0x00000000
  83#define RACK_L  0x00040000
  84#define ACK_R   0x00000000
  85#define ACK_W   0x00020000
  86#define ACK_H   0x00000000
  87#define ACK_L   0x00010000
  88#define DM_INC  0x00004000
  89#define DM_DEC  0x00008000
  90#define DM_FIX  0x0000c000
  91#define SM_INC  0x00001000
  92#define SM_DEC  0x00002000
  93#define SM_FIX  0x00003000
  94#define RS_IN   0x00000200
  95#define RS_OUT  0x00000300
  96#define TS_BLK  0x00000040
  97#define TM_BUR  0x00000020
  98#define CHCR_DE 0x00000001
  99#define CHCR_TE 0x00000002
 100#define CHCR_IE 0x00000004
 101
 102#endif
 103