1/* 2 * Copyright (c) 2001-2002 by David Brownell 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, but 10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software Foundation, 16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 17 */ 18 19#ifndef __LINUX_USB_EHCI_DEF_H 20#define __LINUX_USB_EHCI_DEF_H 21 22/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */ 23 24/* Section 2.2 Host Controller Capability Registers */ 25struct ehci_caps { 26 /* these fields are specified as 8 and 16 bit registers, 27 * but some hosts can't perform 8 or 16 bit PCI accesses. 28 * some hosts treat caplength and hciversion as parts of a 32-bit 29 * register, others treat them as two separate registers, this 30 * affects the memory map for big endian controllers. 31 */ 32 u32 hc_capbase; 33#define HC_LENGTH(ehci, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \ 34 (ehci_big_endian_capbase(ehci) ? 24 : 0))) 35#define HC_VERSION(ehci, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \ 36 (ehci_big_endian_capbase(ehci) ? 0 : 16))) 37 u32 hcs_params; /* HCSPARAMS - offset 0x4 */ 38#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */ 39#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */ 40#define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */ 41#define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */ 42#define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */ 43#define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */ 44#define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */ 45 46 u32 hcc_params; /* HCCPARAMS - offset 0x8 */ 47/* EHCI 1.1 addendum */ 48#define HCC_32FRAME_PERIODIC_LIST(p) ((p)&(1 << 19)) 49#define HCC_PER_PORT_CHANGE_EVENT(p) ((p)&(1 << 18)) 50#define HCC_LPM(p) ((p)&(1 << 17)) 51#define HCC_HW_PREFETCH(p) ((p)&(1 << 16)) 52 53#define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */ 54#define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */ 55#define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */ 56#define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */ 57#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/ 58#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */ 59 u8 portroute[8]; /* nibbles for routing - offset 0xC */ 60}; 61 62 63/* Section 2.3 Host Controller Operational Registers */ 64struct ehci_regs { 65 66 /* USBCMD: offset 0x00 */ 67 u32 command; 68 69/* EHCI 1.1 addendum */ 70#define CMD_HIRD (0xf<<24) /* host initiated resume duration */ 71#define CMD_PPCEE (1<<15) /* per port change event enable */ 72#define CMD_FSP (1<<14) /* fully synchronized prefetch */ 73#define CMD_ASPE (1<<13) /* async schedule prefetch enable */ 74#define CMD_PSPE (1<<12) /* periodic schedule prefetch enable */ 75/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */ 76#define CMD_PARK (1<<11) /* enable "park" on async qh */ 77#define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */ 78#define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */ 79#define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */ 80#define CMD_ASE (1<<5) /* async schedule enable */ 81#define CMD_PSE (1<<4) /* periodic schedule enable */ 82/* 3:2 is periodic frame list size */ 83#define CMD_RESET (1<<1) /* reset HC not bus */ 84#define CMD_RUN (1<<0) /* start/stop HC */ 85 86 /* USBSTS: offset 0x04 */ 87 u32 status; 88#define STS_PPCE_MASK (0xff<<16) /* Per-Port change event 1-16 */ 89#define STS_ASS (1<<15) /* Async Schedule Status */ 90#define STS_PSS (1<<14) /* Periodic Schedule Status */ 91#define STS_RECL (1<<13) /* Reclamation */ 92#define STS_HALT (1<<12) /* Not running (any reason) */ 93/* some bits reserved */ 94 /* these STS_* flags are also intr_enable bits (USBINTR) */ 95#define STS_IAA (1<<5) /* Interrupted on async advance */ 96#define STS_FATAL (1<<4) /* such as some PCI access errors */ 97#define STS_FLR (1<<3) /* frame list rolled over */ 98#define STS_PCD (1<<2) /* port change detect */ 99#define STS_ERR (1<<1) /* "error" completion (overflow, ...) */ 100#define STS_INT (1<<0) /* "normal" completion (short, ...) */ 101 102 /* USBINTR: offset 0x08 */ 103 u32 intr_enable; 104 105 /* FRINDEX: offset 0x0C */ 106 u32 frame_index; /* current microframe number */ 107 /* CTRLDSSEGMENT: offset 0x10 */ 108 u32 segment; /* address bits 63:32 if needed */ 109 /* PERIODICLISTBASE: offset 0x14 */ 110 u32 frame_list; /* points to periodic list */ 111 /* ASYNCLISTADDR: offset 0x18 */ 112 u32 async_next; /* address of next async queue head */ 113 114 u32 reserved1[2]; 115 116 /* TXFILLTUNING: offset 0x24 */ 117 u32 txfill_tuning; /* TX FIFO Tuning register */ 118#define TXFIFO_DEFAULT (8<<16) /* FIFO burst threshold 8 */ 119 120 u32 reserved2[6]; 121 122 /* CONFIGFLAG: offset 0x40 */ 123 u32 configured_flag; 124#define FLAG_CF (1<<0) /* true: we'll support "high speed" */ 125 126 /* PORTSC: offset 0x44 */ 127 u32 port_status[0]; /* up to N_PORTS */ 128/* EHCI 1.1 addendum */ 129#define PORTSC_SUSPEND_STS_ACK 0 130#define PORTSC_SUSPEND_STS_NYET 1 131#define PORTSC_SUSPEND_STS_STALL 2 132#define PORTSC_SUSPEND_STS_ERR 3 133 134#define PORT_DEV_ADDR (0x7f<<25) /* device address */ 135#define PORT_SSTS (0x3<<23) /* suspend status */ 136/* 31:23 reserved */ 137#define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */ 138#define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */ 139#define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */ 140/* 19:16 for port testing */ 141#define PORT_TEST(x) (((x)&0xf)<<16) /* Port Test Control */ 142#define PORT_TEST_PKT PORT_TEST(0x4) /* Port Test Control - packet test */ 143#define PORT_TEST_FORCE PORT_TEST(0x5) /* Port Test Control - force enable */ 144#define PORT_LED_OFF (0<<14) 145#define PORT_LED_AMBER (1<<14) 146#define PORT_LED_GREEN (2<<14) 147#define PORT_LED_MASK (3<<14) 148#define PORT_OWNER (1<<13) /* true: companion hc owns this port */ 149#define PORT_POWER (1<<12) /* true: has power (see PPC) */ 150#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10)) /* USB 1.1 device */ 151/* 11:10 for detecting lowspeed devices (reset vs release ownership) */ 152/* 9 reserved */ 153#define PORT_LPM (1<<9) /* LPM transaction */ 154#define PORT_RESET (1<<8) /* reset port */ 155#define PORT_SUSPEND (1<<7) /* suspend port */ 156#define PORT_RESUME (1<<6) /* resume it */ 157#define PORT_OCC (1<<5) /* over current change */ 158#define PORT_OC (1<<4) /* over current active */ 159#define PORT_PEC (1<<3) /* port enable change */ 160#define PORT_PE (1<<2) /* port enable */ 161#define PORT_CSC (1<<1) /* connect status change */ 162#define PORT_CONNECT (1<<0) /* device connected */ 163#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC) 164 165 u32 reserved3[9]; 166 167 /* USBMODE: offset 0x68 */ 168 u32 usbmode; /* USB Device mode */ 169#define USBMODE_SDIS (1<<3) /* Stream disable */ 170#define USBMODE_BE (1<<2) /* BE/LE endianness select */ 171#define USBMODE_CM_HC (3<<0) /* host controller mode */ 172#define USBMODE_CM_IDLE (0<<0) /* idle state */ 173 174 u32 reserved4[6]; 175 176/* Moorestown has some non-standard registers, partially due to the fact that 177 * its EHCI controller has both TT and LPM support. HOSTPCx are extensions to 178 * PORTSCx 179 */ 180 /* HOSTPC: offset 0x84 */ 181 u32 hostpc[1]; /* HOSTPC extension */ 182#define HOSTPC_PHCD (1<<22) /* Phy clock disable */ 183#define HOSTPC_PSPD (3<<25) /* Port speed detection */ 184 185 u32 reserved5[16]; 186 187 /* USBMODE_EX: offset 0xc8 */ 188 u32 usbmode_ex; /* USB Device mode extension */ 189#define USBMODE_EX_VBPS (1<<5) /* VBus Power Select On */ 190#define USBMODE_EX_HC (3<<0) /* host controller mode */ 191}; 192 193/* Appendix C, Debug port ... intended for use with special "debug devices" 194 * that can help if there's no serial console. (nonstandard enumeration.) 195 */ 196struct ehci_dbg_port { 197 u32 control; 198#define DBGP_OWNER (1<<30) 199#define DBGP_ENABLED (1<<28) 200#define DBGP_DONE (1<<16) 201#define DBGP_INUSE (1<<10) 202#define DBGP_ERRCODE(x) (((x)>>7)&0x07) 203# define DBGP_ERR_BAD 1 204# define DBGP_ERR_SIGNAL 2 205#define DBGP_ERROR (1<<6) 206#define DBGP_GO (1<<5) 207#define DBGP_OUT (1<<4) 208#define DBGP_LEN(x) (((x)>>0)&0x0f) 209 u32 pids; 210#define DBGP_PID_GET(x) (((x)>>16)&0xff) 211#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok)) 212 u32 data03; 213 u32 data47; 214 u32 address; 215#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep)) 216}; 217 218#ifdef CONFIG_EARLY_PRINTK_DBGP 219#include <linux/init.h> 220extern int __init early_dbgp_init(char *s); 221extern struct console early_dbgp_console; 222#endif /* CONFIG_EARLY_PRINTK_DBGP */ 223 224struct usb_hcd; 225 226#ifdef CONFIG_XEN_DOM0 227extern int xen_dbgp_reset_prep(struct usb_hcd *); 228extern int xen_dbgp_external_startup(struct usb_hcd *); 229#else 230static inline int xen_dbgp_reset_prep(struct usb_hcd *hcd) 231{ 232 return 1; /* Shouldn't this be 0? */ 233} 234 235static inline int xen_dbgp_external_startup(struct usb_hcd *hcd) 236{ 237 return -1; 238} 239#endif 240 241#ifdef CONFIG_EARLY_PRINTK_DBGP 242/* Call backs from ehci host driver to ehci debug driver */ 243extern int dbgp_external_startup(struct usb_hcd *); 244extern int dbgp_reset_prep(struct usb_hcd *hcd); 245#else 246static inline int dbgp_reset_prep(struct usb_hcd *hcd) 247{ 248 return xen_dbgp_reset_prep(hcd); 249} 250static inline int dbgp_external_startup(struct usb_hcd *hcd) 251{ 252 return xen_dbgp_external_startup(hcd); 253} 254#endif 255 256#endif /* __LINUX_USB_EHCI_DEF_H */ 257