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18#include <linux/types.h>
19#include <linux/slab.h>
20#include <linux/pci.h>
21#include <linux/io.h>
22#include <linux/string.h>
23#include <linux/kernel.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include "cthw20k2.h"
27#include "ct20k2reg.h"
28
29#if BITS_PER_LONG == 32
30#define CT_XFI_DMA_MASK DMA_BIT_MASK(32)
31#else
32#define CT_XFI_DMA_MASK DMA_BIT_MASK(64)
33#endif
34
35struct hw20k2 {
36 struct hw hw;
37
38 unsigned char dev_id;
39 unsigned char addr_size;
40 unsigned char data_size;
41
42 int mic_source;
43};
44
45static u32 hw_read_20kx(struct hw *hw, u32 reg);
46static void hw_write_20kx(struct hw *hw, u32 reg, u32 data);
47
48
49
50
51
52
53
54
55
56
57
58#define SRCCTL_STATE 0x00000007
59#define SRCCTL_BM 0x00000008
60#define SRCCTL_RSR 0x00000030
61#define SRCCTL_SF 0x000001C0
62#define SRCCTL_WR 0x00000200
63#define SRCCTL_PM 0x00000400
64#define SRCCTL_ROM 0x00001800
65#define SRCCTL_VO 0x00002000
66#define SRCCTL_ST 0x00004000
67#define SRCCTL_IE 0x00008000
68#define SRCCTL_ILSZ 0x000F0000
69#define SRCCTL_BP 0x00100000
70
71#define SRCCCR_CISZ 0x000007FF
72#define SRCCCR_CWA 0x001FF800
73#define SRCCCR_D 0x00200000
74#define SRCCCR_RS 0x01C00000
75#define SRCCCR_NAL 0x3E000000
76#define SRCCCR_RA 0xC0000000
77
78#define SRCCA_CA 0x0FFFFFFF
79#define SRCCA_RS 0xE0000000
80
81#define SRCSA_SA 0x0FFFFFFF
82
83#define SRCLA_LA 0x0FFFFFFF
84
85
86
87#define MPRLH_PITCH 0xFFFFFFFF
88
89
90union src_dirty {
91 struct {
92 u16 ctl:1;
93 u16 ccr:1;
94 u16 sa:1;
95 u16 la:1;
96 u16 ca:1;
97 u16 mpr:1;
98 u16 czbfs:1;
99 u16 rsv:9;
100 } bf;
101 u16 data;
102};
103
104struct src_rsc_ctrl_blk {
105 unsigned int ctl;
106 unsigned int ccr;
107 unsigned int ca;
108 unsigned int sa;
109 unsigned int la;
110 unsigned int mpr;
111 union src_dirty dirty;
112};
113
114
115union src_mgr_dirty {
116 struct {
117 u16 enb0:1;
118 u16 enb1:1;
119 u16 enb2:1;
120 u16 enb3:1;
121 u16 enb4:1;
122 u16 enb5:1;
123 u16 enb6:1;
124 u16 enb7:1;
125 u16 enbsa:1;
126 u16 rsv:7;
127 } bf;
128 u16 data;
129};
130
131struct src_mgr_ctrl_blk {
132 unsigned int enbsa;
133 unsigned int enb[8];
134 union src_mgr_dirty dirty;
135};
136
137
138#define SRCAIM_ARC 0x00000FFF
139#define SRCAIM_NXT 0x00FF0000
140#define SRCAIM_SRC 0xFF000000
141
142struct srcimap {
143 unsigned int srcaim;
144 unsigned int idx;
145};
146
147
148union srcimp_mgr_dirty {
149 struct {
150 u16 srcimap:1;
151 u16 rsv:15;
152 } bf;
153 u16 data;
154};
155
156struct srcimp_mgr_ctrl_blk {
157 struct srcimap srcimap;
158 union srcimp_mgr_dirty dirty;
159};
160
161
162
163
164
165static int src_get_rsc_ctrl_blk(void **rblk)
166{
167 struct src_rsc_ctrl_blk *blk;
168
169 *rblk = NULL;
170 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
171 if (!blk)
172 return -ENOMEM;
173
174 *rblk = blk;
175
176 return 0;
177}
178
179static int src_put_rsc_ctrl_blk(void *blk)
180{
181 kfree(blk);
182
183 return 0;
184}
185
186static int src_set_state(void *blk, unsigned int state)
187{
188 struct src_rsc_ctrl_blk *ctl = blk;
189
190 set_field(&ctl->ctl, SRCCTL_STATE, state);
191 ctl->dirty.bf.ctl = 1;
192 return 0;
193}
194
195static int src_set_bm(void *blk, unsigned int bm)
196{
197 struct src_rsc_ctrl_blk *ctl = blk;
198
199 set_field(&ctl->ctl, SRCCTL_BM, bm);
200 ctl->dirty.bf.ctl = 1;
201 return 0;
202}
203
204static int src_set_rsr(void *blk, unsigned int rsr)
205{
206 struct src_rsc_ctrl_blk *ctl = blk;
207
208 set_field(&ctl->ctl, SRCCTL_RSR, rsr);
209 ctl->dirty.bf.ctl = 1;
210 return 0;
211}
212
213static int src_set_sf(void *blk, unsigned int sf)
214{
215 struct src_rsc_ctrl_blk *ctl = blk;
216
217 set_field(&ctl->ctl, SRCCTL_SF, sf);
218 ctl->dirty.bf.ctl = 1;
219 return 0;
220}
221
222static int src_set_wr(void *blk, unsigned int wr)
223{
224 struct src_rsc_ctrl_blk *ctl = blk;
225
226 set_field(&ctl->ctl, SRCCTL_WR, wr);
227 ctl->dirty.bf.ctl = 1;
228 return 0;
229}
230
231static int src_set_pm(void *blk, unsigned int pm)
232{
233 struct src_rsc_ctrl_blk *ctl = blk;
234
235 set_field(&ctl->ctl, SRCCTL_PM, pm);
236 ctl->dirty.bf.ctl = 1;
237 return 0;
238}
239
240static int src_set_rom(void *blk, unsigned int rom)
241{
242 struct src_rsc_ctrl_blk *ctl = blk;
243
244 set_field(&ctl->ctl, SRCCTL_ROM, rom);
245 ctl->dirty.bf.ctl = 1;
246 return 0;
247}
248
249static int src_set_vo(void *blk, unsigned int vo)
250{
251 struct src_rsc_ctrl_blk *ctl = blk;
252
253 set_field(&ctl->ctl, SRCCTL_VO, vo);
254 ctl->dirty.bf.ctl = 1;
255 return 0;
256}
257
258static int src_set_st(void *blk, unsigned int st)
259{
260 struct src_rsc_ctrl_blk *ctl = blk;
261
262 set_field(&ctl->ctl, SRCCTL_ST, st);
263 ctl->dirty.bf.ctl = 1;
264 return 0;
265}
266
267static int src_set_ie(void *blk, unsigned int ie)
268{
269 struct src_rsc_ctrl_blk *ctl = blk;
270
271 set_field(&ctl->ctl, SRCCTL_IE, ie);
272 ctl->dirty.bf.ctl = 1;
273 return 0;
274}
275
276static int src_set_ilsz(void *blk, unsigned int ilsz)
277{
278 struct src_rsc_ctrl_blk *ctl = blk;
279
280 set_field(&ctl->ctl, SRCCTL_ILSZ, ilsz);
281 ctl->dirty.bf.ctl = 1;
282 return 0;
283}
284
285static int src_set_bp(void *blk, unsigned int bp)
286{
287 struct src_rsc_ctrl_blk *ctl = blk;
288
289 set_field(&ctl->ctl, SRCCTL_BP, bp);
290 ctl->dirty.bf.ctl = 1;
291 return 0;
292}
293
294static int src_set_cisz(void *blk, unsigned int cisz)
295{
296 struct src_rsc_ctrl_blk *ctl = blk;
297
298 set_field(&ctl->ccr, SRCCCR_CISZ, cisz);
299 ctl->dirty.bf.ccr = 1;
300 return 0;
301}
302
303static int src_set_ca(void *blk, unsigned int ca)
304{
305 struct src_rsc_ctrl_blk *ctl = blk;
306
307 set_field(&ctl->ca, SRCCA_CA, ca);
308 ctl->dirty.bf.ca = 1;
309 return 0;
310}
311
312static int src_set_sa(void *blk, unsigned int sa)
313{
314 struct src_rsc_ctrl_blk *ctl = blk;
315
316 set_field(&ctl->sa, SRCSA_SA, sa);
317 ctl->dirty.bf.sa = 1;
318 return 0;
319}
320
321static int src_set_la(void *blk, unsigned int la)
322{
323 struct src_rsc_ctrl_blk *ctl = blk;
324
325 set_field(&ctl->la, SRCLA_LA, la);
326 ctl->dirty.bf.la = 1;
327 return 0;
328}
329
330static int src_set_pitch(void *blk, unsigned int pitch)
331{
332 struct src_rsc_ctrl_blk *ctl = blk;
333
334 set_field(&ctl->mpr, MPRLH_PITCH, pitch);
335 ctl->dirty.bf.mpr = 1;
336 return 0;
337}
338
339static int src_set_clear_zbufs(void *blk, unsigned int clear)
340{
341 ((struct src_rsc_ctrl_blk *)blk)->dirty.bf.czbfs = (clear ? 1 : 0);
342 return 0;
343}
344
345static int src_set_dirty(void *blk, unsigned int flags)
346{
347 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
348 return 0;
349}
350
351static int src_set_dirty_all(void *blk)
352{
353 ((struct src_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
354 return 0;
355}
356
357#define AR_SLOT_SIZE 4096
358#define AR_SLOT_BLOCK_SIZE 16
359#define AR_PTS_PITCH 6
360#define AR_PARAM_SRC_OFFSET 0x60
361
362static unsigned int src_param_pitch_mixer(unsigned int src_idx)
363{
364 return ((src_idx << 4) + AR_PTS_PITCH + AR_SLOT_SIZE
365 - AR_PARAM_SRC_OFFSET) % AR_SLOT_SIZE;
366
367}
368
369static int src_commit_write(struct hw *hw, unsigned int idx, void *blk)
370{
371 struct src_rsc_ctrl_blk *ctl = blk;
372 int i;
373
374 if (ctl->dirty.bf.czbfs) {
375
376 for (i = 0; i < 8; i++)
377 hw_write_20kx(hw, SRC_UPZ+idx*0x100+i*0x4, 0);
378
379 for (i = 0; i < 4; i++)
380 hw_write_20kx(hw, SRC_DN0Z+idx*0x100+i*0x4, 0);
381
382 for (i = 0; i < 8; i++)
383 hw_write_20kx(hw, SRC_DN1Z+idx*0x100+i*0x4, 0);
384
385 ctl->dirty.bf.czbfs = 0;
386 }
387 if (ctl->dirty.bf.mpr) {
388
389
390
391
392 unsigned int pm_idx = src_param_pitch_mixer(idx);
393 hw_write_20kx(hw, MIXER_PRING_LO_HI+4*pm_idx, ctl->mpr);
394 hw_write_20kx(hw, MIXER_PMOPLO+8*pm_idx, 0x3);
395 hw_write_20kx(hw, MIXER_PMOPHI+8*pm_idx, 0x0);
396 ctl->dirty.bf.mpr = 0;
397 }
398 if (ctl->dirty.bf.sa) {
399 hw_write_20kx(hw, SRC_SA+idx*0x100, ctl->sa);
400 ctl->dirty.bf.sa = 0;
401 }
402 if (ctl->dirty.bf.la) {
403 hw_write_20kx(hw, SRC_LA+idx*0x100, ctl->la);
404 ctl->dirty.bf.la = 0;
405 }
406 if (ctl->dirty.bf.ca) {
407 hw_write_20kx(hw, SRC_CA+idx*0x100, ctl->ca);
408 ctl->dirty.bf.ca = 0;
409 }
410
411
412 hw_write_20kx(hw, SRC_CF+idx*0x100, 0x0);
413
414 if (ctl->dirty.bf.ccr) {
415 hw_write_20kx(hw, SRC_CCR+idx*0x100, ctl->ccr);
416 ctl->dirty.bf.ccr = 0;
417 }
418 if (ctl->dirty.bf.ctl) {
419 hw_write_20kx(hw, SRC_CTL+idx*0x100, ctl->ctl);
420 ctl->dirty.bf.ctl = 0;
421 }
422
423 return 0;
424}
425
426static int src_get_ca(struct hw *hw, unsigned int idx, void *blk)
427{
428 struct src_rsc_ctrl_blk *ctl = blk;
429
430 ctl->ca = hw_read_20kx(hw, SRC_CA+idx*0x100);
431 ctl->dirty.bf.ca = 0;
432
433 return get_field(ctl->ca, SRCCA_CA);
434}
435
436static unsigned int src_get_dirty(void *blk)
437{
438 return ((struct src_rsc_ctrl_blk *)blk)->dirty.data;
439}
440
441static unsigned int src_dirty_conj_mask(void)
442{
443 return 0x20;
444}
445
446static int src_mgr_enbs_src(void *blk, unsigned int idx)
447{
448 ((struct src_mgr_ctrl_blk *)blk)->enbsa |= (0x1 << ((idx%128)/4));
449 ((struct src_mgr_ctrl_blk *)blk)->dirty.bf.enbsa = 1;
450 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
451 return 0;
452}
453
454static int src_mgr_enb_src(void *blk, unsigned int idx)
455{
456 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] |= (0x1 << (idx%32));
457 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
458 return 0;
459}
460
461static int src_mgr_dsb_src(void *blk, unsigned int idx)
462{
463 ((struct src_mgr_ctrl_blk *)blk)->enb[idx/32] &= ~(0x1 << (idx%32));
464 ((struct src_mgr_ctrl_blk *)blk)->dirty.data |= (0x1 << (idx/32));
465 return 0;
466}
467
468static int src_mgr_commit_write(struct hw *hw, void *blk)
469{
470 struct src_mgr_ctrl_blk *ctl = blk;
471 int i;
472 unsigned int ret;
473
474 if (ctl->dirty.bf.enbsa) {
475 do {
476 ret = hw_read_20kx(hw, SRC_ENBSTAT);
477 } while (ret & 0x1);
478 hw_write_20kx(hw, SRC_ENBSA, ctl->enbsa);
479 ctl->dirty.bf.enbsa = 0;
480 }
481 for (i = 0; i < 8; i++) {
482 if ((ctl->dirty.data & (0x1 << i))) {
483 hw_write_20kx(hw, SRC_ENB+(i*0x100), ctl->enb[i]);
484 ctl->dirty.data &= ~(0x1 << i);
485 }
486 }
487
488 return 0;
489}
490
491static int src_mgr_get_ctrl_blk(void **rblk)
492{
493 struct src_mgr_ctrl_blk *blk;
494
495 *rblk = NULL;
496 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
497 if (!blk)
498 return -ENOMEM;
499
500 *rblk = blk;
501
502 return 0;
503}
504
505static int src_mgr_put_ctrl_blk(void *blk)
506{
507 kfree(blk);
508
509 return 0;
510}
511
512static int srcimp_mgr_get_ctrl_blk(void **rblk)
513{
514 struct srcimp_mgr_ctrl_blk *blk;
515
516 *rblk = NULL;
517 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
518 if (!blk)
519 return -ENOMEM;
520
521 *rblk = blk;
522
523 return 0;
524}
525
526static int srcimp_mgr_put_ctrl_blk(void *blk)
527{
528 kfree(blk);
529
530 return 0;
531}
532
533static int srcimp_mgr_set_imaparc(void *blk, unsigned int slot)
534{
535 struct srcimp_mgr_ctrl_blk *ctl = blk;
536
537 set_field(&ctl->srcimap.srcaim, SRCAIM_ARC, slot);
538 ctl->dirty.bf.srcimap = 1;
539 return 0;
540}
541
542static int srcimp_mgr_set_imapuser(void *blk, unsigned int user)
543{
544 struct srcimp_mgr_ctrl_blk *ctl = blk;
545
546 set_field(&ctl->srcimap.srcaim, SRCAIM_SRC, user);
547 ctl->dirty.bf.srcimap = 1;
548 return 0;
549}
550
551static int srcimp_mgr_set_imapnxt(void *blk, unsigned int next)
552{
553 struct srcimp_mgr_ctrl_blk *ctl = blk;
554
555 set_field(&ctl->srcimap.srcaim, SRCAIM_NXT, next);
556 ctl->dirty.bf.srcimap = 1;
557 return 0;
558}
559
560static int srcimp_mgr_set_imapaddr(void *blk, unsigned int addr)
561{
562 ((struct srcimp_mgr_ctrl_blk *)blk)->srcimap.idx = addr;
563 ((struct srcimp_mgr_ctrl_blk *)blk)->dirty.bf.srcimap = 1;
564 return 0;
565}
566
567static int srcimp_mgr_commit_write(struct hw *hw, void *blk)
568{
569 struct srcimp_mgr_ctrl_blk *ctl = blk;
570
571 if (ctl->dirty.bf.srcimap) {
572 hw_write_20kx(hw, SRC_IMAP+ctl->srcimap.idx*0x100,
573 ctl->srcimap.srcaim);
574 ctl->dirty.bf.srcimap = 0;
575 }
576
577 return 0;
578}
579
580
581
582
583
584#define AMOPLO_M 0x00000003
585#define AMOPLO_IV 0x00000004
586#define AMOPLO_X 0x0003FFF0
587#define AMOPLO_Y 0xFFFC0000
588
589#define AMOPHI_SADR 0x000000FF
590#define AMOPHI_SE 0x80000000
591
592
593union amixer_dirty {
594 struct {
595 u16 amoplo:1;
596 u16 amophi:1;
597 u16 rsv:14;
598 } bf;
599 u16 data;
600};
601
602
603struct amixer_rsc_ctrl_blk {
604 unsigned int amoplo;
605 unsigned int amophi;
606 union amixer_dirty dirty;
607};
608
609static int amixer_set_mode(void *blk, unsigned int mode)
610{
611 struct amixer_rsc_ctrl_blk *ctl = blk;
612
613 set_field(&ctl->amoplo, AMOPLO_M, mode);
614 ctl->dirty.bf.amoplo = 1;
615 return 0;
616}
617
618static int amixer_set_iv(void *blk, unsigned int iv)
619{
620 struct amixer_rsc_ctrl_blk *ctl = blk;
621
622 set_field(&ctl->amoplo, AMOPLO_IV, iv);
623 ctl->dirty.bf.amoplo = 1;
624 return 0;
625}
626
627static int amixer_set_x(void *blk, unsigned int x)
628{
629 struct amixer_rsc_ctrl_blk *ctl = blk;
630
631 set_field(&ctl->amoplo, AMOPLO_X, x);
632 ctl->dirty.bf.amoplo = 1;
633 return 0;
634}
635
636static int amixer_set_y(void *blk, unsigned int y)
637{
638 struct amixer_rsc_ctrl_blk *ctl = blk;
639
640 set_field(&ctl->amoplo, AMOPLO_Y, y);
641 ctl->dirty.bf.amoplo = 1;
642 return 0;
643}
644
645static int amixer_set_sadr(void *blk, unsigned int sadr)
646{
647 struct amixer_rsc_ctrl_blk *ctl = blk;
648
649 set_field(&ctl->amophi, AMOPHI_SADR, sadr);
650 ctl->dirty.bf.amophi = 1;
651 return 0;
652}
653
654static int amixer_set_se(void *blk, unsigned int se)
655{
656 struct amixer_rsc_ctrl_blk *ctl = blk;
657
658 set_field(&ctl->amophi, AMOPHI_SE, se);
659 ctl->dirty.bf.amophi = 1;
660 return 0;
661}
662
663static int amixer_set_dirty(void *blk, unsigned int flags)
664{
665 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = (flags & 0xffff);
666 return 0;
667}
668
669static int amixer_set_dirty_all(void *blk)
670{
671 ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data = ~(0x0);
672 return 0;
673}
674
675static int amixer_commit_write(struct hw *hw, unsigned int idx, void *blk)
676{
677 struct amixer_rsc_ctrl_blk *ctl = blk;
678
679 if (ctl->dirty.bf.amoplo || ctl->dirty.bf.amophi) {
680 hw_write_20kx(hw, MIXER_AMOPLO+idx*8, ctl->amoplo);
681 ctl->dirty.bf.amoplo = 0;
682 hw_write_20kx(hw, MIXER_AMOPHI+idx*8, ctl->amophi);
683 ctl->dirty.bf.amophi = 0;
684 }
685
686 return 0;
687}
688
689static int amixer_get_y(void *blk)
690{
691 struct amixer_rsc_ctrl_blk *ctl = blk;
692
693 return get_field(ctl->amoplo, AMOPLO_Y);
694}
695
696static unsigned int amixer_get_dirty(void *blk)
697{
698 return ((struct amixer_rsc_ctrl_blk *)blk)->dirty.data;
699}
700
701static int amixer_rsc_get_ctrl_blk(void **rblk)
702{
703 struct amixer_rsc_ctrl_blk *blk;
704
705 *rblk = NULL;
706 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
707 if (!blk)
708 return -ENOMEM;
709
710 *rblk = blk;
711
712 return 0;
713}
714
715static int amixer_rsc_put_ctrl_blk(void *blk)
716{
717 kfree(blk);
718
719 return 0;
720}
721
722static int amixer_mgr_get_ctrl_blk(void **rblk)
723{
724 *rblk = NULL;
725
726 return 0;
727}
728
729static int amixer_mgr_put_ctrl_blk(void *blk)
730{
731 return 0;
732}
733
734
735
736
737
738
739#define SRTCTL_SRCO 0x000000FF
740#define SRTCTL_SRCM 0x0000FF00
741#define SRTCTL_RSR 0x00030000
742#define SRTCTL_DRAT 0x00300000
743#define SRTCTL_EC 0x01000000
744#define SRTCTL_ET 0x10000000
745
746
747union dai_dirty {
748 struct {
749 u16 srt:1;
750 u16 rsv:15;
751 } bf;
752 u16 data;
753};
754
755
756struct dai_ctrl_blk {
757 unsigned int srt;
758 union dai_dirty dirty;
759};
760
761
762#define AIM_ARC 0x00000FFF
763#define AIM_NXT 0x007F0000
764
765struct daoimap {
766 unsigned int aim;
767 unsigned int idx;
768};
769
770
771#define ATXCTL_EN 0x00000001
772#define ATXCTL_MODE 0x00000010
773#define ATXCTL_CD 0x00000020
774#define ATXCTL_RAW 0x00000100
775#define ATXCTL_MT 0x00000200
776#define ATXCTL_NUC 0x00003000
777#define ATXCTL_BEN 0x00010000
778#define ATXCTL_BMUX 0x00700000
779#define ATXCTL_B24 0x01000000
780#define ATXCTL_CPF 0x02000000
781#define ATXCTL_RIV 0x10000000
782#define ATXCTL_LIV 0x20000000
783#define ATXCTL_RSAT 0x40000000
784#define ATXCTL_LSAT 0x80000000
785
786
787union dao_dirty {
788 struct {
789 u16 atxcsl:1;
790 u16 rsv:15;
791 } bf;
792 u16 data;
793};
794
795
796struct dao_ctrl_blk {
797
798 unsigned int atxcsl;
799 union dao_dirty dirty;
800};
801
802
803#define ARXCTL_EN 0x00000001
804
805
806union daio_mgr_dirty {
807 struct {
808 u32 atxctl:8;
809 u32 arxctl:8;
810 u32 daoimap:1;
811 u32 rsv:15;
812 } bf;
813 u32 data;
814};
815
816
817struct daio_mgr_ctrl_blk {
818 struct daoimap daoimap;
819 unsigned int txctl[8];
820 unsigned int rxctl[8];
821 union daio_mgr_dirty dirty;
822};
823
824static int dai_srt_set_srco(void *blk, unsigned int src)
825{
826 struct dai_ctrl_blk *ctl = blk;
827
828 set_field(&ctl->srt, SRTCTL_SRCO, src);
829 ctl->dirty.bf.srt = 1;
830 return 0;
831}
832
833static int dai_srt_set_srcm(void *blk, unsigned int src)
834{
835 struct dai_ctrl_blk *ctl = blk;
836
837 set_field(&ctl->srt, SRTCTL_SRCM, src);
838 ctl->dirty.bf.srt = 1;
839 return 0;
840}
841
842static int dai_srt_set_rsr(void *blk, unsigned int rsr)
843{
844 struct dai_ctrl_blk *ctl = blk;
845
846 set_field(&ctl->srt, SRTCTL_RSR, rsr);
847 ctl->dirty.bf.srt = 1;
848 return 0;
849}
850
851static int dai_srt_set_drat(void *blk, unsigned int drat)
852{
853 struct dai_ctrl_blk *ctl = blk;
854
855 set_field(&ctl->srt, SRTCTL_DRAT, drat);
856 ctl->dirty.bf.srt = 1;
857 return 0;
858}
859
860static int dai_srt_set_ec(void *blk, unsigned int ec)
861{
862 struct dai_ctrl_blk *ctl = blk;
863
864 set_field(&ctl->srt, SRTCTL_EC, ec ? 1 : 0);
865 ctl->dirty.bf.srt = 1;
866 return 0;
867}
868
869static int dai_srt_set_et(void *blk, unsigned int et)
870{
871 struct dai_ctrl_blk *ctl = blk;
872
873 set_field(&ctl->srt, SRTCTL_ET, et ? 1 : 0);
874 ctl->dirty.bf.srt = 1;
875 return 0;
876}
877
878static int dai_commit_write(struct hw *hw, unsigned int idx, void *blk)
879{
880 struct dai_ctrl_blk *ctl = blk;
881
882 if (ctl->dirty.bf.srt) {
883 hw_write_20kx(hw, AUDIO_IO_RX_SRT_CTL+0x40*idx, ctl->srt);
884 ctl->dirty.bf.srt = 0;
885 }
886
887 return 0;
888}
889
890static int dai_get_ctrl_blk(void **rblk)
891{
892 struct dai_ctrl_blk *blk;
893
894 *rblk = NULL;
895 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
896 if (!blk)
897 return -ENOMEM;
898
899 *rblk = blk;
900
901 return 0;
902}
903
904static int dai_put_ctrl_blk(void *blk)
905{
906 kfree(blk);
907
908 return 0;
909}
910
911static int dao_set_spos(void *blk, unsigned int spos)
912{
913 ((struct dao_ctrl_blk *)blk)->atxcsl = spos;
914 ((struct dao_ctrl_blk *)blk)->dirty.bf.atxcsl = 1;
915 return 0;
916}
917
918static int dao_commit_write(struct hw *hw, unsigned int idx, void *blk)
919{
920 struct dao_ctrl_blk *ctl = blk;
921
922 if (ctl->dirty.bf.atxcsl) {
923 if (idx < 4) {
924
925 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+0x40*idx,
926 ctl->atxcsl);
927 }
928 ctl->dirty.bf.atxcsl = 0;
929 }
930
931 return 0;
932}
933
934static int dao_get_spos(void *blk, unsigned int *spos)
935{
936 *spos = ((struct dao_ctrl_blk *)blk)->atxcsl;
937 return 0;
938}
939
940static int dao_get_ctrl_blk(void **rblk)
941{
942 struct dao_ctrl_blk *blk;
943
944 *rblk = NULL;
945 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
946 if (!blk)
947 return -ENOMEM;
948
949 *rblk = blk;
950
951 return 0;
952}
953
954static int dao_put_ctrl_blk(void *blk)
955{
956 kfree(blk);
957
958 return 0;
959}
960
961static int daio_mgr_enb_dai(void *blk, unsigned int idx)
962{
963 struct daio_mgr_ctrl_blk *ctl = blk;
964
965 set_field(&ctl->rxctl[idx], ARXCTL_EN, 1);
966 ctl->dirty.bf.arxctl |= (0x1 << idx);
967 return 0;
968}
969
970static int daio_mgr_dsb_dai(void *blk, unsigned int idx)
971{
972 struct daio_mgr_ctrl_blk *ctl = blk;
973
974 set_field(&ctl->rxctl[idx], ARXCTL_EN, 0);
975
976 ctl->dirty.bf.arxctl |= (0x1 << idx);
977 return 0;
978}
979
980static int daio_mgr_enb_dao(void *blk, unsigned int idx)
981{
982 struct daio_mgr_ctrl_blk *ctl = blk;
983
984 set_field(&ctl->txctl[idx], ATXCTL_EN, 1);
985 ctl->dirty.bf.atxctl |= (0x1 << idx);
986 return 0;
987}
988
989static int daio_mgr_dsb_dao(void *blk, unsigned int idx)
990{
991 struct daio_mgr_ctrl_blk *ctl = blk;
992
993 set_field(&ctl->txctl[idx], ATXCTL_EN, 0);
994 ctl->dirty.bf.atxctl |= (0x1 << idx);
995 return 0;
996}
997
998static int daio_mgr_dao_init(void *blk, unsigned int idx, unsigned int conf)
999{
1000 struct daio_mgr_ctrl_blk *ctl = blk;
1001
1002 if (idx < 4) {
1003
1004 switch ((conf & 0x7)) {
1005 case 1:
1006 set_field(&ctl->txctl[idx], ATXCTL_NUC, 0);
1007 break;
1008 case 2:
1009 set_field(&ctl->txctl[idx], ATXCTL_NUC, 1);
1010 break;
1011 case 4:
1012 set_field(&ctl->txctl[idx], ATXCTL_NUC, 2);
1013 break;
1014 case 8:
1015 set_field(&ctl->txctl[idx], ATXCTL_NUC, 3);
1016 break;
1017 default:
1018 break;
1019 }
1020
1021 set_field(&ctl->txctl[idx], ATXCTL_CD, (!(conf & 0x7)));
1022
1023 set_field(&ctl->txctl[idx], ATXCTL_LIV, (conf >> 4) & 0x1);
1024
1025 set_field(&ctl->txctl[idx], ATXCTL_RIV, (conf >> 4) & 0x1);
1026 set_field(&ctl->txctl[idx], ATXCTL_RAW,
1027 ((conf >> 3) & 0x1) ? 0 : 0);
1028 ctl->dirty.bf.atxctl |= (0x1 << idx);
1029 } else {
1030
1031
1032 }
1033 return 0;
1034}
1035
1036static int daio_mgr_set_imaparc(void *blk, unsigned int slot)
1037{
1038 struct daio_mgr_ctrl_blk *ctl = blk;
1039
1040 set_field(&ctl->daoimap.aim, AIM_ARC, slot);
1041 ctl->dirty.bf.daoimap = 1;
1042 return 0;
1043}
1044
1045static int daio_mgr_set_imapnxt(void *blk, unsigned int next)
1046{
1047 struct daio_mgr_ctrl_blk *ctl = blk;
1048
1049 set_field(&ctl->daoimap.aim, AIM_NXT, next);
1050 ctl->dirty.bf.daoimap = 1;
1051 return 0;
1052}
1053
1054static int daio_mgr_set_imapaddr(void *blk, unsigned int addr)
1055{
1056 ((struct daio_mgr_ctrl_blk *)blk)->daoimap.idx = addr;
1057 ((struct daio_mgr_ctrl_blk *)blk)->dirty.bf.daoimap = 1;
1058 return 0;
1059}
1060
1061static int daio_mgr_commit_write(struct hw *hw, void *blk)
1062{
1063 struct daio_mgr_ctrl_blk *ctl = blk;
1064 unsigned int data;
1065 int i;
1066
1067 for (i = 0; i < 8; i++) {
1068 if ((ctl->dirty.bf.atxctl & (0x1 << i))) {
1069 data = ctl->txctl[i];
1070 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1071 ctl->dirty.bf.atxctl &= ~(0x1 << i);
1072 mdelay(1);
1073 }
1074 if ((ctl->dirty.bf.arxctl & (0x1 << i))) {
1075 data = ctl->rxctl[i];
1076 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1077 ctl->dirty.bf.arxctl &= ~(0x1 << i);
1078 mdelay(1);
1079 }
1080 }
1081 if (ctl->dirty.bf.daoimap) {
1082 hw_write_20kx(hw, AUDIO_IO_AIM+ctl->daoimap.idx*4,
1083 ctl->daoimap.aim);
1084 ctl->dirty.bf.daoimap = 0;
1085 }
1086
1087 return 0;
1088}
1089
1090static int daio_mgr_get_ctrl_blk(struct hw *hw, void **rblk)
1091{
1092 struct daio_mgr_ctrl_blk *blk;
1093 int i;
1094
1095 *rblk = NULL;
1096 blk = kzalloc(sizeof(*blk), GFP_KERNEL);
1097 if (!blk)
1098 return -ENOMEM;
1099
1100 for (i = 0; i < 8; i++) {
1101 blk->txctl[i] = hw_read_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i));
1102 blk->rxctl[i] = hw_read_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i));
1103 }
1104
1105 *rblk = blk;
1106
1107 return 0;
1108}
1109
1110static int daio_mgr_put_ctrl_blk(void *blk)
1111{
1112 kfree(blk);
1113
1114 return 0;
1115}
1116
1117
1118static int set_timer_irq(struct hw *hw, int enable)
1119{
1120 hw_write_20kx(hw, GIE, enable ? IT_INT : 0);
1121 return 0;
1122}
1123
1124static int set_timer_tick(struct hw *hw, unsigned int ticks)
1125{
1126 if (ticks)
1127 ticks |= TIMR_IE | TIMR_IP;
1128 hw_write_20kx(hw, TIMR, ticks);
1129 return 0;
1130}
1131
1132static unsigned int get_wc(struct hw *hw)
1133{
1134 return hw_read_20kx(hw, WC);
1135}
1136
1137
1138struct dac_conf {
1139 unsigned int msr;
1140};
1141
1142struct adc_conf {
1143 unsigned int msr;
1144 unsigned char input;
1145 unsigned char mic20db;
1146};
1147
1148struct daio_conf {
1149 unsigned int msr;
1150};
1151
1152struct trn_conf {
1153 unsigned long vm_pgt_phys;
1154};
1155
1156static int hw_daio_init(struct hw *hw, const struct daio_conf *info)
1157{
1158 u32 data;
1159 int i;
1160
1161
1162
1163 if (1 == info->msr) {
1164 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x01010101);
1165 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x01010101);
1166 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1167 } else if (2 == info->msr) {
1168 if (hw->model != CTSB1270) {
1169 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11111111);
1170 } else {
1171
1172 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x11011111);
1173 }
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x11111111);
1184 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1185 } else if ((4 == info->msr) && (hw->model == CTSB1270)) {
1186 hw_write_20kx(hw, AUDIO_IO_MCLK, 0x21011111);
1187 hw_write_20kx(hw, AUDIO_IO_TX_BLRCLK, 0x21212121);
1188 hw_write_20kx(hw, AUDIO_IO_RX_BLRCLK, 0);
1189 } else {
1190 printk(KERN_ALERT "ctxfi: ERROR!!! Invalid sampling rate!!!\n");
1191 return -EINVAL;
1192 }
1193
1194 for (i = 0; i < 8; i++) {
1195 if (i <= 3) {
1196
1197
1198
1199 if (i == 3)
1200 data = 0x1001001;
1201 else
1202 data = 0x1000001;
1203
1204 hw_write_20kx(hw, (AUDIO_IO_TX_CTL+(0x40*i)), data);
1205 hw_write_20kx(hw, (AUDIO_IO_RX_CTL+(0x40*i)), data);
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_L+(0x40*i),
1218 0x02109204);
1219
1220 hw_write_20kx(hw, AUDIO_IO_TX_CSTAT_H+(0x40*i), 0x0B);
1221 } else {
1222
1223
1224 data = 0x11;
1225 hw_write_20kx(hw, AUDIO_IO_RX_CTL+(0x40*i), data);
1226 if (2 == info->msr) {
1227
1228 data |= 0x1000;
1229 } else if (4 == info->msr) {
1230
1231 data |= 0x2000;
1232 }
1233 hw_write_20kx(hw, AUDIO_IO_TX_CTL+(0x40*i), data);
1234 }
1235 }
1236
1237 return 0;
1238}
1239
1240
1241static int hw_trn_init(struct hw *hw, const struct trn_conf *info)
1242{
1243 u32 vmctl, data;
1244 u32 ptp_phys_low, ptp_phys_high;
1245 int i;
1246
1247
1248 if ((~0UL) == info->vm_pgt_phys) {
1249 printk(KERN_ALERT "ctxfi: "
1250 "Wrong device page table page address!!!\n");
1251 return -1;
1252 }
1253
1254 vmctl = 0x80000C0F;
1255 ptp_phys_low = (u32)info->vm_pgt_phys;
1256 ptp_phys_high = upper_32_bits(info->vm_pgt_phys);
1257 if (sizeof(void *) == 8)
1258 vmctl |= (3 << 8);
1259
1260 for (i = 0; i < 64; i++) {
1261 hw_write_20kx(hw, VMEM_PTPAL+(16*i), ptp_phys_low);
1262 hw_write_20kx(hw, VMEM_PTPAH+(16*i), ptp_phys_high);
1263 }
1264
1265 hw_write_20kx(hw, VMEM_CTL, vmctl);
1266
1267 hw_write_20kx(hw, TRANSPORT_CTL, 0x03);
1268 hw_write_20kx(hw, TRANSPORT_INT, 0x200c01);
1269
1270 data = hw_read_20kx(hw, TRANSPORT_ENB);
1271 hw_write_20kx(hw, TRANSPORT_ENB, (data | 0x03));
1272
1273 return 0;
1274}
1275
1276
1277#define GCTL_AIE 0x00000001
1278#define GCTL_UAA 0x00000002
1279#define GCTL_DPC 0x00000004
1280#define GCTL_DBP 0x00000008
1281#define GCTL_ABP 0x00000010
1282#define GCTL_TBP 0x00000020
1283#define GCTL_SBP 0x00000040
1284#define GCTL_FBP 0x00000080
1285#define GCTL_ME 0x00000100
1286#define GCTL_AID 0x00001000
1287
1288#define PLLCTL_SRC 0x00000007
1289#define PLLCTL_SPE 0x00000008
1290#define PLLCTL_RD 0x000000F0
1291#define PLLCTL_FD 0x0001FF00
1292#define PLLCTL_OD 0x00060000
1293#define PLLCTL_B 0x00080000
1294#define PLLCTL_AS 0x00100000
1295#define PLLCTL_LF 0x03E00000
1296#define PLLCTL_SPS 0x1C000000
1297#define PLLCTL_AD 0x60000000
1298
1299#define PLLSTAT_CCS 0x00000007
1300#define PLLSTAT_SPL 0x00000008
1301#define PLLSTAT_CRD 0x000000F0
1302#define PLLSTAT_CFD 0x0001FF00
1303#define PLLSTAT_SL 0x00020000
1304#define PLLSTAT_FAS 0x00040000
1305#define PLLSTAT_B 0x00080000
1306#define PLLSTAT_PD 0x00100000
1307#define PLLSTAT_OCA 0x00200000
1308#define PLLSTAT_NCA 0x00400000
1309
1310static int hw_pll_init(struct hw *hw, unsigned int rsr)
1311{
1312 unsigned int pllenb;
1313 unsigned int pllctl;
1314 unsigned int pllstat;
1315 int i;
1316
1317 pllenb = 0xB;
1318 hw_write_20kx(hw, PLL_ENB, pllenb);
1319 pllctl = 0x20C00000;
1320 set_field(&pllctl, PLLCTL_B, 0);
1321 set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 4 : 147 - 4);
1322 set_field(&pllctl, PLLCTL_RD, 48000 == rsr ? 1 - 1 : 10 - 1);
1323 hw_write_20kx(hw, PLL_CTL, pllctl);
1324 mdelay(40);
1325
1326 pllctl = hw_read_20kx(hw, PLL_CTL);
1327 set_field(&pllctl, PLLCTL_FD, 48000 == rsr ? 16 - 2 : 147 - 2);
1328 hw_write_20kx(hw, PLL_CTL, pllctl);
1329 mdelay(40);
1330
1331 for (i = 0; i < 1000; i++) {
1332 pllstat = hw_read_20kx(hw, PLL_STAT);
1333 if (get_field(pllstat, PLLSTAT_PD))
1334 continue;
1335
1336 if (get_field(pllstat, PLLSTAT_B) !=
1337 get_field(pllctl, PLLCTL_B))
1338 continue;
1339
1340 if (get_field(pllstat, PLLSTAT_CCS) !=
1341 get_field(pllctl, PLLCTL_SRC))
1342 continue;
1343
1344 if (get_field(pllstat, PLLSTAT_CRD) !=
1345 get_field(pllctl, PLLCTL_RD))
1346 continue;
1347
1348 if (get_field(pllstat, PLLSTAT_CFD) !=
1349 get_field(pllctl, PLLCTL_FD))
1350 continue;
1351
1352 break;
1353 }
1354 if (i >= 1000) {
1355 printk(KERN_ALERT "ctxfi: PLL initialization failed!!!\n");
1356 return -EBUSY;
1357 }
1358
1359 return 0;
1360}
1361
1362static int hw_auto_init(struct hw *hw)
1363{
1364 unsigned int gctl;
1365 int i;
1366
1367 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1368 set_field(&gctl, GCTL_AIE, 0);
1369 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1370 set_field(&gctl, GCTL_AIE, 1);
1371 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
1372 mdelay(10);
1373 for (i = 0; i < 400000; i++) {
1374 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
1375 if (get_field(gctl, GCTL_AID))
1376 break;
1377 }
1378 if (!get_field(gctl, GCTL_AID)) {
1379 printk(KERN_ALERT "ctxfi: Card Auto-init failed!!!\n");
1380 return -EBUSY;
1381 }
1382
1383 return 0;
1384}
1385
1386
1387
1388#define CS4382_MC1 0x1
1389#define CS4382_MC2 0x2
1390#define CS4382_MC3 0x3
1391#define CS4382_FC 0x4
1392#define CS4382_IC 0x5
1393#define CS4382_XC1 0x6
1394#define CS4382_VCA1 0x7
1395#define CS4382_VCB1 0x8
1396#define CS4382_XC2 0x9
1397#define CS4382_VCA2 0xA
1398#define CS4382_VCB2 0xB
1399#define CS4382_XC3 0xC
1400#define CS4382_VCA3 0xD
1401#define CS4382_VCB3 0xE
1402#define CS4382_XC4 0xF
1403#define CS4382_VCA4 0x10
1404#define CS4382_VCB4 0x11
1405#define CS4382_CREV 0x12
1406
1407
1408#define STATE_LOCKED 0x00
1409#define STATE_UNLOCKED 0xAA
1410#define DATA_READY 0x800000
1411#define DATA_ABORT 0x10000
1412
1413#define I2C_STATUS_DCM 0x00000001
1414#define I2C_STATUS_BC 0x00000006
1415#define I2C_STATUS_APD 0x00000008
1416#define I2C_STATUS_AB 0x00010000
1417#define I2C_STATUS_DR 0x00800000
1418
1419#define I2C_ADDRESS_PTAD 0x0000FFFF
1420#define I2C_ADDRESS_SLAD 0x007F0000
1421
1422struct regs_cs4382 {
1423 u32 mode_control_1;
1424 u32 mode_control_2;
1425 u32 mode_control_3;
1426
1427 u32 filter_control;
1428 u32 invert_control;
1429
1430 u32 mix_control_P1;
1431 u32 vol_control_A1;
1432 u32 vol_control_B1;
1433
1434 u32 mix_control_P2;
1435 u32 vol_control_A2;
1436 u32 vol_control_B2;
1437
1438 u32 mix_control_P3;
1439 u32 vol_control_A3;
1440 u32 vol_control_B3;
1441
1442 u32 mix_control_P4;
1443 u32 vol_control_A4;
1444 u32 vol_control_B4;
1445};
1446
1447static int hw20k2_i2c_unlock_full_access(struct hw *hw)
1448{
1449 u8 UnlockKeySequence_FLASH_FULLACCESS_MODE[2] = {0xB3, 0xD4};
1450
1451
1452 hw_write_20kx(hw, I2C_IF_WLOCK,
1453 UnlockKeySequence_FLASH_FULLACCESS_MODE[0]);
1454 hw_write_20kx(hw, I2C_IF_WLOCK,
1455 UnlockKeySequence_FLASH_FULLACCESS_MODE[1]);
1456
1457 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_UNLOCKED)
1458 return 0;
1459
1460 return -1;
1461}
1462
1463static int hw20k2_i2c_lock_chip(struct hw *hw)
1464{
1465
1466 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1467 hw_write_20kx(hw, I2C_IF_WLOCK, STATE_LOCKED);
1468 if (hw_read_20kx(hw, I2C_IF_WLOCK) == STATE_LOCKED)
1469 return 0;
1470
1471 return -1;
1472}
1473
1474static int hw20k2_i2c_init(struct hw *hw, u8 dev_id, u8 addr_size, u8 data_size)
1475{
1476 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1477 int err;
1478 unsigned int i2c_status;
1479 unsigned int i2c_addr;
1480
1481 err = hw20k2_i2c_unlock_full_access(hw);
1482 if (err < 0)
1483 return err;
1484
1485 hw20k2->addr_size = addr_size;
1486 hw20k2->data_size = data_size;
1487 hw20k2->dev_id = dev_id;
1488
1489 i2c_addr = 0;
1490 set_field(&i2c_addr, I2C_ADDRESS_SLAD, dev_id);
1491
1492 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1493
1494 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1495
1496 set_field(&i2c_status, I2C_STATUS_DCM, 1);
1497
1498 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1499
1500 return 0;
1501}
1502
1503static int hw20k2_i2c_uninit(struct hw *hw)
1504{
1505 unsigned int i2c_status;
1506 unsigned int i2c_addr;
1507
1508 i2c_addr = 0;
1509 set_field(&i2c_addr, I2C_ADDRESS_SLAD, 0x57);
1510
1511 hw_write_20kx(hw, I2C_IF_ADDRESS, i2c_addr);
1512
1513 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1514
1515 set_field(&i2c_status, I2C_STATUS_DCM, 0);
1516
1517 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1518
1519 return hw20k2_i2c_lock_chip(hw);
1520}
1521
1522static int hw20k2_i2c_wait_data_ready(struct hw *hw)
1523{
1524 int i = 0x400000;
1525 unsigned int ret;
1526
1527 do {
1528 ret = hw_read_20kx(hw, I2C_IF_STATUS);
1529 } while ((!(ret & DATA_READY)) && --i);
1530
1531 return i;
1532}
1533
1534static int hw20k2_i2c_read(struct hw *hw, u16 addr, u32 *datap)
1535{
1536 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1537 unsigned int i2c_status;
1538
1539 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1540 set_field(&i2c_status, I2C_STATUS_BC,
1541 (4 == hw20k2->addr_size) ? 0 : hw20k2->addr_size);
1542 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1543 if (!hw20k2_i2c_wait_data_ready(hw))
1544 return -1;
1545
1546 hw_write_20kx(hw, I2C_IF_WDATA, addr);
1547 if (!hw20k2_i2c_wait_data_ready(hw))
1548 return -1;
1549
1550
1551 hw_write_20kx(hw, I2C_IF_RDATA, 0);
1552 if (!hw20k2_i2c_wait_data_ready(hw))
1553 return -1;
1554
1555 *datap = hw_read_20kx(hw, I2C_IF_RDATA);
1556
1557 return 0;
1558}
1559
1560static int hw20k2_i2c_write(struct hw *hw, u16 addr, u32 data)
1561{
1562 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1563 unsigned int i2c_data = (data << (hw20k2->addr_size * 8)) | addr;
1564 unsigned int i2c_status;
1565
1566 i2c_status = hw_read_20kx(hw, I2C_IF_STATUS);
1567
1568 set_field(&i2c_status, I2C_STATUS_BC,
1569 (4 == (hw20k2->addr_size + hw20k2->data_size)) ?
1570 0 : (hw20k2->addr_size + hw20k2->data_size));
1571
1572 hw_write_20kx(hw, I2C_IF_STATUS, i2c_status);
1573 hw20k2_i2c_wait_data_ready(hw);
1574
1575 hw_write_20kx(hw, I2C_IF_WDATA, 0);
1576 hw20k2_i2c_wait_data_ready(hw);
1577
1578
1579 hw_write_20kx(hw, I2C_IF_WDATA, i2c_data);
1580 hw20k2_i2c_wait_data_ready(hw);
1581
1582 return 0;
1583}
1584
1585static void hw_dac_stop(struct hw *hw)
1586{
1587 u32 data;
1588 data = hw_read_20kx(hw, GPIO_DATA);
1589 data &= 0xFFFFFFFD;
1590 hw_write_20kx(hw, GPIO_DATA, data);
1591 mdelay(10);
1592}
1593
1594static void hw_dac_start(struct hw *hw)
1595{
1596 u32 data;
1597 data = hw_read_20kx(hw, GPIO_DATA);
1598 data |= 0x2;
1599 hw_write_20kx(hw, GPIO_DATA, data);
1600 mdelay(50);
1601}
1602
1603static void hw_dac_reset(struct hw *hw)
1604{
1605 hw_dac_stop(hw);
1606 hw_dac_start(hw);
1607}
1608
1609static int hw_dac_init(struct hw *hw, const struct dac_conf *info)
1610{
1611 int err;
1612 u32 data;
1613 int i;
1614 struct regs_cs4382 cs_read = {0};
1615 struct regs_cs4382 cs_def = {
1616 0x00000001,
1617 0x00000000,
1618 0x00000084,
1619 0x00000000,
1620 0x00000000,
1621 0x00000024,
1622 0x00000000,
1623 0x00000000,
1624 0x00000024,
1625 0x00000000,
1626 0x00000000,
1627 0x00000024,
1628 0x00000000,
1629 0x00000000,
1630 0x00000024,
1631 0x00000000,
1632 0x00000000
1633 };
1634
1635 if (hw->model == CTSB1270) {
1636 hw_dac_stop(hw);
1637 data = hw_read_20kx(hw, GPIO_DATA);
1638 data &= ~0x0600;
1639 if (1 == info->msr)
1640 data |= 0x0000;
1641 else if (2 == info->msr)
1642 data |= 0x0200;
1643 else
1644 data |= 0x0600;
1645 hw_write_20kx(hw, GPIO_DATA, data);
1646 hw_dac_start(hw);
1647 return 0;
1648 }
1649
1650
1651 data = hw_read_20kx(hw, GPIO_CTRL);
1652 data |= 0x02;
1653 hw_write_20kx(hw, GPIO_CTRL, data);
1654
1655 err = hw20k2_i2c_init(hw, 0x18, 1, 1);
1656 if (err < 0)
1657 goto End;
1658
1659 for (i = 0; i < 2; i++) {
1660
1661
1662 hw_dac_reset(hw);
1663 hw_dac_reset(hw);
1664
1665 if (hw20k2_i2c_read(hw, CS4382_MC1, &cs_read.mode_control_1))
1666 continue;
1667
1668 if (hw20k2_i2c_read(hw, CS4382_MC2, &cs_read.mode_control_2))
1669 continue;
1670
1671 if (hw20k2_i2c_read(hw, CS4382_MC3, &cs_read.mode_control_3))
1672 continue;
1673
1674 if (hw20k2_i2c_read(hw, CS4382_FC, &cs_read.filter_control))
1675 continue;
1676
1677 if (hw20k2_i2c_read(hw, CS4382_IC, &cs_read.invert_control))
1678 continue;
1679
1680 if (hw20k2_i2c_read(hw, CS4382_XC1, &cs_read.mix_control_P1))
1681 continue;
1682
1683 if (hw20k2_i2c_read(hw, CS4382_VCA1, &cs_read.vol_control_A1))
1684 continue;
1685
1686 if (hw20k2_i2c_read(hw, CS4382_VCB1, &cs_read.vol_control_B1))
1687 continue;
1688
1689 if (hw20k2_i2c_read(hw, CS4382_XC2, &cs_read.mix_control_P2))
1690 continue;
1691
1692 if (hw20k2_i2c_read(hw, CS4382_VCA2, &cs_read.vol_control_A2))
1693 continue;
1694
1695 if (hw20k2_i2c_read(hw, CS4382_VCB2, &cs_read.vol_control_B2))
1696 continue;
1697
1698 if (hw20k2_i2c_read(hw, CS4382_XC3, &cs_read.mix_control_P3))
1699 continue;
1700
1701 if (hw20k2_i2c_read(hw, CS4382_VCA3, &cs_read.vol_control_A3))
1702 continue;
1703
1704 if (hw20k2_i2c_read(hw, CS4382_VCB3, &cs_read.vol_control_B3))
1705 continue;
1706
1707 if (hw20k2_i2c_read(hw, CS4382_XC4, &cs_read.mix_control_P4))
1708 continue;
1709
1710 if (hw20k2_i2c_read(hw, CS4382_VCA4, &cs_read.vol_control_A4))
1711 continue;
1712
1713 if (hw20k2_i2c_read(hw, CS4382_VCB4, &cs_read.vol_control_B4))
1714 continue;
1715
1716 if (memcmp(&cs_read, &cs_def, sizeof(cs_read)))
1717 continue;
1718 else
1719 break;
1720 }
1721
1722 if (i >= 2)
1723 goto End;
1724
1725
1726
1727 hw20k2_i2c_write(hw, CS4382_MC1, 0x80);
1728 hw20k2_i2c_write(hw, CS4382_MC2, 0x10);
1729 if (1 == info->msr) {
1730 hw20k2_i2c_write(hw, CS4382_XC1, 0x24);
1731 hw20k2_i2c_write(hw, CS4382_XC2, 0x24);
1732 hw20k2_i2c_write(hw, CS4382_XC3, 0x24);
1733 hw20k2_i2c_write(hw, CS4382_XC4, 0x24);
1734 } else if (2 == info->msr) {
1735 hw20k2_i2c_write(hw, CS4382_XC1, 0x25);
1736 hw20k2_i2c_write(hw, CS4382_XC2, 0x25);
1737 hw20k2_i2c_write(hw, CS4382_XC3, 0x25);
1738 hw20k2_i2c_write(hw, CS4382_XC4, 0x25);
1739 } else {
1740 hw20k2_i2c_write(hw, CS4382_XC1, 0x26);
1741 hw20k2_i2c_write(hw, CS4382_XC2, 0x26);
1742 hw20k2_i2c_write(hw, CS4382_XC3, 0x26);
1743 hw20k2_i2c_write(hw, CS4382_XC4, 0x26);
1744 }
1745
1746 return 0;
1747End:
1748
1749 hw20k2_i2c_uninit(hw);
1750 return -1;
1751}
1752
1753
1754#define MAKE_WM8775_ADDR(addr, data) (u32)(((addr<<1)&0xFE)|((data>>8)&0x1))
1755#define MAKE_WM8775_DATA(data) (u32)(data&0xFF)
1756
1757#define WM8775_IC 0x0B
1758#define WM8775_MMC 0x0C
1759#define WM8775_AADCL 0x0E
1760#define WM8775_AADCR 0x0F
1761#define WM8775_ADCMC 0x15
1762#define WM8775_RESET 0x17
1763
1764static int hw_is_adc_input_selected(struct hw *hw, enum ADCSRC type)
1765{
1766 u32 data;
1767 if (hw->model == CTSB1270) {
1768
1769
1770 return 1;
1771 }
1772 data = hw_read_20kx(hw, GPIO_DATA);
1773 switch (type) {
1774 case ADC_MICIN:
1775 data = (data & (0x1 << 14)) ? 1 : 0;
1776 break;
1777 case ADC_LINEIN:
1778 data = (data & (0x1 << 14)) ? 0 : 1;
1779 break;
1780 default:
1781 data = 0;
1782 }
1783 return data;
1784}
1785
1786#define MIC_BOOST_0DB 0xCF
1787#define MIC_BOOST_STEPS_PER_DB 2
1788
1789static void hw_wm8775_input_select(struct hw *hw, u8 input, s8 gain_in_db)
1790{
1791 u32 adcmc, gain;
1792
1793 if (input > 3)
1794 input = 3;
1795
1796 adcmc = ((u32)1 << input) | 0x100;
1797
1798 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_ADCMC, adcmc),
1799 MAKE_WM8775_DATA(adcmc));
1800
1801 if (gain_in_db < -103)
1802 gain_in_db = -103;
1803 if (gain_in_db > 24)
1804 gain_in_db = 24;
1805
1806 gain = gain_in_db * MIC_BOOST_STEPS_PER_DB + MIC_BOOST_0DB;
1807
1808 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCL, gain),
1809 MAKE_WM8775_DATA(gain));
1810
1811 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_AADCR, gain),
1812 MAKE_WM8775_DATA(gain));
1813}
1814
1815static int hw_adc_input_select(struct hw *hw, enum ADCSRC type)
1816{
1817 u32 data;
1818 data = hw_read_20kx(hw, GPIO_DATA);
1819 switch (type) {
1820 case ADC_MICIN:
1821 data |= (0x1 << 14);
1822 hw_write_20kx(hw, GPIO_DATA, data);
1823 hw_wm8775_input_select(hw, 0, 20);
1824 break;
1825 case ADC_LINEIN:
1826 data &= ~(0x1 << 14);
1827 hw_write_20kx(hw, GPIO_DATA, data);
1828 hw_wm8775_input_select(hw, 1, 0);
1829 break;
1830 default:
1831 break;
1832 }
1833
1834 return 0;
1835}
1836
1837static int hw_adc_init(struct hw *hw, const struct adc_conf *info)
1838{
1839 int err;
1840 u32 data, ctl;
1841
1842
1843 data = hw_read_20kx(hw, GPIO_CTRL);
1844 data |= (0x1 << 15);
1845 hw_write_20kx(hw, GPIO_CTRL, data);
1846
1847
1848 err = hw20k2_i2c_init(hw, 0x1A, 1, 1);
1849 if (err < 0) {
1850 printk(KERN_ALERT "ctxfi: Failure to acquire I2C!!!\n");
1851 goto error;
1852 }
1853
1854
1855 data = hw_read_20kx(hw, GPIO_DATA);
1856 data &= ~(0x1 << 15);
1857 hw_write_20kx(hw, GPIO_DATA, data);
1858
1859 if (hw->model == CTSB1270) {
1860
1861 data &= ~0x0C;
1862 if (1 == info->msr)
1863 data |= 0x00;
1864 else if (2 == info->msr)
1865 data |= 0x08;
1866 else
1867 data |= 0x04;
1868 hw_write_20kx(hw, GPIO_DATA, data);
1869 }
1870
1871 mdelay(10);
1872
1873 data |= (0x1 << 15);
1874 hw_write_20kx(hw, GPIO_DATA, data);
1875 mdelay(50);
1876
1877
1878
1879
1880 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_IC, 0x26),
1881 MAKE_WM8775_DATA(0x26));
1882
1883
1884 if (1 == info->msr) {
1885
1886 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x02),
1887 MAKE_WM8775_DATA(0x02));
1888 } else if ((2 == info->msr) || (4 == info->msr)) {
1889
1890 hw20k2_i2c_write(hw, MAKE_WM8775_ADDR(WM8775_MMC, 0x0A),
1891 MAKE_WM8775_DATA(0x0A));
1892 } else {
1893 printk(KERN_ALERT "ctxfi: Invalid master sampling "
1894 "rate (msr %d)!!!\n", info->msr);
1895 err = -EINVAL;
1896 goto error;
1897 }
1898
1899 if (hw->model != CTSB1270) {
1900
1901 ctl = hw_read_20kx(hw, GPIO_CTRL);
1902 ctl |= 0x1 << 14;
1903 hw_write_20kx(hw, GPIO_CTRL, ctl);
1904 hw_adc_input_select(hw, ADC_LINEIN);
1905 } else {
1906 hw_wm8775_input_select(hw, 0, 0);
1907 }
1908
1909 return 0;
1910error:
1911 hw20k2_i2c_uninit(hw);
1912 return err;
1913}
1914
1915static struct capabilities hw_capabilities(struct hw *hw)
1916{
1917 struct capabilities cap;
1918
1919 cap.digit_io_switch = 0;
1920 cap.dedicated_mic = hw->model == CTSB1270;
1921 cap.output_switch = hw->model == CTSB1270;
1922 cap.mic_source_switch = hw->model == CTSB1270;
1923
1924 return cap;
1925}
1926
1927static int hw_output_switch_get(struct hw *hw)
1928{
1929 u32 data = hw_read_20kx(hw, GPIO_EXT_DATA);
1930
1931 switch (data & 0x30) {
1932 case 0x00:
1933 return 0;
1934 case 0x10:
1935 return 1;
1936 case 0x20:
1937 return 2;
1938 default:
1939 return 3;
1940 }
1941}
1942
1943static int hw_output_switch_put(struct hw *hw, int position)
1944{
1945 u32 data;
1946
1947 if (position == hw_output_switch_get(hw))
1948 return 0;
1949
1950
1951 data = hw_read_20kx(hw, GPIO_DATA);
1952 data |= (0x03 << 11);
1953 hw_write_20kx(hw, GPIO_DATA, data);
1954
1955 data = hw_read_20kx(hw, GPIO_EXT_DATA) & ~0x30;
1956 switch (position) {
1957 case 0:
1958 break;
1959 case 1:
1960 data |= 0x10;
1961 break;
1962 default:
1963 data |= 0x20;
1964 }
1965 hw_write_20kx(hw, GPIO_EXT_DATA, data);
1966
1967
1968 data = hw_read_20kx(hw, GPIO_DATA);
1969 data &= ~(0x03 << 11);
1970 hw_write_20kx(hw, GPIO_DATA, data);
1971
1972 return 1;
1973}
1974
1975static int hw_mic_source_switch_get(struct hw *hw)
1976{
1977 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1978
1979 return hw20k2->mic_source;
1980}
1981
1982static int hw_mic_source_switch_put(struct hw *hw, int position)
1983{
1984 struct hw20k2 *hw20k2 = (struct hw20k2 *)hw;
1985
1986 if (position == hw20k2->mic_source)
1987 return 0;
1988
1989 switch (position) {
1990 case 0:
1991 hw_wm8775_input_select(hw, 0, 0);
1992 break;
1993 case 1:
1994 hw_wm8775_input_select(hw, 1, 0);
1995 break;
1996 case 2:
1997 hw_wm8775_input_select(hw, 3, 0);
1998 break;
1999 default:
2000 return 0;
2001 }
2002
2003 hw20k2->mic_source = position;
2004
2005 return 1;
2006}
2007
2008static irqreturn_t ct_20k2_interrupt(int irq, void *dev_id)
2009{
2010 struct hw *hw = dev_id;
2011 unsigned int status;
2012
2013 status = hw_read_20kx(hw, GIP);
2014 if (!status)
2015 return IRQ_NONE;
2016
2017 if (hw->irq_callback)
2018 hw->irq_callback(hw->irq_callback_data, status);
2019
2020 hw_write_20kx(hw, GIP, status);
2021 return IRQ_HANDLED;
2022}
2023
2024static int hw_card_start(struct hw *hw)
2025{
2026 int err = 0;
2027 struct pci_dev *pci = hw->pci;
2028 unsigned int gctl;
2029
2030 err = pci_enable_device(pci);
2031 if (err < 0)
2032 return err;
2033
2034
2035 if (pci_set_dma_mask(pci, CT_XFI_DMA_MASK) < 0 ||
2036 pci_set_consistent_dma_mask(pci, CT_XFI_DMA_MASK) < 0) {
2037 printk(KERN_ERR "ctxfi: architecture does not support PCI "
2038 "busmaster DMA with mask 0x%llx\n", CT_XFI_DMA_MASK);
2039 err = -ENXIO;
2040 goto error1;
2041 }
2042
2043 if (!hw->io_base) {
2044 err = pci_request_regions(pci, "XFi");
2045 if (err < 0)
2046 goto error1;
2047
2048 hw->io_base = pci_resource_start(hw->pci, 2);
2049 hw->mem_base = (unsigned long)ioremap(hw->io_base,
2050 pci_resource_len(hw->pci, 2));
2051 if (!hw->mem_base) {
2052 err = -ENOENT;
2053 goto error2;
2054 }
2055 }
2056
2057
2058 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
2059 set_field(&gctl, GCTL_UAA, 0);
2060 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
2061
2062 if (hw->irq < 0) {
2063 err = request_irq(pci->irq, ct_20k2_interrupt, IRQF_SHARED,
2064 KBUILD_MODNAME, hw);
2065 if (err < 0) {
2066 printk(KERN_ERR "XFi: Cannot get irq %d\n", pci->irq);
2067 goto error2;
2068 }
2069 hw->irq = pci->irq;
2070 }
2071
2072 pci_set_master(pci);
2073
2074 return 0;
2075
2076
2077
2078
2079error2:
2080 pci_release_regions(pci);
2081 hw->io_base = 0;
2082error1:
2083 pci_disable_device(pci);
2084 return err;
2085}
2086
2087static int hw_card_stop(struct hw *hw)
2088{
2089 unsigned int data;
2090
2091
2092 hw_write_20kx(hw, TRANSPORT_CTL, 0x00);
2093
2094
2095 data = hw_read_20kx(hw, PLL_ENB);
2096 hw_write_20kx(hw, PLL_ENB, (data & (~0x07)));
2097
2098
2099 return 0;
2100}
2101
2102static int hw_card_shutdown(struct hw *hw)
2103{
2104 if (hw->irq >= 0)
2105 free_irq(hw->irq, hw);
2106
2107 hw->irq = -1;
2108
2109 if (hw->mem_base)
2110 iounmap((void *)hw->mem_base);
2111
2112 hw->mem_base = (unsigned long)NULL;
2113
2114 if (hw->io_base)
2115 pci_release_regions(hw->pci);
2116
2117 hw->io_base = 0;
2118
2119 pci_disable_device(hw->pci);
2120
2121 return 0;
2122}
2123
2124static int hw_card_init(struct hw *hw, struct card_conf *info)
2125{
2126 int err;
2127 unsigned int gctl;
2128 u32 data = 0;
2129 struct dac_conf dac_info = {0};
2130 struct adc_conf adc_info = {0};
2131 struct daio_conf daio_info = {0};
2132 struct trn_conf trn_info = {0};
2133
2134
2135
2136 err = hw_card_start(hw);
2137 if (err)
2138 return err;
2139
2140
2141 err = hw_pll_init(hw, info->rsr);
2142 if (err < 0)
2143 return err;
2144
2145
2146 err = hw_auto_init(hw);
2147 if (err < 0)
2148 return err;
2149
2150 gctl = hw_read_20kx(hw, GLOBAL_CNTL_GCTL);
2151 set_field(&gctl, GCTL_DBP, 1);
2152 set_field(&gctl, GCTL_TBP, 1);
2153 set_field(&gctl, GCTL_FBP, 1);
2154 set_field(&gctl, GCTL_DPC, 0);
2155 hw_write_20kx(hw, GLOBAL_CNTL_GCTL, gctl);
2156
2157
2158 hw_write_20kx(hw, GIE, 0);
2159
2160 hw_write_20kx(hw, SRC_IP, 0);
2161
2162 if (hw->model != CTSB1270) {
2163
2164
2165
2166
2167
2168 hw_write_20kx(hw, GPIO_CTRL, 0xD802);
2169 } else {
2170 hw_write_20kx(hw, GPIO_CTRL, 0x9E5F);
2171 }
2172
2173 hw_write_20kx(hw, MIXER_AR_ENABLE, 0x01);
2174
2175 trn_info.vm_pgt_phys = info->vm_pgt_phys;
2176 err = hw_trn_init(hw, &trn_info);
2177 if (err < 0)
2178 return err;
2179
2180 daio_info.msr = info->msr;
2181 err = hw_daio_init(hw, &daio_info);
2182 if (err < 0)
2183 return err;
2184
2185 dac_info.msr = info->msr;
2186 err = hw_dac_init(hw, &dac_info);
2187 if (err < 0)
2188 return err;
2189
2190 adc_info.msr = info->msr;
2191 adc_info.input = ADC_LINEIN;
2192 adc_info.mic20db = 0;
2193 err = hw_adc_init(hw, &adc_info);
2194 if (err < 0)
2195 return err;
2196
2197 data = hw_read_20kx(hw, SRC_MCTL);
2198 data |= 0x1;
2199 hw_write_20kx(hw, SRC_MCTL, data);
2200
2201 return 0;
2202}
2203
2204#ifdef CONFIG_PM_SLEEP
2205static int hw_suspend(struct hw *hw)
2206{
2207 struct pci_dev *pci = hw->pci;
2208
2209 hw_card_stop(hw);
2210
2211 pci_disable_device(pci);
2212 pci_save_state(pci);
2213 pci_set_power_state(pci, PCI_D3hot);
2214
2215 return 0;
2216}
2217
2218static int hw_resume(struct hw *hw, struct card_conf *info)
2219{
2220 struct pci_dev *pci = hw->pci;
2221
2222 pci_set_power_state(pci, PCI_D0);
2223 pci_restore_state(pci);
2224
2225
2226 return hw_card_init(hw, info);
2227}
2228#endif
2229
2230static u32 hw_read_20kx(struct hw *hw, u32 reg)
2231{
2232 return readl((void *)(hw->mem_base + reg));
2233}
2234
2235static void hw_write_20kx(struct hw *hw, u32 reg, u32 data)
2236{
2237 writel(data, (void *)(hw->mem_base + reg));
2238}
2239
2240static struct hw ct20k2_preset = {
2241 .irq = -1,
2242
2243 .card_init = hw_card_init,
2244 .card_stop = hw_card_stop,
2245 .pll_init = hw_pll_init,
2246 .is_adc_source_selected = hw_is_adc_input_selected,
2247 .select_adc_source = hw_adc_input_select,
2248 .capabilities = hw_capabilities,
2249 .output_switch_get = hw_output_switch_get,
2250 .output_switch_put = hw_output_switch_put,
2251 .mic_source_switch_get = hw_mic_source_switch_get,
2252 .mic_source_switch_put = hw_mic_source_switch_put,
2253#ifdef CONFIG_PM_SLEEP
2254 .suspend = hw_suspend,
2255 .resume = hw_resume,
2256#endif
2257
2258 .src_rsc_get_ctrl_blk = src_get_rsc_ctrl_blk,
2259 .src_rsc_put_ctrl_blk = src_put_rsc_ctrl_blk,
2260 .src_mgr_get_ctrl_blk = src_mgr_get_ctrl_blk,
2261 .src_mgr_put_ctrl_blk = src_mgr_put_ctrl_blk,
2262 .src_set_state = src_set_state,
2263 .src_set_bm = src_set_bm,
2264 .src_set_rsr = src_set_rsr,
2265 .src_set_sf = src_set_sf,
2266 .src_set_wr = src_set_wr,
2267 .src_set_pm = src_set_pm,
2268 .src_set_rom = src_set_rom,
2269 .src_set_vo = src_set_vo,
2270 .src_set_st = src_set_st,
2271 .src_set_ie = src_set_ie,
2272 .src_set_ilsz = src_set_ilsz,
2273 .src_set_bp = src_set_bp,
2274 .src_set_cisz = src_set_cisz,
2275 .src_set_ca = src_set_ca,
2276 .src_set_sa = src_set_sa,
2277 .src_set_la = src_set_la,
2278 .src_set_pitch = src_set_pitch,
2279 .src_set_dirty = src_set_dirty,
2280 .src_set_clear_zbufs = src_set_clear_zbufs,
2281 .src_set_dirty_all = src_set_dirty_all,
2282 .src_commit_write = src_commit_write,
2283 .src_get_ca = src_get_ca,
2284 .src_get_dirty = src_get_dirty,
2285 .src_dirty_conj_mask = src_dirty_conj_mask,
2286 .src_mgr_enbs_src = src_mgr_enbs_src,
2287 .src_mgr_enb_src = src_mgr_enb_src,
2288 .src_mgr_dsb_src = src_mgr_dsb_src,
2289 .src_mgr_commit_write = src_mgr_commit_write,
2290
2291 .srcimp_mgr_get_ctrl_blk = srcimp_mgr_get_ctrl_blk,
2292 .srcimp_mgr_put_ctrl_blk = srcimp_mgr_put_ctrl_blk,
2293 .srcimp_mgr_set_imaparc = srcimp_mgr_set_imaparc,
2294 .srcimp_mgr_set_imapuser = srcimp_mgr_set_imapuser,
2295 .srcimp_mgr_set_imapnxt = srcimp_mgr_set_imapnxt,
2296 .srcimp_mgr_set_imapaddr = srcimp_mgr_set_imapaddr,
2297 .srcimp_mgr_commit_write = srcimp_mgr_commit_write,
2298
2299 .amixer_rsc_get_ctrl_blk = amixer_rsc_get_ctrl_blk,
2300 .amixer_rsc_put_ctrl_blk = amixer_rsc_put_ctrl_blk,
2301 .amixer_mgr_get_ctrl_blk = amixer_mgr_get_ctrl_blk,
2302 .amixer_mgr_put_ctrl_blk = amixer_mgr_put_ctrl_blk,
2303 .amixer_set_mode = amixer_set_mode,
2304 .amixer_set_iv = amixer_set_iv,
2305 .amixer_set_x = amixer_set_x,
2306 .amixer_set_y = amixer_set_y,
2307 .amixer_set_sadr = amixer_set_sadr,
2308 .amixer_set_se = amixer_set_se,
2309 .amixer_set_dirty = amixer_set_dirty,
2310 .amixer_set_dirty_all = amixer_set_dirty_all,
2311 .amixer_commit_write = amixer_commit_write,
2312 .amixer_get_y = amixer_get_y,
2313 .amixer_get_dirty = amixer_get_dirty,
2314
2315 .dai_get_ctrl_blk = dai_get_ctrl_blk,
2316 .dai_put_ctrl_blk = dai_put_ctrl_blk,
2317 .dai_srt_set_srco = dai_srt_set_srco,
2318 .dai_srt_set_srcm = dai_srt_set_srcm,
2319 .dai_srt_set_rsr = dai_srt_set_rsr,
2320 .dai_srt_set_drat = dai_srt_set_drat,
2321 .dai_srt_set_ec = dai_srt_set_ec,
2322 .dai_srt_set_et = dai_srt_set_et,
2323 .dai_commit_write = dai_commit_write,
2324
2325 .dao_get_ctrl_blk = dao_get_ctrl_blk,
2326 .dao_put_ctrl_blk = dao_put_ctrl_blk,
2327 .dao_set_spos = dao_set_spos,
2328 .dao_commit_write = dao_commit_write,
2329 .dao_get_spos = dao_get_spos,
2330
2331 .daio_mgr_get_ctrl_blk = daio_mgr_get_ctrl_blk,
2332 .daio_mgr_put_ctrl_blk = daio_mgr_put_ctrl_blk,
2333 .daio_mgr_enb_dai = daio_mgr_enb_dai,
2334 .daio_mgr_dsb_dai = daio_mgr_dsb_dai,
2335 .daio_mgr_enb_dao = daio_mgr_enb_dao,
2336 .daio_mgr_dsb_dao = daio_mgr_dsb_dao,
2337 .daio_mgr_dao_init = daio_mgr_dao_init,
2338 .daio_mgr_set_imaparc = daio_mgr_set_imaparc,
2339 .daio_mgr_set_imapnxt = daio_mgr_set_imapnxt,
2340 .daio_mgr_set_imapaddr = daio_mgr_set_imapaddr,
2341 .daio_mgr_commit_write = daio_mgr_commit_write,
2342
2343 .set_timer_irq = set_timer_irq,
2344 .set_timer_tick = set_timer_tick,
2345 .get_wc = get_wc,
2346};
2347
2348int create_20k2_hw_obj(struct hw **rhw)
2349{
2350 struct hw20k2 *hw20k2;
2351
2352 *rhw = NULL;
2353 hw20k2 = kzalloc(sizeof(*hw20k2), GFP_KERNEL);
2354 if (!hw20k2)
2355 return -ENOMEM;
2356
2357 hw20k2->hw = ct20k2_preset;
2358 *rhw = &hw20k2->hw;
2359
2360 return 0;
2361}
2362
2363int destroy_20k2_hw_obj(struct hw *hw)
2364{
2365 if (hw->io_base)
2366 hw_card_shutdown(hw);
2367
2368 kfree(hw);
2369 return 0;
2370}
2371