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35#include <linux/module.h>
36#include <linux/moduleparam.h>
37#include <linux/init.h>
38#include <linux/delay.h>
39#include <linux/pm.h>
40#include <linux/i2c.h>
41#include <linux/gpio.h>
42#include <linux/regulator/consumer.h>
43#include <linux/of_gpio.h>
44#include <linux/slab.h>
45#include <sound/core.h>
46#include <sound/pcm.h>
47#include <sound/pcm_params.h>
48#include <sound/soc.h>
49#include <sound/initval.h>
50#include <sound/tlv.h>
51#include <sound/tlv320aic3x.h>
52
53#include "tlv320aic3x.h"
54
55#define AIC3X_NUM_SUPPLIES 4
56static const char *aic3x_supply_names[AIC3X_NUM_SUPPLIES] = {
57 "IOVDD",
58 "DVDD",
59 "AVDD",
60 "DRVDD",
61};
62
63static LIST_HEAD(reset_list);
64
65struct aic3x_priv;
66
67struct aic3x_disable_nb {
68 struct notifier_block nb;
69 struct aic3x_priv *aic3x;
70};
71
72
73struct aic3x_priv {
74 struct snd_soc_codec *codec;
75 struct regulator_bulk_data supplies[AIC3X_NUM_SUPPLIES];
76 struct aic3x_disable_nb disable_nb[AIC3X_NUM_SUPPLIES];
77 enum snd_soc_control_type control_type;
78 struct aic3x_setup_data *setup;
79 unsigned int sysclk;
80 struct list_head list;
81 int master;
82 int gpio_reset;
83 int power;
84#define AIC3X_MODEL_3X 0
85#define AIC3X_MODEL_33 1
86#define AIC3X_MODEL_3007 2
87 u16 model;
88
89
90 enum aic3x_micbias_voltage micbias_vg;
91};
92
93
94
95
96
97
98
99static const u8 aic3x_reg[AIC3X_CACHEREGNUM] = {
100 0x00, 0x00, 0x00, 0x10,
101 0x04, 0x00, 0x00, 0x00,
102 0x00, 0x00, 0x00, 0x01,
103 0x00, 0x00, 0x00, 0x80,
104 0x80, 0xff, 0xff, 0x78,
105 0x78, 0x78, 0x78, 0x78,
106 0x78, 0x00, 0x00, 0xfe,
107 0x00, 0x00, 0xfe, 0x00,
108 0x18, 0x18, 0x00, 0x00,
109 0x00, 0x00, 0x00, 0x00,
110 0x00, 0x00, 0x00, 0x80,
111 0x80, 0x00, 0x00, 0x00,
112 0x00, 0x00, 0x00, 0x04,
113 0x00, 0x00, 0x00, 0x00,
114 0x00, 0x00, 0x04, 0x00,
115 0x00, 0x00, 0x00, 0x00,
116 0x00, 0x04, 0x00, 0x00,
117 0x00, 0x00, 0x00, 0x00,
118 0x04, 0x00, 0x00, 0x00,
119 0x00, 0x00, 0x00, 0x00,
120 0x00, 0x00, 0x00, 0x00,
121 0x00, 0x00, 0x00, 0x00,
122 0x00, 0x00, 0x00, 0x00,
123 0x00, 0x00, 0x00, 0x00,
124 0x00, 0x00, 0x00, 0x00,
125 0x00, 0x00, 0x02, 0x00,
126 0x00, 0x00, 0x00, 0x00,
127 0x00, 0x00,
128};
129
130#define SOC_DAPM_SINGLE_AIC3X(xname, reg, shift, mask, invert) \
131 SOC_SINGLE_EXT(xname, reg, shift, mask, invert, \
132 snd_soc_dapm_get_volsw, snd_soc_dapm_put_volsw_aic3x)
133
134
135
136
137
138static int snd_soc_dapm_put_volsw_aic3x(struct snd_kcontrol *kcontrol,
139 struct snd_ctl_elem_value *ucontrol)
140{
141 struct snd_soc_dapm_widget_list *wlist = snd_kcontrol_chip(kcontrol);
142 struct snd_soc_dapm_widget *widget = wlist->widgets[0];
143 struct soc_mixer_control *mc =
144 (struct soc_mixer_control *)kcontrol->private_value;
145 unsigned int reg = mc->reg;
146 unsigned int shift = mc->shift;
147 int max = mc->max;
148 unsigned int mask = (1 << fls(max)) - 1;
149 unsigned int invert = mc->invert;
150 unsigned short val, val_mask;
151 int ret;
152 struct snd_soc_dapm_path *path;
153 int found = 0;
154
155 val = (ucontrol->value.integer.value[0] & mask);
156
157 mask = 0xf;
158 if (val)
159 val = mask;
160
161 if (invert)
162 val = mask - val;
163 val_mask = mask << shift;
164 val = val << shift;
165
166 mutex_lock(&widget->codec->mutex);
167
168 if (snd_soc_test_bits(widget->codec, reg, val_mask, val)) {
169
170 list_for_each_entry(path, &widget->dapm->card->paths, list) {
171 if (path->kcontrol != kcontrol)
172 continue;
173
174
175 found = 1;
176 if (val)
177
178 path->connect = invert ? 0 : 1;
179 else
180
181 path->connect = invert ? 1 : 0;
182
183 dapm_mark_dirty(path->source, "tlv320aic3x source");
184 dapm_mark_dirty(path->sink, "tlv320aic3x sink");
185
186 break;
187 }
188 }
189
190 mutex_unlock(&widget->codec->mutex);
191
192 if (found)
193 snd_soc_dapm_sync(widget->dapm);
194
195 ret = snd_soc_update_bits_locked(widget->codec, reg, val_mask, val);
196 return ret;
197}
198
199
200
201
202
203
204
205
206
207
208static int mic_bias_event(struct snd_soc_dapm_widget *w,
209 struct snd_kcontrol *kcontrol, int event)
210{
211 struct snd_soc_codec *codec = w->codec;
212 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
213
214 switch (event) {
215 case SND_SOC_DAPM_POST_PMU:
216
217 snd_soc_update_bits(codec, MICBIAS_CTRL,
218 MICBIAS_LEVEL_MASK,
219 aic3x->micbias_vg << MICBIAS_LEVEL_SHIFT);
220 break;
221
222 case SND_SOC_DAPM_PRE_PMD:
223 snd_soc_update_bits(codec, MICBIAS_CTRL,
224 MICBIAS_LEVEL_MASK, 0);
225 break;
226 }
227 return 0;
228}
229
230static const char *aic3x_left_dac_mux[] = { "DAC_L1", "DAC_L3", "DAC_L2" };
231static const char *aic3x_right_dac_mux[] = { "DAC_R1", "DAC_R3", "DAC_R2" };
232static const char *aic3x_left_hpcom_mux[] =
233 { "differential of HPLOUT", "constant VCM", "single-ended" };
234static const char *aic3x_right_hpcom_mux[] =
235 { "differential of HPROUT", "constant VCM", "single-ended",
236 "differential of HPLCOM", "external feedback" };
237static const char *aic3x_linein_mode_mux[] = { "single-ended", "differential" };
238static const char *aic3x_adc_hpf[] =
239 { "Disabled", "0.0045xFs", "0.0125xFs", "0.025xFs" };
240
241#define LDAC_ENUM 0
242#define RDAC_ENUM 1
243#define LHPCOM_ENUM 2
244#define RHPCOM_ENUM 3
245#define LINE1L_2_L_ENUM 4
246#define LINE1L_2_R_ENUM 5
247#define LINE1R_2_L_ENUM 6
248#define LINE1R_2_R_ENUM 7
249#define LINE2L_ENUM 8
250#define LINE2R_ENUM 9
251#define ADC_HPF_ENUM 10
252
253static const struct soc_enum aic3x_enum[] = {
254 SOC_ENUM_SINGLE(DAC_LINE_MUX, 6, 3, aic3x_left_dac_mux),
255 SOC_ENUM_SINGLE(DAC_LINE_MUX, 4, 3, aic3x_right_dac_mux),
256 SOC_ENUM_SINGLE(HPLCOM_CFG, 4, 3, aic3x_left_hpcom_mux),
257 SOC_ENUM_SINGLE(HPRCOM_CFG, 3, 5, aic3x_right_hpcom_mux),
258 SOC_ENUM_SINGLE(LINE1L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
259 SOC_ENUM_SINGLE(LINE1L_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
260 SOC_ENUM_SINGLE(LINE1R_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
261 SOC_ENUM_SINGLE(LINE1R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
262 SOC_ENUM_SINGLE(LINE2L_2_LADC_CTRL, 7, 2, aic3x_linein_mode_mux),
263 SOC_ENUM_SINGLE(LINE2R_2_RADC_CTRL, 7, 2, aic3x_linein_mode_mux),
264 SOC_ENUM_DOUBLE(AIC3X_CODEC_DFILT_CTRL, 6, 4, 4, aic3x_adc_hpf),
265};
266
267static const char *aic3x_agc_level[] =
268 { "-5.5dB", "-8dB", "-10dB", "-12dB", "-14dB", "-17dB", "-20dB", "-24dB" };
269static const struct soc_enum aic3x_agc_level_enum[] = {
270 SOC_ENUM_SINGLE(LAGC_CTRL_A, 4, 8, aic3x_agc_level),
271 SOC_ENUM_SINGLE(RAGC_CTRL_A, 4, 8, aic3x_agc_level),
272};
273
274static const char *aic3x_agc_attack[] = { "8ms", "11ms", "16ms", "20ms" };
275static const struct soc_enum aic3x_agc_attack_enum[] = {
276 SOC_ENUM_SINGLE(LAGC_CTRL_A, 2, 4, aic3x_agc_attack),
277 SOC_ENUM_SINGLE(RAGC_CTRL_A, 2, 4, aic3x_agc_attack),
278};
279
280static const char *aic3x_agc_decay[] = { "100ms", "200ms", "400ms", "500ms" };
281static const struct soc_enum aic3x_agc_decay_enum[] = {
282 SOC_ENUM_SINGLE(LAGC_CTRL_A, 0, 4, aic3x_agc_decay),
283 SOC_ENUM_SINGLE(RAGC_CTRL_A, 0, 4, aic3x_agc_decay),
284};
285
286
287
288
289static DECLARE_TLV_DB_SCALE(dac_tlv, -6350, 50, 0);
290
291static DECLARE_TLV_DB_SCALE(adc_tlv, 0, 50, 0);
292
293
294
295
296
297
298
299
300
301static DECLARE_TLV_DB_SCALE(output_stage_tlv, -5900, 50, 1);
302
303static const struct snd_kcontrol_new aic3x_snd_controls[] = {
304
305 SOC_DOUBLE_R_TLV("PCM Playback Volume",
306 LDAC_VOL, RDAC_VOL, 0, 0x7f, 1, dac_tlv),
307
308
309
310
311
312
313 SOC_SINGLE_TLV("Left Line Mixer Line2R Bypass Volume",
314 LINE2R_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
315 SOC_SINGLE_TLV("Left Line Mixer PGAR Bypass Volume",
316 PGAR_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
317 SOC_SINGLE_TLV("Left Line Mixer DACR1 Playback Volume",
318 DACR1_2_LLOPM_VOL, 0, 118, 1, output_stage_tlv),
319
320 SOC_SINGLE_TLV("Right Line Mixer Line2L Bypass Volume",
321 LINE2L_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
322 SOC_SINGLE_TLV("Right Line Mixer PGAL Bypass Volume",
323 PGAL_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
324 SOC_SINGLE_TLV("Right Line Mixer DACL1 Playback Volume",
325 DACL1_2_RLOPM_VOL, 0, 118, 1, output_stage_tlv),
326
327 SOC_SINGLE_TLV("Left HP Mixer Line2R Bypass Volume",
328 LINE2R_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
329 SOC_SINGLE_TLV("Left HP Mixer PGAR Bypass Volume",
330 PGAR_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
331 SOC_SINGLE_TLV("Left HP Mixer DACR1 Playback Volume",
332 DACR1_2_HPLOUT_VOL, 0, 118, 1, output_stage_tlv),
333
334 SOC_SINGLE_TLV("Right HP Mixer Line2L Bypass Volume",
335 LINE2L_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
336 SOC_SINGLE_TLV("Right HP Mixer PGAL Bypass Volume",
337 PGAL_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
338 SOC_SINGLE_TLV("Right HP Mixer DACL1 Playback Volume",
339 DACL1_2_HPROUT_VOL, 0, 118, 1, output_stage_tlv),
340
341 SOC_SINGLE_TLV("Left HPCOM Mixer Line2R Bypass Volume",
342 LINE2R_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
343 SOC_SINGLE_TLV("Left HPCOM Mixer PGAR Bypass Volume",
344 PGAR_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
345 SOC_SINGLE_TLV("Left HPCOM Mixer DACR1 Playback Volume",
346 DACR1_2_HPLCOM_VOL, 0, 118, 1, output_stage_tlv),
347
348 SOC_SINGLE_TLV("Right HPCOM Mixer Line2L Bypass Volume",
349 LINE2L_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
350 SOC_SINGLE_TLV("Right HPCOM Mixer PGAL Bypass Volume",
351 PGAL_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
352 SOC_SINGLE_TLV("Right HPCOM Mixer DACL1 Playback Volume",
353 DACL1_2_HPRCOM_VOL, 0, 118, 1, output_stage_tlv),
354
355
356 SOC_DOUBLE_R_TLV("Line Line2 Bypass Volume",
357 LINE2L_2_LLOPM_VOL, LINE2R_2_RLOPM_VOL,
358 0, 118, 1, output_stage_tlv),
359 SOC_DOUBLE_R_TLV("Line PGA Bypass Volume",
360 PGAL_2_LLOPM_VOL, PGAR_2_RLOPM_VOL,
361 0, 118, 1, output_stage_tlv),
362 SOC_DOUBLE_R_TLV("Line DAC Playback Volume",
363 DACL1_2_LLOPM_VOL, DACR1_2_RLOPM_VOL,
364 0, 118, 1, output_stage_tlv),
365
366 SOC_DOUBLE_R_TLV("Mono Line2 Bypass Volume",
367 LINE2L_2_MONOLOPM_VOL, LINE2R_2_MONOLOPM_VOL,
368 0, 118, 1, output_stage_tlv),
369 SOC_DOUBLE_R_TLV("Mono PGA Bypass Volume",
370 PGAL_2_MONOLOPM_VOL, PGAR_2_MONOLOPM_VOL,
371 0, 118, 1, output_stage_tlv),
372 SOC_DOUBLE_R_TLV("Mono DAC Playback Volume",
373 DACL1_2_MONOLOPM_VOL, DACR1_2_MONOLOPM_VOL,
374 0, 118, 1, output_stage_tlv),
375
376 SOC_DOUBLE_R_TLV("HP Line2 Bypass Volume",
377 LINE2L_2_HPLOUT_VOL, LINE2R_2_HPROUT_VOL,
378 0, 118, 1, output_stage_tlv),
379 SOC_DOUBLE_R_TLV("HP PGA Bypass Volume",
380 PGAL_2_HPLOUT_VOL, PGAR_2_HPROUT_VOL,
381 0, 118, 1, output_stage_tlv),
382 SOC_DOUBLE_R_TLV("HP DAC Playback Volume",
383 DACL1_2_HPLOUT_VOL, DACR1_2_HPROUT_VOL,
384 0, 118, 1, output_stage_tlv),
385
386 SOC_DOUBLE_R_TLV("HPCOM Line2 Bypass Volume",
387 LINE2L_2_HPLCOM_VOL, LINE2R_2_HPRCOM_VOL,
388 0, 118, 1, output_stage_tlv),
389 SOC_DOUBLE_R_TLV("HPCOM PGA Bypass Volume",
390 PGAL_2_HPLCOM_VOL, PGAR_2_HPRCOM_VOL,
391 0, 118, 1, output_stage_tlv),
392 SOC_DOUBLE_R_TLV("HPCOM DAC Playback Volume",
393 DACL1_2_HPLCOM_VOL, DACR1_2_HPRCOM_VOL,
394 0, 118, 1, output_stage_tlv),
395
396
397 SOC_DOUBLE_R("Line Playback Switch", LLOPM_CTRL, RLOPM_CTRL, 3,
398 0x01, 0),
399 SOC_SINGLE("Mono Playback Switch", MONOLOPM_CTRL, 3, 0x01, 0),
400 SOC_DOUBLE_R("HP Playback Switch", HPLOUT_CTRL, HPROUT_CTRL, 3,
401 0x01, 0),
402 SOC_DOUBLE_R("HPCOM Playback Switch", HPLCOM_CTRL, HPRCOM_CTRL, 3,
403 0x01, 0),
404
405
406
407
408
409 SOC_DOUBLE_R("AGC Switch", LAGC_CTRL_A, RAGC_CTRL_A, 7, 0x01, 0),
410 SOC_ENUM("Left AGC Target level", aic3x_agc_level_enum[0]),
411 SOC_ENUM("Right AGC Target level", aic3x_agc_level_enum[1]),
412 SOC_ENUM("Left AGC Attack time", aic3x_agc_attack_enum[0]),
413 SOC_ENUM("Right AGC Attack time", aic3x_agc_attack_enum[1]),
414 SOC_ENUM("Left AGC Decay time", aic3x_agc_decay_enum[0]),
415 SOC_ENUM("Right AGC Decay time", aic3x_agc_decay_enum[1]),
416
417
418 SOC_DOUBLE("De-emphasis Switch", AIC3X_CODEC_DFILT_CTRL, 2, 0, 0x01, 0),
419
420
421 SOC_DOUBLE_R_TLV("PGA Capture Volume", LADC_VOL, RADC_VOL,
422 0, 119, 0, adc_tlv),
423 SOC_DOUBLE_R("PGA Capture Switch", LADC_VOL, RADC_VOL, 7, 0x01, 1),
424
425 SOC_ENUM("ADC HPF Cut-off", aic3x_enum[ADC_HPF_ENUM]),
426};
427
428
429
430
431static DECLARE_TLV_DB_SCALE(classd_amp_tlv, 0, 600, 0);
432
433static const struct snd_kcontrol_new aic3x_classd_amp_gain_ctrl =
434 SOC_DOUBLE_TLV("Class-D Playback Volume", CLASSD_CTRL, 6, 4, 3, 0, classd_amp_tlv);
435
436
437static const struct snd_kcontrol_new aic3x_left_dac_mux_controls =
438SOC_DAPM_ENUM("Route", aic3x_enum[LDAC_ENUM]);
439
440
441static const struct snd_kcontrol_new aic3x_right_dac_mux_controls =
442SOC_DAPM_ENUM("Route", aic3x_enum[RDAC_ENUM]);
443
444
445static const struct snd_kcontrol_new aic3x_left_hpcom_mux_controls =
446SOC_DAPM_ENUM("Route", aic3x_enum[LHPCOM_ENUM]);
447
448
449static const struct snd_kcontrol_new aic3x_right_hpcom_mux_controls =
450SOC_DAPM_ENUM("Route", aic3x_enum[RHPCOM_ENUM]);
451
452
453static const struct snd_kcontrol_new aic3x_left_line_mixer_controls[] = {
454 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_LLOPM_VOL, 7, 1, 0),
455 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_LLOPM_VOL, 7, 1, 0),
456 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_LLOPM_VOL, 7, 1, 0),
457 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_LLOPM_VOL, 7, 1, 0),
458 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_LLOPM_VOL, 7, 1, 0),
459 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_LLOPM_VOL, 7, 1, 0),
460};
461
462
463static const struct snd_kcontrol_new aic3x_right_line_mixer_controls[] = {
464 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_RLOPM_VOL, 7, 1, 0),
465 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_RLOPM_VOL, 7, 1, 0),
466 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_RLOPM_VOL, 7, 1, 0),
467 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_RLOPM_VOL, 7, 1, 0),
468 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_RLOPM_VOL, 7, 1, 0),
469 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_RLOPM_VOL, 7, 1, 0),
470};
471
472
473static const struct snd_kcontrol_new aic3x_mono_mixer_controls[] = {
474 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_MONOLOPM_VOL, 7, 1, 0),
475 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_MONOLOPM_VOL, 7, 1, 0),
476 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_MONOLOPM_VOL, 7, 1, 0),
477 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_MONOLOPM_VOL, 7, 1, 0),
478 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_MONOLOPM_VOL, 7, 1, 0),
479 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_MONOLOPM_VOL, 7, 1, 0),
480};
481
482
483static const struct snd_kcontrol_new aic3x_left_hp_mixer_controls[] = {
484 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLOUT_VOL, 7, 1, 0),
485 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLOUT_VOL, 7, 1, 0),
486 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLOUT_VOL, 7, 1, 0),
487 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLOUT_VOL, 7, 1, 0),
488 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLOUT_VOL, 7, 1, 0),
489 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLOUT_VOL, 7, 1, 0),
490};
491
492
493static const struct snd_kcontrol_new aic3x_right_hp_mixer_controls[] = {
494 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPROUT_VOL, 7, 1, 0),
495 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPROUT_VOL, 7, 1, 0),
496 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPROUT_VOL, 7, 1, 0),
497 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPROUT_VOL, 7, 1, 0),
498 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPROUT_VOL, 7, 1, 0),
499 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPROUT_VOL, 7, 1, 0),
500};
501
502
503static const struct snd_kcontrol_new aic3x_left_hpcom_mixer_controls[] = {
504 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPLCOM_VOL, 7, 1, 0),
505 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPLCOM_VOL, 7, 1, 0),
506 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPLCOM_VOL, 7, 1, 0),
507 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPLCOM_VOL, 7, 1, 0),
508 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPLCOM_VOL, 7, 1, 0),
509 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPLCOM_VOL, 7, 1, 0),
510};
511
512
513static const struct snd_kcontrol_new aic3x_right_hpcom_mixer_controls[] = {
514 SOC_DAPM_SINGLE("Line2L Bypass Switch", LINE2L_2_HPRCOM_VOL, 7, 1, 0),
515 SOC_DAPM_SINGLE("PGAL Bypass Switch", PGAL_2_HPRCOM_VOL, 7, 1, 0),
516 SOC_DAPM_SINGLE("DACL1 Switch", DACL1_2_HPRCOM_VOL, 7, 1, 0),
517 SOC_DAPM_SINGLE("Line2R Bypass Switch", LINE2R_2_HPRCOM_VOL, 7, 1, 0),
518 SOC_DAPM_SINGLE("PGAR Bypass Switch", PGAR_2_HPRCOM_VOL, 7, 1, 0),
519 SOC_DAPM_SINGLE("DACR1 Switch", DACR1_2_HPRCOM_VOL, 7, 1, 0),
520};
521
522
523static const struct snd_kcontrol_new aic3x_left_pga_mixer_controls[] = {
524 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_LADC_CTRL, 3, 1, 1),
525 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_LADC_CTRL, 3, 1, 1),
526 SOC_DAPM_SINGLE_AIC3X("Line2L Switch", LINE2L_2_LADC_CTRL, 3, 1, 1),
527 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_LADC_CTRL, 4, 1, 1),
528 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_LADC_CTRL, 0, 1, 1),
529};
530
531
532static const struct snd_kcontrol_new aic3x_right_pga_mixer_controls[] = {
533 SOC_DAPM_SINGLE_AIC3X("Line1R Switch", LINE1R_2_RADC_CTRL, 3, 1, 1),
534 SOC_DAPM_SINGLE_AIC3X("Line1L Switch", LINE1L_2_RADC_CTRL, 3, 1, 1),
535 SOC_DAPM_SINGLE_AIC3X("Line2R Switch", LINE2R_2_RADC_CTRL, 3, 1, 1),
536 SOC_DAPM_SINGLE_AIC3X("Mic3L Switch", MIC3LR_2_RADC_CTRL, 4, 1, 1),
537 SOC_DAPM_SINGLE_AIC3X("Mic3R Switch", MIC3LR_2_RADC_CTRL, 0, 1, 1),
538};
539
540
541static const struct snd_kcontrol_new aic3x_left_line1l_mux_controls =
542SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_L_ENUM]);
543static const struct snd_kcontrol_new aic3x_right_line1l_mux_controls =
544SOC_DAPM_ENUM("Route", aic3x_enum[LINE1L_2_R_ENUM]);
545
546
547static const struct snd_kcontrol_new aic3x_right_line1r_mux_controls =
548SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_R_ENUM]);
549static const struct snd_kcontrol_new aic3x_left_line1r_mux_controls =
550SOC_DAPM_ENUM("Route", aic3x_enum[LINE1R_2_L_ENUM]);
551
552
553static const struct snd_kcontrol_new aic3x_left_line2_mux_controls =
554SOC_DAPM_ENUM("Route", aic3x_enum[LINE2L_ENUM]);
555
556
557static const struct snd_kcontrol_new aic3x_right_line2_mux_controls =
558SOC_DAPM_ENUM("Route", aic3x_enum[LINE2R_ENUM]);
559
560static const struct snd_soc_dapm_widget aic3x_dapm_widgets[] = {
561
562 SND_SOC_DAPM_DAC("Left DAC", "Left Playback", DAC_PWR, 7, 0),
563 SND_SOC_DAPM_MUX("Left DAC Mux", SND_SOC_NOPM, 0, 0,
564 &aic3x_left_dac_mux_controls),
565 SND_SOC_DAPM_MUX("Left HPCOM Mux", SND_SOC_NOPM, 0, 0,
566 &aic3x_left_hpcom_mux_controls),
567 SND_SOC_DAPM_PGA("Left Line Out", LLOPM_CTRL, 0, 0, NULL, 0),
568 SND_SOC_DAPM_PGA("Left HP Out", HPLOUT_CTRL, 0, 0, NULL, 0),
569 SND_SOC_DAPM_PGA("Left HP Com", HPLCOM_CTRL, 0, 0, NULL, 0),
570
571
572 SND_SOC_DAPM_DAC("Right DAC", "Right Playback", DAC_PWR, 6, 0),
573 SND_SOC_DAPM_MUX("Right DAC Mux", SND_SOC_NOPM, 0, 0,
574 &aic3x_right_dac_mux_controls),
575 SND_SOC_DAPM_MUX("Right HPCOM Mux", SND_SOC_NOPM, 0, 0,
576 &aic3x_right_hpcom_mux_controls),
577 SND_SOC_DAPM_PGA("Right Line Out", RLOPM_CTRL, 0, 0, NULL, 0),
578 SND_SOC_DAPM_PGA("Right HP Out", HPROUT_CTRL, 0, 0, NULL, 0),
579 SND_SOC_DAPM_PGA("Right HP Com", HPRCOM_CTRL, 0, 0, NULL, 0),
580
581
582 SND_SOC_DAPM_PGA("Mono Out", MONOLOPM_CTRL, 0, 0, NULL, 0),
583
584
585 SND_SOC_DAPM_ADC("Left ADC", "Left Capture", LINE1L_2_LADC_CTRL, 2, 0),
586 SND_SOC_DAPM_MIXER("Left PGA Mixer", SND_SOC_NOPM, 0, 0,
587 &aic3x_left_pga_mixer_controls[0],
588 ARRAY_SIZE(aic3x_left_pga_mixer_controls)),
589 SND_SOC_DAPM_MUX("Left Line1L Mux", SND_SOC_NOPM, 0, 0,
590 &aic3x_left_line1l_mux_controls),
591 SND_SOC_DAPM_MUX("Left Line1R Mux", SND_SOC_NOPM, 0, 0,
592 &aic3x_left_line1r_mux_controls),
593 SND_SOC_DAPM_MUX("Left Line2L Mux", SND_SOC_NOPM, 0, 0,
594 &aic3x_left_line2_mux_controls),
595
596
597 SND_SOC_DAPM_ADC("Right ADC", "Right Capture",
598 LINE1R_2_RADC_CTRL, 2, 0),
599 SND_SOC_DAPM_MIXER("Right PGA Mixer", SND_SOC_NOPM, 0, 0,
600 &aic3x_right_pga_mixer_controls[0],
601 ARRAY_SIZE(aic3x_right_pga_mixer_controls)),
602 SND_SOC_DAPM_MUX("Right Line1L Mux", SND_SOC_NOPM, 0, 0,
603 &aic3x_right_line1l_mux_controls),
604 SND_SOC_DAPM_MUX("Right Line1R Mux", SND_SOC_NOPM, 0, 0,
605 &aic3x_right_line1r_mux_controls),
606 SND_SOC_DAPM_MUX("Right Line2R Mux", SND_SOC_NOPM, 0, 0,
607 &aic3x_right_line2_mux_controls),
608
609
610
611
612
613
614 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "GPIO1 dmic modclk",
615 AIC3X_GPIO1_REG, 4, 0xf,
616 AIC3X_GPIO1_FUNC_DIGITAL_MIC_MODCLK,
617 AIC3X_GPIO1_FUNC_DISABLED),
618
619
620
621
622
623 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 128",
624 AIC3X_ASD_INTF_CTRLA, 0, 3, 1, 0),
625 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 64",
626 AIC3X_ASD_INTF_CTRLA, 0, 3, 2, 0),
627 SND_SOC_DAPM_REG(snd_soc_dapm_micbias, "DMic Rate 32",
628 AIC3X_ASD_INTF_CTRLA, 0, 3, 3, 0),
629
630
631 SND_SOC_DAPM_SUPPLY("Mic Bias", MICBIAS_CTRL, 6, 0,
632 mic_bias_event,
633 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
634
635
636 SND_SOC_DAPM_MIXER("Left Line Mixer", SND_SOC_NOPM, 0, 0,
637 &aic3x_left_line_mixer_controls[0],
638 ARRAY_SIZE(aic3x_left_line_mixer_controls)),
639 SND_SOC_DAPM_MIXER("Right Line Mixer", SND_SOC_NOPM, 0, 0,
640 &aic3x_right_line_mixer_controls[0],
641 ARRAY_SIZE(aic3x_right_line_mixer_controls)),
642 SND_SOC_DAPM_MIXER("Mono Mixer", SND_SOC_NOPM, 0, 0,
643 &aic3x_mono_mixer_controls[0],
644 ARRAY_SIZE(aic3x_mono_mixer_controls)),
645 SND_SOC_DAPM_MIXER("Left HP Mixer", SND_SOC_NOPM, 0, 0,
646 &aic3x_left_hp_mixer_controls[0],
647 ARRAY_SIZE(aic3x_left_hp_mixer_controls)),
648 SND_SOC_DAPM_MIXER("Right HP Mixer", SND_SOC_NOPM, 0, 0,
649 &aic3x_right_hp_mixer_controls[0],
650 ARRAY_SIZE(aic3x_right_hp_mixer_controls)),
651 SND_SOC_DAPM_MIXER("Left HPCOM Mixer", SND_SOC_NOPM, 0, 0,
652 &aic3x_left_hpcom_mixer_controls[0],
653 ARRAY_SIZE(aic3x_left_hpcom_mixer_controls)),
654 SND_SOC_DAPM_MIXER("Right HPCOM Mixer", SND_SOC_NOPM, 0, 0,
655 &aic3x_right_hpcom_mixer_controls[0],
656 ARRAY_SIZE(aic3x_right_hpcom_mixer_controls)),
657
658 SND_SOC_DAPM_OUTPUT("LLOUT"),
659 SND_SOC_DAPM_OUTPUT("RLOUT"),
660 SND_SOC_DAPM_OUTPUT("MONO_LOUT"),
661 SND_SOC_DAPM_OUTPUT("HPLOUT"),
662 SND_SOC_DAPM_OUTPUT("HPROUT"),
663 SND_SOC_DAPM_OUTPUT("HPLCOM"),
664 SND_SOC_DAPM_OUTPUT("HPRCOM"),
665
666 SND_SOC_DAPM_INPUT("MIC3L"),
667 SND_SOC_DAPM_INPUT("MIC3R"),
668 SND_SOC_DAPM_INPUT("LINE1L"),
669 SND_SOC_DAPM_INPUT("LINE1R"),
670 SND_SOC_DAPM_INPUT("LINE2L"),
671 SND_SOC_DAPM_INPUT("LINE2R"),
672
673
674
675
676
677
678
679 SND_SOC_DAPM_OUTPUT("Detection"),
680};
681
682static const struct snd_soc_dapm_widget aic3007_dapm_widgets[] = {
683
684 SND_SOC_DAPM_PGA("Left Class-D Out", CLASSD_CTRL, 3, 0, NULL, 0),
685 SND_SOC_DAPM_PGA("Right Class-D Out", CLASSD_CTRL, 2, 0, NULL, 0),
686
687 SND_SOC_DAPM_OUTPUT("SPOP"),
688 SND_SOC_DAPM_OUTPUT("SPOM"),
689};
690
691static const struct snd_soc_dapm_route intercon[] = {
692
693 {"Left Line1L Mux", "single-ended", "LINE1L"},
694 {"Left Line1L Mux", "differential", "LINE1L"},
695
696 {"Left Line2L Mux", "single-ended", "LINE2L"},
697 {"Left Line2L Mux", "differential", "LINE2L"},
698
699 {"Left PGA Mixer", "Line1L Switch", "Left Line1L Mux"},
700 {"Left PGA Mixer", "Line1R Switch", "Left Line1R Mux"},
701 {"Left PGA Mixer", "Line2L Switch", "Left Line2L Mux"},
702 {"Left PGA Mixer", "Mic3L Switch", "MIC3L"},
703 {"Left PGA Mixer", "Mic3R Switch", "MIC3R"},
704
705 {"Left ADC", NULL, "Left PGA Mixer"},
706 {"Left ADC", NULL, "GPIO1 dmic modclk"},
707
708
709 {"Right Line1R Mux", "single-ended", "LINE1R"},
710 {"Right Line1R Mux", "differential", "LINE1R"},
711
712 {"Right Line2R Mux", "single-ended", "LINE2R"},
713 {"Right Line2R Mux", "differential", "LINE2R"},
714
715 {"Right PGA Mixer", "Line1L Switch", "Right Line1L Mux"},
716 {"Right PGA Mixer", "Line1R Switch", "Right Line1R Mux"},
717 {"Right PGA Mixer", "Line2R Switch", "Right Line2R Mux"},
718 {"Right PGA Mixer", "Mic3L Switch", "MIC3L"},
719 {"Right PGA Mixer", "Mic3R Switch", "MIC3R"},
720
721 {"Right ADC", NULL, "Right PGA Mixer"},
722 {"Right ADC", NULL, "GPIO1 dmic modclk"},
723
724
725
726
727
728 {"GPIO1 dmic modclk", NULL, "DMic Rate 128"},
729 {"GPIO1 dmic modclk", NULL, "DMic Rate 64"},
730 {"GPIO1 dmic modclk", NULL, "DMic Rate 32"},
731
732
733 {"Left DAC Mux", "DAC_L1", "Left DAC"},
734 {"Left DAC Mux", "DAC_L2", "Left DAC"},
735 {"Left DAC Mux", "DAC_L3", "Left DAC"},
736
737
738 {"Right DAC Mux", "DAC_R1", "Right DAC"},
739 {"Right DAC Mux", "DAC_R2", "Right DAC"},
740 {"Right DAC Mux", "DAC_R3", "Right DAC"},
741
742
743 {"Left Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
744 {"Left Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
745 {"Left Line Mixer", "DACL1 Switch", "Left DAC Mux"},
746 {"Left Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
747 {"Left Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
748 {"Left Line Mixer", "DACR1 Switch", "Right DAC Mux"},
749
750 {"Left Line Out", NULL, "Left Line Mixer"},
751 {"Left Line Out", NULL, "Left DAC Mux"},
752 {"LLOUT", NULL, "Left Line Out"},
753
754
755 {"Right Line Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
756 {"Right Line Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
757 {"Right Line Mixer", "DACL1 Switch", "Left DAC Mux"},
758 {"Right Line Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
759 {"Right Line Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
760 {"Right Line Mixer", "DACR1 Switch", "Right DAC Mux"},
761
762 {"Right Line Out", NULL, "Right Line Mixer"},
763 {"Right Line Out", NULL, "Right DAC Mux"},
764 {"RLOUT", NULL, "Right Line Out"},
765
766
767 {"Mono Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
768 {"Mono Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
769 {"Mono Mixer", "DACL1 Switch", "Left DAC Mux"},
770 {"Mono Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
771 {"Mono Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
772 {"Mono Mixer", "DACR1 Switch", "Right DAC Mux"},
773
774 {"Mono Out", NULL, "Mono Mixer"},
775 {"MONO_LOUT", NULL, "Mono Out"},
776
777
778 {"Left HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
779 {"Left HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
780 {"Left HP Mixer", "DACL1 Switch", "Left DAC Mux"},
781 {"Left HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
782 {"Left HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
783 {"Left HP Mixer", "DACR1 Switch", "Right DAC Mux"},
784
785 {"Left HP Out", NULL, "Left HP Mixer"},
786 {"Left HP Out", NULL, "Left DAC Mux"},
787 {"HPLOUT", NULL, "Left HP Out"},
788
789
790 {"Right HP Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
791 {"Right HP Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
792 {"Right HP Mixer", "DACL1 Switch", "Left DAC Mux"},
793 {"Right HP Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
794 {"Right HP Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
795 {"Right HP Mixer", "DACR1 Switch", "Right DAC Mux"},
796
797 {"Right HP Out", NULL, "Right HP Mixer"},
798 {"Right HP Out", NULL, "Right DAC Mux"},
799 {"HPROUT", NULL, "Right HP Out"},
800
801
802 {"Left HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
803 {"Left HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
804 {"Left HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
805 {"Left HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
806 {"Left HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
807 {"Left HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
808
809 {"Left HPCOM Mux", "differential of HPLOUT", "Left HP Mixer"},
810 {"Left HPCOM Mux", "constant VCM", "Left HPCOM Mixer"},
811 {"Left HPCOM Mux", "single-ended", "Left HPCOM Mixer"},
812 {"Left HP Com", NULL, "Left HPCOM Mux"},
813 {"HPLCOM", NULL, "Left HP Com"},
814
815
816 {"Right HPCOM Mixer", "Line2L Bypass Switch", "Left Line2L Mux"},
817 {"Right HPCOM Mixer", "PGAL Bypass Switch", "Left PGA Mixer"},
818 {"Right HPCOM Mixer", "DACL1 Switch", "Left DAC Mux"},
819 {"Right HPCOM Mixer", "Line2R Bypass Switch", "Right Line2R Mux"},
820 {"Right HPCOM Mixer", "PGAR Bypass Switch", "Right PGA Mixer"},
821 {"Right HPCOM Mixer", "DACR1 Switch", "Right DAC Mux"},
822
823 {"Right HPCOM Mux", "differential of HPROUT", "Right HP Mixer"},
824 {"Right HPCOM Mux", "constant VCM", "Right HPCOM Mixer"},
825 {"Right HPCOM Mux", "single-ended", "Right HPCOM Mixer"},
826 {"Right HPCOM Mux", "differential of HPLCOM", "Left HPCOM Mixer"},
827 {"Right HPCOM Mux", "external feedback", "Right HPCOM Mixer"},
828 {"Right HP Com", NULL, "Right HPCOM Mux"},
829 {"HPRCOM", NULL, "Right HP Com"},
830};
831
832static const struct snd_soc_dapm_route intercon_3007[] = {
833
834 {"Left Class-D Out", NULL, "Left Line Out"},
835 {"Right Class-D Out", NULL, "Left Line Out"},
836 {"SPOP", NULL, "Left Class-D Out"},
837 {"SPOM", NULL, "Right Class-D Out"},
838};
839
840static int aic3x_add_widgets(struct snd_soc_codec *codec)
841{
842 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
843 struct snd_soc_dapm_context *dapm = &codec->dapm;
844
845 snd_soc_dapm_new_controls(dapm, aic3x_dapm_widgets,
846 ARRAY_SIZE(aic3x_dapm_widgets));
847
848
849 snd_soc_dapm_add_routes(dapm, intercon, ARRAY_SIZE(intercon));
850
851 if (aic3x->model == AIC3X_MODEL_3007) {
852 snd_soc_dapm_new_controls(dapm, aic3007_dapm_widgets,
853 ARRAY_SIZE(aic3007_dapm_widgets));
854 snd_soc_dapm_add_routes(dapm, intercon_3007,
855 ARRAY_SIZE(intercon_3007));
856 }
857
858 return 0;
859}
860
861static int aic3x_hw_params(struct snd_pcm_substream *substream,
862 struct snd_pcm_hw_params *params,
863 struct snd_soc_dai *dai)
864{
865 struct snd_soc_codec *codec = dai->codec;
866 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
867 int codec_clk = 0, bypass_pll = 0, fsref, last_clk = 0;
868 u8 data, j, r, p, pll_q, pll_p = 1, pll_r = 1, pll_j = 1;
869 u16 d, pll_d = 1;
870 int clk;
871
872
873 data = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & (~(0x3 << 4));
874 switch (params_format(params)) {
875 case SNDRV_PCM_FORMAT_S16_LE:
876 break;
877 case SNDRV_PCM_FORMAT_S20_3LE:
878 data |= (0x01 << 4);
879 break;
880 case SNDRV_PCM_FORMAT_S24_LE:
881 data |= (0x02 << 4);
882 break;
883 case SNDRV_PCM_FORMAT_S32_LE:
884 data |= (0x03 << 4);
885 break;
886 }
887 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, data);
888
889
890 fsref = (params_rate(params) % 11025 == 0) ? 44100 : 48000;
891
892
893
894 for (pll_q = 2; pll_q < 18; pll_q++)
895 if (aic3x->sysclk / (128 * pll_q) == fsref) {
896 bypass_pll = 1;
897 break;
898 }
899
900 if (bypass_pll) {
901 pll_q &= 0xf;
902 snd_soc_write(codec, AIC3X_PLL_PROGA_REG, pll_q << PLLQ_SHIFT);
903 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_CLKDIV);
904
905 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLL_ENABLE, 0);
906
907 } else {
908 snd_soc_write(codec, AIC3X_GPIOB_REG, CODEC_CLKIN_PLLDIV);
909
910 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
911 PLL_ENABLE, PLL_ENABLE);
912 }
913
914
915
916 data = (LDAC2LCH | RDAC2RCH);
917 data |= (fsref == 44100) ? FSREF_44100 : FSREF_48000;
918 if (params_rate(params) >= 64000)
919 data |= DUAL_RATE_MODE;
920 snd_soc_write(codec, AIC3X_CODEC_DATAPATH_REG, data);
921
922
923 data = (fsref * 20) / params_rate(params);
924 if (params_rate(params) < 64000)
925 data /= 2;
926 data /= 5;
927 data -= 2;
928 data |= (data << 4);
929 snd_soc_write(codec, AIC3X_SAMPLE_RATE_SEL_REG, data);
930
931 if (bypass_pll)
932 return 0;
933
934
935
936
937
938
939
940 codec_clk = (2048 * fsref) / (aic3x->sysclk / 1000);
941
942 for (r = 1; r <= 16; r++)
943 for (p = 1; p <= 8; p++) {
944 for (j = 4; j <= 55; j++) {
945
946
947
948
949 int tmp_clk = (1000 * j * r) / p;
950
951
952
953
954 if (abs(codec_clk - tmp_clk) <
955 abs(codec_clk - last_clk)) {
956 pll_j = j; pll_d = 0;
957 pll_r = r; pll_p = p;
958 last_clk = tmp_clk;
959 }
960
961
962 if (tmp_clk == codec_clk)
963 goto found;
964 }
965 }
966
967
968 for (p = 1; p <= 8; p++) {
969 j = codec_clk * p / 1000;
970
971 if (j < 4 || j > 11)
972 continue;
973
974
975 d = ((2048 * p * fsref) - j * aic3x->sysclk)
976 * 100 / (aic3x->sysclk/100);
977
978 clk = (10000 * j + d) / (10 * p);
979
980
981
982 if (abs(codec_clk - clk) < abs(codec_clk - last_clk)) {
983 pll_j = j; pll_d = d; pll_r = 1; pll_p = p;
984 last_clk = clk;
985 }
986
987
988 if (clk == codec_clk)
989 goto found;
990 }
991
992 if (last_clk == 0) {
993 printk(KERN_ERR "%s(): unable to setup PLL\n", __func__);
994 return -EINVAL;
995 }
996
997found:
998 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG, PLLP_MASK, pll_p);
999 snd_soc_write(codec, AIC3X_OVRF_STATUS_AND_PLLR_REG,
1000 pll_r << PLLR_SHIFT);
1001 snd_soc_write(codec, AIC3X_PLL_PROGB_REG, pll_j << PLLJ_SHIFT);
1002 snd_soc_write(codec, AIC3X_PLL_PROGC_REG,
1003 (pll_d >> 6) << PLLD_MSB_SHIFT);
1004 snd_soc_write(codec, AIC3X_PLL_PROGD_REG,
1005 (pll_d & 0x3F) << PLLD_LSB_SHIFT);
1006
1007 return 0;
1008}
1009
1010static int aic3x_mute(struct snd_soc_dai *dai, int mute)
1011{
1012 struct snd_soc_codec *codec = dai->codec;
1013 u8 ldac_reg = snd_soc_read(codec, LDAC_VOL) & ~MUTE_ON;
1014 u8 rdac_reg = snd_soc_read(codec, RDAC_VOL) & ~MUTE_ON;
1015
1016 if (mute) {
1017 snd_soc_write(codec, LDAC_VOL, ldac_reg | MUTE_ON);
1018 snd_soc_write(codec, RDAC_VOL, rdac_reg | MUTE_ON);
1019 } else {
1020 snd_soc_write(codec, LDAC_VOL, ldac_reg);
1021 snd_soc_write(codec, RDAC_VOL, rdac_reg);
1022 }
1023
1024 return 0;
1025}
1026
1027static int aic3x_set_dai_sysclk(struct snd_soc_dai *codec_dai,
1028 int clk_id, unsigned int freq, int dir)
1029{
1030 struct snd_soc_codec *codec = codec_dai->codec;
1031 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1032
1033
1034 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, PLLCLK_IN_MASK,
1035 clk_id << PLLCLK_IN_SHIFT);
1036 snd_soc_update_bits(codec, AIC3X_CLKGEN_CTRL_REG, CLKDIV_IN_MASK,
1037 clk_id << CLKDIV_IN_SHIFT);
1038
1039 aic3x->sysclk = freq;
1040 return 0;
1041}
1042
1043static int aic3x_set_dai_fmt(struct snd_soc_dai *codec_dai,
1044 unsigned int fmt)
1045{
1046 struct snd_soc_codec *codec = codec_dai->codec;
1047 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1048 u8 iface_areg, iface_breg;
1049 int delay = 0;
1050
1051 iface_areg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLA) & 0x3f;
1052 iface_breg = snd_soc_read(codec, AIC3X_ASD_INTF_CTRLB) & 0x3f;
1053
1054
1055 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
1056 case SND_SOC_DAIFMT_CBM_CFM:
1057 aic3x->master = 1;
1058 iface_areg |= BIT_CLK_MASTER | WORD_CLK_MASTER;
1059 break;
1060 case SND_SOC_DAIFMT_CBS_CFS:
1061 aic3x->master = 0;
1062 iface_areg &= ~(BIT_CLK_MASTER | WORD_CLK_MASTER);
1063 break;
1064 default:
1065 return -EINVAL;
1066 }
1067
1068
1069
1070
1071
1072 switch (fmt & (SND_SOC_DAIFMT_FORMAT_MASK |
1073 SND_SOC_DAIFMT_INV_MASK)) {
1074 case (SND_SOC_DAIFMT_I2S | SND_SOC_DAIFMT_NB_NF):
1075 break;
1076 case (SND_SOC_DAIFMT_DSP_A | SND_SOC_DAIFMT_IB_NF):
1077 delay = 1;
1078 case (SND_SOC_DAIFMT_DSP_B | SND_SOC_DAIFMT_IB_NF):
1079 iface_breg |= (0x01 << 6);
1080 break;
1081 case (SND_SOC_DAIFMT_RIGHT_J | SND_SOC_DAIFMT_NB_NF):
1082 iface_breg |= (0x02 << 6);
1083 break;
1084 case (SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_NB_NF):
1085 iface_breg |= (0x03 << 6);
1086 break;
1087 default:
1088 return -EINVAL;
1089 }
1090
1091
1092 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLA, iface_areg);
1093 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLB, iface_breg);
1094 snd_soc_write(codec, AIC3X_ASD_INTF_CTRLC, delay);
1095
1096 return 0;
1097}
1098
1099static int aic3x_init_3007(struct snd_soc_codec *codec)
1100{
1101 u8 tmp1, tmp2, *cache = codec->reg_cache;
1102
1103
1104
1105
1106
1107 tmp1 = cache[0xD];
1108 tmp2 = cache[0x8];
1109
1110 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x0D);
1111 snd_soc_write(codec, 0xD, 0x0D);
1112 snd_soc_write(codec, 0x8, 0x5C);
1113 snd_soc_write(codec, 0x8, 0x5D);
1114 snd_soc_write(codec, 0x8, 0x5C);
1115 snd_soc_write(codec, AIC3X_PAGE_SELECT, 0x00);
1116 cache[0xD] = tmp1;
1117 cache[0x8] = tmp2;
1118
1119 return 0;
1120}
1121
1122static int aic3x_regulator_event(struct notifier_block *nb,
1123 unsigned long event, void *data)
1124{
1125 struct aic3x_disable_nb *disable_nb =
1126 container_of(nb, struct aic3x_disable_nb, nb);
1127 struct aic3x_priv *aic3x = disable_nb->aic3x;
1128
1129 if (event & REGULATOR_EVENT_DISABLE) {
1130
1131
1132
1133
1134 if (gpio_is_valid(aic3x->gpio_reset))
1135 gpio_set_value(aic3x->gpio_reset, 0);
1136 aic3x->codec->cache_sync = 1;
1137 }
1138
1139 return 0;
1140}
1141
1142static int aic3x_set_power(struct snd_soc_codec *codec, int power)
1143{
1144 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1145 int i, ret;
1146 u8 *cache = codec->reg_cache;
1147
1148 if (power) {
1149 ret = regulator_bulk_enable(ARRAY_SIZE(aic3x->supplies),
1150 aic3x->supplies);
1151 if (ret)
1152 goto out;
1153 aic3x->power = 1;
1154
1155
1156
1157
1158 if (!codec->cache_sync)
1159 goto out;
1160
1161 if (gpio_is_valid(aic3x->gpio_reset)) {
1162 udelay(1);
1163 gpio_set_value(aic3x->gpio_reset, 1);
1164 }
1165
1166
1167 codec->cache_only = 0;
1168 for (i = AIC3X_SAMPLE_RATE_SEL_REG; i < ARRAY_SIZE(aic3x_reg); i++)
1169 snd_soc_write(codec, i, cache[i]);
1170 if (aic3x->model == AIC3X_MODEL_3007)
1171 aic3x_init_3007(codec);
1172 codec->cache_sync = 0;
1173 } else {
1174
1175
1176
1177
1178
1179 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1180 codec->cache_sync = 1;
1181 aic3x->power = 0;
1182
1183 codec->cache_only = 1;
1184 ret = regulator_bulk_disable(ARRAY_SIZE(aic3x->supplies),
1185 aic3x->supplies);
1186 }
1187out:
1188 return ret;
1189}
1190
1191static int aic3x_set_bias_level(struct snd_soc_codec *codec,
1192 enum snd_soc_bias_level level)
1193{
1194 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1195
1196 switch (level) {
1197 case SND_SOC_BIAS_ON:
1198 break;
1199 case SND_SOC_BIAS_PREPARE:
1200 if (codec->dapm.bias_level == SND_SOC_BIAS_STANDBY &&
1201 aic3x->master) {
1202
1203 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1204 PLL_ENABLE, PLL_ENABLE);
1205 }
1206 break;
1207 case SND_SOC_BIAS_STANDBY:
1208 if (!aic3x->power)
1209 aic3x_set_power(codec, 1);
1210 if (codec->dapm.bias_level == SND_SOC_BIAS_PREPARE &&
1211 aic3x->master) {
1212
1213 snd_soc_update_bits(codec, AIC3X_PLL_PROGA_REG,
1214 PLL_ENABLE, 0);
1215 }
1216 break;
1217 case SND_SOC_BIAS_OFF:
1218 if (aic3x->power)
1219 aic3x_set_power(codec, 0);
1220 break;
1221 }
1222 codec->dapm.bias_level = level;
1223
1224 return 0;
1225}
1226
1227#define AIC3X_RATES SNDRV_PCM_RATE_8000_96000
1228#define AIC3X_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE | \
1229 SNDRV_PCM_FMTBIT_S24_3LE | SNDRV_PCM_FMTBIT_S32_LE)
1230
1231static const struct snd_soc_dai_ops aic3x_dai_ops = {
1232 .hw_params = aic3x_hw_params,
1233 .digital_mute = aic3x_mute,
1234 .set_sysclk = aic3x_set_dai_sysclk,
1235 .set_fmt = aic3x_set_dai_fmt,
1236};
1237
1238static struct snd_soc_dai_driver aic3x_dai = {
1239 .name = "tlv320aic3x-hifi",
1240 .playback = {
1241 .stream_name = "Playback",
1242 .channels_min = 2,
1243 .channels_max = 2,
1244 .rates = AIC3X_RATES,
1245 .formats = AIC3X_FORMATS,},
1246 .capture = {
1247 .stream_name = "Capture",
1248 .channels_min = 2,
1249 .channels_max = 2,
1250 .rates = AIC3X_RATES,
1251 .formats = AIC3X_FORMATS,},
1252 .ops = &aic3x_dai_ops,
1253 .symmetric_rates = 1,
1254};
1255
1256static int aic3x_suspend(struct snd_soc_codec *codec)
1257{
1258 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1259
1260 return 0;
1261}
1262
1263static int aic3x_resume(struct snd_soc_codec *codec)
1264{
1265 aic3x_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
1266
1267 return 0;
1268}
1269
1270
1271
1272
1273
1274static int aic3x_init(struct snd_soc_codec *codec)
1275{
1276 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1277
1278 snd_soc_write(codec, AIC3X_PAGE_SELECT, PAGE0_SELECT);
1279 snd_soc_write(codec, AIC3X_RESET, SOFT_RESET);
1280
1281
1282 snd_soc_write(codec, LDAC_VOL, DEFAULT_VOL | MUTE_ON);
1283 snd_soc_write(codec, RDAC_VOL, DEFAULT_VOL | MUTE_ON);
1284
1285
1286 snd_soc_write(codec, DACL1_2_HPLOUT_VOL, DEFAULT_VOL | ROUTE_ON);
1287 snd_soc_write(codec, DACR1_2_HPROUT_VOL, DEFAULT_VOL | ROUTE_ON);
1288 snd_soc_write(codec, DACL1_2_HPLCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1289 snd_soc_write(codec, DACR1_2_HPRCOM_VOL, DEFAULT_VOL | ROUTE_ON);
1290
1291 snd_soc_write(codec, DACL1_2_LLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1292 snd_soc_write(codec, DACR1_2_RLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1293
1294 snd_soc_write(codec, DACL1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1295 snd_soc_write(codec, DACR1_2_MONOLOPM_VOL, DEFAULT_VOL | ROUTE_ON);
1296
1297
1298 snd_soc_update_bits(codec, LLOPM_CTRL, UNMUTE, UNMUTE);
1299 snd_soc_update_bits(codec, RLOPM_CTRL, UNMUTE, UNMUTE);
1300 snd_soc_update_bits(codec, MONOLOPM_CTRL, UNMUTE, UNMUTE);
1301 snd_soc_update_bits(codec, HPLOUT_CTRL, UNMUTE, UNMUTE);
1302 snd_soc_update_bits(codec, HPROUT_CTRL, UNMUTE, UNMUTE);
1303 snd_soc_update_bits(codec, HPLCOM_CTRL, UNMUTE, UNMUTE);
1304 snd_soc_update_bits(codec, HPRCOM_CTRL, UNMUTE, UNMUTE);
1305
1306
1307 snd_soc_write(codec, LADC_VOL, DEFAULT_GAIN);
1308 snd_soc_write(codec, RADC_VOL, DEFAULT_GAIN);
1309
1310 snd_soc_write(codec, LINE1L_2_LADC_CTRL, 0x0);
1311 snd_soc_write(codec, LINE1R_2_RADC_CTRL, 0x0);
1312
1313
1314 snd_soc_write(codec, PGAL_2_HPLOUT_VOL, DEFAULT_VOL);
1315 snd_soc_write(codec, PGAR_2_HPROUT_VOL, DEFAULT_VOL);
1316 snd_soc_write(codec, PGAL_2_HPLCOM_VOL, DEFAULT_VOL);
1317 snd_soc_write(codec, PGAR_2_HPRCOM_VOL, DEFAULT_VOL);
1318
1319 snd_soc_write(codec, PGAL_2_LLOPM_VOL, DEFAULT_VOL);
1320 snd_soc_write(codec, PGAR_2_RLOPM_VOL, DEFAULT_VOL);
1321
1322 snd_soc_write(codec, PGAL_2_MONOLOPM_VOL, DEFAULT_VOL);
1323 snd_soc_write(codec, PGAR_2_MONOLOPM_VOL, DEFAULT_VOL);
1324
1325
1326 snd_soc_write(codec, LINE2L_2_HPLOUT_VOL, DEFAULT_VOL);
1327 snd_soc_write(codec, LINE2R_2_HPROUT_VOL, DEFAULT_VOL);
1328 snd_soc_write(codec, LINE2L_2_HPLCOM_VOL, DEFAULT_VOL);
1329 snd_soc_write(codec, LINE2R_2_HPRCOM_VOL, DEFAULT_VOL);
1330
1331 snd_soc_write(codec, LINE2L_2_LLOPM_VOL, DEFAULT_VOL);
1332 snd_soc_write(codec, LINE2R_2_RLOPM_VOL, DEFAULT_VOL);
1333
1334 snd_soc_write(codec, LINE2L_2_MONOLOPM_VOL, DEFAULT_VOL);
1335 snd_soc_write(codec, LINE2R_2_MONOLOPM_VOL, DEFAULT_VOL);
1336
1337 if (aic3x->model == AIC3X_MODEL_3007) {
1338 aic3x_init_3007(codec);
1339 snd_soc_write(codec, CLASSD_CTRL, 0);
1340 }
1341
1342 return 0;
1343}
1344
1345static bool aic3x_is_shared_reset(struct aic3x_priv *aic3x)
1346{
1347 struct aic3x_priv *a;
1348
1349 list_for_each_entry(a, &reset_list, list) {
1350 if (gpio_is_valid(aic3x->gpio_reset) &&
1351 aic3x->gpio_reset == a->gpio_reset)
1352 return true;
1353 }
1354
1355 return false;
1356}
1357
1358static int aic3x_probe(struct snd_soc_codec *codec)
1359{
1360 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1361 int ret, i;
1362
1363 INIT_LIST_HEAD(&aic3x->list);
1364 aic3x->codec = codec;
1365
1366 ret = snd_soc_codec_set_cache_io(codec, 8, 8, aic3x->control_type);
1367 if (ret != 0) {
1368 dev_err(codec->dev, "Failed to set cache I/O: %d\n", ret);
1369 return ret;
1370 }
1371
1372 if (gpio_is_valid(aic3x->gpio_reset) &&
1373 !aic3x_is_shared_reset(aic3x)) {
1374 ret = gpio_request(aic3x->gpio_reset, "tlv320aic3x reset");
1375 if (ret != 0)
1376 goto err_gpio;
1377 gpio_direction_output(aic3x->gpio_reset, 0);
1378 }
1379
1380 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1381 aic3x->supplies[i].supply = aic3x_supply_names[i];
1382
1383 ret = regulator_bulk_get(codec->dev, ARRAY_SIZE(aic3x->supplies),
1384 aic3x->supplies);
1385 if (ret != 0) {
1386 dev_err(codec->dev, "Failed to request supplies: %d\n", ret);
1387 goto err_get;
1388 }
1389 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++) {
1390 aic3x->disable_nb[i].nb.notifier_call = aic3x_regulator_event;
1391 aic3x->disable_nb[i].aic3x = aic3x;
1392 ret = regulator_register_notifier(aic3x->supplies[i].consumer,
1393 &aic3x->disable_nb[i].nb);
1394 if (ret) {
1395 dev_err(codec->dev,
1396 "Failed to request regulator notifier: %d\n",
1397 ret);
1398 goto err_notif;
1399 }
1400 }
1401
1402 codec->cache_only = 1;
1403 aic3x_init(codec);
1404
1405 if (aic3x->setup) {
1406
1407 snd_soc_write(codec, AIC3X_GPIO1_REG,
1408 (aic3x->setup->gpio_func[0] & 0xf) << 4);
1409 snd_soc_write(codec, AIC3X_GPIO2_REG,
1410 (aic3x->setup->gpio_func[1] & 0xf) << 4);
1411 }
1412
1413 snd_soc_add_codec_controls(codec, aic3x_snd_controls,
1414 ARRAY_SIZE(aic3x_snd_controls));
1415 if (aic3x->model == AIC3X_MODEL_3007)
1416 snd_soc_add_codec_controls(codec, &aic3x_classd_amp_gain_ctrl, 1);
1417
1418
1419 switch (aic3x->micbias_vg) {
1420 case AIC3X_MICBIAS_2_0V:
1421 case AIC3X_MICBIAS_2_5V:
1422 case AIC3X_MICBIAS_AVDDV:
1423 snd_soc_update_bits(codec, MICBIAS_CTRL,
1424 MICBIAS_LEVEL_MASK,
1425 (aic3x->micbias_vg) << MICBIAS_LEVEL_SHIFT);
1426 break;
1427 case AIC3X_MICBIAS_OFF:
1428
1429
1430
1431
1432
1433 break;
1434 }
1435
1436 aic3x_add_widgets(codec);
1437 list_add(&aic3x->list, &reset_list);
1438
1439 return 0;
1440
1441err_notif:
1442 while (i--)
1443 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1444 &aic3x->disable_nb[i].nb);
1445 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1446err_get:
1447 if (gpio_is_valid(aic3x->gpio_reset) &&
1448 !aic3x_is_shared_reset(aic3x))
1449 gpio_free(aic3x->gpio_reset);
1450err_gpio:
1451 return ret;
1452}
1453
1454static int aic3x_remove(struct snd_soc_codec *codec)
1455{
1456 struct aic3x_priv *aic3x = snd_soc_codec_get_drvdata(codec);
1457 int i;
1458
1459 aic3x_set_bias_level(codec, SND_SOC_BIAS_OFF);
1460 list_del(&aic3x->list);
1461 if (gpio_is_valid(aic3x->gpio_reset) &&
1462 !aic3x_is_shared_reset(aic3x)) {
1463 gpio_set_value(aic3x->gpio_reset, 0);
1464 gpio_free(aic3x->gpio_reset);
1465 }
1466 for (i = 0; i < ARRAY_SIZE(aic3x->supplies); i++)
1467 regulator_unregister_notifier(aic3x->supplies[i].consumer,
1468 &aic3x->disable_nb[i].nb);
1469 regulator_bulk_free(ARRAY_SIZE(aic3x->supplies), aic3x->supplies);
1470
1471 return 0;
1472}
1473
1474static struct snd_soc_codec_driver soc_codec_dev_aic3x = {
1475 .set_bias_level = aic3x_set_bias_level,
1476 .idle_bias_off = true,
1477 .reg_cache_size = ARRAY_SIZE(aic3x_reg),
1478 .reg_word_size = sizeof(u8),
1479 .reg_cache_default = aic3x_reg,
1480 .probe = aic3x_probe,
1481 .remove = aic3x_remove,
1482 .suspend = aic3x_suspend,
1483 .resume = aic3x_resume,
1484};
1485
1486
1487
1488
1489
1490
1491static const struct i2c_device_id aic3x_i2c_id[] = {
1492 { "tlv320aic3x", AIC3X_MODEL_3X },
1493 { "tlv320aic33", AIC3X_MODEL_33 },
1494 { "tlv320aic3007", AIC3X_MODEL_3007 },
1495 { }
1496};
1497MODULE_DEVICE_TABLE(i2c, aic3x_i2c_id);
1498
1499
1500
1501
1502
1503static int aic3x_i2c_probe(struct i2c_client *i2c,
1504 const struct i2c_device_id *id)
1505{
1506 struct aic3x_pdata *pdata = i2c->dev.platform_data;
1507 struct aic3x_priv *aic3x;
1508 struct aic3x_setup_data *ai3x_setup;
1509 struct device_node *np = i2c->dev.of_node;
1510 int ret;
1511 u32 value;
1512
1513 aic3x = devm_kzalloc(&i2c->dev, sizeof(struct aic3x_priv), GFP_KERNEL);
1514 if (aic3x == NULL) {
1515 dev_err(&i2c->dev, "failed to create private data\n");
1516 return -ENOMEM;
1517 }
1518
1519 aic3x->control_type = SND_SOC_I2C;
1520
1521 i2c_set_clientdata(i2c, aic3x);
1522 if (pdata) {
1523 aic3x->gpio_reset = pdata->gpio_reset;
1524 aic3x->setup = pdata->setup;
1525 aic3x->micbias_vg = pdata->micbias_vg;
1526 } else if (np) {
1527 ai3x_setup = devm_kzalloc(&i2c->dev, sizeof(*ai3x_setup),
1528 GFP_KERNEL);
1529 if (ai3x_setup == NULL) {
1530 dev_err(&i2c->dev, "failed to create private data\n");
1531 return -ENOMEM;
1532 }
1533
1534 ret = of_get_named_gpio(np, "gpio-reset", 0);
1535 if (ret >= 0)
1536 aic3x->gpio_reset = ret;
1537 else
1538 aic3x->gpio_reset = -1;
1539
1540 if (of_property_read_u32_array(np, "ai3x-gpio-func",
1541 ai3x_setup->gpio_func, 2) >= 0) {
1542 aic3x->setup = ai3x_setup;
1543 }
1544
1545 if (!of_property_read_u32(np, "ai3x-micbias-vg", &value)) {
1546 switch (value) {
1547 case 1 :
1548 aic3x->micbias_vg = AIC3X_MICBIAS_2_0V;
1549 break;
1550 case 2 :
1551 aic3x->micbias_vg = AIC3X_MICBIAS_2_5V;
1552 break;
1553 case 3 :
1554 aic3x->micbias_vg = AIC3X_MICBIAS_AVDDV;
1555 break;
1556 default :
1557 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1558 dev_err(&i2c->dev, "Unsuitable MicBias voltage "
1559 "found in DT\n");
1560 }
1561 } else {
1562 aic3x->micbias_vg = AIC3X_MICBIAS_OFF;
1563 }
1564
1565 } else {
1566 aic3x->gpio_reset = -1;
1567 }
1568
1569 aic3x->model = id->driver_data;
1570
1571 ret = snd_soc_register_codec(&i2c->dev,
1572 &soc_codec_dev_aic3x, &aic3x_dai, 1);
1573 return ret;
1574}
1575
1576static int aic3x_i2c_remove(struct i2c_client *client)
1577{
1578 snd_soc_unregister_codec(&client->dev);
1579 return 0;
1580}
1581
1582#if defined(CONFIG_OF)
1583static const struct of_device_id tlv320aic3x_of_match[] = {
1584 { .compatible = "ti,tlv320aic3x", },
1585 {},
1586};
1587MODULE_DEVICE_TABLE(of, tlv320aic3x_of_match);
1588#endif
1589
1590
1591static struct i2c_driver aic3x_i2c_driver = {
1592 .driver = {
1593 .name = "tlv320aic3x-codec",
1594 .owner = THIS_MODULE,
1595 .of_match_table = of_match_ptr(tlv320aic3x_of_match),
1596 },
1597 .probe = aic3x_i2c_probe,
1598 .remove = aic3x_i2c_remove,
1599 .id_table = aic3x_i2c_id,
1600};
1601
1602module_i2c_driver(aic3x_i2c_driver);
1603
1604MODULE_DESCRIPTION("ASoC TLV320AIC3X codec driver");
1605MODULE_AUTHOR("Vladimir Barinov");
1606MODULE_LICENSE("GPL");
1607
