1#ifndef _UAPI__ASM_ALPHA_FPU_H 2#define _UAPI__ASM_ALPHA_FPU_H 3 4 5/* 6 * Alpha floating-point control register defines: 7 */ 8#define FPCR_DNOD (1UL<<47) /* denorm INV trap disable */ 9#define FPCR_DNZ (1UL<<48) /* denorms to zero */ 10#define FPCR_INVD (1UL<<49) /* invalid op disable (opt.) */ 11#define FPCR_DZED (1UL<<50) /* division by zero disable (opt.) */ 12#define FPCR_OVFD (1UL<<51) /* overflow disable (optional) */ 13#define FPCR_INV (1UL<<52) /* invalid operation */ 14#define FPCR_DZE (1UL<<53) /* division by zero */ 15#define FPCR_OVF (1UL<<54) /* overflow */ 16#define FPCR_UNF (1UL<<55) /* underflow */ 17#define FPCR_INE (1UL<<56) /* inexact */ 18#define FPCR_IOV (1UL<<57) /* integer overflow */ 19#define FPCR_UNDZ (1UL<<60) /* underflow to zero (opt.) */ 20#define FPCR_UNFD (1UL<<61) /* underflow disable (opt.) */ 21#define FPCR_INED (1UL<<62) /* inexact disable (opt.) */ 22#define FPCR_SUM (1UL<<63) /* summary bit */ 23 24#define FPCR_DYN_SHIFT 58 /* first dynamic rounding mode bit */ 25#define FPCR_DYN_CHOPPED (0x0UL << FPCR_DYN_SHIFT) /* towards 0 */ 26#define FPCR_DYN_MINUS (0x1UL << FPCR_DYN_SHIFT) /* towards -INF */ 27#define FPCR_DYN_NORMAL (0x2UL << FPCR_DYN_SHIFT) /* towards nearest */ 28#define FPCR_DYN_PLUS (0x3UL << FPCR_DYN_SHIFT) /* towards +INF */ 29#define FPCR_DYN_MASK (0x3UL << FPCR_DYN_SHIFT) 30 31#define FPCR_MASK 0xffff800000000000L 32 33/* 34 * IEEE trap enables are implemented in software. These per-thread 35 * bits are stored in the "ieee_state" field of "struct thread_info". 36 * Thus, the bits are defined so as not to conflict with the 37 * floating-point enable bit (which is architected). On top of that, 38 * we want to make these bits compatible with OSF/1 so 39 * ieee_set_fp_control() etc. can be implemented easily and 40 * compatibly. The corresponding definitions are in 41 * /usr/include/machine/fpu.h under OSF/1. 42 */ 43#define IEEE_TRAP_ENABLE_INV (1UL<<1) /* invalid op */ 44#define IEEE_TRAP_ENABLE_DZE (1UL<<2) /* division by zero */ 45#define IEEE_TRAP_ENABLE_OVF (1UL<<3) /* overflow */ 46#define IEEE_TRAP_ENABLE_UNF (1UL<<4) /* underflow */ 47#define IEEE_TRAP_ENABLE_INE (1UL<<5) /* inexact */ 48#define IEEE_TRAP_ENABLE_DNO (1UL<<6) /* denorm */ 49#define IEEE_TRAP_ENABLE_MASK (IEEE_TRAP_ENABLE_INV | IEEE_TRAP_ENABLE_DZE |\ 50 IEEE_TRAP_ENABLE_OVF | IEEE_TRAP_ENABLE_UNF |\ 51 IEEE_TRAP_ENABLE_INE | IEEE_TRAP_ENABLE_DNO) 52 53/* Denorm and Underflow flushing */ 54#define IEEE_MAP_DMZ (1UL<<12) /* Map denorm inputs to zero */ 55#define IEEE_MAP_UMZ (1UL<<13) /* Map underflowed outputs to zero */ 56 57#define IEEE_MAP_MASK (IEEE_MAP_DMZ | IEEE_MAP_UMZ) 58 59/* status bits coming from fpcr: */ 60#define IEEE_STATUS_INV (1UL<<17) 61#define IEEE_STATUS_DZE (1UL<<18) 62#define IEEE_STATUS_OVF (1UL<<19) 63#define IEEE_STATUS_UNF (1UL<<20) 64#define IEEE_STATUS_INE (1UL<<21) 65#define IEEE_STATUS_DNO (1UL<<22) 66 67#define IEEE_STATUS_MASK (IEEE_STATUS_INV | IEEE_STATUS_DZE | \ 68 IEEE_STATUS_OVF | IEEE_STATUS_UNF | \ 69 IEEE_STATUS_INE | IEEE_STATUS_DNO) 70 71#define IEEE_SW_MASK (IEEE_TRAP_ENABLE_MASK | \ 72 IEEE_STATUS_MASK | IEEE_MAP_MASK) 73 74#define IEEE_CURRENT_RM_SHIFT 32 75#define IEEE_CURRENT_RM_MASK (3UL<<IEEE_CURRENT_RM_SHIFT) 76 77#define IEEE_STATUS_TO_EXCSUM_SHIFT 16 78 79#define IEEE_INHERIT (1UL<<63) /* inherit on thread create? */ 80 81/* 82 * Convert the software IEEE trap enable and status bits into the 83 * hardware fpcr format. 84 * 85 * Digital Unix engineers receive my thanks for not defining the 86 * software bits identical to the hardware bits. The chip designers 87 * receive my thanks for making all the not-implemented fpcr bits 88 * RAZ forcing us to use system calls to read/write this value. 89 */ 90 91static inline unsigned long 92ieee_swcr_to_fpcr(unsigned long sw) 93{ 94 unsigned long fp; 95 fp = (sw & IEEE_STATUS_MASK) << 35; 96 fp |= (sw & IEEE_MAP_DMZ) << 36; 97 fp |= (sw & IEEE_STATUS_MASK ? FPCR_SUM : 0); 98 fp |= (~sw & (IEEE_TRAP_ENABLE_INV 99 | IEEE_TRAP_ENABLE_DZE 100 | IEEE_TRAP_ENABLE_OVF)) << 48; 101 fp |= (~sw & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE)) << 57; 102 fp |= (sw & IEEE_MAP_UMZ ? FPCR_UNDZ | FPCR_UNFD : 0); 103 fp |= (~sw & IEEE_TRAP_ENABLE_DNO) << 41; 104 return fp; 105} 106 107static inline unsigned long 108ieee_fpcr_to_swcr(unsigned long fp) 109{ 110 unsigned long sw; 111 sw = (fp >> 35) & IEEE_STATUS_MASK; 112 sw |= (fp >> 36) & IEEE_MAP_DMZ; 113 sw |= (~fp >> 48) & (IEEE_TRAP_ENABLE_INV 114 | IEEE_TRAP_ENABLE_DZE 115 | IEEE_TRAP_ENABLE_OVF); 116 sw |= (~fp >> 57) & (IEEE_TRAP_ENABLE_UNF | IEEE_TRAP_ENABLE_INE); 117 sw |= (fp >> 47) & IEEE_MAP_UMZ; 118 sw |= (~fp >> 41) & IEEE_TRAP_ENABLE_DNO; 119 return sw; 120} 121 122 123#endif /* _UAPI__ASM_ALPHA_FPU_H */ 124