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9#ifndef __ASM_TLB_MMU_V1_H__
10#define __ASM_TLB_MMU_V1_H__
11
12#include <asm/mmu.h>
13
14#if defined(__ASSEMBLY__) && (CONFIG_ARC_MMU_VER == 1)
15
16.macro TLB_WRITE_HEURISTICS
17
18#define JH_HACK1
19#undef JH_HACK2
20#undef JH_HACK3
21
22#ifdef JH_HACK3
23; Calculate set index for 2-way MMU
24; -avoiding use of GetIndex from MMU
25; and its unpleasant LFSR pseudo-random sequence
26;
27; r1 = TLBPD0 from TLB_RELOAD above
28;
29; -- jh_ex_way_set not cleared on startup
30; didn't want to change setup.c
31; hence extra instruction to clean
32;
33; -- should be in cache since in same line
34; as r0/r1 saves above
35;
36ld r0,[jh_ex_way_sel] ; victim pointer
37and r0,r0,1 ; clean
38xor.f r0,r0,1 ; flip
39st r0,[jh_ex_way_sel] ; store back
40asr r0,r1,12 ; get set # <<1, note bit 12=R=0
41or.nz r0,r0,1 ; set way bit
42and r0,r0,0xff ; clean
43sr r0,[ARC_REG_TLBINDEX]
44#endif
45
46#ifdef JH_HACK2
47; JH hack #2
48; Faster than hack #1 in non-thrash case, but hard-coded for 2-way MMU
49; Slower in thrash case (where it matters) because more code is executed
50; Inefficient due to two-register paradigm of this miss handler
51;
52
53lr r0,[eret]
54xor r0,r0,r1
55and.f r0,r0,0x000fe000
56bne 88f
57
58lr r0,[eret]
59and r0,r0,PAGE_MASK
60; lr r1,[ARC_REG_TLBPD0]
61and r1,r1,0xff
62or r0,r0,r1
63
64lr r1,[ARC_REG_TLBPD0]
65sr r0,[ARC_REG_TLBPD0]
66sr TLBProbe, [ARC_REG_TLBCOMMAND]
67lr r0,[ARC_REG_TLBINDEX]
68sr r1,[ARC_REG_TLBPD0]
69
70xor r0,r0,1
71b.d 89f
72sr r0,[ARC_REG_TLBINDEX]
7388:
74sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
7589:
76#endif
77
78#ifdef JH_HACK1
79;
80; Always checks whether instruction will be kicked out by dtlb miss
81;
82mov_s r3, r1 ; save PD0 prepared by TLB_RELOAD in r3
83lr r0,[eret]
84and r0,r0,PAGE_MASK
85bmsk r1,r3,7
86or_s r0,r0,r1
87
88sr r0,[ARC_REG_TLBPD0]
89sr TLBProbe, [ARC_REG_TLBCOMMAND]
90lr r0,[ARC_REG_TLBINDEX]
91sr r3,[ARC_REG_TLBPD0]
92
93sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
94lr r1,[ARC_REG_TLBINDEX]
95cmp r0,r1
96xor.eq r1,r1,1
97sr r1,[ARC_REG_TLBINDEX]
98#endif
99
100.endm
101
102#endif
103
104#endif
105