LXR linux/arch/arm/include/asm/io.h

   1/*
   2 *  arch/arm/include/asm/io.h
   3 *
   4 *  Copyright (C) 1996-2000 Russell King
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 *
  10 * Modifications:
  11 *  16-Sep-1996 RMK     Inlined the inx/outx functions & optimised for both
  12 *                      constant addresses and variable addresses.
  13 *  04-Dec-1997 RMK     Moved a lot of this stuff to the new architecture
  14 *                      specific IO header files.
  15 *  27-Mar-1999 PJB     Second parameter of memcpy_toio is const..
  16 *  04-Apr-1999 PJB     Added check_signature.
  17 *  12-Dec-1999 RMK     More cleanups
  18 *  18-Jun-2000 RMK     Removed virt_to_* and friends definitions
  19 *  05-Oct-2004 BJD     Moved memory string functions to use void __iomem
  20 */
  21#ifndef __ASM_ARM_IO_H
  22#define __ASM_ARM_IO_H
  23
  24#ifdef __KERNEL__
  25
  26#include <linux/types.h>
  27#include <asm/byteorder.h>
  28#include <asm/memory.h>
  29#include <asm-generic/pci_iomap.h>
  30
  31/*
  32 * ISA I/O bus memory addresses are 1:1 with the physical address.
  33 */
  34#define isa_virt_to_bus virt_to_phys
  35#define isa_page_to_bus page_to_phys
  36#define isa_bus_to_virt phys_to_virt
  37
  38/*
  39 * Generic IO read/write.  These perform native-endian accesses.  Note
  40 * that some architectures will want to re-define __raw_{read,write}w.
  41 */
  42extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
  43extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
  44extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);
  45
  46extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
  47extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
  48extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
  49
  50#if __LINUX_ARM_ARCH__ < 6
  51/*
  52 * Half-word accesses are problematic with RiscPC due to limitations of
  53 * the bus. Rather than special-case the machine, just let the compiler
  54 * generate the access for CPUs prior to ARMv6.
  55 */
  56#define __raw_readw(a)         (__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
  57#define __raw_writew(v,a)      ((void)(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v)))
  58#else
  59/*
  60 * When running under a hypervisor, we want to avoid I/O accesses with
  61 * writeback addressing modes as these incur a significant performance
  62 * overhead (the address generation must be emulated in software).
  63 */
  64static inline void __raw_writew(u16 val, volatile void __iomem *addr)
  65{
  66        asm volatile("strh %1, %0"
  67                     : "+Q" (*(volatile u16 __force *)addr)
  68                     : "r" (val));
  69}
  70
  71static inline u16 __raw_readw(const volatile void __iomem *addr)
  72{
  73        u16 val;
  74        asm volatile("ldrh %1, %0"
  75                     : "+Q" (*(volatile u16 __force *)addr),
  76                       "=r" (val));
  77        return val;
  78}
  79#endif
  80
  81static inline void __raw_writeb(u8 val, volatile void __iomem *addr)
  82{
  83        asm volatile("strb %1, %0"
  84                     : "+Qo" (*(volatile u8 __force *)addr)
  85                     : "r" (val));
  86}
  87
  88static inline void __raw_writel(u32 val, volatile void __iomem *addr)
  89{
  90        asm volatile("str %1, %0"
  91                     : "+Qo" (*(volatile u32 __force *)addr)
  92                     : "r" (val));
  93}
  94
  95static inline u8 __raw_readb(const volatile void __iomem *addr)
  96{
  97        u8 val;
  98        asm volatile("ldrb %1, %0"
  99                     : "+Qo" (*(volatile u8 __force *)addr),
 100                       "=r" (val));
 101        return val;
 102}
 103
 104static inline u32 __raw_readl(const volatile void __iomem *addr)
 105{
 106        u32 val;
 107        asm volatile("ldr %1, %0"
 108                     : "+Qo" (*(volatile u32 __force *)addr),
 109                       "=r" (val));
 110        return val;
 111}
 112
 113/*
 114 * Architecture ioremap implementation.
 115 */
 116#define MT_DEVICE               0
 117#define MT_DEVICE_NONSHARED     1
 118#define MT_DEVICE_CACHED        2
 119#define MT_DEVICE_WC            3
 120/*
 121 * types 4 onwards can be found in asm/mach/map.h and are undefined
 122 * for ioremap
 123 */
 124
 125/*
 126 * __arm_ioremap takes CPU physical address.
 127 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
 128 * The _caller variety takes a __builtin_return_address(0) value for
 129 * /proc/vmalloc to use - and should only be used in non-inline functions.
 130 */
 131extern void __iomem *__arm_ioremap_pfn_caller(unsigned long, unsigned long,
 132        size_t, unsigned int, void *);
 133extern void __iomem *__arm_ioremap_caller(phys_addr_t, size_t, unsigned int,
 134        void *);
 135
 136extern void __iomem *__arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
 137extern void __iomem *__arm_ioremap(phys_addr_t, size_t, unsigned int);
 138extern void __iomem *__arm_ioremap_exec(phys_addr_t, size_t, bool cached);
 139extern void __iounmap(volatile void __iomem *addr);
 140extern void __arm_iounmap(volatile void __iomem *addr);
 141
 142extern void __iomem * (*arch_ioremap_caller)(phys_addr_t, size_t,
 143        unsigned int, void *);
 144extern void (*arch_iounmap)(volatile void __iomem *);
 145
 146/*
 147 * Bad read/write accesses...
 148 */
 149extern void __readwrite_bug(const char *fn);
 150
 151/*
 152 * A typesafe __io() helper
 153 */
 154static inline void __iomem *__typesafe_io(unsigned long addr)
 155{
 156        return (void __iomem *)addr;
 157}
 158
 159#define IOMEM(x)        ((void __force __iomem *)(x))
 160
 161/* IO barriers */
 162#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
 163#include <asm/barrier.h>
 164#define __iormb()               rmb()
 165#define __iowmb()               wmb()
 166#else
 167#define __iormb()               do { } while (0)
 168#define __iowmb()               do { } while (0)
 169#endif
 170
 171/* PCI fixed i/o mapping */
 172#define PCI_IO_VIRT_BASE        0xfee00000
 173
 174extern int pci_ioremap_io(unsigned int offset, phys_addr_t phys_addr);
 175
 176/*
 177 * Now, pick up the machine-defined IO definitions
 178 */
 179#ifdef CONFIG_NEED_MACH_IO_H
 180#include <mach/io.h>
 181#elif defined(CONFIG_PCI)
 182#define IO_SPACE_LIMIT  ((resource_size_t)0xfffff)
 183#define __io(a)         __typesafe_io(PCI_IO_VIRT_BASE + ((a) & IO_SPACE_LIMIT))
 184#else
 185#define __io(a)         __typesafe_io((a) & IO_SPACE_LIMIT)
 186#endif
 187
 188/*
 189 * This is the limit of PC card/PCI/ISA IO space, which is by default
 190 * 64K if we have PC card, PCI or ISA support.  Otherwise, default to
 191 * zero to prevent ISA/PCI drivers claiming IO space (and potentially
 192 * oopsing.)
 193 *
 194 * Only set this larger if you really need inb() et.al. to operate over
 195 * a larger address space.  Note that SOC_COMMON ioremaps each sockets
 196 * IO space area, and so inb() et.al. must be defined to operate as per
 197 * readb() et.al. on such platforms.
 198 */
 199#ifndef IO_SPACE_LIMIT
 200#if defined(CONFIG_PCMCIA_SOC_COMMON) || defined(CONFIG_PCMCIA_SOC_COMMON_MODULE)
 201#define IO_SPACE_LIMIT ((resource_size_t)0xffffffff)
 202#elif defined(CONFIG_PCI) || defined(CONFIG_ISA) || defined(CONFIG_PCCARD)
 203#define IO_SPACE_LIMIT ((resource_size_t)0xffff)
 204#else
 205#define IO_SPACE_LIMIT ((resource_size_t)0)
 206#endif
 207#endif
 208
 209/*
 210 *  IO port access primitives
 211 *  -------------------------
 212 *
 213 * The ARM doesn't have special IO access instructions; all IO is memory
 214 * mapped.  Note that these are defined to perform little endian accesses
 215 * only.  Their primary purpose is to access PCI and ISA peripherals.
 216 *
 217 * Note that for a big endian machine, this implies that the following
 218 * big endian mode connectivity is in place, as described by numerous
 219 * ARM documents:
 220 *
 221 *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
 222 *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
 223 *
 224 * The machine specific io.h include defines __io to translate an "IO"
 225 * address to a memory address.
 226 *
 227 * Note that we prevent GCC re-ordering or caching values in expressions
 228 * by introducing sequence points into the in*() definitions.  Note that
 229 * __raw_* do not guarantee this behaviour.
 230 *
 231 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
 232 */
 233#ifdef __io
 234#define outb(v,p)       ({ __iowmb(); __raw_writeb(v,__io(p)); })
 235#define outw(v,p)       ({ __iowmb(); __raw_writew((__force __u16) \
 236                                        cpu_to_le16(v),__io(p)); })
 237#define outl(v,p)       ({ __iowmb(); __raw_writel((__force __u32) \
 238                                        cpu_to_le32(v),__io(p)); })
 239
 240#define inb(p)  ({ __u8 __v = __raw_readb(__io(p)); __iormb(); __v; })
 241#define inw(p)  ({ __u16 __v = le16_to_cpu((__force __le16) \
 242                        __raw_readw(__io(p))); __iormb(); __v; })
 243#define inl(p)  ({ __u32 __v = le32_to_cpu((__force __le32) \
 244                        __raw_readl(__io(p))); __iormb(); __v; })
 245
 246#define outsb(p,d,l)            __raw_writesb(__io(p),d,l)
 247#define outsw(p,d,l)            __raw_writesw(__io(p),d,l)
 248#define outsl(p,d,l)            __raw_writesl(__io(p),d,l)
 249
 250#define insb(p,d,l)             __raw_readsb(__io(p),d,l)
 251#define insw(p,d,l)             __raw_readsw(__io(p),d,l)
 252#define insl(p,d,l)             __raw_readsl(__io(p),d,l)
 253#endif
 254
 255#define outb_p(val,port)        outb((val),(port))
 256#define outw_p(val,port)        outw((val),(port))
 257#define outl_p(val,port)        outl((val),(port))
 258#define inb_p(port)             inb((port))
 259#define inw_p(port)             inw((port))
 260#define inl_p(port)             inl((port))
 261
 262#define outsb_p(port,from,len)  outsb(port,from,len)
 263#define outsw_p(port,from,len)  outsw(port,from,len)
 264#define outsl_p(port,from,len)  outsl(port,from,len)
 265#define insb_p(port,to,len)     insb(port,to,len)
 266#define insw_p(port,to,len)     insw(port,to,len)
 267#define insl_p(port,to,len)     insl(port,to,len)
 268
 269/*
 270 * String version of IO memory access ops:
 271 */
 272extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
 273extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
 274extern void _memset_io(volatile void __iomem *, int, size_t);
 275
 276#define mmiowb()
 277
 278/*
 279 *  Memory access primitives
 280 *  ------------------------
 281 *
 282 * These perform PCI memory accesses via an ioremap region.  They don't
 283 * take an address as such, but a cookie.
 284 *
 285 * Again, this are defined to perform little endian accesses.  See the
 286 * IO port primitives for more information.
 287 */
 288#ifndef readl
 289#define readb_relaxed(c) ({ u8  __r = __raw_readb(c); __r; })
 290#define readw_relaxed(c) ({ u16 __r = le16_to_cpu((__force __le16) \
 291                                        __raw_readw(c)); __r; })
 292#define readl_relaxed(c) ({ u32 __r = le32_to_cpu((__force __le32) \
 293                                        __raw_readl(c)); __r; })
 294
 295#define writeb_relaxed(v,c)     __raw_writeb(v,c)
 296#define writew_relaxed(v,c)     __raw_writew((__force u16) cpu_to_le16(v),c)
 297#define writel_relaxed(v,c)     __raw_writel((__force u32) cpu_to_le32(v),c)
 298
 299#define readb(c)                ({ u8  __v = readb_relaxed(c); __iormb(); __v; })
 300#define readw(c)                ({ u16 __v = readw_relaxed(c); __iormb(); __v; })
 301#define readl(c)                ({ u32 __v = readl_relaxed(c); __iormb(); __v; })
 302
 303#define writeb(v,c)             ({ __iowmb(); writeb_relaxed(v,c); })
 304#define writew(v,c)             ({ __iowmb(); writew_relaxed(v,c); })
 305#define writel(v,c)             ({ __iowmb(); writel_relaxed(v,c); })
 306
 307#define readsb(p,d,l)           __raw_readsb(p,d,l)
 308#define readsw(p,d,l)           __raw_readsw(p,d,l)
 309#define readsl(p,d,l)           __raw_readsl(p,d,l)
 310
 311#define writesb(p,d,l)          __raw_writesb(p,d,l)
 312#define writesw(p,d,l)          __raw_writesw(p,d,l)
 313#define writesl(p,d,l)          __raw_writesl(p,d,l)
 314
 315#define memset_io(c,v,l)        _memset_io(c,(v),(l))
 316#define memcpy_fromio(a,c,l)    _memcpy_fromio((a),c,(l))
 317#define memcpy_toio(c,a,l)      _memcpy_toio(c,(a),(l))
 318
 319#endif  /* readl */
 320
 321/*
 322 * ioremap and friends.
 323 *
 324 * ioremap takes a PCI memory address, as specified in
 325 * Documentation/io-mapping.txt.
 326 *
 327 */
 328#define ioremap(cookie,size)            __arm_ioremap((cookie), (size), MT_DEVICE)
 329#define ioremap_nocache(cookie,size)    __arm_ioremap((cookie), (size), MT_DEVICE)
 330#define ioremap_cached(cookie,size)     __arm_ioremap((cookie), (size), MT_DEVICE_CACHED)
 331#define ioremap_wc(cookie,size)         __arm_ioremap((cookie), (size), MT_DEVICE_WC)
 332#define iounmap                         __arm_iounmap
 333
 334/*
 335 * io{read,write}{8,16,32} macros
 336 */
 337#ifndef ioread8
 338#define ioread8(p)      ({ unsigned int __v = __raw_readb(p); __iormb(); __v; })
 339#define ioread16(p)     ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __iormb(); __v; })
 340#define ioread32(p)     ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __iormb(); __v; })
 341
 342#define ioread16be(p)   ({ unsigned int __v = be16_to_cpu((__force __be16)__raw_readw(p)); __iormb(); __v; })
 343#define ioread32be(p)   ({ unsigned int __v = be32_to_cpu((__force __be32)__raw_readl(p)); __iormb(); __v; })
 344
 345#define iowrite8(v,p)   ({ __iowmb(); __raw_writeb(v, p); })
 346#define iowrite16(v,p)  ({ __iowmb(); __raw_writew((__force __u16)cpu_to_le16(v), p); })
 347#define iowrite32(v,p)  ({ __iowmb(); __raw_writel((__force __u32)cpu_to_le32(v), p); })
 348
 349#define iowrite16be(v,p) ({ __iowmb(); __raw_writew((__force __u16)cpu_to_be16(v), p); })
 350#define iowrite32be(v,p) ({ __iowmb(); __raw_writel((__force __u32)cpu_to_be32(v), p); })
 351
 352#define ioread8_rep(p,d,c)      __raw_readsb(p,d,c)
 353#define ioread16_rep(p,d,c)     __raw_readsw(p,d,c)
 354#define ioread32_rep(p,d,c)     __raw_readsl(p,d,c)
 355
 356#define iowrite8_rep(p,s,c)     __raw_writesb(p,s,c)
 357#define iowrite16_rep(p,s,c)    __raw_writesw(p,s,c)
 358#define iowrite32_rep(p,s,c)    __raw_writesl(p,s,c)
 359
 360extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
 361extern void ioport_unmap(void __iomem *addr);
 362#endif
 363
 364struct pci_dev;
 365
 366extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
 367
 368/*
 369 * can the hardware map this into one segment or not, given no other
 370 * constraints.
 371 */
 372#define BIOVEC_MERGEABLE(vec1, vec2)    \
 373        ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
 374
 375#ifdef CONFIG_MMU
 376#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
 377extern int valid_phys_addr_range(phys_addr_t addr, size_t size);
 378extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
 379extern int devmem_is_allowed(unsigned long pfn);
 380#endif
 381
 382/*
 383 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 384 * access
 385 */
 386#define xlate_dev_mem_ptr(p)    __va(p)
 387
 388/*
 389 * Convert a virtual cached pointer to an uncached pointer
 390 */
 391#define xlate_dev_kmem_ptr(p)   p
 392
 393/*
 394 * Register ISA memory and port locations for glibc iopl/inb/outb
 395 * emulation.
 396 */
 397extern void register_isa_ports(unsigned int mmio, unsigned int io,
 398                               unsigned int io_shift);
 399
 400#endif  /* __KERNEL__ */
 401#endif  /* __ASM_ARM_IO_H */
 402