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8#include <linux/export.h>
9#include <linux/kernel.h>
10#include <linux/pci.h>
11#include <linux/slab.h>
12#include <linux/init.h>
13#include <linux/io.h>
14
15#include <asm/mach-types.h>
16#include <asm/mach/map.h>
17#include <asm/mach/pci.h>
18
19static int debug_pci;
20
21
22
23
24
25static void pcibios_bus_report_status(struct pci_bus *bus, u_int status_mask, int warn)
26{
27 struct pci_dev *dev;
28
29 list_for_each_entry(dev, &bus->devices, bus_list) {
30 u16 status;
31
32
33
34
35
36 if (dev->bus->number == 0 && dev->devfn == 0)
37 continue;
38
39 pci_read_config_word(dev, PCI_STATUS, &status);
40 if (status == 0xffff)
41 continue;
42
43 if ((status & status_mask) == 0)
44 continue;
45
46
47 pci_write_config_word(dev, PCI_STATUS, status & status_mask);
48
49 if (warn)
50 printk("(%s: %04X) ", pci_name(dev), status);
51 }
52
53 list_for_each_entry(dev, &bus->devices, bus_list)
54 if (dev->subordinate)
55 pcibios_bus_report_status(dev->subordinate, status_mask, warn);
56}
57
58void pcibios_report_status(u_int status_mask, int warn)
59{
60 struct list_head *l;
61
62 list_for_each(l, &pci_root_buses) {
63 struct pci_bus *bus = pci_bus_b(l);
64
65 pcibios_bus_report_status(bus, status_mask, warn);
66 }
67}
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80
81static void pci_fixup_83c553(struct pci_dev *dev)
82{
83
84
85
86 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, PCI_BASE_ADDRESS_SPACE_MEMORY);
87 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_IO);
88
89 dev->resource[0].end -= dev->resource[0].start;
90 dev->resource[0].start = 0;
91
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93
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95 pci_write_config_byte(dev, 0x48, 0xff);
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102 pci_write_config_byte(dev, 0x42, 0x01);
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107 pci_write_config_byte(dev, 0x40, 0x22);
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115 pci_write_config_byte(dev, 0x83, 0x02);
116
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121 pci_write_config_byte(dev, 0x80, 0x11);
122 pci_write_config_byte(dev, 0x81, 0x00);
123
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127
128 pci_write_config_word(dev, 0x44, 0xb000);
129 outb(0x08, 0x4d1);
130}
131DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_83C553, pci_fixup_83c553);
132
133static void pci_fixup_unassign(struct pci_dev *dev)
134{
135 dev->resource[0].end -= dev->resource[0].start;
136 dev->resource[0].start = 0;
137}
138DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND2, PCI_DEVICE_ID_WINBOND2_89C940F, pci_fixup_unassign);
139
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144
145static void pci_fixup_dec21285(struct pci_dev *dev)
146{
147 int i;
148
149 if (dev->devfn == 0) {
150 dev->class &= 0xff;
151 dev->class |= PCI_CLASS_BRIDGE_HOST << 8;
152 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
153 dev->resource[i].start = 0;
154 dev->resource[i].end = 0;
155 dev->resource[i].flags = 0;
156 }
157 }
158}
159DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21285, pci_fixup_dec21285);
160
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163
164static void pci_fixup_ide_bases(struct pci_dev *dev)
165{
166 struct resource *r;
167 int i;
168
169 if ((dev->class >> 8) != PCI_CLASS_STORAGE_IDE)
170 return;
171
172 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
173 r = dev->resource + i;
174 if ((r->start & ~0x80) == 0x374) {
175 r->start |= 2;
176 r->end = r->start;
177 }
178 }
179}
180DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases);
181
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183
184
185static void pci_fixup_dec21142(struct pci_dev *dev)
186{
187 pci_write_config_dword(dev, 0x40, 0x80000000);
188}
189DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_21142, pci_fixup_dec21142);
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207static void pci_fixup_cy82c693(struct pci_dev *dev)
208{
209 if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE) {
210 u32 base0, base1;
211
212 if (dev->class & 0x80) {
213 base0 = 0x1f0;
214 base1 = 0x3f4;
215 } else {
216 base0 = 0x170;
217 base1 = 0x374;
218 }
219
220 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0,
221 base0 | PCI_BASE_ADDRESS_SPACE_IO);
222 pci_write_config_dword(dev, PCI_BASE_ADDRESS_1,
223 base1 | PCI_BASE_ADDRESS_SPACE_IO);
224
225 dev->resource[0].start = 0;
226 dev->resource[0].end = 0;
227 dev->resource[0].flags = 0;
228
229 dev->resource[1].start = 0;
230 dev->resource[1].end = 0;
231 dev->resource[1].flags = 0;
232 } else if (PCI_FUNC(dev->devfn) == 0) {
233
234
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236 pci_write_config_byte(dev, 0x4b, 14);
237 pci_write_config_byte(dev, 0x4c, 15);
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242 pci_write_config_byte(dev, 0x4d, 0x41);
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247 pci_write_config_byte(dev, 0x44, 0x17);
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252 pci_write_config_byte(dev, 0x45, 0x03);
253 }
254}
255DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, pci_fixup_cy82c693);
256
257static void pci_fixup_it8152(struct pci_dev *dev)
258{
259 int i;
260
261
262 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_HOST ||
263 dev->class == 0x68000 ||
264 dev->class == 0x80103) {
265 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
266 dev->resource[i].start = 0;
267 dev->resource[i].end = 0;
268 dev->resource[i].flags = 0;
269 }
270 }
271}
272DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8152, pci_fixup_it8152);
273
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277
278static inline int pdev_bad_for_parity(struct pci_dev *dev)
279{
280 return ((dev->vendor == PCI_VENDOR_ID_INTERG &&
281 (dev->device == PCI_DEVICE_ID_INTERG_2000 ||
282 dev->device == PCI_DEVICE_ID_INTERG_2010)) ||
283 (dev->vendor == PCI_VENDOR_ID_ITE &&
284 dev->device == PCI_DEVICE_ID_ITE_8152));
285
286}
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291
292void pcibios_fixup_bus(struct pci_bus *bus)
293{
294 struct pci_dev *dev;
295 u16 features = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_FAST_BACK;
296
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300
301 list_for_each_entry(dev, &bus->devices, bus_list) {
302 u16 status;
303
304 pci_read_config_word(dev, PCI_STATUS, &status);
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311
312 if (!(status & PCI_STATUS_FAST_BACK))
313 features &= ~PCI_COMMAND_FAST_BACK;
314
315 if (pdev_bad_for_parity(dev))
316 features &= ~(PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
317
318 switch (dev->class >> 8) {
319 case PCI_CLASS_BRIDGE_PCI:
320 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &status);
321 status |= PCI_BRIDGE_CTL_PARITY|PCI_BRIDGE_CTL_MASTER_ABORT;
322 status &= ~(PCI_BRIDGE_CTL_BUS_RESET|PCI_BRIDGE_CTL_FAST_BACK);
323 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, status);
324 break;
325
326 case PCI_CLASS_BRIDGE_CARDBUS:
327 pci_read_config_word(dev, PCI_CB_BRIDGE_CONTROL, &status);
328 status |= PCI_CB_BRIDGE_CTL_PARITY|PCI_CB_BRIDGE_CTL_MASTER_ABORT;
329 pci_write_config_word(dev, PCI_CB_BRIDGE_CONTROL, status);
330 break;
331 }
332 }
333
334
335
336
337 list_for_each_entry(dev, &bus->devices, bus_list) {
338 u16 cmd;
339
340 pci_read_config_word(dev, PCI_COMMAND, &cmd);
341 cmd |= features;
342 pci_write_config_word(dev, PCI_COMMAND, cmd);
343
344 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE,
345 L1_CACHE_BYTES >> 2);
346 }
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351 if (bus->self && bus->self->hdr_type == PCI_HEADER_TYPE_BRIDGE) {
352 if (features & PCI_COMMAND_FAST_BACK)
353 bus->bridge_ctl |= PCI_BRIDGE_CTL_FAST_BACK;
354 if (features & PCI_COMMAND_PARITY)
355 bus->bridge_ctl |= PCI_BRIDGE_CTL_PARITY;
356 }
357
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360
361 printk(KERN_INFO "PCI: bus%d: Fast back to back transfers %sabled\n",
362 bus->number, (features & PCI_COMMAND_FAST_BACK) ? "en" : "dis");
363}
364EXPORT_SYMBOL(pcibios_fixup_bus);
365
366void pcibios_add_bus(struct pci_bus *bus)
367{
368 struct pci_sys_data *sys = bus->sysdata;
369 if (sys->add_bus)
370 sys->add_bus(bus);
371}
372
373void pcibios_remove_bus(struct pci_bus *bus)
374{
375 struct pci_sys_data *sys = bus->sysdata;
376 if (sys->remove_bus)
377 sys->remove_bus(bus);
378}
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395static u8 pcibios_swizzle(struct pci_dev *dev, u8 *pin)
396{
397 struct pci_sys_data *sys = dev->sysdata;
398 int slot, oldpin = *pin;
399
400 if (sys->swizzle)
401 slot = sys->swizzle(dev, pin);
402 else
403 slot = pci_common_swizzle(dev, pin);
404
405 if (debug_pci)
406 printk("PCI: %s swizzling pin %d => pin %d slot %d\n",
407 pci_name(dev), oldpin, *pin, slot);
408
409 return slot;
410}
411
412
413
414
415static int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
416{
417 struct pci_sys_data *sys = dev->sysdata;
418 int irq = -1;
419
420 if (sys->map_irq)
421 irq = sys->map_irq(dev, slot, pin);
422
423 if (debug_pci)
424 printk("PCI: %s mapping slot %d pin %d => irq %d\n",
425 pci_name(dev), slot, pin, irq);
426
427 return irq;
428}
429
430static int pcibios_init_resources(int busnr, struct pci_sys_data *sys)
431{
432 int ret;
433 struct pci_host_bridge_window *window;
434
435 if (list_empty(&sys->resources)) {
436 pci_add_resource_offset(&sys->resources,
437 &iomem_resource, sys->mem_offset);
438 }
439
440 list_for_each_entry(window, &sys->resources, list) {
441 if (resource_type(window->res) == IORESOURCE_IO)
442 return 0;
443 }
444
445 sys->io_res.start = (busnr * SZ_64K) ? : pcibios_min_io;
446 sys->io_res.end = (busnr + 1) * SZ_64K - 1;
447 sys->io_res.flags = IORESOURCE_IO;
448 sys->io_res.name = sys->io_res_name;
449 sprintf(sys->io_res_name, "PCI%d I/O", busnr);
450
451 ret = request_resource(&ioport_resource, &sys->io_res);
452 if (ret) {
453 pr_err("PCI: unable to allocate I/O port region (%d)\n", ret);
454 return ret;
455 }
456 pci_add_resource_offset(&sys->resources, &sys->io_res,
457 sys->io_offset);
458
459 return 0;
460}
461
462static void pcibios_init_hw(struct device *parent, struct hw_pci *hw,
463 struct list_head *head)
464{
465 struct pci_sys_data *sys = NULL;
466 int ret;
467 int nr, busnr;
468
469 for (nr = busnr = 0; nr < hw->nr_controllers; nr++) {
470 sys = kzalloc(sizeof(struct pci_sys_data), GFP_KERNEL);
471 if (!sys)
472 panic("PCI: unable to allocate sys data!");
473
474#ifdef CONFIG_PCI_DOMAINS
475 sys->domain = hw->domain;
476#endif
477 sys->busnr = busnr;
478 sys->swizzle = hw->swizzle;
479 sys->map_irq = hw->map_irq;
480 sys->align_resource = hw->align_resource;
481 sys->add_bus = hw->add_bus;
482 sys->remove_bus = hw->remove_bus;
483 INIT_LIST_HEAD(&sys->resources);
484
485 if (hw->private_data)
486 sys->private_data = hw->private_data[nr];
487
488 ret = hw->setup(nr, sys);
489
490 if (ret > 0) {
491 ret = pcibios_init_resources(nr, sys);
492 if (ret) {
493 kfree(sys);
494 break;
495 }
496
497 if (hw->scan)
498 sys->bus = hw->scan(nr, sys);
499 else
500 sys->bus = pci_scan_root_bus(parent, sys->busnr,
501 hw->ops, sys, &sys->resources);
502
503 if (!sys->bus)
504 panic("PCI: unable to scan bus!");
505
506 busnr = sys->bus->busn_res.end + 1;
507
508 list_add(&sys->node, head);
509 } else {
510 kfree(sys);
511 if (ret < 0)
512 break;
513 }
514 }
515}
516
517void pci_common_init_dev(struct device *parent, struct hw_pci *hw)
518{
519 struct pci_sys_data *sys;
520 LIST_HEAD(head);
521
522 pci_add_flags(PCI_REASSIGN_ALL_RSRC);
523 if (hw->preinit)
524 hw->preinit();
525 pcibios_init_hw(parent, hw, &head);
526 if (hw->postinit)
527 hw->postinit();
528
529 pci_fixup_irqs(pcibios_swizzle, pcibios_map_irq);
530
531 list_for_each_entry(sys, &head, node) {
532 struct pci_bus *bus = sys->bus;
533
534 if (!pci_has_flag(PCI_PROBE_ONLY)) {
535
536
537
538 pci_bus_size_bridges(bus);
539
540
541
542
543 pci_bus_assign_resources(bus);
544 }
545
546
547
548
549 pci_bus_add_devices(bus);
550 }
551}
552
553#ifndef CONFIG_PCI_HOST_ITE8152
554void pcibios_set_master(struct pci_dev *dev)
555{
556
557}
558#endif
559
560char * __init pcibios_setup(char *str)
561{
562 if (!strcmp(str, "debug")) {
563 debug_pci = 1;
564 return NULL;
565 } else if (!strcmp(str, "firmware")) {
566 pci_add_flags(PCI_PROBE_ONLY);
567 return NULL;
568 }
569 return str;
570}
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586
587resource_size_t pcibios_align_resource(void *data, const struct resource *res,
588 resource_size_t size, resource_size_t align)
589{
590 struct pci_dev *dev = data;
591 struct pci_sys_data *sys = dev->sysdata;
592 resource_size_t start = res->start;
593
594 if (res->flags & IORESOURCE_IO && start & 0x300)
595 start = (start + 0x3ff) & ~0x3ff;
596
597 start = (start + align - 1) & ~(align - 1);
598
599 if (sys->align_resource)
600 return sys->align_resource(dev, res, start, size, align);
601
602 return start;
603}
604
605
606
607
608
609int pcibios_enable_device(struct pci_dev *dev, int mask)
610{
611 u16 cmd, old_cmd;
612 int idx;
613 struct resource *r;
614
615 pci_read_config_word(dev, PCI_COMMAND, &cmd);
616 old_cmd = cmd;
617 for (idx = 0; idx < 6; idx++) {
618
619 if (!(mask & (1 << idx)))
620 continue;
621
622 r = dev->resource + idx;
623 if (!r->start && r->end) {
624 printk(KERN_ERR "PCI: Device %s not available because"
625 " of resource collisions\n", pci_name(dev));
626 return -EINVAL;
627 }
628 if (r->flags & IORESOURCE_IO)
629 cmd |= PCI_COMMAND_IO;
630 if (r->flags & IORESOURCE_MEM)
631 cmd |= PCI_COMMAND_MEMORY;
632 }
633
634
635
636
637 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
638 cmd |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
639
640 if (cmd != old_cmd) {
641 printk("PCI: enabling device %s (%04x -> %04x)\n",
642 pci_name(dev), old_cmd, cmd);
643 pci_write_config_word(dev, PCI_COMMAND, cmd);
644 }
645 return 0;
646}
647
648int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
649 enum pci_mmap_state mmap_state, int write_combine)
650{
651 struct pci_sys_data *root = dev->sysdata;
652 unsigned long phys;
653
654 if (mmap_state == pci_mmap_io) {
655 return -EINVAL;
656 } else {
657 phys = vma->vm_pgoff + (root->mem_offset >> PAGE_SHIFT);
658 }
659
660
661
662
663 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
664
665 if (remap_pfn_range(vma, vma->vm_start, phys,
666 vma->vm_end - vma->vm_start,
667 vma->vm_page_prot))
668 return -EAGAIN;
669
670 return 0;
671}
672
673void __init pci_map_io_early(unsigned long pfn)
674{
675 struct map_desc pci_io_desc = {
676 .virtual = PCI_IO_VIRT_BASE,
677 .type = MT_DEVICE,
678 .length = SZ_64K,
679 };
680
681 pci_io_desc.pfn = pfn;
682 iotable_init(&pci_io_desc, 1);
683}
684