linux/arch/arm/mach-omap1/include/mach/hardware.h
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   1/*
   2 * arch/arm/mach-omap1/include/mach/hardware.h
   3 *
   4 * Hardware definitions for TI OMAP processors and boards
   5 *
   6 * NOTE: Please put device driver specific defines into a separate header
   7 *       file for each driver.
   8 *
   9 * Copyright (C) 2001 RidgeRun, Inc.
  10 * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
  11 *
  12 * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
  13 *                          and Dirk Behme <dirk.behme@de.bosch.com>
  14 *
  15 * This program is free software; you can redistribute it and/or modify it
  16 * under the terms of the GNU General Public License as published by the
  17 * Free Software Foundation; either version 2 of the License, or (at your
  18 * option) any later version.
  19 *
  20 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  23 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  26 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30 *
  31 * You should have received a copy of the GNU General Public License along
  32 * with this program; if not, write to the Free Software Foundation, Inc.,
  33 * 675 Mass Ave, Cambridge, MA 02139, USA.
  34 */
  35
  36#ifndef __ASM_ARCH_OMAP_HARDWARE_H
  37#define __ASM_ARCH_OMAP_HARDWARE_H
  38
  39#include <asm/sizes.h>
  40#ifndef __ASSEMBLER__
  41#include <asm/types.h>
  42#include <mach/soc.h>
  43
  44/*
  45 * NOTE: Please use ioremap + __raw_read/write where possible instead of these
  46 */
  47extern u8 omap_readb(u32 pa);
  48extern u16 omap_readw(u32 pa);
  49extern u32 omap_readl(u32 pa);
  50extern void omap_writeb(u8 v, u32 pa);
  51extern void omap_writew(u16 v, u32 pa);
  52extern void omap_writel(u32 v, u32 pa);
  53
  54#include <mach/tc.h>
  55
  56/* Almost all documentation for chip and board memory maps assumes
  57 * BM is clear.  Most devel boards have a switch to control booting
  58 * from NOR flash (using external chipselect 3) rather than mask ROM,
  59 * which uses BM to interchange the physical CS0 and CS3 addresses.
  60 */
  61static inline u32 omap_cs0m_phys(void)
  62{
  63        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
  64                        ?  OMAP_CS3_PHYS : 0;
  65}
  66
  67static inline u32 omap_cs3_phys(void)
  68{
  69        return (omap_readl(EMIFS_CONFIG) & OMAP_EMIFS_CONFIG_BM)
  70                        ? 0 : OMAP_CS3_PHYS;
  71}
  72
  73#endif  /* ifndef __ASSEMBLER__ */
  74
  75#define OMAP1_IO_OFFSET         0x01000000      /* Virtual IO = 0xfefb0000 */
  76#define OMAP1_IO_ADDRESS(pa)    IOMEM((pa) - OMAP1_IO_OFFSET)
  77
  78#include <mach/serial.h>
  79
  80/*
  81 * ---------------------------------------------------------------------------
  82 * Common definitions for all OMAP processors
  83 * NOTE: Put all processor or board specific parts to the special header
  84 *       files.
  85 * ---------------------------------------------------------------------------
  86 */
  87
  88/*
  89 * ----------------------------------------------------------------------------
  90 * Timers
  91 * ----------------------------------------------------------------------------
  92 */
  93#define OMAP_MPU_TIMER1_BASE    (0xfffec500)
  94#define OMAP_MPU_TIMER2_BASE    (0xfffec600)
  95#define OMAP_MPU_TIMER3_BASE    (0xfffec700)
  96#define MPU_TIMER_FREE          (1 << 6)
  97#define MPU_TIMER_CLOCK_ENABLE  (1 << 5)
  98#define MPU_TIMER_AR            (1 << 1)
  99#define MPU_TIMER_ST            (1 << 0)
 100
 101/*
 102 * ----------------------------------------------------------------------------
 103 * Clocks
 104 * ----------------------------------------------------------------------------
 105 */
 106#define CLKGEN_REG_BASE         (0xfffece00)
 107#define ARM_CKCTL               (CLKGEN_REG_BASE + 0x0)
 108#define ARM_IDLECT1             (CLKGEN_REG_BASE + 0x4)
 109#define ARM_IDLECT2             (CLKGEN_REG_BASE + 0x8)
 110#define ARM_EWUPCT              (CLKGEN_REG_BASE + 0xC)
 111#define ARM_RSTCT1              (CLKGEN_REG_BASE + 0x10)
 112#define ARM_RSTCT2              (CLKGEN_REG_BASE + 0x14)
 113#define ARM_SYSST               (CLKGEN_REG_BASE + 0x18)
 114#define ARM_IDLECT3             (CLKGEN_REG_BASE + 0x24)
 115
 116#define CK_RATEF                1
 117#define CK_IDLEF                2
 118#define CK_ENABLEF              4
 119#define CK_SELECTF              8
 120#define SETARM_IDLE_SHIFT
 121
 122/* DPLL control registers */
 123#define DPLL_CTL                (0xfffecf00)
 124
 125/* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
 126#define DSP_CONFIG_REG_BASE     IOMEM(0xe1008000)
 127#define DSP_CKCTL               (DSP_CONFIG_REG_BASE + 0x0)
 128#define DSP_IDLECT1             (DSP_CONFIG_REG_BASE + 0x4)
 129#define DSP_IDLECT2             (DSP_CONFIG_REG_BASE + 0x8)
 130#define DSP_RSTCT2              (DSP_CONFIG_REG_BASE + 0x14)
 131
 132/*
 133 * ---------------------------------------------------------------------------
 134 * UPLD
 135 * ---------------------------------------------------------------------------
 136 */
 137#define ULPD_REG_BASE           (0xfffe0800)
 138#define ULPD_IT_STATUS          (ULPD_REG_BASE + 0x14)
 139#define ULPD_SETUP_ANALOG_CELL_3        (ULPD_REG_BASE + 0x24)
 140#define ULPD_CLOCK_CTRL         (ULPD_REG_BASE + 0x30)
 141#       define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
 142#       define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
 143#define ULPD_SOFT_REQ           (ULPD_REG_BASE + 0x34)
 144#       define SOFT_UDC_REQ             (1 << 4)
 145#       define SOFT_USB_CLK_REQ         (1 << 3)
 146#       define SOFT_DPLL_REQ            (1 << 0)
 147#define ULPD_DPLL_CTRL          (ULPD_REG_BASE + 0x3c)
 148#define ULPD_STATUS_REQ         (ULPD_REG_BASE + 0x40)
 149#define ULPD_APLL_CTRL          (ULPD_REG_BASE + 0x4c)
 150#define ULPD_POWER_CTRL         (ULPD_REG_BASE + 0x50)
 151#define ULPD_SOFT_DISABLE_REQ_REG       (ULPD_REG_BASE + 0x68)
 152#       define DIS_MMC2_DPLL_REQ        (1 << 11)
 153#       define DIS_MMC1_DPLL_REQ        (1 << 10)
 154#       define DIS_UART3_DPLL_REQ       (1 << 9)
 155#       define DIS_UART2_DPLL_REQ       (1 << 8)
 156#       define DIS_UART1_DPLL_REQ       (1 << 7)
 157#       define DIS_USB_HOST_DPLL_REQ    (1 << 6)
 158#define ULPD_SDW_CLK_DIV_CTRL_SEL       (ULPD_REG_BASE + 0x74)
 159#define ULPD_CAM_CLK_CTRL       (ULPD_REG_BASE + 0x7c)
 160
 161/*
 162 * ---------------------------------------------------------------------------
 163 * Watchdog timer
 164 * ---------------------------------------------------------------------------
 165 */
 166
 167/* Watchdog timer within the OMAP3.2 gigacell */
 168#define OMAP_MPU_WATCHDOG_BASE  (0xfffec800)
 169#define OMAP_WDT_TIMER          (OMAP_MPU_WATCHDOG_BASE + 0x0)
 170#define OMAP_WDT_LOAD_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
 171#define OMAP_WDT_READ_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
 172#define OMAP_WDT_TIMER_MODE     (OMAP_MPU_WATCHDOG_BASE + 0x8)
 173
 174/*
 175 * ---------------------------------------------------------------------------
 176 * Interrupts
 177 * ---------------------------------------------------------------------------
 178 */
 179#ifdef CONFIG_ARCH_OMAP1
 180
 181/*
 182 * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
 183 * or something similar.. -- PFM.
 184 */
 185
 186#define OMAP_IH1_BASE           0xfffecb00
 187#define OMAP_IH2_BASE           0xfffe0000
 188
 189#define OMAP_IH1_ITR            (OMAP_IH1_BASE + 0x00)
 190#define OMAP_IH1_MIR            (OMAP_IH1_BASE + 0x04)
 191#define OMAP_IH1_SIR_IRQ        (OMAP_IH1_BASE + 0x10)
 192#define OMAP_IH1_SIR_FIQ        (OMAP_IH1_BASE + 0x14)
 193#define OMAP_IH1_CONTROL        (OMAP_IH1_BASE + 0x18)
 194#define OMAP_IH1_ILR0           (OMAP_IH1_BASE + 0x1c)
 195#define OMAP_IH1_ISR            (OMAP_IH1_BASE + 0x9c)
 196
 197#define OMAP_IH2_ITR            (OMAP_IH2_BASE + 0x00)
 198#define OMAP_IH2_MIR            (OMAP_IH2_BASE + 0x04)
 199#define OMAP_IH2_SIR_IRQ        (OMAP_IH2_BASE + 0x10)
 200#define OMAP_IH2_SIR_FIQ        (OMAP_IH2_BASE + 0x14)
 201#define OMAP_IH2_CONTROL        (OMAP_IH2_BASE + 0x18)
 202#define OMAP_IH2_ILR0           (OMAP_IH2_BASE + 0x1c)
 203#define OMAP_IH2_ISR            (OMAP_IH2_BASE + 0x9c)
 204
 205#define IRQ_ITR_REG_OFFSET      0x00
 206#define IRQ_MIR_REG_OFFSET      0x04
 207#define IRQ_SIR_IRQ_REG_OFFSET  0x10
 208#define IRQ_SIR_FIQ_REG_OFFSET  0x14
 209#define IRQ_CONTROL_REG_OFFSET  0x18
 210#define IRQ_ISR_REG_OFFSET      0x9c
 211#define IRQ_ILR0_REG_OFFSET     0x1c
 212#define IRQ_GMR_REG_OFFSET      0xa0
 213
 214#endif
 215
 216/*
 217 * ----------------------------------------------------------------------------
 218 * System control registers
 219 * ----------------------------------------------------------------------------
 220 */
 221#define MOD_CONF_CTRL_0         0xfffe1080
 222#define MOD_CONF_CTRL_1         0xfffe1110
 223
 224/*
 225 * ----------------------------------------------------------------------------
 226 * Pin multiplexing registers
 227 * ----------------------------------------------------------------------------
 228 */
 229#define FUNC_MUX_CTRL_0         0xfffe1000
 230#define FUNC_MUX_CTRL_1         0xfffe1004
 231#define FUNC_MUX_CTRL_2         0xfffe1008
 232#define COMP_MODE_CTRL_0        0xfffe100c
 233#define FUNC_MUX_CTRL_3         0xfffe1010
 234#define FUNC_MUX_CTRL_4         0xfffe1014
 235#define FUNC_MUX_CTRL_5         0xfffe1018
 236#define FUNC_MUX_CTRL_6         0xfffe101C
 237#define FUNC_MUX_CTRL_7         0xfffe1020
 238#define FUNC_MUX_CTRL_8         0xfffe1024
 239#define FUNC_MUX_CTRL_9         0xfffe1028
 240#define FUNC_MUX_CTRL_A         0xfffe102C
 241#define FUNC_MUX_CTRL_B         0xfffe1030
 242#define FUNC_MUX_CTRL_C         0xfffe1034
 243#define FUNC_MUX_CTRL_D         0xfffe1038
 244#define PULL_DWN_CTRL_0         0xfffe1040
 245#define PULL_DWN_CTRL_1         0xfffe1044
 246#define PULL_DWN_CTRL_2         0xfffe1048
 247#define PULL_DWN_CTRL_3         0xfffe104c
 248#define PULL_DWN_CTRL_4         0xfffe10ac
 249
 250/* OMAP-1610 specific multiplexing registers */
 251#define FUNC_MUX_CTRL_E         0xfffe1090
 252#define FUNC_MUX_CTRL_F         0xfffe1094
 253#define FUNC_MUX_CTRL_10        0xfffe1098
 254#define FUNC_MUX_CTRL_11        0xfffe109c
 255#define FUNC_MUX_CTRL_12        0xfffe10a0
 256#define PU_PD_SEL_0             0xfffe10b4
 257#define PU_PD_SEL_1             0xfffe10b8
 258#define PU_PD_SEL_2             0xfffe10bc
 259#define PU_PD_SEL_3             0xfffe10c0
 260#define PU_PD_SEL_4             0xfffe10c4
 261
 262/* Timer32K for 1610 and 1710*/
 263#define OMAP_TIMER32K_BASE      0xFFFBC400
 264
 265/*
 266 * ---------------------------------------------------------------------------
 267 * TIPB bus interface
 268 * ---------------------------------------------------------------------------
 269 */
 270#define TIPB_PUBLIC_CNTL_BASE           0xfffed300
 271#define MPU_PUBLIC_TIPB_CNTL            (TIPB_PUBLIC_CNTL_BASE + 0x8)
 272#define TIPB_PRIVATE_CNTL_BASE          0xfffeca00
 273#define MPU_PRIVATE_TIPB_CNTL           (TIPB_PRIVATE_CNTL_BASE + 0x8)
 274
 275/*
 276 * ----------------------------------------------------------------------------
 277 * MPUI interface
 278 * ----------------------------------------------------------------------------
 279 */
 280#define MPUI_BASE                       (0xfffec900)
 281#define MPUI_CTRL                       (MPUI_BASE + 0x0)
 282#define MPUI_DEBUG_ADDR                 (MPUI_BASE + 0x4)
 283#define MPUI_DEBUG_DATA                 (MPUI_BASE + 0x8)
 284#define MPUI_DEBUG_FLAG                 (MPUI_BASE + 0xc)
 285#define MPUI_STATUS_REG                 (MPUI_BASE + 0x10)
 286#define MPUI_DSP_STATUS                 (MPUI_BASE + 0x14)
 287#define MPUI_DSP_BOOT_CONFIG            (MPUI_BASE + 0x18)
 288#define MPUI_DSP_API_CONFIG             (MPUI_BASE + 0x1c)
 289
 290/*
 291 * ----------------------------------------------------------------------------
 292 * LED Pulse Generator
 293 * ----------------------------------------------------------------------------
 294 */
 295#define OMAP_LPG1_BASE                  0xfffbd000
 296#define OMAP_LPG2_BASE                  0xfffbd800
 297#define OMAP_LPG1_LCR                   (OMAP_LPG1_BASE + 0x00)
 298#define OMAP_LPG1_PMR                   (OMAP_LPG1_BASE + 0x04)
 299#define OMAP_LPG2_LCR                   (OMAP_LPG2_BASE + 0x00)
 300#define OMAP_LPG2_PMR                   (OMAP_LPG2_BASE + 0x04)
 301
 302/*
 303 * ----------------------------------------------------------------------------
 304 * Pulse-Width Light
 305 * ----------------------------------------------------------------------------
 306 */
 307#define OMAP_PWL_BASE                   0xfffb5800
 308#define OMAP_PWL_ENABLE                 (OMAP_PWL_BASE + 0x00)
 309#define OMAP_PWL_CLK_ENABLE             (OMAP_PWL_BASE + 0x04)
 310
 311/*
 312 * ---------------------------------------------------------------------------
 313 * Processor specific defines
 314 * ---------------------------------------------------------------------------
 315 */
 316
 317#include "omap7xx.h"
 318#include "omap1510.h"
 319#include "omap16xx.h"
 320
 321#endif  /* __ASM_ARCH_OMAP_HARDWARE_H */
 322