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15#undef DEBUG
16
17#include <linux/kernel.h>
18#include <linux/export.h>
19#include <linux/list.h>
20#include <linux/errno.h>
21#include <linux/err.h>
22#include <linux/delay.h>
23#include <linux/clk-provider.h>
24#include <linux/io.h>
25#include <linux/bitops.h>
26#include <linux/clk-private.h>
27#include <asm/cpu.h>
28
29
30#include <trace/events/power.h>
31
32#include "soc.h"
33#include "clockdomain.h"
34#include "clock.h"
35#include "cm.h"
36#include "cm2xxx.h"
37#include "cm3xxx.h"
38#include "cm-regbits-24xx.h"
39#include "cm-regbits-34xx.h"
40#include "common.h"
41
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43
44
45
46#define MAX_MODULE_ENABLE_WAIT 100000
47
48u16 cpu_mask;
49
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55
56static bool clkdm_control = true;
57
58static LIST_HEAD(clk_hw_omap_clocks);
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63
64unsigned long omap_fixed_divisor_recalc(struct clk_hw *hw,
65 unsigned long parent_rate)
66{
67 struct clk_hw_omap *oclk;
68
69 if (!hw) {
70 pr_warn("%s: hw is NULL\n", __func__);
71 return -EINVAL;
72 }
73
74 oclk = to_clk_hw_omap(hw);
75
76 WARN_ON(!oclk->fixed_div);
77
78 return parent_rate / oclk->fixed_div;
79}
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101static int _wait_idlest_generic(void __iomem *reg, u32 mask, u8 idlest,
102 const char *name)
103{
104 int i = 0, ena = 0;
105
106 ena = (idlest) ? 0 : mask;
107
108 omap_test_timeout(((__raw_readl(reg) & mask) == ena),
109 MAX_MODULE_ENABLE_WAIT, i);
110
111 if (i < MAX_MODULE_ENABLE_WAIT)
112 pr_debug("omap clock: module associated with clock %s ready after %d loops\n",
113 name, i);
114 else
115 pr_err("omap clock: module associated with clock %s didn't enable in %d tries\n",
116 name, MAX_MODULE_ENABLE_WAIT);
117
118 return (i < MAX_MODULE_ENABLE_WAIT) ? 1 : 0;
119};
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131static void _omap2_module_wait_ready(struct clk_hw_omap *clk)
132{
133 void __iomem *companion_reg, *idlest_reg;
134 u8 other_bit, idlest_bit, idlest_val, idlest_reg_id;
135 s16 prcm_mod;
136 int r;
137
138
139 if (clk->ops->find_companion) {
140 clk->ops->find_companion(clk, &companion_reg, &other_bit);
141 if (!(__raw_readl(companion_reg) & (1 << other_bit)))
142 return;
143 }
144
145 clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
146 r = cm_split_idlest_reg(idlest_reg, &prcm_mod, &idlest_reg_id);
147 if (r) {
148
149 _wait_idlest_generic(idlest_reg, (1 << idlest_bit), idlest_val,
150 __clk_get_name(clk->hw.clk));
151 } else {
152 cm_wait_module_ready(prcm_mod, idlest_reg_id, idlest_bit);
153 };
154}
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166void omap2_init_clk_clkdm(struct clk_hw *hw)
167{
168 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
169 struct clockdomain *clkdm;
170 const char *clk_name;
171
172 if (!clk->clkdm_name)
173 return;
174
175 clk_name = __clk_get_name(hw->clk);
176
177 clkdm = clkdm_lookup(clk->clkdm_name);
178 if (clkdm) {
179 pr_debug("clock: associated clk %s to clkdm %s\n",
180 clk_name, clk->clkdm_name);
181 clk->clkdm = clkdm;
182 } else {
183 pr_debug("clock: could not associate clk %s to clkdm %s\n",
184 clk_name, clk->clkdm_name);
185 }
186}
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196void __init omap2_clk_disable_clkdm_control(void)
197{
198 clkdm_control = false;
199}
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222void omap2_clk_dflt_find_companion(struct clk_hw_omap *clk,
223 void __iomem **other_reg, u8 *other_bit)
224{
225 u32 r;
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231 r = ((__force u32)clk->enable_reg ^ (CM_FCLKEN ^ CM_ICLKEN));
232
233 *other_reg = (__force void __iomem *)r;
234 *other_bit = clk->enable_bit;
235}
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251void omap2_clk_dflt_find_idlest(struct clk_hw_omap *clk,
252 void __iomem **idlest_reg, u8 *idlest_bit, u8 *idlest_val)
253{
254 u32 r;
255
256 r = (((__force u32)clk->enable_reg & ~0xf0) | 0x20);
257 *idlest_reg = (__force void __iomem *)r;
258 *idlest_bit = clk->enable_bit;
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265 if (cpu_is_omap24xx())
266 *idlest_val = OMAP24XX_CM_IDLEST_VAL;
267 else if (cpu_is_omap34xx())
268 *idlest_val = OMAP34XX_CM_IDLEST_VAL;
269 else
270 BUG();
271
272}
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285
286int omap2_dflt_clk_enable(struct clk_hw *hw)
287{
288 struct clk_hw_omap *clk;
289 u32 v;
290 int ret = 0;
291
292 clk = to_clk_hw_omap(hw);
293
294 if (clkdm_control && clk->clkdm) {
295 ret = clkdm_clk_enable(clk->clkdm, hw->clk);
296 if (ret) {
297 WARN(1, "%s: could not enable %s's clockdomain %s: %d\n",
298 __func__, __clk_get_name(hw->clk),
299 clk->clkdm->name, ret);
300 return ret;
301 }
302 }
303
304 if (unlikely(clk->enable_reg == NULL)) {
305 pr_err("%s: %s missing enable_reg\n", __func__,
306 __clk_get_name(hw->clk));
307 ret = -EINVAL;
308 goto err;
309 }
310
311
312 v = __raw_readl(clk->enable_reg);
313 if (clk->flags & INVERT_ENABLE)
314 v &= ~(1 << clk->enable_bit);
315 else
316 v |= (1 << clk->enable_bit);
317 __raw_writel(v, clk->enable_reg);
318 v = __raw_readl(clk->enable_reg);
319
320 if (clk->ops && clk->ops->find_idlest)
321 _omap2_module_wait_ready(clk);
322
323 return 0;
324
325err:
326 if (clkdm_control && clk->clkdm)
327 clkdm_clk_disable(clk->clkdm, hw->clk);
328 return ret;
329}
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340void omap2_dflt_clk_disable(struct clk_hw *hw)
341{
342 struct clk_hw_omap *clk;
343 u32 v;
344
345 clk = to_clk_hw_omap(hw);
346 if (!clk->enable_reg) {
347
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350
351 pr_err("%s: independent clock %s has no enable_reg\n",
352 __func__, __clk_get_name(hw->clk));
353 return;
354 }
355
356 v = __raw_readl(clk->enable_reg);
357 if (clk->flags & INVERT_ENABLE)
358 v |= (1 << clk->enable_bit);
359 else
360 v &= ~(1 << clk->enable_bit);
361 __raw_writel(v, clk->enable_reg);
362
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364 if (clkdm_control && clk->clkdm)
365 clkdm_clk_disable(clk->clkdm, hw->clk);
366}
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380int omap2_clkops_enable_clkdm(struct clk_hw *hw)
381{
382 struct clk_hw_omap *clk;
383 int ret = 0;
384
385 clk = to_clk_hw_omap(hw);
386
387 if (unlikely(!clk->clkdm)) {
388 pr_err("%s: %s: no clkdm set ?!\n", __func__,
389 __clk_get_name(hw->clk));
390 return -EINVAL;
391 }
392
393 if (unlikely(clk->enable_reg))
394 pr_err("%s: %s: should use dflt_clk_enable ?!\n", __func__,
395 __clk_get_name(hw->clk));
396
397 if (!clkdm_control) {
398 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
399 __func__, __clk_get_name(hw->clk));
400 return 0;
401 }
402
403 ret = clkdm_clk_enable(clk->clkdm, hw->clk);
404 WARN(ret, "%s: could not enable %s's clockdomain %s: %d\n",
405 __func__, __clk_get_name(hw->clk), clk->clkdm->name, ret);
406
407 return ret;
408}
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419void omap2_clkops_disable_clkdm(struct clk_hw *hw)
420{
421 struct clk_hw_omap *clk;
422
423 clk = to_clk_hw_omap(hw);
424
425 if (unlikely(!clk->clkdm)) {
426 pr_err("%s: %s: no clkdm set ?!\n", __func__,
427 __clk_get_name(hw->clk));
428 return;
429 }
430
431 if (unlikely(clk->enable_reg))
432 pr_err("%s: %s: should use dflt_clk_disable ?!\n", __func__,
433 __clk_get_name(hw->clk));
434
435 if (!clkdm_control) {
436 pr_err("%s: %s: clkfw-based clockdomain control disabled ?!\n",
437 __func__, __clk_get_name(hw->clk));
438 return;
439 }
440
441 clkdm_clk_disable(clk->clkdm, hw->clk);
442}
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452int omap2_dflt_clk_is_enabled(struct clk_hw *hw)
453{
454 struct clk_hw_omap *clk = to_clk_hw_omap(hw);
455 u32 v;
456
457 v = __raw_readl(clk->enable_reg);
458
459 if (clk->flags & INVERT_ENABLE)
460 v ^= BIT(clk->enable_bit);
461
462 v &= BIT(clk->enable_bit);
463
464 return v ? 1 : 0;
465}
466
467static int __initdata mpurate;
468
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472
473static int __init omap_clk_setup(char *str)
474{
475 get_option(&str, &mpurate);
476
477 if (!mpurate)
478 return 1;
479
480 if (mpurate < 1000)
481 mpurate *= 1000000;
482
483 return 1;
484}
485__setup("mpurate=", omap_clk_setup);
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496void omap2_init_clk_hw_omap_clocks(struct clk *clk)
497{
498 struct clk_hw_omap *c;
499
500 if (__clk_get_flags(clk) & CLK_IS_BASIC)
501 return;
502
503 c = to_clk_hw_omap(__clk_get_hw(clk));
504 list_add(&c->node, &clk_hw_omap_clocks);
505}
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516int omap2_clk_enable_autoidle_all(void)
517{
518 struct clk_hw_omap *c;
519
520 list_for_each_entry(c, &clk_hw_omap_clocks, node)
521 if (c->ops && c->ops->allow_idle)
522 c->ops->allow_idle(c);
523 return 0;
524}
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535int omap2_clk_disable_autoidle_all(void)
536{
537 struct clk_hw_omap *c;
538
539 list_for_each_entry(c, &clk_hw_omap_clocks, node)
540 if (c->ops && c->ops->deny_idle)
541 c->ops->deny_idle(c);
542 return 0;
543}
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555void omap2_clk_enable_init_clocks(const char **clk_names, u8 num_clocks)
556{
557 struct clk *init_clk;
558 int i;
559
560 for (i = 0; i < num_clocks; i++) {
561 init_clk = clk_get(NULL, clk_names[i]);
562 clk_prepare_enable(init_clk);
563 }
564}
565
566const struct clk_hw_omap_ops clkhwops_wait = {
567 .find_idlest = omap2_clk_dflt_find_idlest,
568 .find_companion = omap2_clk_dflt_find_companion,
569};
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575void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
576{
577 struct omap_clk *c;
578
579 for (c = oclks; c < oclks + cnt; c++) {
580 clkdev_add(&c->lk);
581 if (!__clk_init(NULL, c->lk.clk))
582 omap2_init_clk_hw_omap_clocks(c->lk.clk);
583 }
584}
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601int __init omap2_clk_switch_mpurate_at_boot(const char *mpurate_ck_name)
602{
603 struct clk *mpurate_ck;
604 int r;
605
606 if (!mpurate)
607 return -EINVAL;
608
609 mpurate_ck = clk_get(NULL, mpurate_ck_name);
610 if (WARN(IS_ERR(mpurate_ck), "Failed to get %s.\n", mpurate_ck_name))
611 return -ENOENT;
612
613 r = clk_set_rate(mpurate_ck, mpurate);
614 if (r < 0) {
615 WARN(1, "clock: %s: unable to set MPU rate to %d: %d\n",
616 mpurate_ck_name, mpurate, r);
617 clk_put(mpurate_ck);
618 return -EINVAL;
619 }
620
621 calibrate_delay();
622 clk_put(mpurate_ck);
623
624 return 0;
625}
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639void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
640 const char *core_ck_name,
641 const char *mpu_ck_name)
642{
643 struct clk *hfclkin_ck, *core_ck, *mpu_ck;
644 unsigned long hfclkin_rate;
645
646 mpu_ck = clk_get(NULL, mpu_ck_name);
647 if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
648 return;
649
650 core_ck = clk_get(NULL, core_ck_name);
651 if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
652 return;
653
654 hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
655 if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
656 return;
657
658 hfclkin_rate = clk_get_rate(hfclkin_ck);
659
660 pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
661 (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
662 (clk_get_rate(core_ck) / 1000000),
663 (clk_get_rate(mpu_ck) / 1000000));
664}
665