LXR linux/arch/arm/mach-u300/timer.c

   1/*
   2 *
   3 * arch/arm/mach-u300/timer.c
   4 *
   5 *
   6 * Copyright (C) 2007-2009 ST-Ericsson AB
   7 * License terms: GNU General Public License (GPL) version 2
   8 * Timer COH 901 328, runs the OS timer interrupt.
   9 * Author: Linus Walleij <linus.walleij@stericsson.com>
  10 */
  11#include <linux/interrupt.h>
  12#include <linux/time.h>
  13#include <linux/timex.h>
  14#include <linux/clockchips.h>
  15#include <linux/clocksource.h>
  16#include <linux/types.h>
  17#include <linux/io.h>
  18#include <linux/clk.h>
  19#include <linux/err.h>
  20#include <linux/irq.h>
  21#include <linux/delay.h>
  22#include <linux/of_address.h>
  23#include <linux/of_irq.h>
  24#include <linux/sched_clock.h>
  25
  26/* Generic stuff */
  27#include <asm/mach/map.h>
  28#include <asm/mach/time.h>
  29
  30/*
  31 * APP side special timer registers
  32 * This timer contains four timers which can fire an interrupt each.
  33 * OS (operating system) timer @ 32768 Hz
  34 * DD (device driver) timer @ 1 kHz
  35 * GP1 (general purpose 1) timer @ 1MHz
  36 * GP2 (general purpose 2) timer @ 1MHz
  37 */
  38
  39/* Reset OS Timer 32bit (-/W) */
  40#define U300_TIMER_APP_ROST                                     (0x0000)
  41#define U300_TIMER_APP_ROST_TIMER_RESET                         (0x00000000)
  42/* Enable OS Timer 32bit (-/W) */
  43#define U300_TIMER_APP_EOST                                     (0x0004)
  44#define U300_TIMER_APP_EOST_TIMER_ENABLE                        (0x00000000)
  45/* Disable OS Timer 32bit (-/W) */
  46#define U300_TIMER_APP_DOST                                     (0x0008)
  47#define U300_TIMER_APP_DOST_TIMER_DISABLE                       (0x00000000)
  48/* OS Timer Mode Register 32bit (-/W) */
  49#define U300_TIMER_APP_SOSTM                                    (0x000c)
  50#define U300_TIMER_APP_SOSTM_MODE_CONTINUOUS                    (0x00000000)
  51#define U300_TIMER_APP_SOSTM_MODE_ONE_SHOT                      (0x00000001)
  52/* OS Timer Status Register 32bit (R/-) */
  53#define U300_TIMER_APP_OSTS                                     (0x0010)
  54#define U300_TIMER_APP_OSTS_TIMER_STATE_MASK                    (0x0000000F)
  55#define U300_TIMER_APP_OSTS_TIMER_STATE_IDLE                    (0x00000001)
  56#define U300_TIMER_APP_OSTS_TIMER_STATE_ACTIVE                  (0x00000002)
  57#define U300_TIMER_APP_OSTS_ENABLE_IND                          (0x00000010)
  58#define U300_TIMER_APP_OSTS_MODE_MASK                           (0x00000020)
  59#define U300_TIMER_APP_OSTS_MODE_CONTINUOUS                     (0x00000000)
  60#define U300_TIMER_APP_OSTS_MODE_ONE_SHOT                       (0x00000020)
  61#define U300_TIMER_APP_OSTS_IRQ_ENABLED_IND                     (0x00000040)
  62#define U300_TIMER_APP_OSTS_IRQ_PENDING_IND                     (0x00000080)
  63/* OS Timer Current Count Register 32bit (R/-) */
  64#define U300_TIMER_APP_OSTCC                                    (0x0014)
  65/* OS Timer Terminal Count Register 32bit (R/W) */
  66#define U300_TIMER_APP_OSTTC                                    (0x0018)
  67/* OS Timer Interrupt Enable Register 32bit (-/W) */
  68#define U300_TIMER_APP_OSTIE                                    (0x001c)
  69#define U300_TIMER_APP_OSTIE_IRQ_DISABLE                        (0x00000000)
  70#define U300_TIMER_APP_OSTIE_IRQ_ENABLE                         (0x00000001)
  71/* OS Timer Interrupt Acknowledge Register 32bit (-/W) */
  72#define U300_TIMER_APP_OSTIA                                    (0x0020)
  73#define U300_TIMER_APP_OSTIA_IRQ_ACK                            (0x00000080)
  74
  75/* Reset DD Timer 32bit (-/W) */
  76#define U300_TIMER_APP_RDDT                                     (0x0040)
  77#define U300_TIMER_APP_RDDT_TIMER_RESET                         (0x00000000)
  78/* Enable DD Timer 32bit (-/W) */
  79#define U300_TIMER_APP_EDDT                                     (0x0044)
  80#define U300_TIMER_APP_EDDT_TIMER_ENABLE                        (0x00000000)
  81/* Disable DD Timer 32bit (-/W) */
  82#define U300_TIMER_APP_DDDT                                     (0x0048)
  83#define U300_TIMER_APP_DDDT_TIMER_DISABLE                       (0x00000000)
  84/* DD Timer Mode Register 32bit (-/W) */
  85#define U300_TIMER_APP_SDDTM                                    (0x004c)
  86#define U300_TIMER_APP_SDDTM_MODE_CONTINUOUS                    (0x00000000)
  87#define U300_TIMER_APP_SDDTM_MODE_ONE_SHOT                      (0x00000001)
  88/* DD Timer Status Register 32bit (R/-) */
  89#define U300_TIMER_APP_DDTS                                     (0x0050)
  90#define U300_TIMER_APP_DDTS_TIMER_STATE_MASK                    (0x0000000F)
  91#define U300_TIMER_APP_DDTS_TIMER_STATE_IDLE                    (0x00000001)
  92#define U300_TIMER_APP_DDTS_TIMER_STATE_ACTIVE                  (0x00000002)
  93#define U300_TIMER_APP_DDTS_ENABLE_IND                          (0x00000010)
  94#define U300_TIMER_APP_DDTS_MODE_MASK                           (0x00000020)
  95#define U300_TIMER_APP_DDTS_MODE_CONTINUOUS                     (0x00000000)
  96#define U300_TIMER_APP_DDTS_MODE_ONE_SHOT                       (0x00000020)
  97#define U300_TIMER_APP_DDTS_IRQ_ENABLED_IND                     (0x00000040)
  98#define U300_TIMER_APP_DDTS_IRQ_PENDING_IND                     (0x00000080)
  99/* DD Timer Current Count Register 32bit (R/-) */
 100#define U300_TIMER_APP_DDTCC                                    (0x0054)
 101/* DD Timer Terminal Count Register 32bit (R/W) */
 102#define U300_TIMER_APP_DDTTC                                    (0x0058)
 103/* DD Timer Interrupt Enable Register 32bit (-/W) */
 104#define U300_TIMER_APP_DDTIE                                    (0x005c)
 105#define U300_TIMER_APP_DDTIE_IRQ_DISABLE                        (0x00000000)
 106#define U300_TIMER_APP_DDTIE_IRQ_ENABLE                         (0x00000001)
 107/* DD Timer Interrupt Acknowledge Register 32bit (-/W) */
 108#define U300_TIMER_APP_DDTIA                                    (0x0060)
 109#define U300_TIMER_APP_DDTIA_IRQ_ACK                            (0x00000080)
 110
 111/* Reset GP1 Timer 32bit (-/W) */
 112#define U300_TIMER_APP_RGPT1                                    (0x0080)
 113#define U300_TIMER_APP_RGPT1_TIMER_RESET                        (0x00000000)
 114/* Enable GP1 Timer 32bit (-/W) */
 115#define U300_TIMER_APP_EGPT1                                    (0x0084)
 116#define U300_TIMER_APP_EGPT1_TIMER_ENABLE                       (0x00000000)
 117/* Disable GP1 Timer 32bit (-/W) */
 118#define U300_TIMER_APP_DGPT1                                    (0x0088)
 119#define U300_TIMER_APP_DGPT1_TIMER_DISABLE                      (0x00000000)
 120/* GP1 Timer Mode Register 32bit (-/W) */
 121#define U300_TIMER_APP_SGPT1M                                   (0x008c)
 122#define U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS                   (0x00000000)
 123#define U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT                     (0x00000001)
 124/* GP1 Timer Status Register 32bit (R/-) */
 125#define U300_TIMER_APP_GPT1S                                    (0x0090)
 126#define U300_TIMER_APP_GPT1S_TIMER_STATE_MASK                   (0x0000000F)
 127#define U300_TIMER_APP_GPT1S_TIMER_STATE_IDLE                   (0x00000001)
 128#define U300_TIMER_APP_GPT1S_TIMER_STATE_ACTIVE                 (0x00000002)
 129#define U300_TIMER_APP_GPT1S_ENABLE_IND                         (0x00000010)
 130#define U300_TIMER_APP_GPT1S_MODE_MASK                          (0x00000020)
 131#define U300_TIMER_APP_GPT1S_MODE_CONTINUOUS                    (0x00000000)
 132#define U300_TIMER_APP_GPT1S_MODE_ONE_SHOT                      (0x00000020)
 133#define U300_TIMER_APP_GPT1S_IRQ_ENABLED_IND                    (0x00000040)
 134#define U300_TIMER_APP_GPT1S_IRQ_PENDING_IND                    (0x00000080)
 135/* GP1 Timer Current Count Register 32bit (R/-) */
 136#define U300_TIMER_APP_GPT1CC                                   (0x0094)
 137/* GP1 Timer Terminal Count Register 32bit (R/W) */
 138#define U300_TIMER_APP_GPT1TC                                   (0x0098)
 139/* GP1 Timer Interrupt Enable Register 32bit (-/W) */
 140#define U300_TIMER_APP_GPT1IE                                   (0x009c)
 141#define U300_TIMER_APP_GPT1IE_IRQ_DISABLE                       (0x00000000)
 142#define U300_TIMER_APP_GPT1IE_IRQ_ENABLE                        (0x00000001)
 143/* GP1 Timer Interrupt Acknowledge Register 32bit (-/W) */
 144#define U300_TIMER_APP_GPT1IA                                   (0x00a0)
 145#define U300_TIMER_APP_GPT1IA_IRQ_ACK                           (0x00000080)
 146
 147/* Reset GP2 Timer 32bit (-/W) */
 148#define U300_TIMER_APP_RGPT2                                    (0x00c0)
 149#define U300_TIMER_APP_RGPT2_TIMER_RESET                        (0x00000000)
 150/* Enable GP2 Timer 32bit (-/W) */
 151#define U300_TIMER_APP_EGPT2                                    (0x00c4)
 152#define U300_TIMER_APP_EGPT2_TIMER_ENABLE                       (0x00000000)
 153/* Disable GP2 Timer 32bit (-/W) */
 154#define U300_TIMER_APP_DGPT2                                    (0x00c8)
 155#define U300_TIMER_APP_DGPT2_TIMER_DISABLE                      (0x00000000)
 156/* GP2 Timer Mode Register 32bit (-/W) */
 157#define U300_TIMER_APP_SGPT2M                                   (0x00cc)
 158#define U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS                   (0x00000000)
 159#define U300_TIMER_APP_SGPT2M_MODE_ONE_SHOT                     (0x00000001)
 160/* GP2 Timer Status Register 32bit (R/-) */
 161#define U300_TIMER_APP_GPT2S                                    (0x00d0)
 162#define U300_TIMER_APP_GPT2S_TIMER_STATE_MASK                   (0x0000000F)
 163#define U300_TIMER_APP_GPT2S_TIMER_STATE_IDLE                   (0x00000001)
 164#define U300_TIMER_APP_GPT2S_TIMER_STATE_ACTIVE                 (0x00000002)
 165#define U300_TIMER_APP_GPT2S_ENABLE_IND                         (0x00000010)
 166#define U300_TIMER_APP_GPT2S_MODE_MASK                          (0x00000020)
 167#define U300_TIMER_APP_GPT2S_MODE_CONTINUOUS                    (0x00000000)
 168#define U300_TIMER_APP_GPT2S_MODE_ONE_SHOT                      (0x00000020)
 169#define U300_TIMER_APP_GPT2S_IRQ_ENABLED_IND                    (0x00000040)
 170#define U300_TIMER_APP_GPT2S_IRQ_PENDING_IND                    (0x00000080)
 171/* GP2 Timer Current Count Register 32bit (R/-) */
 172#define U300_TIMER_APP_GPT2CC                                   (0x00d4)
 173/* GP2 Timer Terminal Count Register 32bit (R/W) */
 174#define U300_TIMER_APP_GPT2TC                                   (0x00d8)
 175/* GP2 Timer Interrupt Enable Register 32bit (-/W) */
 176#define U300_TIMER_APP_GPT2IE                                   (0x00dc)
 177#define U300_TIMER_APP_GPT2IE_IRQ_DISABLE                       (0x00000000)
 178#define U300_TIMER_APP_GPT2IE_IRQ_ENABLE                        (0x00000001)
 179/* GP2 Timer Interrupt Acknowledge Register 32bit (-/W) */
 180#define U300_TIMER_APP_GPT2IA                                   (0x00e0)
 181#define U300_TIMER_APP_GPT2IA_IRQ_ACK                           (0x00000080)
 182
 183/* Clock request control register - all four timers */
 184#define U300_TIMER_APP_CRC                                      (0x100)
 185#define U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE                 (0x00000001)
 186
 187#define TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
 188#define US_PER_TICK ((1000000 + (HZ/2)) / HZ)
 189
 190static void __iomem *u300_timer_base;
 191
 192/*
 193 * The u300_set_mode() function is always called first, if we
 194 * have oneshot timer active, the oneshot scheduling function
 195 * u300_set_next_event() is called immediately after.
 196 */
 197static void u300_set_mode(enum clock_event_mode mode,
 198                          struct clock_event_device *evt)
 199{
 200        switch (mode) {
 201        case CLOCK_EVT_MODE_PERIODIC:
 202                /* Disable interrupts on GPT1 */
 203                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 204                       u300_timer_base + U300_TIMER_APP_GPT1IE);
 205                /* Disable GP1 while we're reprogramming it. */
 206                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 207                       u300_timer_base + U300_TIMER_APP_DGPT1);
 208                /*
 209                 * Set the periodic mode to a certain number of ticks per
 210                 * jiffy.
 211                 */
 212                writel(TICKS_PER_JIFFY,
 213                       u300_timer_base + U300_TIMER_APP_GPT1TC);
 214                /*
 215                 * Set continuous mode, so the timer keeps triggering
 216                 * interrupts.
 217                 */
 218                writel(U300_TIMER_APP_SGPT1M_MODE_CONTINUOUS,
 219                       u300_timer_base + U300_TIMER_APP_SGPT1M);
 220                /* Enable timer interrupts */
 221                writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 222                       u300_timer_base + U300_TIMER_APP_GPT1IE);
 223                /* Then enable the OS timer again */
 224                writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 225                       u300_timer_base + U300_TIMER_APP_EGPT1);
 226                break;
 227        case CLOCK_EVT_MODE_ONESHOT:
 228                /* Just break; here? */
 229                /*
 230                 * The actual event will be programmed by the next event hook,
 231                 * so we just set a dummy value somewhere at the end of the
 232                 * universe here.
 233                 */
 234                /* Disable interrupts on GPT1 */
 235                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 236                       u300_timer_base + U300_TIMER_APP_GPT1IE);
 237                /* Disable GP1 while we're reprogramming it. */
 238                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 239                       u300_timer_base + U300_TIMER_APP_DGPT1);
 240                /*
 241                 * Expire far in the future, u300_set_next_event() will be
 242                 * called soon...
 243                 */
 244                writel(0xFFFFFFFF, u300_timer_base + U300_TIMER_APP_GPT1TC);
 245                /* We run one shot per tick here! */
 246                writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 247                       u300_timer_base + U300_TIMER_APP_SGPT1M);
 248                /* Enable interrupts for this timer */
 249                writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 250                       u300_timer_base + U300_TIMER_APP_GPT1IE);
 251                /* Enable timer */
 252                writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 253                       u300_timer_base + U300_TIMER_APP_EGPT1);
 254                break;
 255        case CLOCK_EVT_MODE_UNUSED:
 256        case CLOCK_EVT_MODE_SHUTDOWN:
 257                /* Disable interrupts on GP1 */
 258                writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 259                       u300_timer_base + U300_TIMER_APP_GPT1IE);
 260                /* Disable GP1 */
 261                writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 262                       u300_timer_base + U300_TIMER_APP_DGPT1);
 263                break;
 264        case CLOCK_EVT_MODE_RESUME:
 265                /* Ignore this call */
 266                break;
 267        }
 268}
 269
 270/*
 271 * The app timer in one shot mode obviously has to be reprogrammed
 272 * in EXACTLY this sequence to work properly. Do NOT try to e.g. replace
 273 * the interrupt disable + timer disable commands with a reset command,
 274 * it will fail miserably. Apparently (and I found this the hard way)
 275 * the timer is very sensitive to the instruction order, though you don't
 276 * get that impression from the data sheet.
 277 */
 278static int u300_set_next_event(unsigned long cycles,
 279                               struct clock_event_device *evt)
 280
 281{
 282        /* Disable interrupts on GPT1 */
 283        writel(U300_TIMER_APP_GPT1IE_IRQ_DISABLE,
 284               u300_timer_base + U300_TIMER_APP_GPT1IE);
 285        /* Disable GP1 while we're reprogramming it. */
 286        writel(U300_TIMER_APP_DGPT1_TIMER_DISABLE,
 287               u300_timer_base + U300_TIMER_APP_DGPT1);
 288        /* Reset the General Purpose timer 1. */
 289        writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 290               u300_timer_base + U300_TIMER_APP_RGPT1);
 291        /* IRQ in n * cycles */
 292        writel(cycles, u300_timer_base + U300_TIMER_APP_GPT1TC);
 293        /*
 294         * We run one shot per tick here! (This is necessary to reconfigure,
 295         * the timer will tilt if you don't!)
 296         */
 297        writel(U300_TIMER_APP_SGPT1M_MODE_ONE_SHOT,
 298               u300_timer_base + U300_TIMER_APP_SGPT1M);
 299        /* Enable timer interrupts */
 300        writel(U300_TIMER_APP_GPT1IE_IRQ_ENABLE,
 301               u300_timer_base + U300_TIMER_APP_GPT1IE);
 302        /* Then enable the OS timer again */
 303        writel(U300_TIMER_APP_EGPT1_TIMER_ENABLE,
 304               u300_timer_base + U300_TIMER_APP_EGPT1);
 305        return 0;
 306}
 307
 308
 309/* Use general purpose timer 1 as clock event */
 310static struct clock_event_device clockevent_u300_1mhz = {
 311        .name           = "GPT1",
 312        .rating         = 300, /* Reasonably fast and accurate clock event */
 313        .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 314        .set_next_event = u300_set_next_event,
 315        .set_mode       = u300_set_mode,
 316};
 317
 318/* Clock event timer interrupt handler */
 319static irqreturn_t u300_timer_interrupt(int irq, void *dev_id)
 320{
 321        struct clock_event_device *evt = &clockevent_u300_1mhz;
 322        /* ACK/Clear timer IRQ for the APP GPT1 Timer */
 323
 324        writel(U300_TIMER_APP_GPT1IA_IRQ_ACK,
 325                u300_timer_base + U300_TIMER_APP_GPT1IA);
 326        evt->event_handler(evt);
 327        return IRQ_HANDLED;
 328}
 329
 330static struct irqaction u300_timer_irq = {
 331        .name           = "U300 Timer Tick",
 332        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 333        .handler        = u300_timer_interrupt,
 334};
 335
 336/*
 337 * Override the global weak sched_clock symbol with this
 338 * local implementation which uses the clocksource to get some
 339 * better resolution when scheduling the kernel. We accept that
 340 * this wraps around for now, since it is just a relative time
 341 * stamp. (Inspired by OMAP implementation.)
 342 */
 343
 344static u32 notrace u300_read_sched_clock(void)
 345{
 346        return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 347}
 348
 349static unsigned long u300_read_current_timer(void)
 350{
 351        return readl(u300_timer_base + U300_TIMER_APP_GPT2CC);
 352}
 353
 354static struct delay_timer u300_delay_timer;
 355
 356/*
 357 * This sets up the system timers, clock source and clock event.
 358 */
 359static void __init u300_timer_init_of(struct device_node *np)
 360{
 361        struct resource irq_res;
 362        int irq;
 363        struct clk *clk;
 364        unsigned long rate;
 365
 366        u300_timer_base = of_iomap(np, 0);
 367        if (!u300_timer_base)
 368                panic("could not ioremap system timer\n");
 369
 370        /* Get the IRQ for the GP1 timer */
 371        irq = of_irq_to_resource(np, 2, &irq_res);
 372        if (irq <= 0)
 373                panic("no IRQ for system timer\n");
 374
 375        pr_info("U300 GP1 timer @ base: %p, IRQ: %d\n", u300_timer_base, irq);
 376
 377        /* Clock the interrupt controller */
 378        clk = of_clk_get(np, 0);
 379        BUG_ON(IS_ERR(clk));
 380        clk_prepare_enable(clk);
 381        rate = clk_get_rate(clk);
 382
 383        setup_sched_clock(u300_read_sched_clock, 32, rate);
 384
 385        u300_delay_timer.read_current_timer = &u300_read_current_timer;
 386        u300_delay_timer.freq = rate;
 387        register_current_timer_delay(&u300_delay_timer);
 388
 389        /*
 390         * Disable the "OS" and "DD" timers - these are designed for Symbian!
 391         * Example usage in cnh1601578 cpu subsystem pd_timer_app.c
 392         */
 393        writel(U300_TIMER_APP_CRC_CLOCK_REQUEST_ENABLE,
 394                u300_timer_base + U300_TIMER_APP_CRC);
 395        writel(U300_TIMER_APP_ROST_TIMER_RESET,
 396                u300_timer_base + U300_TIMER_APP_ROST);
 397        writel(U300_TIMER_APP_DOST_TIMER_DISABLE,
 398                u300_timer_base + U300_TIMER_APP_DOST);
 399        writel(U300_TIMER_APP_RDDT_TIMER_RESET,
 400                u300_timer_base + U300_TIMER_APP_RDDT);
 401        writel(U300_TIMER_APP_DDDT_TIMER_DISABLE,
 402                u300_timer_base + U300_TIMER_APP_DDDT);
 403
 404        /* Reset the General Purpose timer 1. */
 405        writel(U300_TIMER_APP_RGPT1_TIMER_RESET,
 406                u300_timer_base + U300_TIMER_APP_RGPT1);
 407
 408        /* Set up the IRQ handler */
 409        setup_irq(irq, &u300_timer_irq);
 410
 411        /* Reset the General Purpose timer 2 */
 412        writel(U300_TIMER_APP_RGPT2_TIMER_RESET,
 413                u300_timer_base + U300_TIMER_APP_RGPT2);
 414        /* Set this timer to run around forever */
 415        writel(0xFFFFFFFFU, u300_timer_base + U300_TIMER_APP_GPT2TC);
 416        /* Set continuous mode so it wraps around */
 417        writel(U300_TIMER_APP_SGPT2M_MODE_CONTINUOUS,
 418               u300_timer_base + U300_TIMER_APP_SGPT2M);
 419        /* Disable timer interrupts */
 420        writel(U300_TIMER_APP_GPT2IE_IRQ_DISABLE,
 421                u300_timer_base + U300_TIMER_APP_GPT2IE);
 422        /* Then enable the GP2 timer to use as a free running us counter */
 423        writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
 424                u300_timer_base + U300_TIMER_APP_EGPT2);
 425
 426        /* Use general purpose timer 2 as clock source */
 427        if (clocksource_mmio_init(u300_timer_base + U300_TIMER_APP_GPT2CC,
 428                        "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
 429                pr_err("timer: failed to initialize U300 clock source\n");
 430
 431        /* Configure and register the clockevent */
 432        clockevents_config_and_register(&clockevent_u300_1mhz, rate,
 433                                        1, 0xffffffff);
 434
 435        /*
 436         * TODO: init and register the rest of the timers too, they can be
 437         * used by hrtimers!
 438         */
 439}
 440
 441CLOCKSOURCE_OF_DECLARE(u300_timer, "stericsson,u300-apptimer",
 442                       u300_timer_init_of);
 443