linux/arch/blackfin/include/asm/bfin_spi3.h
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   1/*
   2 * Analog Devices SPI3 controller driver
   3 *
   4 * Copyright (c) 2011 Analog Devices Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 *
  10 * This program is distributed in the hope that it will be useful,
  11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13 * GNU General Public License for more details.
  14 *
  15 * You should have received a copy of the GNU General Public License
  16 * along with this program; if not, write to the Free Software
  17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18 */
  19
  20#ifndef _SPI_CHANNEL_H_
  21#define _SPI_CHANNEL_H_
  22
  23#include <linux/types.h>
  24
  25/* SPI_CONTROL */
  26#define SPI_CTL_EN                  0x00000001    /* Enable */
  27#define SPI_CTL_MSTR                0x00000002    /* Master/Slave */
  28#define SPI_CTL_PSSE                0x00000004    /* controls modf error in master mode */
  29#define SPI_CTL_ODM                 0x00000008    /* Open Drain Mode */
  30#define SPI_CTL_CPHA                0x00000010    /* Clock Phase */
  31#define SPI_CTL_CPOL                0x00000020    /* Clock Polarity */
  32#define SPI_CTL_ASSEL               0x00000040    /* Slave Select Pin Control */
  33#define SPI_CTL_SELST               0x00000080    /* Slave Select Polarity in-between transfers */
  34#define SPI_CTL_EMISO               0x00000100    /* Enable MISO */
  35#define SPI_CTL_SIZE                0x00000600    /* Word Transfer Size */
  36#define SPI_CTL_SIZE08              0x00000000    /* SIZE: 8 bits */
  37#define SPI_CTL_SIZE16              0x00000200    /* SIZE: 16 bits */
  38#define SPI_CTL_SIZE32              0x00000400    /* SIZE: 32 bits */
  39#define SPI_CTL_LSBF                0x00001000    /* LSB First */
  40#define SPI_CTL_FCEN                0x00002000    /* Flow-Control Enable */
  41#define SPI_CTL_FCCH                0x00004000    /* Flow-Control Channel Selection */
  42#define SPI_CTL_FCPL                0x00008000    /* Flow-Control Polarity */
  43#define SPI_CTL_FCWM                0x00030000    /* Flow-Control Water-Mark */
  44#define SPI_CTL_FIFO0               0x00000000    /* FCWM: TFIFO empty or RFIFO Full */
  45#define SPI_CTL_FIFO1               0x00010000    /* FCWM: TFIFO 75% or more empty or RFIFO 75% or more full */
  46#define SPI_CTL_FIFO2               0x00020000    /* FCWM: TFIFO 50% or more empty or RFIFO 50% or more full */
  47#define SPI_CTL_FMODE               0x00040000    /* Fast-mode Enable */
  48#define SPI_CTL_MIOM                0x00300000    /* Multiple I/O Mode */
  49#define SPI_CTL_MIO_DIS             0x00000000    /* MIOM: Disable */
  50#define SPI_CTL_MIO_DUAL            0x00100000    /* MIOM: Enable DIOM (Dual I/O Mode) */
  51#define SPI_CTL_MIO_QUAD            0x00200000    /* MIOM: Enable QUAD (Quad SPI Mode) */
  52#define SPI_CTL_SOSI                0x00400000    /* Start on MOSI */
  53/* SPI_RX_CONTROL */
  54#define SPI_RXCTL_REN               0x00000001    /* Receive Channel Enable */
  55#define SPI_RXCTL_RTI               0x00000004    /* Receive Transfer Initiate */
  56#define SPI_RXCTL_RWCEN             0x00000008    /* Receive Word Counter Enable */
  57#define SPI_RXCTL_RDR               0x00000070    /* Receive Data Request */
  58#define SPI_RXCTL_RDR_DIS           0x00000000    /* RDR: Disabled */
  59#define SPI_RXCTL_RDR_NE            0x00000010    /* RDR: RFIFO not empty */
  60#define SPI_RXCTL_RDR_25            0x00000020    /* RDR: RFIFO 25% full */
  61#define SPI_RXCTL_RDR_50            0x00000030    /* RDR: RFIFO 50% full */
  62#define SPI_RXCTL_RDR_75            0x00000040    /* RDR: RFIFO 75% full */
  63#define SPI_RXCTL_RDR_FULL          0x00000050    /* RDR: RFIFO full */
  64#define SPI_RXCTL_RDO               0x00000100    /* Receive Data Over-Run */
  65#define SPI_RXCTL_RRWM              0x00003000    /* FIFO Regular Water-Mark */
  66#define SPI_RXCTL_RWM_0             0x00000000    /* RRWM: RFIFO Empty */
  67#define SPI_RXCTL_RWM_25            0x00001000    /* RRWM: RFIFO 25% full */
  68#define SPI_RXCTL_RWM_50            0x00002000    /* RRWM: RFIFO 50% full */
  69#define SPI_RXCTL_RWM_75            0x00003000    /* RRWM: RFIFO 75% full */
  70#define SPI_RXCTL_RUWM              0x00070000    /* FIFO Urgent Water-Mark */
  71#define SPI_RXCTL_UWM_DIS           0x00000000    /* RUWM: Disabled */
  72#define SPI_RXCTL_UWM_25            0x00010000    /* RUWM: RFIFO 25% full */
  73#define SPI_RXCTL_UWM_50            0x00020000    /* RUWM: RFIFO 50% full */
  74#define SPI_RXCTL_UWM_75            0x00030000    /* RUWM: RFIFO 75% full */
  75#define SPI_RXCTL_UWM_FULL          0x00040000    /* RUWM: RFIFO full */
  76/* SPI_TX_CONTROL */
  77#define SPI_TXCTL_TEN               0x00000001    /* Transmit Channel Enable */
  78#define SPI_TXCTL_TTI               0x00000004    /* Transmit Transfer Initiate */
  79#define SPI_TXCTL_TWCEN             0x00000008    /* Transmit Word Counter Enable */
  80#define SPI_TXCTL_TDR               0x00000070    /* Transmit Data Request */
  81#define SPI_TXCTL_TDR_DIS           0x00000000    /* TDR: Disabled */
  82#define SPI_TXCTL_TDR_NF            0x00000010    /* TDR: TFIFO not full */
  83#define SPI_TXCTL_TDR_25            0x00000020    /* TDR: TFIFO 25% empty */
  84#define SPI_TXCTL_TDR_50            0x00000030    /* TDR: TFIFO 50% empty */
  85#define SPI_TXCTL_TDR_75            0x00000040    /* TDR: TFIFO 75% empty */
  86#define SPI_TXCTL_TDR_EMPTY         0x00000050    /* TDR: TFIFO empty */
  87#define SPI_TXCTL_TDU               0x00000100    /* Transmit Data Under-Run */
  88#define SPI_TXCTL_TRWM              0x00003000    /* FIFO Regular Water-Mark */
  89#define SPI_TXCTL_RWM_FULL          0x00000000    /* TRWM: TFIFO full */
  90#define SPI_TXCTL_RWM_25            0x00001000    /* TRWM: TFIFO 25% empty */
  91#define SPI_TXCTL_RWM_50            0x00002000    /* TRWM: TFIFO 50% empty */
  92#define SPI_TXCTL_RWM_75            0x00003000    /* TRWM: TFIFO 75% empty */
  93#define SPI_TXCTL_TUWM              0x00070000    /* FIFO Urgent Water-Mark */
  94#define SPI_TXCTL_UWM_DIS           0x00000000    /* TUWM: Disabled */
  95#define SPI_TXCTL_UWM_25            0x00010000    /* TUWM: TFIFO 25% empty */
  96#define SPI_TXCTL_UWM_50            0x00020000    /* TUWM: TFIFO 50% empty */
  97#define SPI_TXCTL_UWM_75            0x00030000    /* TUWM: TFIFO 75% empty */
  98#define SPI_TXCTL_UWM_EMPTY         0x00040000    /* TUWM: TFIFO empty */
  99/* SPI_CLOCK */
 100#define SPI_CLK_BAUD                0x0000FFFF    /* Baud Rate */
 101/* SPI_DELAY */
 102#define SPI_DLY_STOP                0x000000FF    /* Transfer delay time in multiples of SCK period */
 103#define SPI_DLY_LEADX               0x00000100    /* Extended (1 SCK) LEAD Control */
 104#define SPI_DLY_LAGX                0x00000200    /* Extended (1 SCK) LAG control */
 105/* SPI_SSEL */
 106#define SPI_SLVSEL_SSE1             0x00000002    /* SPISSEL1 Enable */
 107#define SPI_SLVSEL_SSE2             0x00000004    /* SPISSEL2 Enable */
 108#define SPI_SLVSEL_SSE3             0x00000008    /* SPISSEL3 Enable */
 109#define SPI_SLVSEL_SSE4             0x00000010    /* SPISSEL4 Enable */
 110#define SPI_SLVSEL_SSE5             0x00000020    /* SPISSEL5 Enable */
 111#define SPI_SLVSEL_SSE6             0x00000040    /* SPISSEL6 Enable */
 112#define SPI_SLVSEL_SSE7             0x00000080    /* SPISSEL7 Enable */
 113#define SPI_SLVSEL_SSEL1            0x00000200    /* SPISSEL1 Value */
 114#define SPI_SLVSEL_SSEL2            0x00000400    /* SPISSEL2 Value */
 115#define SPI_SLVSEL_SSEL3            0x00000800    /* SPISSEL3 Value */
 116#define SPI_SLVSEL_SSEL4            0x00001000    /* SPISSEL4 Value */
 117#define SPI_SLVSEL_SSEL5            0x00002000    /* SPISSEL5 Value */
 118#define SPI_SLVSEL_SSEL6            0x00004000    /* SPISSEL6 Value */
 119#define SPI_SLVSEL_SSEL7            0x00008000    /* SPISSEL7 Value */
 120/* SPI_RWC */
 121#define SPI_RWC_VALUE               0x0000FFFF    /* Received Word-Count */
 122/* SPI_RWCR */
 123#define SPI_RWCR_VALUE              0x0000FFFF    /* Received Word-Count Reload */
 124/* SPI_TWC */
 125#define SPI_TWC_VALUE               0x0000FFFF    /* Transmitted Word-Count */
 126/* SPI_TWCR */
 127#define SPI_TWCR_VALUE              0x0000FFFF    /* Transmitted Word-Count Reload */
 128/* SPI_IMASK */
 129#define SPI_IMSK_RUWM               0x00000002    /* Receive Urgent Water-Mark Interrupt Mask */
 130#define SPI_IMSK_TUWM               0x00000004    /* Transmit Urgent Water-Mark Interrupt Mask */
 131#define SPI_IMSK_ROM                0x00000010    /* Receive Over-Run Error Interrupt Mask */
 132#define SPI_IMSK_TUM                0x00000020    /* Transmit Under-Run Error Interrupt Mask */
 133#define SPI_IMSK_TCM                0x00000040    /* Transmit Collision Error Interrupt Mask */
 134#define SPI_IMSK_MFM                0x00000080    /* Mode Fault Error Interrupt Mask */
 135#define SPI_IMSK_RSM                0x00000100    /* Receive Start Interrupt Mask */
 136#define SPI_IMSK_TSM                0x00000200    /* Transmit Start Interrupt Mask */
 137#define SPI_IMSK_RFM                0x00000400    /* Receive Finish Interrupt Mask */
 138#define SPI_IMSK_TFM                0x00000800    /* Transmit Finish Interrupt Mask */
 139/* SPI_IMASKCL */
 140#define SPI_IMSK_CLR_RUW            0x00000002    /* Receive Urgent Water-Mark Interrupt Mask */
 141#define SPI_IMSK_CLR_TUWM           0x00000004    /* Transmit Urgent Water-Mark Interrupt Mask */
 142#define SPI_IMSK_CLR_ROM            0x00000010    /* Receive Over-Run Error Interrupt Mask */
 143#define SPI_IMSK_CLR_TUM            0x00000020    /* Transmit Under-Run Error Interrupt Mask */
 144#define SPI_IMSK_CLR_TCM            0x00000040    /* Transmit Collision Error Interrupt Mask */
 145#define SPI_IMSK_CLR_MFM            0x00000080    /* Mode Fault Error Interrupt Mask */
 146#define SPI_IMSK_CLR_RSM            0x00000100    /* Receive Start Interrupt Mask */
 147#define SPI_IMSK_CLR_TSM            0x00000200    /* Transmit Start Interrupt Mask */
 148#define SPI_IMSK_CLR_RFM            0x00000400    /* Receive Finish Interrupt Mask */
 149#define SPI_IMSK_CLR_TFM            0x00000800    /* Transmit Finish Interrupt Mask */
 150/* SPI_IMASKST */
 151#define SPI_IMSK_SET_RUWM           0x00000002    /* Receive Urgent Water-Mark Interrupt Mask */
 152#define SPI_IMSK_SET_TUWM           0x00000004    /* Transmit Urgent Water-Mark Interrupt Mask */
 153#define SPI_IMSK_SET_ROM            0x00000010    /* Receive Over-Run Error Interrupt Mask */
 154#define SPI_IMSK_SET_TUM            0x00000020    /* Transmit Under-Run Error Interrupt Mask */
 155#define SPI_IMSK_SET_TCM            0x00000040    /* Transmit Collision Error Interrupt Mask */
 156#define SPI_IMSK_SET_MFM            0x00000080    /* Mode Fault Error Interrupt Mask */
 157#define SPI_IMSK_SET_RSM            0x00000100    /* Receive Start Interrupt Mask */
 158#define SPI_IMSK_SET_TSM            0x00000200    /* Transmit Start Interrupt Mask */
 159#define SPI_IMSK_SET_RFM            0x00000400    /* Receive Finish Interrupt Mask */
 160#define SPI_IMSK_SET_TFM            0x00000800    /* Transmit Finish Interrupt Mask */
 161/* SPI_STATUS */
 162#define SPI_STAT_SPIF               0x00000001    /* SPI Finished */
 163#define SPI_STAT_RUWM               0x00000002    /* Receive Urgent Water-Mark Breached */
 164#define SPI_STAT_TUWM               0x00000004    /* Transmit Urgent Water-Mark Breached */
 165#define SPI_STAT_ROE                0x00000010    /* Receive Over-Run Error Indication */
 166#define SPI_STAT_TUE                0x00000020    /* Transmit Under-Run Error Indication */
 167#define SPI_STAT_TCE                0x00000040    /* Transmit Collision Error Indication */
 168#define SPI_STAT_MODF               0x00000080    /* Mode Fault Error Indication */
 169#define SPI_STAT_RS                 0x00000100    /* Receive Start Indication */
 170#define SPI_STAT_TS                 0x00000200    /* Transmit Start Indication */
 171#define SPI_STAT_RF                 0x00000400    /* Receive Finish Indication */
 172#define SPI_STAT_TF                 0x00000800    /* Transmit Finish Indication */
 173#define SPI_STAT_RFS                0x00007000    /* SPI_RFIFO status */
 174#define SPI_STAT_RFIFO_EMPTY        0x00000000    /* RFS: RFIFO Empty */
 175#define SPI_STAT_RFIFO_25           0x00001000    /* RFS: RFIFO 25% Full */
 176#define SPI_STAT_RFIFO_50           0x00002000    /* RFS: RFIFO 50% Full */
 177#define SPI_STAT_RFIFO_75           0x00003000    /* RFS: RFIFO 75% Full */
 178#define SPI_STAT_RFIFO_FULL         0x00004000    /* RFS: RFIFO Full */
 179#define SPI_STAT_TFS                0x00070000    /* SPI_TFIFO status */
 180#define SPI_STAT_TFIFO_FULL         0x00000000    /* TFS: TFIFO full */
 181#define SPI_STAT_TFIFO_25           0x00010000    /* TFS: TFIFO 25% empty */
 182#define SPI_STAT_TFIFO_50           0x00020000    /* TFS: TFIFO 50% empty */
 183#define SPI_STAT_TFIFO_75           0x00030000    /* TFS: TFIFO 75% empty */
 184#define SPI_STAT_TFIFO_EMPTY        0x00040000    /* TFS: TFIFO empty */
 185#define SPI_STAT_FCS                0x00100000    /* Flow-Control Stall Indication */
 186#define SPI_STAT_RFE                0x00400000    /* SPI_RFIFO Empty */
 187#define SPI_STAT_TFF                0x00800000    /* SPI_TFIFO Full */
 188/* SPI_ILAT */
 189#define SPI_ILAT_RUWMI              0x00000002    /* Receive Urgent Water Mark Interrupt */
 190#define SPI_ILAT_TUWMI              0x00000004    /* Transmit Urgent Water Mark Interrupt */
 191#define SPI_ILAT_ROI                0x00000010    /* Receive Over-Run Error Indication */
 192#define SPI_ILAT_TUI                0x00000020    /* Transmit Under-Run Error Indication */
 193#define SPI_ILAT_TCI                0x00000040    /* Transmit Collision Error Indication */
 194#define SPI_ILAT_MFI                0x00000080    /* Mode Fault Error Indication */
 195#define SPI_ILAT_RSI                0x00000100    /* Receive Start Indication */
 196#define SPI_ILAT_TSI                0x00000200    /* Transmit Start Indication */
 197#define SPI_ILAT_RFI                0x00000400    /* Receive Finish Indication */
 198#define SPI_ILAT_TFI                0x00000800    /* Transmit Finish Indication */
 199/* SPI_ILATCL */
 200#define SPI_ILAT_CLR_RUWMI          0x00000002    /* Receive Urgent Water Mark Interrupt */
 201#define SPI_ILAT_CLR_TUWMI          0x00000004    /* Transmit Urgent Water Mark Interrupt */
 202#define SPI_ILAT_CLR_ROI            0x00000010    /* Receive Over-Run Error Indication */
 203#define SPI_ILAT_CLR_TUI            0x00000020    /* Transmit Under-Run Error Indication */
 204#define SPI_ILAT_CLR_TCI            0x00000040    /* Transmit Collision Error Indication */
 205#define SPI_ILAT_CLR_MFI            0x00000080    /* Mode Fault Error Indication */
 206#define SPI_ILAT_CLR_RSI            0x00000100    /* Receive Start Indication */
 207#define SPI_ILAT_CLR_TSI            0x00000200    /* Transmit Start Indication */
 208#define SPI_ILAT_CLR_RFI            0x00000400    /* Receive Finish Indication */
 209#define SPI_ILAT_CLR_TFI            0x00000800    /* Transmit Finish Indication */
 210
 211/*
 212 * bfin spi3 registers layout
 213 */
 214struct bfin_spi_regs {
 215        u32 revid;
 216        u32 control;
 217        u32 rx_control;
 218        u32 tx_control;
 219        u32 clock;
 220        u32 delay;
 221        u32 ssel;
 222        u32 rwc;
 223        u32 rwcr;
 224        u32 twc;
 225        u32 twcr;
 226        u32 reserved0;
 227        u32 emask;
 228        u32 emaskcl;
 229        u32 emaskst;
 230        u32 reserved1;
 231        u32 status;
 232        u32 elat;
 233        u32 elatcl;
 234        u32 reserved2;
 235        u32 rfifo;
 236        u32 reserved3;
 237        u32 tfifo;
 238};
 239
 240#define MAX_CTRL_CS          8  /* cs in spi controller */
 241
 242/* device.platform_data for SSP controller devices */
 243struct bfin_spi3_master {
 244        u16 num_chipselect;
 245        u16 pin_req[7];
 246};
 247
 248/* spi_board_info.controller_data for SPI slave devices,
 249 * copied to spi_device.platform_data ... mostly for dma tuning
 250 */
 251struct bfin_spi3_chip {
 252        u32 control;
 253        u16 cs_chg_udelay; /* Some devices require 16-bit delays */
 254        u32 tx_dummy_val; /* tx value for rx only transfer */
 255        bool enable_dma;
 256};
 257
 258#endif /* _SPI_CHANNEL_H_ */
 259
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.