LXR linux/arch/blackfin/include/asm/bfin

   1/*
   2 * bfin_twi.h - interface to Blackfin TWIs
   3 *
   4 * Copyright 2005-2010 Analog Devices Inc.
   5 *
   6 * Licensed under the GPL-2 or later.
   7 */
   8
   9#ifndef __ASM_BFIN_TWI_H__
  10#define __ASM_BFIN_TWI_H__
  11
  12#include <linux/types.h>
  13#include <linux/i2c.h>
  14
  15/*
  16 * All Blackfin system MMRs are padded to 32bits even if the register
  17 * itself is only 16bits.  So use a helper macro to streamline this.
  18 */
  19#define __BFP(m) u16 m; u16 __pad_##m
  20
  21/*
  22 * bfin twi registers layout
  23 */
  24struct bfin_twi_regs {
  25        __BFP(clkdiv);
  26        __BFP(control);
  27        __BFP(slave_ctl);
  28        __BFP(slave_stat);
  29        __BFP(slave_addr);
  30        __BFP(master_ctl);
  31        __BFP(master_stat);
  32        __BFP(master_addr);
  33        __BFP(int_stat);
  34        __BFP(int_mask);
  35        __BFP(fifo_ctl);
  36        __BFP(fifo_stat);
  37        u32 __pad[20];
  38        __BFP(xmt_data8);
  39        __BFP(xmt_data16);
  40        __BFP(rcv_data8);
  41        __BFP(rcv_data16);
  42};
  43
  44#undef __BFP
  45
  46struct bfin_twi_iface {
  47        int                     irq;
  48        spinlock_t              lock;
  49        char                    read_write;
  50        u8                      command;
  51        u8                      *transPtr;
  52        int                     readNum;
  53        int                     writeNum;
  54        int                     cur_mode;
  55        int                     manual_stop;
  56        int                     result;
  57        struct i2c_adapter      adap;
  58        struct completion       complete;
  59        struct i2c_msg          *pmsg;
  60        int                     msg_num;
  61        int                     cur_msg;
  62        u16                     saved_clkdiv;
  63        u16                     saved_control;
  64        struct bfin_twi_regs __iomem *regs_base;
  65};
  66
  67#define DEFINE_TWI_REG(reg_name, reg) \
  68static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
  69        { return bfin_read16(&iface->regs_base->reg); } \
  70static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
  71        { bfin_write16(&iface->regs_base->reg, v); }
  72
  73DEFINE_TWI_REG(CLKDIV, clkdiv)
  74DEFINE_TWI_REG(CONTROL, control)
  75DEFINE_TWI_REG(SLAVE_CTL, slave_ctl)
  76DEFINE_TWI_REG(SLAVE_STAT, slave_stat)
  77DEFINE_TWI_REG(SLAVE_ADDR, slave_addr)
  78DEFINE_TWI_REG(MASTER_CTL, master_ctl)
  79DEFINE_TWI_REG(MASTER_STAT, master_stat)
  80DEFINE_TWI_REG(MASTER_ADDR, master_addr)
  81DEFINE_TWI_REG(INT_STAT, int_stat)
  82DEFINE_TWI_REG(INT_MASK, int_mask)
  83DEFINE_TWI_REG(FIFO_CTL, fifo_ctl)
  84DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
  85DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
  86DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
  87#if !ANOMALY_16000030
  88DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
  89DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
  90#else
  91static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
  92{
  93        u16 ret;
  94        unsigned long flags;
  95
  96        flags = hard_local_irq_save();
  97        ret = bfin_read16(&iface->regs_base->rcv_data8);
  98        hard_local_irq_restore(flags);
  99
 100        return ret;
 101}
 102
 103static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
 104{
 105        u16 ret;
 106        unsigned long flags;
 107
 108        flags = hard_local_irq_save();
 109        ret = bfin_read16(&iface->regs_base->rcv_data16);
 110        hard_local_irq_restore(flags);
 111
 112        return ret;
 113}
 114#endif
 115
 116
 117/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
 118/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
 119#define CLKLOW(x)       ((x) & 0xFF)    /* Periods Clock Is Held Low                    */
 120#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
 121
 122/* TWI_PRESCALE Masks                                                                                                                   */
 123#define PRESCALE        0x007F  /* SCLKs Per Internal Time Reference (10MHz)    */
 124#define TWI_ENA         0x0080  /* TWI Enable                                                                   */
 125#define SCCB            0x0200  /* SCCB Compatibility Enable                                    */
 126
 127/* TWI_SLAVE_CTL Masks                                                                                                                  */
 128#define SEN                     0x0001  /* Slave Enable                                                                 */
 129#define SADD_LEN        0x0002  /* Slave Address Length                                                 */
 130#define STDVAL          0x0004  /* Slave Transmit Data Valid                                    */
 131#define NAK                     0x0008  /* NAK/ACK* Generated At Conclusion Of Transfer */
 132#define GEN                     0x0010  /* General Call Address Matching Enabled                */
 133
 134/* TWI_SLAVE_STAT Masks                                                                                                                 */
 135#define SDIR            0x0001  /* Slave Transfer Direction (Transmit/Receive*) */
 136#define GCALL           0x0002  /* General Call Indicator                                               */
 137
 138/* TWI_MASTER_CTL Masks                                                                                                 */
 139#define MEN                     0x0001  /* Master Mode Enable                                           */
 140#define MADD_LEN        0x0002  /* Master Address Length                                        */
 141#define MDIR            0x0004  /* Master Transmit Direction (RX/TX*)           */
 142#define FAST            0x0008  /* Use Fast Mode Timing Specs                           */
 143#define STOP            0x0010  /* Issue Stop Condition                                         */
 144#define RSTART          0x0020  /* Repeat Start or Stop* At End Of Transfer     */
 145#define DCNT            0x3FC0  /* Data Bytes To Transfer                                       */
 146#define SDAOVR          0x4000  /* Serial Data Override                                         */
 147#define SCLOVR          0x8000  /* Serial Clock Override                                        */
 148
 149/* TWI_MASTER_STAT Masks                                                                                                                */
 150#define MPROG           0x0001  /* Master Transfer In Progress                                  */
 151#define LOSTARB         0x0002  /* Lost Arbitration Indicator (Xfer Aborted)    */
 152#define ANAK            0x0004  /* Address Not Acknowledged                                             */
 153#define DNAK            0x0008  /* Data Not Acknowledged                                                */
 154#define BUFRDERR        0x0010  /* Buffer Read Error                                                    */
 155#define BUFWRERR        0x0020  /* Buffer Write Error                                                   */
 156#define SDASEN          0x0040  /* Serial Data Sense                                                    */
 157#define SCLSEN          0x0080  /* Serial Clock Sense                                                   */
 158#define BUSBUSY         0x0100  /* Bus Busy Indicator                                                   */
 159
 160/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
 161#define SINIT           0x0001  /* Slave Transfer Initiated     */
 162#define SCOMP           0x0002  /* Slave Transfer Complete      */
 163#define SERR            0x0004  /* Slave Transfer Error         */
 164#define SOVF            0x0008  /* Slave Overflow                       */
 165#define MCOMP           0x0010  /* Master Transfer Complete     */
 166#define MERR            0x0020  /* Master Transfer Error        */
 167#define XMTSERV         0x0040  /* Transmit FIFO Service        */
 168#define RCVSERV         0x0080  /* Receive FIFO Service         */
 169
 170/* TWI_FIFO_CTRL Masks                                                                                          */
 171#define XMTFLUSH        0x0001  /* Transmit Buffer Flush                        */
 172#define RCVFLUSH        0x0002  /* Receive Buffer Flush                         */
 173#define XMTINTLEN       0x0004  /* Transmit Buffer Interrupt Length     */
 174#define RCVINTLEN       0x0008  /* Receive Buffer Interrupt Length      */
 175
 176/* TWI_FIFO_STAT Masks                                                                                                                  */
 177#define XMTSTAT         0x0003  /* Transmit FIFO Status                                                 */
 178#define XMT_EMPTY       0x0000  /*              Transmit FIFO Empty                                             */
 179#define XMT_HALF        0x0001  /*              Transmit FIFO Has 1 Byte To Write               */
 180#define XMT_FULL        0x0003  /*              Transmit FIFO Full (2 Bytes To Write)   */
 181
 182#define RCVSTAT         0x000C  /* Receive FIFO Status                                                  */
 183#define RCV_EMPTY       0x0000  /*              Receive FIFO Empty                                              */
 184#define RCV_HALF        0x0004  /*              Receive FIFO Has 1 Byte To Read                 */
 185#define RCV_FULL        0x000C  /*              Receive FIFO Full (2 Bytes To Read)             */
 186
 187#endif
 188