1/* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2004 Cavium Networks 7 */ 8#ifndef __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H 9#define __ASM_MACH_CAVIUM_OCTEON_CPU_FEATURE_OVERRIDES_H 10 11#include <linux/types.h> 12#include <asm/mipsregs.h> 13 14/* 15 * Cavium Octeons are MIPS64v2 processors 16 */ 17#define cpu_dcache_line_size() 128 18#define cpu_icache_line_size() 128 19 20 21#define cpu_has_4kex 1 22#define cpu_has_3k_cache 0 23#define cpu_has_4k_cache 0 24#define cpu_has_tx39_cache 0 25#define cpu_has_fpu 0 26#define cpu_has_counter 1 27#define cpu_has_watch 1 28#define cpu_has_divec 1 29#define cpu_has_vce 0 30#define cpu_has_cache_cdex_p 0 31#define cpu_has_cache_cdex_s 0 32#define cpu_has_prefetch 1 33 34#define cpu_has_llsc 1 35/* 36 * We Disable LL/SC on non SMP systems as it is faster to disable 37 * interrupts for atomic access than a LL/SC. 38 */ 39#ifdef CONFIG_SMP 40# define kernel_uses_llsc 1 41#else 42# define kernel_uses_llsc 0 43#endif 44#define cpu_has_vtag_icache 1 45#define cpu_has_dc_aliases 0 46#define cpu_has_ic_fills_f_dc 0 47#define cpu_has_64bits 1 48#define cpu_has_octeon_cache 1 49#define cpu_has_saa octeon_has_saa() 50#define cpu_has_mips32r1 0 51#define cpu_has_mips32r2 0 52#define cpu_has_mips64r1 0 53#define cpu_has_mips64r2 1 54#define cpu_has_mips_r2_exec_hazard 0 55#define cpu_has_dsp 0 56#define cpu_has_dsp2 0 57#define cpu_has_mipsmt 0 58#define cpu_has_vint 0 59#define cpu_has_veic 0 60#define cpu_hwrena_impl_bits 0xc0000000 61 62#define cpu_has_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON) 63 64#define ARCH_HAS_IRQ_PER_CPU 1 65#define ARCH_HAS_SPINLOCK_PREFETCH 1 66#define spin_lock_prefetch(x) prefetch(x) 67#define PREFETCH_STRIDE 128 68 69#ifdef __OCTEON__ 70/* 71 * All gcc versions that have OCTEON support define __OCTEON__ and have the 72 * __builtin_popcount support. 73 */ 74#define ARCH_HAS_USABLE_BUILTIN_POPCOUNT 1 75#endif 76 77static inline int octeon_has_saa(void) 78{ 79 int id; 80 asm volatile ("mfc0 %0, $15,0" : "=r" (id)); 81 return id >= 0x000d0300; 82} 83 84/* 85 * The last 256MB are reserved for device to device mappings and the 86 * BAR1 hole. 87 */ 88#define MAX_DMA32_PFN (((1ULL << 32) - (1ULL << 28)) >> PAGE_SHIFT) 89 90#endif 91