1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_MIO_DEFS_H__ 29#define __CVMX_MIO_DEFS_H__ 30 31#define CVMX_MIO_BOOT_BIST_STAT (CVMX_ADD_IO_SEG(0x00011800000000F8ull)) 32#define CVMX_MIO_BOOT_COMP (CVMX_ADD_IO_SEG(0x00011800000000B8ull)) 33#define CVMX_MIO_BOOT_DMA_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000100ull) + ((offset) & 3) * 8) 34#define CVMX_MIO_BOOT_DMA_INTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000138ull) + ((offset) & 3) * 8) 35#define CVMX_MIO_BOOT_DMA_INT_ENX(offset) (CVMX_ADD_IO_SEG(0x0001180000000150ull) + ((offset) & 3) * 8) 36#define CVMX_MIO_BOOT_DMA_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000120ull) + ((offset) & 3) * 8) 37#define CVMX_MIO_BOOT_ERR (CVMX_ADD_IO_SEG(0x00011800000000A0ull)) 38#define CVMX_MIO_BOOT_INT (CVMX_ADD_IO_SEG(0x00011800000000A8ull)) 39#define CVMX_MIO_BOOT_LOC_ADR (CVMX_ADD_IO_SEG(0x0001180000000090ull)) 40#define CVMX_MIO_BOOT_LOC_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000080ull) + ((offset) & 1) * 8) 41#define CVMX_MIO_BOOT_LOC_DAT (CVMX_ADD_IO_SEG(0x0001180000000098ull)) 42#define CVMX_MIO_BOOT_PIN_DEFS (CVMX_ADD_IO_SEG(0x00011800000000C0ull)) 43#define CVMX_MIO_BOOT_REG_CFGX(offset) (CVMX_ADD_IO_SEG(0x0001180000000000ull) + ((offset) & 7) * 8) 44#define CVMX_MIO_BOOT_REG_TIMX(offset) (CVMX_ADD_IO_SEG(0x0001180000000040ull) + ((offset) & 7) * 8) 45#define CVMX_MIO_BOOT_THR (CVMX_ADD_IO_SEG(0x00011800000000B0ull)) 46#define CVMX_MIO_EMM_BUF_DAT (CVMX_ADD_IO_SEG(0x00011800000020E8ull)) 47#define CVMX_MIO_EMM_BUF_IDX (CVMX_ADD_IO_SEG(0x00011800000020E0ull)) 48#define CVMX_MIO_EMM_CFG (CVMX_ADD_IO_SEG(0x0001180000002000ull)) 49#define CVMX_MIO_EMM_CMD (CVMX_ADD_IO_SEG(0x0001180000002058ull)) 50#define CVMX_MIO_EMM_DMA (CVMX_ADD_IO_SEG(0x0001180000002050ull)) 51#define CVMX_MIO_EMM_INT (CVMX_ADD_IO_SEG(0x0001180000002078ull)) 52#define CVMX_MIO_EMM_INT_EN (CVMX_ADD_IO_SEG(0x0001180000002080ull)) 53#define CVMX_MIO_EMM_MODEX(offset) (CVMX_ADD_IO_SEG(0x0001180000002008ull) + ((offset) & 3) * 8) 54#define CVMX_MIO_EMM_RCA (CVMX_ADD_IO_SEG(0x00011800000020A0ull)) 55#define CVMX_MIO_EMM_RSP_HI (CVMX_ADD_IO_SEG(0x0001180000002070ull)) 56#define CVMX_MIO_EMM_RSP_LO (CVMX_ADD_IO_SEG(0x0001180000002068ull)) 57#define CVMX_MIO_EMM_RSP_STS (CVMX_ADD_IO_SEG(0x0001180000002060ull)) 58#define CVMX_MIO_EMM_SAMPLE (CVMX_ADD_IO_SEG(0x0001180000002090ull)) 59#define CVMX_MIO_EMM_STS_MASK (CVMX_ADD_IO_SEG(0x0001180000002098ull)) 60#define CVMX_MIO_EMM_SWITCH (CVMX_ADD_IO_SEG(0x0001180000002048ull)) 61#define CVMX_MIO_EMM_WDOG (CVMX_ADD_IO_SEG(0x0001180000002088ull)) 62#define CVMX_MIO_FUS_BNK_DATX(offset) (CVMX_ADD_IO_SEG(0x0001180000001520ull) + ((offset) & 3) * 8) 63#define CVMX_MIO_FUS_DAT0 (CVMX_ADD_IO_SEG(0x0001180000001400ull)) 64#define CVMX_MIO_FUS_DAT1 (CVMX_ADD_IO_SEG(0x0001180000001408ull)) 65#define CVMX_MIO_FUS_DAT2 (CVMX_ADD_IO_SEG(0x0001180000001410ull)) 66#define CVMX_MIO_FUS_DAT3 (CVMX_ADD_IO_SEG(0x0001180000001418ull)) 67#define CVMX_MIO_FUS_EMA (CVMX_ADD_IO_SEG(0x0001180000001550ull)) 68#define CVMX_MIO_FUS_PDF (CVMX_ADD_IO_SEG(0x0001180000001420ull)) 69#define CVMX_MIO_FUS_PLL (CVMX_ADD_IO_SEG(0x0001180000001580ull)) 70#define CVMX_MIO_FUS_PROG (CVMX_ADD_IO_SEG(0x0001180000001510ull)) 71#define CVMX_MIO_FUS_PROG_TIMES (CVMX_ADD_IO_SEG(0x0001180000001518ull)) 72#define CVMX_MIO_FUS_RCMD (CVMX_ADD_IO_SEG(0x0001180000001500ull)) 73#define CVMX_MIO_FUS_READ_TIMES (CVMX_ADD_IO_SEG(0x0001180000001570ull)) 74#define CVMX_MIO_FUS_REPAIR_RES0 (CVMX_ADD_IO_SEG(0x0001180000001558ull)) 75#define CVMX_MIO_FUS_REPAIR_RES1 (CVMX_ADD_IO_SEG(0x0001180000001560ull)) 76#define CVMX_MIO_FUS_REPAIR_RES2 (CVMX_ADD_IO_SEG(0x0001180000001568ull)) 77#define CVMX_MIO_FUS_SPR_REPAIR_RES (CVMX_ADD_IO_SEG(0x0001180000001548ull)) 78#define CVMX_MIO_FUS_SPR_REPAIR_SUM (CVMX_ADD_IO_SEG(0x0001180000001540ull)) 79#define CVMX_MIO_FUS_TGG (CVMX_ADD_IO_SEG(0x0001180000001428ull)) 80#define CVMX_MIO_FUS_UNLOCK (CVMX_ADD_IO_SEG(0x0001180000001578ull)) 81#define CVMX_MIO_FUS_WADR (CVMX_ADD_IO_SEG(0x0001180000001508ull)) 82#define CVMX_MIO_GPIO_COMP (CVMX_ADD_IO_SEG(0x00011800000000C8ull)) 83#define CVMX_MIO_NDF_DMA_CFG (CVMX_ADD_IO_SEG(0x0001180000000168ull)) 84#define CVMX_MIO_NDF_DMA_INT (CVMX_ADD_IO_SEG(0x0001180000000170ull)) 85#define CVMX_MIO_NDF_DMA_INT_EN (CVMX_ADD_IO_SEG(0x0001180000000178ull)) 86#define CVMX_MIO_PLL_CTL (CVMX_ADD_IO_SEG(0x0001180000001448ull)) 87#define CVMX_MIO_PLL_SETTING (CVMX_ADD_IO_SEG(0x0001180000001440ull)) 88#define CVMX_MIO_PTP_CKOUT_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F40ull)) 89#define CVMX_MIO_PTP_CKOUT_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F48ull)) 90#define CVMX_MIO_PTP_CKOUT_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F38ull)) 91#define CVMX_MIO_PTP_CKOUT_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F30ull)) 92#define CVMX_MIO_PTP_CLOCK_CFG (CVMX_ADD_IO_SEG(0x0001070000000F00ull)) 93#define CVMX_MIO_PTP_CLOCK_COMP (CVMX_ADD_IO_SEG(0x0001070000000F18ull)) 94#define CVMX_MIO_PTP_CLOCK_HI (CVMX_ADD_IO_SEG(0x0001070000000F10ull)) 95#define CVMX_MIO_PTP_CLOCK_LO (CVMX_ADD_IO_SEG(0x0001070000000F08ull)) 96#define CVMX_MIO_PTP_EVT_CNT (CVMX_ADD_IO_SEG(0x0001070000000F28ull)) 97#define CVMX_MIO_PTP_PHY_1PPS_IN (CVMX_ADD_IO_SEG(0x0001070000000F70ull)) 98#define CVMX_MIO_PTP_PPS_HI_INCR (CVMX_ADD_IO_SEG(0x0001070000000F60ull)) 99#define CVMX_MIO_PTP_PPS_LO_INCR (CVMX_ADD_IO_SEG(0x0001070000000F68ull)) 100#define CVMX_MIO_PTP_PPS_THRESH_HI (CVMX_ADD_IO_SEG(0x0001070000000F58ull)) 101#define CVMX_MIO_PTP_PPS_THRESH_LO (CVMX_ADD_IO_SEG(0x0001070000000F50ull)) 102#define CVMX_MIO_PTP_TIMESTAMP (CVMX_ADD_IO_SEG(0x0001070000000F20ull)) 103#define CVMX_MIO_QLMX_CFG(offset) (CVMX_ADD_IO_SEG(0x0001180000001590ull) + ((offset) & 7) * 8) 104#define CVMX_MIO_RST_BOOT (CVMX_ADD_IO_SEG(0x0001180000001600ull)) 105#define CVMX_MIO_RST_CFG (CVMX_ADD_IO_SEG(0x0001180000001610ull)) 106#define CVMX_MIO_RST_CKILL (CVMX_ADD_IO_SEG(0x0001180000001638ull)) 107#define CVMX_MIO_RST_CNTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001648ull) + ((offset) & 3) * 8) 108#define CVMX_MIO_RST_CTLX(offset) (CVMX_ADD_IO_SEG(0x0001180000001618ull) + ((offset) & 1) * 8) 109#define CVMX_MIO_RST_DELAY (CVMX_ADD_IO_SEG(0x0001180000001608ull)) 110#define CVMX_MIO_RST_INT (CVMX_ADD_IO_SEG(0x0001180000001628ull)) 111#define CVMX_MIO_RST_INT_EN (CVMX_ADD_IO_SEG(0x0001180000001630ull)) 112#define CVMX_MIO_TWSX_INT(offset) (CVMX_ADD_IO_SEG(0x0001180000001010ull) + ((offset) & 1) * 512) 113#define CVMX_MIO_TWSX_SW_TWSI(offset) (CVMX_ADD_IO_SEG(0x0001180000001000ull) + ((offset) & 1) * 512) 114#define CVMX_MIO_TWSX_SW_TWSI_EXT(offset) (CVMX_ADD_IO_SEG(0x0001180000001018ull) + ((offset) & 1) * 512) 115#define CVMX_MIO_TWSX_TWSI_SW(offset) (CVMX_ADD_IO_SEG(0x0001180000001008ull) + ((offset) & 1) * 512) 116#define CVMX_MIO_UART2_DLH (CVMX_ADD_IO_SEG(0x0001180000000488ull)) 117#define CVMX_MIO_UART2_DLL (CVMX_ADD_IO_SEG(0x0001180000000480ull)) 118#define CVMX_MIO_UART2_FAR (CVMX_ADD_IO_SEG(0x0001180000000520ull)) 119#define CVMX_MIO_UART2_FCR (CVMX_ADD_IO_SEG(0x0001180000000450ull)) 120#define CVMX_MIO_UART2_HTX (CVMX_ADD_IO_SEG(0x0001180000000708ull)) 121#define CVMX_MIO_UART2_IER (CVMX_ADD_IO_SEG(0x0001180000000408ull)) 122#define CVMX_MIO_UART2_IIR (CVMX_ADD_IO_SEG(0x0001180000000410ull)) 123#define CVMX_MIO_UART2_LCR (CVMX_ADD_IO_SEG(0x0001180000000418ull)) 124#define CVMX_MIO_UART2_LSR (CVMX_ADD_IO_SEG(0x0001180000000428ull)) 125#define CVMX_MIO_UART2_MCR (CVMX_ADD_IO_SEG(0x0001180000000420ull)) 126#define CVMX_MIO_UART2_MSR (CVMX_ADD_IO_SEG(0x0001180000000430ull)) 127#define CVMX_MIO_UART2_RBR (CVMX_ADD_IO_SEG(0x0001180000000400ull)) 128#define CVMX_MIO_UART2_RFL (CVMX_ADD_IO_SEG(0x0001180000000608ull)) 129#define CVMX_MIO_UART2_RFW (CVMX_ADD_IO_SEG(0x0001180000000530ull)) 130#define CVMX_MIO_UART2_SBCR (CVMX_ADD_IO_SEG(0x0001180000000620ull)) 131#define CVMX_MIO_UART2_SCR (CVMX_ADD_IO_SEG(0x0001180000000438ull)) 132#define CVMX_MIO_UART2_SFE (CVMX_ADD_IO_SEG(0x0001180000000630ull)) 133#define CVMX_MIO_UART2_SRR (CVMX_ADD_IO_SEG(0x0001180000000610ull)) 134#define CVMX_MIO_UART2_SRT (CVMX_ADD_IO_SEG(0x0001180000000638ull)) 135#define CVMX_MIO_UART2_SRTS (CVMX_ADD_IO_SEG(0x0001180000000618ull)) 136#define CVMX_MIO_UART2_STT (CVMX_ADD_IO_SEG(0x0001180000000700ull)) 137#define CVMX_MIO_UART2_TFL (CVMX_ADD_IO_SEG(0x0001180000000600ull)) 138#define CVMX_MIO_UART2_TFR (CVMX_ADD_IO_SEG(0x0001180000000528ull)) 139#define CVMX_MIO_UART2_THR (CVMX_ADD_IO_SEG(0x0001180000000440ull)) 140#define CVMX_MIO_UART2_USR (CVMX_ADD_IO_SEG(0x0001180000000538ull)) 141#define CVMX_MIO_UARTX_DLH(offset) (CVMX_ADD_IO_SEG(0x0001180000000888ull) + ((offset) & 1) * 1024) 142#define CVMX_MIO_UARTX_DLL(offset) (CVMX_ADD_IO_SEG(0x0001180000000880ull) + ((offset) & 1) * 1024) 143#define CVMX_MIO_UARTX_FAR(offset) (CVMX_ADD_IO_SEG(0x0001180000000920ull) + ((offset) & 1) * 1024) 144#define CVMX_MIO_UARTX_FCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000850ull) + ((offset) & 1) * 1024) 145#define CVMX_MIO_UARTX_HTX(offset) (CVMX_ADD_IO_SEG(0x0001180000000B08ull) + ((offset) & 1) * 1024) 146#define CVMX_MIO_UARTX_IER(offset) (CVMX_ADD_IO_SEG(0x0001180000000808ull) + ((offset) & 1) * 1024) 147#define CVMX_MIO_UARTX_IIR(offset) (CVMX_ADD_IO_SEG(0x0001180000000810ull) + ((offset) & 1) * 1024) 148#define CVMX_MIO_UARTX_LCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000818ull) + ((offset) & 1) * 1024) 149#define CVMX_MIO_UARTX_LSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000828ull) + ((offset) & 1) * 1024) 150#define CVMX_MIO_UARTX_MCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000820ull) + ((offset) & 1) * 1024) 151#define CVMX_MIO_UARTX_MSR(offset) (CVMX_ADD_IO_SEG(0x0001180000000830ull) + ((offset) & 1) * 1024) 152#define CVMX_MIO_UARTX_RBR(offset) (CVMX_ADD_IO_SEG(0x0001180000000800ull) + ((offset) & 1) * 1024) 153#define CVMX_MIO_UARTX_RFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A08ull) + ((offset) & 1) * 1024) 154#define CVMX_MIO_UARTX_RFW(offset) (CVMX_ADD_IO_SEG(0x0001180000000930ull) + ((offset) & 1) * 1024) 155#define CVMX_MIO_UARTX_SBCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A20ull) + ((offset) & 1) * 1024) 156#define CVMX_MIO_UARTX_SCR(offset) (CVMX_ADD_IO_SEG(0x0001180000000838ull) + ((offset) & 1) * 1024) 157#define CVMX_MIO_UARTX_SFE(offset) (CVMX_ADD_IO_SEG(0x0001180000000A30ull) + ((offset) & 1) * 1024) 158#define CVMX_MIO_UARTX_SRR(offset) (CVMX_ADD_IO_SEG(0x0001180000000A10ull) + ((offset) & 1) * 1024) 159#define CVMX_MIO_UARTX_SRT(offset) (CVMX_ADD_IO_SEG(0x0001180000000A38ull) + ((offset) & 1) * 1024) 160#define CVMX_MIO_UARTX_SRTS(offset) (CVMX_ADD_IO_SEG(0x0001180000000A18ull) + ((offset) & 1) * 1024) 161#define CVMX_MIO_UARTX_STT(offset) (CVMX_ADD_IO_SEG(0x0001180000000B00ull) + ((offset) & 1) * 1024) 162#define CVMX_MIO_UARTX_TFL(offset) (CVMX_ADD_IO_SEG(0x0001180000000A00ull) + ((offset) & 1) * 1024) 163#define CVMX_MIO_UARTX_TFR(offset) (CVMX_ADD_IO_SEG(0x0001180000000928ull) + ((offset) & 1) * 1024) 164#define CVMX_MIO_UARTX_THR(offset) (CVMX_ADD_IO_SEG(0x0001180000000840ull) + ((offset) & 1) * 1024) 165#define CVMX_MIO_UARTX_USR(offset) (CVMX_ADD_IO_SEG(0x0001180000000938ull) + ((offset) & 1) * 1024) 166 167union cvmx_mio_boot_bist_stat { 168 uint64_t u64; 169 struct cvmx_mio_boot_bist_stat_s { 170#ifdef __BIG_ENDIAN_BITFIELD 171 uint64_t reserved_0_63:64; 172#else 173 uint64_t reserved_0_63:64; 174#endif 175 } s; 176 struct cvmx_mio_boot_bist_stat_cn30xx { 177#ifdef __BIG_ENDIAN_BITFIELD 178 uint64_t reserved_4_63:60; 179 uint64_t ncbo_1:1; 180 uint64_t ncbo_0:1; 181 uint64_t loc:1; 182 uint64_t ncbi:1; 183#else 184 uint64_t ncbi:1; 185 uint64_t loc:1; 186 uint64_t ncbo_0:1; 187 uint64_t ncbo_1:1; 188 uint64_t reserved_4_63:60; 189#endif 190 } cn30xx; 191 struct cvmx_mio_boot_bist_stat_cn30xx cn31xx; 192 struct cvmx_mio_boot_bist_stat_cn38xx { 193#ifdef __BIG_ENDIAN_BITFIELD 194 uint64_t reserved_3_63:61; 195 uint64_t ncbo_0:1; 196 uint64_t loc:1; 197 uint64_t ncbi:1; 198#else 199 uint64_t ncbi:1; 200 uint64_t loc:1; 201 uint64_t ncbo_0:1; 202 uint64_t reserved_3_63:61; 203#endif 204 } cn38xx; 205 struct cvmx_mio_boot_bist_stat_cn38xx cn38xxp2; 206 struct cvmx_mio_boot_bist_stat_cn50xx { 207#ifdef __BIG_ENDIAN_BITFIELD 208 uint64_t reserved_6_63:58; 209 uint64_t pcm_1:1; 210 uint64_t pcm_0:1; 211 uint64_t ncbo_1:1; 212 uint64_t ncbo_0:1; 213 uint64_t loc:1; 214 uint64_t ncbi:1; 215#else 216 uint64_t ncbi:1; 217 uint64_t loc:1; 218 uint64_t ncbo_0:1; 219 uint64_t ncbo_1:1; 220 uint64_t pcm_0:1; 221 uint64_t pcm_1:1; 222 uint64_t reserved_6_63:58; 223#endif 224 } cn50xx; 225 struct cvmx_mio_boot_bist_stat_cn52xx { 226#ifdef __BIG_ENDIAN_BITFIELD 227 uint64_t reserved_6_63:58; 228 uint64_t ndf:2; 229 uint64_t ncbo_0:1; 230 uint64_t dma:1; 231 uint64_t loc:1; 232 uint64_t ncbi:1; 233#else 234 uint64_t ncbi:1; 235 uint64_t loc:1; 236 uint64_t dma:1; 237 uint64_t ncbo_0:1; 238 uint64_t ndf:2; 239 uint64_t reserved_6_63:58; 240#endif 241 } cn52xx; 242 struct cvmx_mio_boot_bist_stat_cn52xxp1 { 243#ifdef __BIG_ENDIAN_BITFIELD 244 uint64_t reserved_4_63:60; 245 uint64_t ncbo_0:1; 246 uint64_t dma:1; 247 uint64_t loc:1; 248 uint64_t ncbi:1; 249#else 250 uint64_t ncbi:1; 251 uint64_t loc:1; 252 uint64_t dma:1; 253 uint64_t ncbo_0:1; 254 uint64_t reserved_4_63:60; 255#endif 256 } cn52xxp1; 257 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xx; 258 struct cvmx_mio_boot_bist_stat_cn52xxp1 cn56xxp1; 259 struct cvmx_mio_boot_bist_stat_cn38xx cn58xx; 260 struct cvmx_mio_boot_bist_stat_cn38xx cn58xxp1; 261 struct cvmx_mio_boot_bist_stat_cn61xx { 262#ifdef __BIG_ENDIAN_BITFIELD 263 uint64_t reserved_12_63:52; 264 uint64_t stat:12; 265#else 266 uint64_t stat:12; 267 uint64_t reserved_12_63:52; 268#endif 269 } cn61xx; 270 struct cvmx_mio_boot_bist_stat_cn63xx { 271#ifdef __BIG_ENDIAN_BITFIELD 272 uint64_t reserved_9_63:55; 273 uint64_t stat:9; 274#else 275 uint64_t stat:9; 276 uint64_t reserved_9_63:55; 277#endif 278 } cn63xx; 279 struct cvmx_mio_boot_bist_stat_cn63xx cn63xxp1; 280 struct cvmx_mio_boot_bist_stat_cn66xx { 281#ifdef __BIG_ENDIAN_BITFIELD 282 uint64_t reserved_10_63:54; 283 uint64_t stat:10; 284#else 285 uint64_t stat:10; 286 uint64_t reserved_10_63:54; 287#endif 288 } cn66xx; 289 struct cvmx_mio_boot_bist_stat_cn66xx cn68xx; 290 struct cvmx_mio_boot_bist_stat_cn66xx cn68xxp1; 291 struct cvmx_mio_boot_bist_stat_cn61xx cnf71xx; 292}; 293 294union cvmx_mio_boot_comp { 295 uint64_t u64; 296 struct cvmx_mio_boot_comp_s { 297#ifdef __BIG_ENDIAN_BITFIELD 298 uint64_t reserved_0_63:64; 299#else 300 uint64_t reserved_0_63:64; 301#endif 302 } s; 303 struct cvmx_mio_boot_comp_cn50xx { 304#ifdef __BIG_ENDIAN_BITFIELD 305 uint64_t reserved_10_63:54; 306 uint64_t pctl:5; 307 uint64_t nctl:5; 308#else 309 uint64_t nctl:5; 310 uint64_t pctl:5; 311 uint64_t reserved_10_63:54; 312#endif 313 } cn50xx; 314 struct cvmx_mio_boot_comp_cn50xx cn52xx; 315 struct cvmx_mio_boot_comp_cn50xx cn52xxp1; 316 struct cvmx_mio_boot_comp_cn50xx cn56xx; 317 struct cvmx_mio_boot_comp_cn50xx cn56xxp1; 318 struct cvmx_mio_boot_comp_cn61xx { 319#ifdef __BIG_ENDIAN_BITFIELD 320 uint64_t reserved_12_63:52; 321 uint64_t pctl:6; 322 uint64_t nctl:6; 323#else 324 uint64_t nctl:6; 325 uint64_t pctl:6; 326 uint64_t reserved_12_63:52; 327#endif 328 } cn61xx; 329 struct cvmx_mio_boot_comp_cn61xx cn63xx; 330 struct cvmx_mio_boot_comp_cn61xx cn63xxp1; 331 struct cvmx_mio_boot_comp_cn61xx cn66xx; 332 struct cvmx_mio_boot_comp_cn61xx cn68xx; 333 struct cvmx_mio_boot_comp_cn61xx cn68xxp1; 334 struct cvmx_mio_boot_comp_cn61xx cnf71xx; 335}; 336 337union cvmx_mio_boot_dma_cfgx { 338 uint64_t u64; 339 struct cvmx_mio_boot_dma_cfgx_s { 340#ifdef __BIG_ENDIAN_BITFIELD 341 uint64_t en:1; 342 uint64_t rw:1; 343 uint64_t clr:1; 344 uint64_t reserved_60_60:1; 345 uint64_t swap32:1; 346 uint64_t swap16:1; 347 uint64_t swap8:1; 348 uint64_t endian:1; 349 uint64_t size:20; 350 uint64_t adr:36; 351#else 352 uint64_t adr:36; 353 uint64_t size:20; 354 uint64_t endian:1; 355 uint64_t swap8:1; 356 uint64_t swap16:1; 357 uint64_t swap32:1; 358 uint64_t reserved_60_60:1; 359 uint64_t clr:1; 360 uint64_t rw:1; 361 uint64_t en:1; 362#endif 363 } s; 364 struct cvmx_mio_boot_dma_cfgx_s cn52xx; 365 struct cvmx_mio_boot_dma_cfgx_s cn52xxp1; 366 struct cvmx_mio_boot_dma_cfgx_s cn56xx; 367 struct cvmx_mio_boot_dma_cfgx_s cn56xxp1; 368 struct cvmx_mio_boot_dma_cfgx_s cn61xx; 369 struct cvmx_mio_boot_dma_cfgx_s cn63xx; 370 struct cvmx_mio_boot_dma_cfgx_s cn63xxp1; 371 struct cvmx_mio_boot_dma_cfgx_s cn66xx; 372 struct cvmx_mio_boot_dma_cfgx_s cn68xx; 373 struct cvmx_mio_boot_dma_cfgx_s cn68xxp1; 374 struct cvmx_mio_boot_dma_cfgx_s cnf71xx; 375}; 376 377union cvmx_mio_boot_dma_intx { 378 uint64_t u64; 379 struct cvmx_mio_boot_dma_intx_s { 380#ifdef __BIG_ENDIAN_BITFIELD 381 uint64_t reserved_2_63:62; 382 uint64_t dmarq:1; 383 uint64_t done:1; 384#else 385 uint64_t done:1; 386 uint64_t dmarq:1; 387 uint64_t reserved_2_63:62; 388#endif 389 } s; 390 struct cvmx_mio_boot_dma_intx_s cn52xx; 391 struct cvmx_mio_boot_dma_intx_s cn52xxp1; 392 struct cvmx_mio_boot_dma_intx_s cn56xx; 393 struct cvmx_mio_boot_dma_intx_s cn56xxp1; 394 struct cvmx_mio_boot_dma_intx_s cn61xx; 395 struct cvmx_mio_boot_dma_intx_s cn63xx; 396 struct cvmx_mio_boot_dma_intx_s cn63xxp1; 397 struct cvmx_mio_boot_dma_intx_s cn66xx; 398 struct cvmx_mio_boot_dma_intx_s cn68xx; 399 struct cvmx_mio_boot_dma_intx_s cn68xxp1; 400 struct cvmx_mio_boot_dma_intx_s cnf71xx; 401}; 402 403union cvmx_mio_boot_dma_int_enx { 404 uint64_t u64; 405 struct cvmx_mio_boot_dma_int_enx_s { 406#ifdef __BIG_ENDIAN_BITFIELD 407 uint64_t reserved_2_63:62; 408 uint64_t dmarq:1; 409 uint64_t done:1; 410#else 411 uint64_t done:1; 412 uint64_t dmarq:1; 413 uint64_t reserved_2_63:62; 414#endif 415 } s; 416 struct cvmx_mio_boot_dma_int_enx_s cn52xx; 417 struct cvmx_mio_boot_dma_int_enx_s cn52xxp1; 418 struct cvmx_mio_boot_dma_int_enx_s cn56xx; 419 struct cvmx_mio_boot_dma_int_enx_s cn56xxp1; 420 struct cvmx_mio_boot_dma_int_enx_s cn61xx; 421 struct cvmx_mio_boot_dma_int_enx_s cn63xx; 422 struct cvmx_mio_boot_dma_int_enx_s cn63xxp1; 423 struct cvmx_mio_boot_dma_int_enx_s cn66xx; 424 struct cvmx_mio_boot_dma_int_enx_s cn68xx; 425 struct cvmx_mio_boot_dma_int_enx_s cn68xxp1; 426 struct cvmx_mio_boot_dma_int_enx_s cnf71xx; 427}; 428 429union cvmx_mio_boot_dma_timx { 430 uint64_t u64; 431 struct cvmx_mio_boot_dma_timx_s { 432#ifdef __BIG_ENDIAN_BITFIELD 433 uint64_t dmack_pi:1; 434 uint64_t dmarq_pi:1; 435 uint64_t tim_mult:2; 436 uint64_t rd_dly:3; 437 uint64_t ddr:1; 438 uint64_t width:1; 439 uint64_t reserved_48_54:7; 440 uint64_t pause:6; 441 uint64_t dmack_h:6; 442 uint64_t we_n:6; 443 uint64_t we_a:6; 444 uint64_t oe_n:6; 445 uint64_t oe_a:6; 446 uint64_t dmack_s:6; 447 uint64_t dmarq:6; 448#else 449 uint64_t dmarq:6; 450 uint64_t dmack_s:6; 451 uint64_t oe_a:6; 452 uint64_t oe_n:6; 453 uint64_t we_a:6; 454 uint64_t we_n:6; 455 uint64_t dmack_h:6; 456 uint64_t pause:6; 457 uint64_t reserved_48_54:7; 458 uint64_t width:1; 459 uint64_t ddr:1; 460 uint64_t rd_dly:3; 461 uint64_t tim_mult:2; 462 uint64_t dmarq_pi:1; 463 uint64_t dmack_pi:1; 464#endif 465 } s; 466 struct cvmx_mio_boot_dma_timx_s cn52xx; 467 struct cvmx_mio_boot_dma_timx_s cn52xxp1; 468 struct cvmx_mio_boot_dma_timx_s cn56xx; 469 struct cvmx_mio_boot_dma_timx_s cn56xxp1; 470 struct cvmx_mio_boot_dma_timx_s cn61xx; 471 struct cvmx_mio_boot_dma_timx_s cn63xx; 472 struct cvmx_mio_boot_dma_timx_s cn63xxp1; 473 struct cvmx_mio_boot_dma_timx_s cn66xx; 474 struct cvmx_mio_boot_dma_timx_s cn68xx; 475 struct cvmx_mio_boot_dma_timx_s cn68xxp1; 476 struct cvmx_mio_boot_dma_timx_s cnf71xx; 477}; 478 479union cvmx_mio_boot_err { 480 uint64_t u64; 481 struct cvmx_mio_boot_err_s { 482#ifdef __BIG_ENDIAN_BITFIELD 483 uint64_t reserved_2_63:62; 484 uint64_t wait_err:1; 485 uint64_t adr_err:1; 486#else 487 uint64_t adr_err:1; 488 uint64_t wait_err:1; 489 uint64_t reserved_2_63:62; 490#endif 491 } s; 492 struct cvmx_mio_boot_err_s cn30xx; 493 struct cvmx_mio_boot_err_s cn31xx; 494 struct cvmx_mio_boot_err_s cn38xx; 495 struct cvmx_mio_boot_err_s cn38xxp2; 496 struct cvmx_mio_boot_err_s cn50xx; 497 struct cvmx_mio_boot_err_s cn52xx; 498 struct cvmx_mio_boot_err_s cn52xxp1; 499 struct cvmx_mio_boot_err_s cn56xx; 500 struct cvmx_mio_boot_err_s cn56xxp1; 501 struct cvmx_mio_boot_err_s cn58xx; 502 struct cvmx_mio_boot_err_s cn58xxp1; 503 struct cvmx_mio_boot_err_s cn61xx; 504 struct cvmx_mio_boot_err_s cn63xx; 505 struct cvmx_mio_boot_err_s cn63xxp1; 506 struct cvmx_mio_boot_err_s cn66xx; 507 struct cvmx_mio_boot_err_s cn68xx; 508 struct cvmx_mio_boot_err_s cn68xxp1; 509 struct cvmx_mio_boot_err_s cnf71xx; 510}; 511 512union cvmx_mio_boot_int { 513 uint64_t u64; 514 struct cvmx_mio_boot_int_s { 515#ifdef __BIG_ENDIAN_BITFIELD 516 uint64_t reserved_2_63:62; 517 uint64_t wait_int:1; 518 uint64_t adr_int:1; 519#else 520 uint64_t adr_int:1; 521 uint64_t wait_int:1; 522 uint64_t reserved_2_63:62; 523#endif 524 } s; 525 struct cvmx_mio_boot_int_s cn30xx; 526 struct cvmx_mio_boot_int_s cn31xx; 527 struct cvmx_mio_boot_int_s cn38xx; 528 struct cvmx_mio_boot_int_s cn38xxp2; 529 struct cvmx_mio_boot_int_s cn50xx; 530 struct cvmx_mio_boot_int_s cn52xx; 531 struct cvmx_mio_boot_int_s cn52xxp1; 532 struct cvmx_mio_boot_int_s cn56xx; 533 struct cvmx_mio_boot_int_s cn56xxp1; 534 struct cvmx_mio_boot_int_s cn58xx; 535 struct cvmx_mio_boot_int_s cn58xxp1; 536 struct cvmx_mio_boot_int_s cn61xx; 537 struct cvmx_mio_boot_int_s cn63xx; 538 struct cvmx_mio_boot_int_s cn63xxp1; 539 struct cvmx_mio_boot_int_s cn66xx; 540 struct cvmx_mio_boot_int_s cn68xx; 541 struct cvmx_mio_boot_int_s cn68xxp1; 542 struct cvmx_mio_boot_int_s cnf71xx; 543}; 544 545union cvmx_mio_boot_loc_adr { 546 uint64_t u64; 547 struct cvmx_mio_boot_loc_adr_s { 548#ifdef __BIG_ENDIAN_BITFIELD 549 uint64_t reserved_8_63:56; 550 uint64_t adr:5; 551 uint64_t reserved_0_2:3; 552#else 553 uint64_t reserved_0_2:3; 554 uint64_t adr:5; 555 uint64_t reserved_8_63:56; 556#endif 557 } s; 558 struct cvmx_mio_boot_loc_adr_s cn30xx; 559 struct cvmx_mio_boot_loc_adr_s cn31xx; 560 struct cvmx_mio_boot_loc_adr_s cn38xx; 561 struct cvmx_mio_boot_loc_adr_s cn38xxp2; 562 struct cvmx_mio_boot_loc_adr_s cn50xx; 563 struct cvmx_mio_boot_loc_adr_s cn52xx; 564 struct cvmx_mio_boot_loc_adr_s cn52xxp1; 565 struct cvmx_mio_boot_loc_adr_s cn56xx; 566 struct cvmx_mio_boot_loc_adr_s cn56xxp1; 567 struct cvmx_mio_boot_loc_adr_s cn58xx; 568 struct cvmx_mio_boot_loc_adr_s cn58xxp1; 569 struct cvmx_mio_boot_loc_adr_s cn61xx; 570 struct cvmx_mio_boot_loc_adr_s cn63xx; 571 struct cvmx_mio_boot_loc_adr_s cn63xxp1; 572 struct cvmx_mio_boot_loc_adr_s cn66xx; 573 struct cvmx_mio_boot_loc_adr_s cn68xx; 574 struct cvmx_mio_boot_loc_adr_s cn68xxp1; 575 struct cvmx_mio_boot_loc_adr_s cnf71xx; 576}; 577 578union cvmx_mio_boot_loc_cfgx { 579 uint64_t u64; 580 struct cvmx_mio_boot_loc_cfgx_s { 581#ifdef __BIG_ENDIAN_BITFIELD 582 uint64_t reserved_32_63:32; 583 uint64_t en:1; 584 uint64_t reserved_28_30:3; 585 uint64_t base:25; 586 uint64_t reserved_0_2:3; 587#else 588 uint64_t reserved_0_2:3; 589 uint64_t base:25; 590 uint64_t reserved_28_30:3; 591 uint64_t en:1; 592 uint64_t reserved_32_63:32; 593#endif 594 } s; 595 struct cvmx_mio_boot_loc_cfgx_s cn30xx; 596 struct cvmx_mio_boot_loc_cfgx_s cn31xx; 597 struct cvmx_mio_boot_loc_cfgx_s cn38xx; 598 struct cvmx_mio_boot_loc_cfgx_s cn38xxp2; 599 struct cvmx_mio_boot_loc_cfgx_s cn50xx; 600 struct cvmx_mio_boot_loc_cfgx_s cn52xx; 601 struct cvmx_mio_boot_loc_cfgx_s cn52xxp1; 602 struct cvmx_mio_boot_loc_cfgx_s cn56xx; 603 struct cvmx_mio_boot_loc_cfgx_s cn56xxp1; 604 struct cvmx_mio_boot_loc_cfgx_s cn58xx; 605 struct cvmx_mio_boot_loc_cfgx_s cn58xxp1; 606 struct cvmx_mio_boot_loc_cfgx_s cn61xx; 607 struct cvmx_mio_boot_loc_cfgx_s cn63xx; 608 struct cvmx_mio_boot_loc_cfgx_s cn63xxp1; 609 struct cvmx_mio_boot_loc_cfgx_s cn66xx; 610 struct cvmx_mio_boot_loc_cfgx_s cn68xx; 611 struct cvmx_mio_boot_loc_cfgx_s cn68xxp1; 612 struct cvmx_mio_boot_loc_cfgx_s cnf71xx; 613}; 614 615union cvmx_mio_boot_loc_dat { 616 uint64_t u64; 617 struct cvmx_mio_boot_loc_dat_s { 618#ifdef __BIG_ENDIAN_BITFIELD 619 uint64_t data:64; 620#else 621 uint64_t data:64; 622#endif 623 } s; 624 struct cvmx_mio_boot_loc_dat_s cn30xx; 625 struct cvmx_mio_boot_loc_dat_s cn31xx; 626 struct cvmx_mio_boot_loc_dat_s cn38xx; 627 struct cvmx_mio_boot_loc_dat_s cn38xxp2; 628 struct cvmx_mio_boot_loc_dat_s cn50xx; 629 struct cvmx_mio_boot_loc_dat_s cn52xx; 630 struct cvmx_mio_boot_loc_dat_s cn52xxp1; 631 struct cvmx_mio_boot_loc_dat_s cn56xx; 632 struct cvmx_mio_boot_loc_dat_s cn56xxp1; 633 struct cvmx_mio_boot_loc_dat_s cn58xx; 634 struct cvmx_mio_boot_loc_dat_s cn58xxp1; 635 struct cvmx_mio_boot_loc_dat_s cn61xx; 636 struct cvmx_mio_boot_loc_dat_s cn63xx; 637 struct cvmx_mio_boot_loc_dat_s cn63xxp1; 638 struct cvmx_mio_boot_loc_dat_s cn66xx; 639 struct cvmx_mio_boot_loc_dat_s cn68xx; 640 struct cvmx_mio_boot_loc_dat_s cn68xxp1; 641 struct cvmx_mio_boot_loc_dat_s cnf71xx; 642}; 643 644union cvmx_mio_boot_pin_defs { 645 uint64_t u64; 646 struct cvmx_mio_boot_pin_defs_s { 647#ifdef __BIG_ENDIAN_BITFIELD 648 uint64_t reserved_32_63:32; 649 uint64_t user1:16; 650 uint64_t ale:1; 651 uint64_t width:1; 652 uint64_t dmack_p2:1; 653 uint64_t dmack_p1:1; 654 uint64_t dmack_p0:1; 655 uint64_t term:2; 656 uint64_t nand:1; 657 uint64_t user0:8; 658#else 659 uint64_t user0:8; 660 uint64_t nand:1; 661 uint64_t term:2; 662 uint64_t dmack_p0:1; 663 uint64_t dmack_p1:1; 664 uint64_t dmack_p2:1; 665 uint64_t width:1; 666 uint64_t ale:1; 667 uint64_t user1:16; 668 uint64_t reserved_32_63:32; 669#endif 670 } s; 671 struct cvmx_mio_boot_pin_defs_cn52xx { 672#ifdef __BIG_ENDIAN_BITFIELD 673 uint64_t reserved_16_63:48; 674 uint64_t ale:1; 675 uint64_t width:1; 676 uint64_t reserved_13_13:1; 677 uint64_t dmack_p1:1; 678 uint64_t dmack_p0:1; 679 uint64_t term:2; 680 uint64_t nand:1; 681 uint64_t reserved_0_7:8; 682#else 683 uint64_t reserved_0_7:8; 684 uint64_t nand:1; 685 uint64_t term:2; 686 uint64_t dmack_p0:1; 687 uint64_t dmack_p1:1; 688 uint64_t reserved_13_13:1; 689 uint64_t width:1; 690 uint64_t ale:1; 691 uint64_t reserved_16_63:48; 692#endif 693 } cn52xx; 694 struct cvmx_mio_boot_pin_defs_cn56xx { 695#ifdef __BIG_ENDIAN_BITFIELD 696 uint64_t reserved_16_63:48; 697 uint64_t ale:1; 698 uint64_t width:1; 699 uint64_t dmack_p2:1; 700 uint64_t dmack_p1:1; 701 uint64_t dmack_p0:1; 702 uint64_t term:2; 703 uint64_t reserved_0_8:9; 704#else 705 uint64_t reserved_0_8:9; 706 uint64_t term:2; 707 uint64_t dmack_p0:1; 708 uint64_t dmack_p1:1; 709 uint64_t dmack_p2:1; 710 uint64_t width:1; 711 uint64_t ale:1; 712 uint64_t reserved_16_63:48; 713#endif 714 } cn56xx; 715 struct cvmx_mio_boot_pin_defs_cn61xx { 716#ifdef __BIG_ENDIAN_BITFIELD 717 uint64_t reserved_32_63:32; 718 uint64_t user1:16; 719 uint64_t ale:1; 720 uint64_t width:1; 721 uint64_t reserved_13_13:1; 722 uint64_t dmack_p1:1; 723 uint64_t dmack_p0:1; 724 uint64_t term:2; 725 uint64_t nand:1; 726 uint64_t user0:8; 727#else 728 uint64_t user0:8; 729 uint64_t nand:1; 730 uint64_t term:2; 731 uint64_t dmack_p0:1; 732 uint64_t dmack_p1:1; 733 uint64_t reserved_13_13:1; 734 uint64_t width:1; 735 uint64_t ale:1; 736 uint64_t user1:16; 737 uint64_t reserved_32_63:32; 738#endif 739 } cn61xx; 740 struct cvmx_mio_boot_pin_defs_cn52xx cn63xx; 741 struct cvmx_mio_boot_pin_defs_cn52xx cn63xxp1; 742 struct cvmx_mio_boot_pin_defs_cn52xx cn66xx; 743 struct cvmx_mio_boot_pin_defs_cn52xx cn68xx; 744 struct cvmx_mio_boot_pin_defs_cn52xx cn68xxp1; 745 struct cvmx_mio_boot_pin_defs_cn61xx cnf71xx; 746}; 747 748union cvmx_mio_boot_reg_cfgx { 749 uint64_t u64; 750 struct cvmx_mio_boot_reg_cfgx_s { 751#ifdef __BIG_ENDIAN_BITFIELD 752 uint64_t reserved_44_63:20; 753 uint64_t dmack:2; 754 uint64_t tim_mult:2; 755 uint64_t rd_dly:3; 756 uint64_t sam:1; 757 uint64_t we_ext:2; 758 uint64_t oe_ext:2; 759 uint64_t en:1; 760 uint64_t orbit:1; 761 uint64_t ale:1; 762 uint64_t width:1; 763 uint64_t size:12; 764 uint64_t base:16; 765#else 766 uint64_t base:16; 767 uint64_t size:12; 768 uint64_t width:1; 769 uint64_t ale:1; 770 uint64_t orbit:1; 771 uint64_t en:1; 772 uint64_t oe_ext:2; 773 uint64_t we_ext:2; 774 uint64_t sam:1; 775 uint64_t rd_dly:3; 776 uint64_t tim_mult:2; 777 uint64_t dmack:2; 778 uint64_t reserved_44_63:20; 779#endif 780 } s; 781 struct cvmx_mio_boot_reg_cfgx_cn30xx { 782#ifdef __BIG_ENDIAN_BITFIELD 783 uint64_t reserved_37_63:27; 784 uint64_t sam:1; 785 uint64_t we_ext:2; 786 uint64_t oe_ext:2; 787 uint64_t en:1; 788 uint64_t orbit:1; 789 uint64_t ale:1; 790 uint64_t width:1; 791 uint64_t size:12; 792 uint64_t base:16; 793#else 794 uint64_t base:16; 795 uint64_t size:12; 796 uint64_t width:1; 797 uint64_t ale:1; 798 uint64_t orbit:1; 799 uint64_t en:1; 800 uint64_t oe_ext:2; 801 uint64_t we_ext:2; 802 uint64_t sam:1; 803 uint64_t reserved_37_63:27; 804#endif 805 } cn30xx; 806 struct cvmx_mio_boot_reg_cfgx_cn30xx cn31xx; 807 struct cvmx_mio_boot_reg_cfgx_cn38xx { 808#ifdef __BIG_ENDIAN_BITFIELD 809 uint64_t reserved_32_63:32; 810 uint64_t en:1; 811 uint64_t orbit:1; 812 uint64_t reserved_28_29:2; 813 uint64_t size:12; 814 uint64_t base:16; 815#else 816 uint64_t base:16; 817 uint64_t size:12; 818 uint64_t reserved_28_29:2; 819 uint64_t orbit:1; 820 uint64_t en:1; 821 uint64_t reserved_32_63:32; 822#endif 823 } cn38xx; 824 struct cvmx_mio_boot_reg_cfgx_cn38xx cn38xxp2; 825 struct cvmx_mio_boot_reg_cfgx_cn50xx { 826#ifdef __BIG_ENDIAN_BITFIELD 827 uint64_t reserved_42_63:22; 828 uint64_t tim_mult:2; 829 uint64_t rd_dly:3; 830 uint64_t sam:1; 831 uint64_t we_ext:2; 832 uint64_t oe_ext:2; 833 uint64_t en:1; 834 uint64_t orbit:1; 835 uint64_t ale:1; 836 uint64_t width:1; 837 uint64_t size:12; 838 uint64_t base:16; 839#else 840 uint64_t base:16; 841 uint64_t size:12; 842 uint64_t width:1; 843 uint64_t ale:1; 844 uint64_t orbit:1; 845 uint64_t en:1; 846 uint64_t oe_ext:2; 847 uint64_t we_ext:2; 848 uint64_t sam:1; 849 uint64_t rd_dly:3; 850 uint64_t tim_mult:2; 851 uint64_t reserved_42_63:22; 852#endif 853 } cn50xx; 854 struct cvmx_mio_boot_reg_cfgx_s cn52xx; 855 struct cvmx_mio_boot_reg_cfgx_s cn52xxp1; 856 struct cvmx_mio_boot_reg_cfgx_s cn56xx; 857 struct cvmx_mio_boot_reg_cfgx_s cn56xxp1; 858 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xx; 859 struct cvmx_mio_boot_reg_cfgx_cn30xx cn58xxp1; 860 struct cvmx_mio_boot_reg_cfgx_s cn61xx; 861 struct cvmx_mio_boot_reg_cfgx_s cn63xx; 862 struct cvmx_mio_boot_reg_cfgx_s cn63xxp1; 863 struct cvmx_mio_boot_reg_cfgx_s cn66xx; 864 struct cvmx_mio_boot_reg_cfgx_s cn68xx; 865 struct cvmx_mio_boot_reg_cfgx_s cn68xxp1; 866 struct cvmx_mio_boot_reg_cfgx_s cnf71xx; 867}; 868 869union cvmx_mio_boot_reg_timx { 870 uint64_t u64; 871 struct cvmx_mio_boot_reg_timx_s { 872#ifdef __BIG_ENDIAN_BITFIELD 873 uint64_t pagem:1; 874 uint64_t waitm:1; 875 uint64_t pages:2; 876 uint64_t ale:6; 877 uint64_t page:6; 878 uint64_t wait:6; 879 uint64_t pause:6; 880 uint64_t wr_hld:6; 881 uint64_t rd_hld:6; 882 uint64_t we:6; 883 uint64_t oe:6; 884 uint64_t ce:6; 885 uint64_t adr:6; 886#else 887 uint64_t adr:6; 888 uint64_t ce:6; 889 uint64_t oe:6; 890 uint64_t we:6; 891 uint64_t rd_hld:6; 892 uint64_t wr_hld:6; 893 uint64_t pause:6; 894 uint64_t wait:6; 895 uint64_t page:6; 896 uint64_t ale:6; 897 uint64_t pages:2; 898 uint64_t waitm:1; 899 uint64_t pagem:1; 900#endif 901 } s; 902 struct cvmx_mio_boot_reg_timx_s cn30xx; 903 struct cvmx_mio_boot_reg_timx_s cn31xx; 904 struct cvmx_mio_boot_reg_timx_cn38xx { 905#ifdef __BIG_ENDIAN_BITFIELD 906 uint64_t pagem:1; 907 uint64_t waitm:1; 908 uint64_t pages:2; 909 uint64_t reserved_54_59:6; 910 uint64_t page:6; 911 uint64_t wait:6; 912 uint64_t pause:6; 913 uint64_t wr_hld:6; 914 uint64_t rd_hld:6; 915 uint64_t we:6; 916 uint64_t oe:6; 917 uint64_t ce:6; 918 uint64_t adr:6; 919#else 920 uint64_t adr:6; 921 uint64_t ce:6; 922 uint64_t oe:6; 923 uint64_t we:6; 924 uint64_t rd_hld:6; 925 uint64_t wr_hld:6; 926 uint64_t pause:6; 927 uint64_t wait:6; 928 uint64_t page:6; 929 uint64_t reserved_54_59:6; 930 uint64_t pages:2; 931 uint64_t waitm:1; 932 uint64_t pagem:1; 933#endif 934 } cn38xx; 935 struct cvmx_mio_boot_reg_timx_cn38xx cn38xxp2; 936 struct cvmx_mio_boot_reg_timx_s cn50xx; 937 struct cvmx_mio_boot_reg_timx_s cn52xx; 938 struct cvmx_mio_boot_reg_timx_s cn52xxp1; 939 struct cvmx_mio_boot_reg_timx_s cn56xx; 940 struct cvmx_mio_boot_reg_timx_s cn56xxp1; 941 struct cvmx_mio_boot_reg_timx_s cn58xx; 942 struct cvmx_mio_boot_reg_timx_s cn58xxp1; 943 struct cvmx_mio_boot_reg_timx_s cn61xx; 944 struct cvmx_mio_boot_reg_timx_s cn63xx; 945 struct cvmx_mio_boot_reg_timx_s cn63xxp1; 946 struct cvmx_mio_boot_reg_timx_s cn66xx; 947 struct cvmx_mio_boot_reg_timx_s cn68xx; 948 struct cvmx_mio_boot_reg_timx_s cn68xxp1; 949 struct cvmx_mio_boot_reg_timx_s cnf71xx; 950}; 951 952union cvmx_mio_boot_thr { 953 uint64_t u64; 954 struct cvmx_mio_boot_thr_s { 955#ifdef __BIG_ENDIAN_BITFIELD 956 uint64_t reserved_22_63:42; 957 uint64_t dma_thr:6; 958 uint64_t reserved_14_15:2; 959 uint64_t fif_cnt:6; 960 uint64_t reserved_6_7:2; 961 uint64_t fif_thr:6; 962#else 963 uint64_t fif_thr:6; 964 uint64_t reserved_6_7:2; 965 uint64_t fif_cnt:6; 966 uint64_t reserved_14_15:2; 967 uint64_t dma_thr:6; 968 uint64_t reserved_22_63:42; 969#endif 970 } s; 971 struct cvmx_mio_boot_thr_cn30xx { 972#ifdef __BIG_ENDIAN_BITFIELD 973 uint64_t reserved_14_63:50; 974 uint64_t fif_cnt:6; 975 uint64_t reserved_6_7:2; 976 uint64_t fif_thr:6; 977#else 978 uint64_t fif_thr:6; 979 uint64_t reserved_6_7:2; 980 uint64_t fif_cnt:6; 981 uint64_t reserved_14_63:50; 982#endif 983 } cn30xx; 984 struct cvmx_mio_boot_thr_cn30xx cn31xx; 985 struct cvmx_mio_boot_thr_cn30xx cn38xx; 986 struct cvmx_mio_boot_thr_cn30xx cn38xxp2; 987 struct cvmx_mio_boot_thr_cn30xx cn50xx; 988 struct cvmx_mio_boot_thr_s cn52xx; 989 struct cvmx_mio_boot_thr_s cn52xxp1; 990 struct cvmx_mio_boot_thr_s cn56xx; 991 struct cvmx_mio_boot_thr_s cn56xxp1; 992 struct cvmx_mio_boot_thr_cn30xx cn58xx; 993 struct cvmx_mio_boot_thr_cn30xx cn58xxp1; 994 struct cvmx_mio_boot_thr_s cn61xx; 995 struct cvmx_mio_boot_thr_s cn63xx; 996 struct cvmx_mio_boot_thr_s cn63xxp1; 997 struct cvmx_mio_boot_thr_s cn66xx; 998 struct cvmx_mio_boot_thr_s cn68xx; 999 struct cvmx_mio_boot_thr_s cn68xxp1; 1000 struct cvmx_mio_boot_thr_s cnf71xx;
1001}; 1002 1003union cvmx_mio_emm_buf_dat { 1004 uint64_t u64; 1005 struct cvmx_mio_emm_buf_dat_s { 1006#ifdef __BIG_ENDIAN_BITFIELD 1007 uint64_t dat:64; 1008#else 1009 uint64_t dat:64; 1010#endif 1011 } s; 1012 struct cvmx_mio_emm_buf_dat_s cn61xx; 1013 struct cvmx_mio_emm_buf_dat_s cnf71xx; 1014}; 1015 1016union cvmx_mio_emm_buf_idx { 1017 uint64_t u64; 1018 struct cvmx_mio_emm_buf_idx_s { 1019#ifdef __BIG_ENDIAN_BITFIELD 1020 uint64_t reserved_17_63:47; 1021 uint64_t inc:1; 1022 uint64_t reserved_7_15:9; 1023 uint64_t buf_num:1; 1024 uint64_t offset:6; 1025#else 1026 uint64_t offset:6; 1027 uint64_t buf_num:1; 1028 uint64_t reserved_7_15:9; 1029 uint64_t inc:1; 1030 uint64_t reserved_17_63:47; 1031#endif 1032 } s; 1033 struct cvmx_mio_emm_buf_idx_s cn61xx; 1034 struct cvmx_mio_emm_buf_idx_s cnf71xx; 1035}; 1036 1037union cvmx_mio_emm_cfg { 1038 uint64_t u64; 1039 struct cvmx_mio_emm_cfg_s { 1040#ifdef __BIG_ENDIAN_BITFIELD 1041 uint64_t reserved_17_63:47; 1042 uint64_t boot_fail:1; 1043 uint64_t reserved_4_15:12; 1044 uint64_t bus_ena:4; 1045#else 1046 uint64_t bus_ena:4; 1047 uint64_t reserved_4_15:12; 1048 uint64_t boot_fail:1; 1049 uint64_t reserved_17_63:47; 1050#endif 1051 } s; 1052 struct cvmx_mio_emm_cfg_s cn61xx; 1053 struct cvmx_mio_emm_cfg_s cnf71xx; 1054}; 1055 1056union cvmx_mio_emm_cmd { 1057 uint64_t u64; 1058 struct cvmx_mio_emm_cmd_s { 1059#ifdef __BIG_ENDIAN_BITFIELD 1060 uint64_t reserved_62_63:2; 1061 uint64_t bus_id:2; 1062 uint64_t cmd_val:1; 1063 uint64_t reserved_56_58:3; 1064 uint64_t dbuf:1; 1065 uint64_t offset:6; 1066 uint64_t reserved_43_48:6; 1067 uint64_t ctype_xor:2; 1068 uint64_t rtype_xor:3; 1069 uint64_t cmd_idx:6; 1070 uint64_t arg:32; 1071#else 1072 uint64_t arg:32; 1073 uint64_t cmd_idx:6; 1074 uint64_t rtype_xor:3; 1075 uint64_t ctype_xor:2; 1076 uint64_t reserved_43_48:6; 1077 uint64_t offset:6; 1078 uint64_t dbuf:1; 1079 uint64_t reserved_56_58:3; 1080 uint64_t cmd_val:1; 1081 uint64_t bus_id:2; 1082 uint64_t reserved_62_63:2; 1083#endif 1084 } s; 1085 struct cvmx_mio_emm_cmd_s cn61xx; 1086 struct cvmx_mio_emm_cmd_s cnf71xx; 1087}; 1088 1089union cvmx_mio_emm_dma { 1090 uint64_t u64; 1091 struct cvmx_mio_emm_dma_s { 1092#ifdef __BIG_ENDIAN_BITFIELD 1093 uint64_t reserved_62_63:2; 1094 uint64_t bus_id:2; 1095 uint64_t dma_val:1; 1096 uint64_t sector:1; 1097 uint64_t dat_null:1; 1098 uint64_t thres:6; 1099 uint64_t rel_wr:1; 1100 uint64_t rw:1; 1101 uint64_t multi:1; 1102 uint64_t block_cnt:16; 1103 uint64_t card_addr:32; 1104#else 1105 uint64_t card_addr:32; 1106 uint64_t block_cnt:16; 1107 uint64_t multi:1; 1108 uint64_t rw:1; 1109 uint64_t rel_wr:1; 1110 uint64_t thres:6; 1111 uint64_t dat_null:1; 1112 uint64_t sector:1; 1113 uint64_t dma_val:1; 1114 uint64_t bus_id:2; 1115 uint64_t reserved_62_63:2; 1116#endif 1117 } s; 1118 struct cvmx_mio_emm_dma_s cn61xx; 1119 struct cvmx_mio_emm_dma_s cnf71xx; 1120}; 1121 1122union cvmx_mio_emm_int { 1123 uint64_t u64; 1124 struct cvmx_mio_emm_int_s { 1125#ifdef __BIG_ENDIAN_BITFIELD 1126 uint64_t reserved_7_63:57; 1127 uint64_t switch_err:1; 1128 uint64_t switch_done:1; 1129 uint64_t dma_err:1; 1130 uint64_t cmd_err:1; 1131 uint64_t dma_done:1; 1132 uint64_t cmd_done:1; 1133 uint64_t buf_done:1; 1134#else 1135 uint64_t buf_done:1; 1136 uint64_t cmd_done:1; 1137 uint64_t dma_done:1; 1138 uint64_t cmd_err:1; 1139 uint64_t dma_err:1; 1140 uint64_t switch_done:1; 1141 uint64_t switch_err:1; 1142 uint64_t reserved_7_63:57; 1143#endif 1144 } s; 1145 struct cvmx_mio_emm_int_s cn61xx; 1146 struct cvmx_mio_emm_int_s cnf71xx; 1147}; 1148 1149union cvmx_mio_emm_int_en { 1150 uint64_t u64; 1151 struct cvmx_mio_emm_int_en_s { 1152#ifdef __BIG_ENDIAN_BITFIELD 1153 uint64_t reserved_7_63:57; 1154 uint64_t switch_err:1; 1155 uint64_t switch_done:1; 1156 uint64_t dma_err:1; 1157 uint64_t cmd_err:1; 1158 uint64_t dma_done:1; 1159 uint64_t cmd_done:1; 1160 uint64_t buf_done:1; 1161#else 1162 uint64_t buf_done:1; 1163 uint64_t cmd_done:1; 1164 uint64_t dma_done:1; 1165 uint64_t cmd_err:1; 1166 uint64_t dma_err:1; 1167 uint64_t switch_done:1; 1168 uint64_t switch_err:1; 1169 uint64_t reserved_7_63:57; 1170#endif 1171 } s; 1172 struct cvmx_mio_emm_int_en_s cn61xx; 1173 struct cvmx_mio_emm_int_en_s cnf71xx; 1174}; 1175 1176union cvmx_mio_emm_modex { 1177 uint64_t u64; 1178 struct cvmx_mio_emm_modex_s { 1179#ifdef __BIG_ENDIAN_BITFIELD 1180 uint64_t reserved_49_63:15; 1181 uint64_t hs_timing:1; 1182 uint64_t reserved_43_47:5; 1183 uint64_t bus_width:3; 1184 uint64_t reserved_36_39:4; 1185 uint64_t power_class:4; 1186 uint64_t clk_hi:16; 1187 uint64_t clk_lo:16; 1188#else 1189 uint64_t clk_lo:16; 1190 uint64_t clk_hi:16; 1191 uint64_t power_class:4; 1192 uint64_t reserved_36_39:4; 1193 uint64_t bus_width:3; 1194 uint64_t reserved_43_47:5; 1195 uint64_t hs_timing:1; 1196 uint64_t reserved_49_63:15; 1197#endif 1198 } s; 1199 struct cvmx_mio_emm_modex_s cn61xx; 1200 struct cvmx_mio_emm_modex_s cnf71xx; 1201}; 1202 1203union cvmx_mio_emm_rca { 1204 uint64_t u64; 1205 struct cvmx_mio_emm_rca_s { 1206#ifdef __BIG_ENDIAN_BITFIELD 1207 uint64_t reserved_16_63:48; 1208 uint64_t card_rca:16; 1209#else 1210 uint64_t card_rca:16; 1211 uint64_t reserved_16_63:48; 1212#endif 1213 } s; 1214 struct cvmx_mio_emm_rca_s cn61xx; 1215 struct cvmx_mio_emm_rca_s cnf71xx; 1216}; 1217 1218union cvmx_mio_emm_rsp_hi { 1219 uint64_t u64; 1220 struct cvmx_mio_emm_rsp_hi_s { 1221#ifdef __BIG_ENDIAN_BITFIELD 1222 uint64_t dat:64; 1223#else 1224 uint64_t dat:64; 1225#endif 1226 } s; 1227 struct cvmx_mio_emm_rsp_hi_s cn61xx; 1228 struct cvmx_mio_emm_rsp_hi_s cnf71xx; 1229}; 1230 1231union cvmx_mio_emm_rsp_lo { 1232 uint64_t u64; 1233 struct cvmx_mio_emm_rsp_lo_s { 1234#ifdef __BIG_ENDIAN_BITFIELD 1235 uint64_t dat:64; 1236#else 1237 uint64_t dat:64; 1238#endif 1239 } s; 1240 struct cvmx_mio_emm_rsp_lo_s cn61xx; 1241 struct cvmx_mio_emm_rsp_lo_s cnf71xx; 1242}; 1243 1244union cvmx_mio_emm_rsp_sts { 1245 uint64_t u64; 1246 struct cvmx_mio_emm_rsp_sts_s { 1247#ifdef __BIG_ENDIAN_BITFIELD 1248 uint64_t reserved_62_63:2; 1249 uint64_t bus_id:2; 1250 uint64_t cmd_val:1; 1251 uint64_t switch_val:1; 1252 uint64_t dma_val:1; 1253 uint64_t dma_pend:1; 1254 uint64_t reserved_29_55:27; 1255 uint64_t dbuf_err:1; 1256 uint64_t reserved_24_27:4; 1257 uint64_t dbuf:1; 1258 uint64_t blk_timeout:1; 1259 uint64_t blk_crc_err:1; 1260 uint64_t rsp_busybit:1; 1261 uint64_t stp_timeout:1; 1262 uint64_t stp_crc_err:1; 1263 uint64_t stp_bad_sts:1; 1264 uint64_t stp_val:1; 1265 uint64_t rsp_timeout:1; 1266 uint64_t rsp_crc_err:1; 1267 uint64_t rsp_bad_sts:1; 1268 uint64_t rsp_val:1; 1269 uint64_t rsp_type:3; 1270 uint64_t cmd_type:2; 1271 uint64_t cmd_idx:6; 1272 uint64_t cmd_done:1; 1273#else 1274 uint64_t cmd_done:1; 1275 uint64_t cmd_idx:6; 1276 uint64_t cmd_type:2; 1277 uint64_t rsp_type:3; 1278 uint64_t rsp_val:1; 1279 uint64_t rsp_bad_sts:1; 1280 uint64_t rsp_crc_err:1; 1281 uint64_t rsp_timeout:1; 1282 uint64_t stp_val:1; 1283 uint64_t stp_bad_sts:1; 1284 uint64_t stp_crc_err:1; 1285 uint64_t stp_timeout:1; 1286 uint64_t rsp_busybit:1; 1287 uint64_t blk_crc_err:1; 1288 uint64_t blk_timeout:1; 1289 uint64_t dbuf:1; 1290 uint64_t reserved_24_27:4; 1291 uint64_t dbuf_err:1; 1292 uint64_t reserved_29_55:27; 1293 uint64_t dma_pend:1; 1294 uint64_t dma_val:1; 1295 uint64_t switch_val:1; 1296 uint64_t cmd_val:1; 1297 uint64_t bus_id:2; 1298 uint64_t reserved_62_63:2; 1299#endif 1300 } s; 1301 struct cvmx_mio_emm_rsp_sts_s cn61xx; 1302 struct cvmx_mio_emm_rsp_sts_s cnf71xx; 1303}; 1304 1305union cvmx_mio_emm_sample { 1306 uint64_t u64; 1307 struct cvmx_mio_emm_sample_s { 1308#ifdef __BIG_ENDIAN_BITFIELD 1309 uint64_t reserved_26_63:38; 1310 uint64_t cmd_cnt:10; 1311 uint64_t reserved_10_15:6; 1312 uint64_t dat_cnt:10; 1313#else 1314 uint64_t dat_cnt:10; 1315 uint64_t reserved_10_15:6; 1316 uint64_t cmd_cnt:10; 1317 uint64_t reserved_26_63:38; 1318#endif 1319 } s; 1320 struct cvmx_mio_emm_sample_s cn61xx; 1321 struct cvmx_mio_emm_sample_s cnf71xx; 1322}; 1323 1324union cvmx_mio_emm_sts_mask { 1325 uint64_t u64; 1326 struct cvmx_mio_emm_sts_mask_s { 1327#ifdef __BIG_ENDIAN_BITFIELD 1328 uint64_t reserved_32_63:32; 1329 uint64_t sts_msk:32; 1330#else 1331 uint64_t sts_msk:32; 1332 uint64_t reserved_32_63:32; 1333#endif 1334 } s; 1335 struct cvmx_mio_emm_sts_mask_s cn61xx; 1336 struct cvmx_mio_emm_sts_mask_s cnf71xx; 1337}; 1338 1339union cvmx_mio_emm_switch { 1340 uint64_t u64; 1341 struct cvmx_mio_emm_switch_s { 1342#ifdef __BIG_ENDIAN_BITFIELD 1343 uint64_t reserved_62_63:2; 1344 uint64_t bus_id:2; 1345 uint64_t switch_exe:1; 1346 uint64_t switch_err0:1; 1347 uint64_t switch_err1:1; 1348 uint64_t switch_err2:1; 1349 uint64_t reserved_49_55:7; 1350 uint64_t hs_timing:1; 1351 uint64_t reserved_43_47:5; 1352 uint64_t bus_width:3; 1353 uint64_t reserved_36_39:4; 1354 uint64_t power_class:4; 1355 uint64_t clk_hi:16; 1356 uint64_t clk_lo:16; 1357#else 1358 uint64_t clk_lo:16; 1359 uint64_t clk_hi:16; 1360 uint64_t power_class:4; 1361 uint64_t reserved_36_39:4; 1362 uint64_t bus_width:3; 1363 uint64_t reserved_43_47:5; 1364 uint64_t hs_timing:1; 1365 uint64_t reserved_49_55:7; 1366 uint64_t switch_err2:1; 1367 uint64_t switch_err1:1; 1368 uint64_t switch_err0:1; 1369 uint64_t switch_exe:1; 1370 uint64_t bus_id:2; 1371 uint64_t reserved_62_63:2; 1372#endif 1373 } s; 1374 struct cvmx_mio_emm_switch_s cn61xx; 1375 struct cvmx_mio_emm_switch_s cnf71xx; 1376}; 1377 1378union cvmx_mio_emm_wdog { 1379 uint64_t u64; 1380 struct cvmx_mio_emm_wdog_s { 1381#ifdef __BIG_ENDIAN_BITFIELD 1382 uint64_t reserved_26_63:38; 1383 uint64_t clk_cnt:26; 1384#else 1385 uint64_t clk_cnt:26; 1386 uint64_t reserved_26_63:38; 1387#endif 1388 } s; 1389 struct cvmx_mio_emm_wdog_s cn61xx; 1390 struct cvmx_mio_emm_wdog_s cnf71xx; 1391}; 1392 1393union cvmx_mio_fus_bnk_datx { 1394 uint64_t u64; 1395 struct cvmx_mio_fus_bnk_datx_s { 1396#ifdef __BIG_ENDIAN_BITFIELD 1397 uint64_t dat:64; 1398#else 1399 uint64_t dat:64; 1400#endif 1401 } s; 1402 struct cvmx_mio_fus_bnk_datx_s cn50xx; 1403 struct cvmx_mio_fus_bnk_datx_s cn52xx; 1404 struct cvmx_mio_fus_bnk_datx_s cn52xxp1; 1405 struct cvmx_mio_fus_bnk_datx_s cn56xx; 1406 struct cvmx_mio_fus_bnk_datx_s cn56xxp1; 1407 struct cvmx_mio_fus_bnk_datx_s cn58xx; 1408 struct cvmx_mio_fus_bnk_datx_s cn58xxp1; 1409 struct cvmx_mio_fus_bnk_datx_s cn61xx; 1410 struct cvmx_mio_fus_bnk_datx_s cn63xx; 1411 struct cvmx_mio_fus_bnk_datx_s cn63xxp1; 1412 struct cvmx_mio_fus_bnk_datx_s cn66xx; 1413 struct cvmx_mio_fus_bnk_datx_s cn68xx; 1414 struct cvmx_mio_fus_bnk_datx_s cn68xxp1; 1415 struct cvmx_mio_fus_bnk_datx_s cnf71xx; 1416}; 1417 1418union cvmx_mio_fus_dat0 { 1419 uint64_t u64; 1420 struct cvmx_mio_fus_dat0_s { 1421#ifdef __BIG_ENDIAN_BITFIELD 1422 uint64_t reserved_32_63:32; 1423 uint64_t man_info:32; 1424#else 1425 uint64_t man_info:32; 1426 uint64_t reserved_32_63:32; 1427#endif 1428 } s; 1429 struct cvmx_mio_fus_dat0_s cn30xx; 1430 struct cvmx_mio_fus_dat0_s cn31xx; 1431 struct cvmx_mio_fus_dat0_s cn38xx; 1432 struct cvmx_mio_fus_dat0_s cn38xxp2; 1433 struct cvmx_mio_fus_dat0_s cn50xx; 1434 struct cvmx_mio_fus_dat0_s cn52xx; 1435 struct cvmx_mio_fus_dat0_s cn52xxp1; 1436 struct cvmx_mio_fus_dat0_s cn56xx; 1437 struct cvmx_mio_fus_dat0_s cn56xxp1; 1438 struct cvmx_mio_fus_dat0_s cn58xx; 1439 struct cvmx_mio_fus_dat0_s cn58xxp1; 1440 struct cvmx_mio_fus_dat0_s cn61xx; 1441 struct cvmx_mio_fus_dat0_s cn63xx; 1442 struct cvmx_mio_fus_dat0_s cn63xxp1; 1443 struct cvmx_mio_fus_dat0_s cn66xx; 1444 struct cvmx_mio_fus_dat0_s cn68xx; 1445 struct cvmx_mio_fus_dat0_s cn68xxp1; 1446 struct cvmx_mio_fus_dat0_s cnf71xx; 1447}; 1448 1449union cvmx_mio_fus_dat1 { 1450 uint64_t u64; 1451 struct cvmx_mio_fus_dat1_s { 1452#ifdef __BIG_ENDIAN_BITFIELD 1453 uint64_t reserved_32_63:32; 1454 uint64_t man_info:32; 1455#else 1456 uint64_t man_info:32; 1457 uint64_t reserved_32_63:32; 1458#endif 1459 } s; 1460 struct cvmx_mio_fus_dat1_s cn30xx; 1461 struct cvmx_mio_fus_dat1_s cn31xx; 1462 struct cvmx_mio_fus_dat1_s cn38xx; 1463 struct cvmx_mio_fus_dat1_s cn38xxp2; 1464 struct cvmx_mio_fus_dat1_s cn50xx; 1465 struct cvmx_mio_fus_dat1_s cn52xx; 1466 struct cvmx_mio_fus_dat1_s cn52xxp1; 1467 struct cvmx_mio_fus_dat1_s cn56xx; 1468 struct cvmx_mio_fus_dat1_s cn56xxp1; 1469 struct cvmx_mio_fus_dat1_s cn58xx; 1470 struct cvmx_mio_fus_dat1_s cn58xxp1; 1471 struct cvmx_mio_fus_dat1_s cn61xx; 1472 struct cvmx_mio_fus_dat1_s cn63xx; 1473 struct cvmx_mio_fus_dat1_s cn63xxp1; 1474 struct cvmx_mio_fus_dat1_s cn66xx; 1475 struct cvmx_mio_fus_dat1_s cn68xx; 1476 struct cvmx_mio_fus_dat1_s cn68xxp1; 1477 struct cvmx_mio_fus_dat1_s cnf71xx; 1478}; 1479 1480union cvmx_mio_fus_dat2 { 1481 uint64_t u64; 1482 struct cvmx_mio_fus_dat2_s { 1483#ifdef __BIG_ENDIAN_BITFIELD 1484 uint64_t reserved_48_63:16; 1485 uint64_t fus118:1; 1486 uint64_t rom_info:10; 1487 uint64_t power_limit:2; 1488 uint64_t dorm_crypto:1; 1489 uint64_t fus318:1; 1490 uint64_t raid_en:1; 1491 uint64_t reserved_30_31:2; 1492 uint64_t nokasu:1; 1493 uint64_t nodfa_cp2:1; 1494 uint64_t nomul:1; 1495 uint64_t nocrypto:1; 1496 uint64_t rst_sht:1; 1497 uint64_t bist_dis:1; 1498 uint64_t chip_id:8; 1499 uint64_t reserved_0_15:16; 1500#else 1501 uint64_t reserved_0_15:16; 1502 uint64_t chip_id:8; 1503 uint64_t bist_dis:1; 1504 uint64_t rst_sht:1; 1505 uint64_t nocrypto:1; 1506 uint64_t nomul:1; 1507 uint64_t nodfa_cp2:1; 1508 uint64_t nokasu:1; 1509 uint64_t reserved_30_31:2; 1510 uint64_t raid_en:1; 1511 uint64_t fus318:1; 1512 uint64_t dorm_crypto:1; 1513 uint64_t power_limit:2; 1514 uint64_t rom_info:10; 1515 uint64_t fus118:1; 1516 uint64_t reserved_48_63:16; 1517#endif 1518 } s; 1519 struct cvmx_mio_fus_dat2_cn30xx { 1520#ifdef __BIG_ENDIAN_BITFIELD 1521 uint64_t reserved_29_63:35; 1522 uint64_t nodfa_cp2:1; 1523 uint64_t nomul:1; 1524 uint64_t nocrypto:1; 1525 uint64_t rst_sht:1; 1526 uint64_t bist_dis:1; 1527 uint64_t chip_id:8; 1528 uint64_t pll_off:4; 1529 uint64_t reserved_1_11:11; 1530 uint64_t pp_dis:1; 1531#else 1532 uint64_t pp_dis:1; 1533 uint64_t reserved_1_11:11; 1534 uint64_t pll_off:4; 1535 uint64_t chip_id:8; 1536 uint64_t bist_dis:1; 1537 uint64_t rst_sht:1; 1538 uint64_t nocrypto:1; 1539 uint64_t nomul:1; 1540 uint64_t nodfa_cp2:1; 1541 uint64_t reserved_29_63:35; 1542#endif 1543 } cn30xx; 1544 struct cvmx_mio_fus_dat2_cn31xx { 1545#ifdef __BIG_ENDIAN_BITFIELD 1546 uint64_t reserved_29_63:35; 1547 uint64_t nodfa_cp2:1; 1548 uint64_t nomul:1; 1549 uint64_t nocrypto:1; 1550 uint64_t rst_sht:1; 1551 uint64_t bist_dis:1; 1552 uint64_t chip_id:8; 1553 uint64_t pll_off:4; 1554 uint64_t reserved_2_11:10; 1555 uint64_t pp_dis:2; 1556#else 1557 uint64_t pp_dis:2; 1558 uint64_t reserved_2_11:10; 1559 uint64_t pll_off:4; 1560 uint64_t chip_id:8; 1561 uint64_t bist_dis:1; 1562 uint64_t rst_sht:1; 1563 uint64_t nocrypto:1; 1564 uint64_t nomul:1; 1565 uint64_t nodfa_cp2:1; 1566 uint64_t reserved_29_63:35; 1567#endif 1568 } cn31xx; 1569 struct cvmx_mio_fus_dat2_cn38xx { 1570#ifdef __BIG_ENDIAN_BITFIELD 1571 uint64_t reserved_29_63:35; 1572 uint64_t nodfa_cp2:1; 1573 uint64_t nomul:1; 1574 uint64_t nocrypto:1; 1575 uint64_t rst_sht:1; 1576 uint64_t bist_dis:1; 1577 uint64_t chip_id:8; 1578 uint64_t pp_dis:16; 1579#else 1580 uint64_t pp_dis:16; 1581 uint64_t chip_id:8; 1582 uint64_t bist_dis:1; 1583 uint64_t rst_sht:1; 1584 uint64_t nocrypto:1; 1585 uint64_t nomul:1; 1586 uint64_t nodfa_cp2:1; 1587 uint64_t reserved_29_63:35; 1588#endif 1589 } cn38xx; 1590 struct cvmx_mio_fus_dat2_cn38xx cn38xxp2; 1591 struct cvmx_mio_fus_dat2_cn50xx { 1592#ifdef __BIG_ENDIAN_BITFIELD 1593 uint64_t reserved_34_63:30; 1594 uint64_t fus318:1; 1595 uint64_t raid_en:1; 1596 uint64_t reserved_30_31:2; 1597 uint64_t nokasu:1; 1598 uint64_t nodfa_cp2:1; 1599 uint64_t nomul:1; 1600 uint64_t nocrypto:1; 1601 uint64_t rst_sht:1; 1602 uint64_t bist_dis:1; 1603 uint64_t chip_id:8; 1604 uint64_t reserved_2_15:14; 1605 uint64_t pp_dis:2; 1606#else 1607 uint64_t pp_dis:2; 1608 uint64_t reserved_2_15:14; 1609 uint64_t chip_id:8; 1610 uint64_t bist_dis:1; 1611 uint64_t rst_sht:1; 1612 uint64_t nocrypto:1; 1613 uint64_t nomul:1; 1614 uint64_t nodfa_cp2:1; 1615 uint64_t nokasu:1; 1616 uint64_t reserved_30_31:2; 1617 uint64_t raid_en:1; 1618 uint64_t fus318:1; 1619 uint64_t reserved_34_63:30; 1620#endif 1621 } cn50xx; 1622 struct cvmx_mio_fus_dat2_cn52xx { 1623#ifdef __BIG_ENDIAN_BITFIELD 1624 uint64_t reserved_34_63:30; 1625 uint64_t fus318:1; 1626 uint64_t raid_en:1; 1627 uint64_t reserved_30_31:2; 1628 uint64_t nokasu:1; 1629 uint64_t nodfa_cp2:1; 1630 uint64_t nomul:1; 1631 uint64_t nocrypto:1; 1632 uint64_t rst_sht:1; 1633 uint64_t bist_dis:1; 1634 uint64_t chip_id:8; 1635 uint64_t reserved_4_15:12; 1636 uint64_t pp_dis:4; 1637#else 1638 uint64_t pp_dis:4; 1639 uint64_t reserved_4_15:12; 1640 uint64_t chip_id:8; 1641 uint64_t bist_dis:1; 1642 uint64_t rst_sht:1; 1643 uint64_t nocrypto:1; 1644 uint64_t nomul:1; 1645 uint64_t nodfa_cp2:1; 1646 uint64_t nokasu:1; 1647 uint64_t reserved_30_31:2; 1648 uint64_t raid_en:1; 1649 uint64_t fus318:1; 1650 uint64_t reserved_34_63:30; 1651#endif 1652 } cn52xx; 1653 struct cvmx_mio_fus_dat2_cn52xx cn52xxp1; 1654 struct cvmx_mio_fus_dat2_cn56xx { 1655#ifdef __BIG_ENDIAN_BITFIELD 1656 uint64_t reserved_34_63:30; 1657 uint64_t fus318:1; 1658 uint64_t raid_en:1; 1659 uint64_t reserved_30_31:2; 1660 uint64_t nokasu:1; 1661 uint64_t nodfa_cp2:1; 1662 uint64_t nomul:1; 1663 uint64_t nocrypto:1; 1664 uint64_t rst_sht:1; 1665 uint64_t bist_dis:1; 1666 uint64_t chip_id:8; 1667 uint64_t reserved_12_15:4; 1668 uint64_t pp_dis:12; 1669#else 1670 uint64_t pp_dis:12; 1671 uint64_t reserved_12_15:4; 1672 uint64_t chip_id:8; 1673 uint64_t bist_dis:1; 1674 uint64_t rst_sht:1; 1675 uint64_t nocrypto:1; 1676 uint64_t nomul:1; 1677 uint64_t nodfa_cp2:1; 1678 uint64_t nokasu:1; 1679 uint64_t reserved_30_31:2; 1680 uint64_t raid_en:1; 1681 uint64_t fus318:1; 1682 uint64_t reserved_34_63:30; 1683#endif 1684 } cn56xx; 1685 struct cvmx_mio_fus_dat2_cn56xx cn56xxp1; 1686 struct cvmx_mio_fus_dat2_cn58xx { 1687#ifdef __BIG_ENDIAN_BITFIELD 1688 uint64_t reserved_30_63:34; 1689 uint64_t nokasu:1; 1690 uint64_t nodfa_cp2:1; 1691 uint64_t nomul:1; 1692 uint64_t nocrypto:1; 1693 uint64_t rst_sht:1; 1694 uint64_t bist_dis:1; 1695 uint64_t chip_id:8; 1696 uint64_t pp_dis:16; 1697#else 1698 uint64_t pp_dis:16; 1699 uint64_t chip_id:8; 1700 uint64_t bist_dis:1; 1701 uint64_t rst_sht:1; 1702 uint64_t nocrypto:1; 1703 uint64_t nomul:1; 1704 uint64_t nodfa_cp2:1; 1705 uint64_t nokasu:1; 1706 uint64_t reserved_30_63:34; 1707#endif 1708 } cn58xx; 1709 struct cvmx_mio_fus_dat2_cn58xx cn58xxp1; 1710 struct cvmx_mio_fus_dat2_cn61xx { 1711#ifdef __BIG_ENDIAN_BITFIELD 1712 uint64_t reserved_48_63:16; 1713 uint64_t fus118:1; 1714 uint64_t rom_info:10; 1715 uint64_t power_limit:2; 1716 uint64_t dorm_crypto:1; 1717 uint64_t fus318:1; 1718 uint64_t raid_en:1; 1719 uint64_t reserved_29_31:3; 1720 uint64_t nodfa_cp2:1; 1721 uint64_t nomul:1; 1722 uint64_t nocrypto:1; 1723 uint64_t reserved_24_25:2; 1724 uint64_t chip_id:8; 1725 uint64_t reserved_4_15:12; 1726 uint64_t pp_dis:4; 1727#else 1728 uint64_t pp_dis:4; 1729 uint64_t reserved_4_15:12; 1730 uint64_t chip_id:8; 1731 uint64_t reserved_24_25:2; 1732 uint64_t nocrypto:1; 1733 uint64_t nomul:1; 1734 uint64_t nodfa_cp2:1; 1735 uint64_t reserved_29_31:3; 1736 uint64_t raid_en:1; 1737 uint64_t fus318:1; 1738 uint64_t dorm_crypto:1; 1739 uint64_t power_limit:2; 1740 uint64_t rom_info:10; 1741 uint64_t fus118:1; 1742 uint64_t reserved_48_63:16; 1743#endif 1744 } cn61xx; 1745 struct cvmx_mio_fus_dat2_cn63xx { 1746#ifdef __BIG_ENDIAN_BITFIELD 1747 uint64_t reserved_35_63:29; 1748 uint64_t dorm_crypto:1; 1749 uint64_t fus318:1; 1750 uint64_t raid_en:1; 1751 uint64_t reserved_29_31:3; 1752 uint64_t nodfa_cp2:1; 1753 uint64_t nomul:1; 1754 uint64_t nocrypto:1; 1755 uint64_t reserved_24_25:2; 1756 uint64_t chip_id:8; 1757 uint64_t reserved_6_15:10; 1758 uint64_t pp_dis:6; 1759#else 1760 uint64_t pp_dis:6; 1761 uint64_t reserved_6_15:10; 1762 uint64_t chip_id:8; 1763 uint64_t reserved_24_25:2; 1764 uint64_t nocrypto:1; 1765 uint64_t nomul:1; 1766 uint64_t nodfa_cp2:1; 1767 uint64_t reserved_29_31:3; 1768 uint64_t raid_en:1; 1769 uint64_t fus318:1; 1770 uint64_t dorm_crypto:1; 1771 uint64_t reserved_35_63:29; 1772#endif 1773 } cn63xx; 1774 struct cvmx_mio_fus_dat2_cn63xx cn63xxp1; 1775 struct cvmx_mio_fus_dat2_cn66xx { 1776#ifdef __BIG_ENDIAN_BITFIELD 1777 uint64_t reserved_48_63:16; 1778 uint64_t fus118:1; 1779 uint64_t rom_info:10; 1780 uint64_t power_limit:2; 1781 uint64_t dorm_crypto:1; 1782 uint64_t fus318:1; 1783 uint64_t raid_en:1; 1784 uint64_t reserved_29_31:3; 1785 uint64_t nodfa_cp2:1; 1786 uint64_t nomul:1; 1787 uint64_t nocrypto:1; 1788 uint64_t reserved_24_25:2; 1789 uint64_t chip_id:8; 1790 uint64_t reserved_10_15:6; 1791 uint64_t pp_dis:10; 1792#else 1793 uint64_t pp_dis:10; 1794 uint64_t reserved_10_15:6; 1795 uint64_t chip_id:8; 1796 uint64_t reserved_24_25:2; 1797 uint64_t nocrypto:1; 1798 uint64_t nomul:1; 1799 uint64_t nodfa_cp2:1; 1800 uint64_t reserved_29_31:3; 1801 uint64_t raid_en:1; 1802 uint64_t fus318:1; 1803 uint64_t dorm_crypto:1; 1804 uint64_t power_limit:2; 1805 uint64_t rom_info:10; 1806 uint64_t fus118:1; 1807 uint64_t reserved_48_63:16; 1808#endif 1809 } cn66xx; 1810 struct cvmx_mio_fus_dat2_cn68xx { 1811#ifdef __BIG_ENDIAN_BITFIELD 1812 uint64_t reserved_37_63:27; 1813 uint64_t power_limit:2; 1814 uint64_t dorm_crypto:1; 1815 uint64_t fus318:1; 1816 uint64_t raid_en:1; 1817 uint64_t reserved_29_31:3; 1818 uint64_t nodfa_cp2:1; 1819 uint64_t nomul:1; 1820 uint64_t nocrypto:1; 1821 uint64_t reserved_24_25:2; 1822 uint64_t chip_id:8; 1823 uint64_t reserved_0_15:16; 1824#else 1825 uint64_t reserved_0_15:16; 1826 uint64_t chip_id:8; 1827 uint64_t reserved_24_25:2; 1828 uint64_t nocrypto:1; 1829 uint64_t nomul:1; 1830 uint64_t nodfa_cp2:1; 1831 uint64_t reserved_29_31:3; 1832 uint64_t raid_en:1; 1833 uint64_t fus318:1; 1834 uint64_t dorm_crypto:1; 1835 uint64_t power_limit:2; 1836 uint64_t reserved_37_63:27; 1837#endif 1838 } cn68xx; 1839 struct cvmx_mio_fus_dat2_cn68xx cn68xxp1; 1840 struct cvmx_mio_fus_dat2_cn61xx cnf71xx; 1841}; 1842 1843union cvmx_mio_fus_dat3 { 1844 uint64_t u64; 1845 struct cvmx_mio_fus_dat3_s { 1846#ifdef __BIG_ENDIAN_BITFIELD 1847 uint64_t reserved_58_63:6; 1848 uint64_t pll_ctl:10; 1849 uint64_t dfa_info_dte:3; 1850 uint64_t dfa_info_clm:4; 1851 uint64_t reserved_40_40:1; 1852 uint64_t ema:2; 1853 uint64_t efus_lck_rsv:1; 1854 uint64_t efus_lck_man:1; 1855 uint64_t pll_half_dis:1; 1856 uint64_t l2c_crip:3; 1857 uint64_t pll_div4:1; 1858 uint64_t reserved_29_30:2; 1859 uint64_t bar2_en:1; 1860 uint64_t efus_lck:1; 1861 uint64_t efus_ign:1; 1862 uint64_t nozip:1; 1863 uint64_t nodfa_dte:1; 1864 uint64_t icache:24; 1865#else 1866 uint64_t icache:24; 1867 uint64_t nodfa_dte:1; 1868 uint64_t nozip:1; 1869 uint64_t efus_ign:1; 1870 uint64_t efus_lck:1; 1871 uint64_t bar2_en:1; 1872 uint64_t reserved_29_30:2; 1873 uint64_t pll_div4:1; 1874 uint64_t l2c_crip:3; 1875 uint64_t pll_half_dis:1; 1876 uint64_t efus_lck_man:1; 1877 uint64_t efus_lck_rsv:1; 1878 uint64_t ema:2; 1879 uint64_t reserved_40_40:1; 1880 uint64_t dfa_info_clm:4; 1881 uint64_t dfa_info_dte:3; 1882 uint64_t pll_ctl:10; 1883 uint64_t reserved_58_63:6; 1884#endif 1885 } s; 1886 struct cvmx_mio_fus_dat3_cn30xx { 1887#ifdef __BIG_ENDIAN_BITFIELD 1888 uint64_t reserved_32_63:32; 1889 uint64_t pll_div4:1; 1890 uint64_t reserved_29_30:2; 1891 uint64_t bar2_en:1; 1892 uint64_t efus_lck:1; 1893 uint64_t efus_ign:1; 1894 uint64_t nozip:1; 1895 uint64_t nodfa_dte:1; 1896 uint64_t icache:24; 1897#else 1898 uint64_t icache:24; 1899 uint64_t nodfa_dte:1; 1900 uint64_t nozip:1; 1901 uint64_t efus_ign:1; 1902 uint64_t efus_lck:1; 1903 uint64_t bar2_en:1; 1904 uint64_t reserved_29_30:2; 1905 uint64_t pll_div4:1; 1906 uint64_t reserved_32_63:32; 1907#endif 1908 } cn30xx; 1909 struct cvmx_mio_fus_dat3_cn31xx { 1910#ifdef __BIG_ENDIAN_BITFIELD 1911 uint64_t reserved_32_63:32; 1912 uint64_t pll_div4:1; 1913 uint64_t zip_crip:2; 1914 uint64_t bar2_en:1; 1915 uint64_t efus_lck:1; 1916 uint64_t efus_ign:1; 1917 uint64_t nozip:1; 1918 uint64_t nodfa_dte:1; 1919 uint64_t icache:24; 1920#else 1921 uint64_t icache:24; 1922 uint64_t nodfa_dte:1; 1923 uint64_t nozip:1; 1924 uint64_t efus_ign:1; 1925 uint64_t efus_lck:1; 1926 uint64_t bar2_en:1; 1927 uint64_t zip_crip:2; 1928 uint64_t pll_div4:1; 1929 uint64_t reserved_32_63:32; 1930#endif 1931 } cn31xx; 1932 struct cvmx_mio_fus_dat3_cn38xx { 1933#ifdef __BIG_ENDIAN_BITFIELD 1934 uint64_t reserved_31_63:33; 1935 uint64_t zip_crip:2; 1936 uint64_t bar2_en:1; 1937 uint64_t efus_lck:1; 1938 uint64_t efus_ign:1; 1939 uint64_t nozip:1; 1940 uint64_t nodfa_dte:1; 1941 uint64_t icache:24; 1942#else 1943 uint64_t icache:24; 1944 uint64_t nodfa_dte:1; 1945 uint64_t nozip:1; 1946 uint64_t efus_ign:1; 1947 uint64_t efus_lck:1; 1948 uint64_t bar2_en:1; 1949 uint64_t zip_crip:2; 1950 uint64_t reserved_31_63:33; 1951#endif 1952 } cn38xx; 1953 struct cvmx_mio_fus_dat3_cn38xxp2 { 1954#ifdef __BIG_ENDIAN_BITFIELD 1955 uint64_t reserved_29_63:35; 1956 uint64_t bar2_en:1; 1957 uint64_t efus_lck:1; 1958 uint64_t efus_ign:1; 1959 uint64_t nozip:1; 1960 uint64_t nodfa_dte:1; 1961 uint64_t icache:24; 1962#else 1963 uint64_t icache:24; 1964 uint64_t nodfa_dte:1; 1965 uint64_t nozip:1; 1966 uint64_t efus_ign:1; 1967 uint64_t efus_lck:1; 1968 uint64_t bar2_en:1; 1969 uint64_t reserved_29_63:35; 1970#endif 1971 } cn38xxp2; 1972 struct cvmx_mio_fus_dat3_cn38xx cn50xx; 1973 struct cvmx_mio_fus_dat3_cn38xx cn52xx; 1974 struct cvmx_mio_fus_dat3_cn38xx cn52xxp1; 1975 struct cvmx_mio_fus_dat3_cn38xx cn56xx; 1976 struct cvmx_mio_fus_dat3_cn38xx cn56xxp1; 1977 struct cvmx_mio_fus_dat3_cn38xx cn58xx; 1978 struct cvmx_mio_fus_dat3_cn38xx cn58xxp1; 1979 struct cvmx_mio_fus_dat3_cn61xx { 1980#ifdef __BIG_ENDIAN_BITFIELD 1981 uint64_t reserved_58_63:6; 1982 uint64_t pll_ctl:10; 1983 uint64_t dfa_info_dte:3; 1984 uint64_t dfa_info_clm:4; 1985 uint64_t reserved_40_40:1; 1986 uint64_t ema:2; 1987 uint64_t efus_lck_rsv:1; 1988 uint64_t efus_lck_man:1; 1989 uint64_t pll_half_dis:1; 1990 uint64_t l2c_crip:3; 1991 uint64_t reserved_31_31:1; 1992 uint64_t zip_info:2; 1993 uint64_t bar2_en:1; 1994 uint64_t efus_lck:1; 1995 uint64_t efus_ign:1; 1996 uint64_t nozip:1; 1997 uint64_t nodfa_dte:1; 1998 uint64_t reserved_0_23:24; 1999#else 2000 uint64_t reserved_0_23:24;
2001 uint64_t nodfa_dte:1; 2002 uint64_t nozip:1; 2003 uint64_t efus_ign:1; 2004 uint64_t efus_lck:1; 2005 uint64_t bar2_en:1; 2006 uint64_t zip_info:2; 2007 uint64_t reserved_31_31:1; 2008 uint64_t l2c_crip:3; 2009 uint64_t pll_half_dis:1; 2010 uint64_t efus_lck_man:1; 2011 uint64_t efus_lck_rsv:1; 2012 uint64_t ema:2; 2013 uint64_t reserved_40_40:1; 2014 uint64_t dfa_info_clm:4; 2015 uint64_t dfa_info_dte:3; 2016 uint64_t pll_ctl:10; 2017 uint64_t reserved_58_63:6; 2018#endif 2019 } cn61xx; 2020 struct cvmx_mio_fus_dat3_cn61xx cn63xx; 2021 struct cvmx_mio_fus_dat3_cn61xx cn63xxp1; 2022 struct cvmx_mio_fus_dat3_cn61xx cn66xx; 2023 struct cvmx_mio_fus_dat3_cn61xx cn68xx; 2024 struct cvmx_mio_fus_dat3_cn61xx cn68xxp1; 2025 struct cvmx_mio_fus_dat3_cn61xx cnf71xx; 2026}; 2027 2028union cvmx_mio_fus_ema { 2029 uint64_t u64; 2030 struct cvmx_mio_fus_ema_s { 2031#ifdef __BIG_ENDIAN_BITFIELD 2032 uint64_t reserved_7_63:57; 2033 uint64_t eff_ema:3; 2034 uint64_t reserved_3_3:1; 2035 uint64_t ema:3; 2036#else 2037 uint64_t ema:3; 2038 uint64_t reserved_3_3:1; 2039 uint64_t eff_ema:3; 2040 uint64_t reserved_7_63:57; 2041#endif 2042 } s; 2043 struct cvmx_mio_fus_ema_s cn50xx; 2044 struct cvmx_mio_fus_ema_s cn52xx; 2045 struct cvmx_mio_fus_ema_s cn52xxp1; 2046 struct cvmx_mio_fus_ema_s cn56xx; 2047 struct cvmx_mio_fus_ema_s cn56xxp1; 2048 struct cvmx_mio_fus_ema_cn58xx { 2049#ifdef __BIG_ENDIAN_BITFIELD 2050 uint64_t reserved_2_63:62; 2051 uint64_t ema:2; 2052#else 2053 uint64_t ema:2; 2054 uint64_t reserved_2_63:62; 2055#endif 2056 } cn58xx; 2057 struct cvmx_mio_fus_ema_cn58xx cn58xxp1; 2058 struct cvmx_mio_fus_ema_s cn61xx; 2059 struct cvmx_mio_fus_ema_s cn63xx; 2060 struct cvmx_mio_fus_ema_s cn63xxp1; 2061 struct cvmx_mio_fus_ema_s cn66xx; 2062 struct cvmx_mio_fus_ema_s cn68xx; 2063 struct cvmx_mio_fus_ema_s cn68xxp1; 2064 struct cvmx_mio_fus_ema_s cnf71xx; 2065}; 2066 2067union cvmx_mio_fus_pdf { 2068 uint64_t u64; 2069 struct cvmx_mio_fus_pdf_s { 2070#ifdef __BIG_ENDIAN_BITFIELD 2071 uint64_t pdf:64; 2072#else 2073 uint64_t pdf:64; 2074#endif 2075 } s; 2076 struct cvmx_mio_fus_pdf_s cn50xx; 2077 struct cvmx_mio_fus_pdf_s cn52xx; 2078 struct cvmx_mio_fus_pdf_s cn52xxp1; 2079 struct cvmx_mio_fus_pdf_s cn56xx; 2080 struct cvmx_mio_fus_pdf_s cn56xxp1; 2081 struct cvmx_mio_fus_pdf_s cn58xx; 2082 struct cvmx_mio_fus_pdf_s cn61xx; 2083 struct cvmx_mio_fus_pdf_s cn63xx; 2084 struct cvmx_mio_fus_pdf_s cn63xxp1; 2085 struct cvmx_mio_fus_pdf_s cn66xx; 2086 struct cvmx_mio_fus_pdf_s cn68xx; 2087 struct cvmx_mio_fus_pdf_s cn68xxp1; 2088 struct cvmx_mio_fus_pdf_s cnf71xx; 2089}; 2090 2091union cvmx_mio_fus_pll { 2092 uint64_t u64; 2093 struct cvmx_mio_fus_pll_s { 2094#ifdef __BIG_ENDIAN_BITFIELD 2095 uint64_t reserved_48_63:16; 2096 uint64_t rclk_align_r:8; 2097 uint64_t rclk_align_l:8; 2098 uint64_t reserved_8_31:24; 2099 uint64_t c_cout_rst:1; 2100 uint64_t c_cout_sel:2; 2101 uint64_t pnr_cout_rst:1; 2102 uint64_t pnr_cout_sel:2; 2103 uint64_t rfslip:1; 2104 uint64_t fbslip:1; 2105#else 2106 uint64_t fbslip:1; 2107 uint64_t rfslip:1; 2108 uint64_t pnr_cout_sel:2; 2109 uint64_t pnr_cout_rst:1; 2110 uint64_t c_cout_sel:2; 2111 uint64_t c_cout_rst:1; 2112 uint64_t reserved_8_31:24; 2113 uint64_t rclk_align_l:8; 2114 uint64_t rclk_align_r:8; 2115 uint64_t reserved_48_63:16; 2116#endif 2117 } s; 2118 struct cvmx_mio_fus_pll_cn50xx { 2119#ifdef __BIG_ENDIAN_BITFIELD 2120 uint64_t reserved_2_63:62; 2121 uint64_t rfslip:1; 2122 uint64_t fbslip:1; 2123#else 2124 uint64_t fbslip:1; 2125 uint64_t rfslip:1; 2126 uint64_t reserved_2_63:62; 2127#endif 2128 } cn50xx; 2129 struct cvmx_mio_fus_pll_cn50xx cn52xx; 2130 struct cvmx_mio_fus_pll_cn50xx cn52xxp1; 2131 struct cvmx_mio_fus_pll_cn50xx cn56xx; 2132 struct cvmx_mio_fus_pll_cn50xx cn56xxp1; 2133 struct cvmx_mio_fus_pll_cn50xx cn58xx; 2134 struct cvmx_mio_fus_pll_cn50xx cn58xxp1; 2135 struct cvmx_mio_fus_pll_cn61xx { 2136#ifdef __BIG_ENDIAN_BITFIELD 2137 uint64_t reserved_8_63:56; 2138 uint64_t c_cout_rst:1; 2139 uint64_t c_cout_sel:2; 2140 uint64_t pnr_cout_rst:1; 2141 uint64_t pnr_cout_sel:2; 2142 uint64_t rfslip:1; 2143 uint64_t fbslip:1; 2144#else 2145 uint64_t fbslip:1; 2146 uint64_t rfslip:1; 2147 uint64_t pnr_cout_sel:2; 2148 uint64_t pnr_cout_rst:1; 2149 uint64_t c_cout_sel:2; 2150 uint64_t c_cout_rst:1; 2151 uint64_t reserved_8_63:56; 2152#endif 2153 } cn61xx; 2154 struct cvmx_mio_fus_pll_cn61xx cn63xx; 2155 struct cvmx_mio_fus_pll_cn61xx cn63xxp1; 2156 struct cvmx_mio_fus_pll_cn61xx cn66xx; 2157 struct cvmx_mio_fus_pll_s cn68xx; 2158 struct cvmx_mio_fus_pll_s cn68xxp1; 2159 struct cvmx_mio_fus_pll_cn61xx cnf71xx; 2160}; 2161 2162union cvmx_mio_fus_prog { 2163 uint64_t u64; 2164 struct cvmx_mio_fus_prog_s { 2165#ifdef __BIG_ENDIAN_BITFIELD 2166 uint64_t reserved_2_63:62; 2167 uint64_t soft:1; 2168 uint64_t prog:1; 2169#else 2170 uint64_t prog:1; 2171 uint64_t soft:1; 2172 uint64_t reserved_2_63:62; 2173#endif 2174 } s; 2175 struct cvmx_mio_fus_prog_cn30xx { 2176#ifdef __BIG_ENDIAN_BITFIELD 2177 uint64_t reserved_1_63:63; 2178 uint64_t prog:1; 2179#else 2180 uint64_t prog:1; 2181 uint64_t reserved_1_63:63; 2182#endif 2183 } cn30xx; 2184 struct cvmx_mio_fus_prog_cn30xx cn31xx; 2185 struct cvmx_mio_fus_prog_cn30xx cn38xx; 2186 struct cvmx_mio_fus_prog_cn30xx cn38xxp2; 2187 struct cvmx_mio_fus_prog_cn30xx cn50xx; 2188 struct cvmx_mio_fus_prog_cn30xx cn52xx; 2189 struct cvmx_mio_fus_prog_cn30xx cn52xxp1; 2190 struct cvmx_mio_fus_prog_cn30xx cn56xx; 2191 struct cvmx_mio_fus_prog_cn30xx cn56xxp1; 2192 struct cvmx_mio_fus_prog_cn30xx cn58xx; 2193 struct cvmx_mio_fus_prog_cn30xx cn58xxp1; 2194 struct cvmx_mio_fus_prog_s cn61xx; 2195 struct cvmx_mio_fus_prog_s cn63xx; 2196 struct cvmx_mio_fus_prog_s cn63xxp1; 2197 struct cvmx_mio_fus_prog_s cn66xx; 2198 struct cvmx_mio_fus_prog_s cn68xx; 2199 struct cvmx_mio_fus_prog_s cn68xxp1; 2200 struct cvmx_mio_fus_prog_s cnf71xx; 2201}; 2202 2203union cvmx_mio_fus_prog_times { 2204 uint64_t u64; 2205 struct cvmx_mio_fus_prog_times_s { 2206#ifdef __BIG_ENDIAN_BITFIELD 2207 uint64_t reserved_35_63:29; 2208 uint64_t vgate_pin:1; 2209 uint64_t fsrc_pin:1; 2210 uint64_t prog_pin:1; 2211 uint64_t reserved_6_31:26; 2212 uint64_t setup:6; 2213#else 2214 uint64_t setup:6; 2215 uint64_t reserved_6_31:26; 2216 uint64_t prog_pin:1; 2217 uint64_t fsrc_pin:1; 2218 uint64_t vgate_pin:1; 2219 uint64_t reserved_35_63:29; 2220#endif 2221 } s; 2222 struct cvmx_mio_fus_prog_times_cn50xx { 2223#ifdef __BIG_ENDIAN_BITFIELD 2224 uint64_t reserved_33_63:31; 2225 uint64_t prog_pin:1; 2226 uint64_t out:8; 2227 uint64_t sclk_lo:4; 2228 uint64_t sclk_hi:12; 2229 uint64_t setup:8; 2230#else 2231 uint64_t setup:8; 2232 uint64_t sclk_hi:12; 2233 uint64_t sclk_lo:4; 2234 uint64_t out:8; 2235 uint64_t prog_pin:1; 2236 uint64_t reserved_33_63:31; 2237#endif 2238 } cn50xx; 2239 struct cvmx_mio_fus_prog_times_cn50xx cn52xx; 2240 struct cvmx_mio_fus_prog_times_cn50xx cn52xxp1; 2241 struct cvmx_mio_fus_prog_times_cn50xx cn56xx; 2242 struct cvmx_mio_fus_prog_times_cn50xx cn56xxp1; 2243 struct cvmx_mio_fus_prog_times_cn50xx cn58xx; 2244 struct cvmx_mio_fus_prog_times_cn50xx cn58xxp1; 2245 struct cvmx_mio_fus_prog_times_cn61xx { 2246#ifdef __BIG_ENDIAN_BITFIELD 2247 uint64_t reserved_35_63:29; 2248 uint64_t vgate_pin:1; 2249 uint64_t fsrc_pin:1; 2250 uint64_t prog_pin:1; 2251 uint64_t out:7; 2252 uint64_t sclk_lo:4; 2253 uint64_t sclk_hi:15; 2254 uint64_t setup:6; 2255#else 2256 uint64_t setup:6; 2257 uint64_t sclk_hi:15; 2258 uint64_t sclk_lo:4; 2259 uint64_t out:7; 2260 uint64_t prog_pin:1; 2261 uint64_t fsrc_pin:1; 2262 uint64_t vgate_pin:1; 2263 uint64_t reserved_35_63:29; 2264#endif 2265 } cn61xx; 2266 struct cvmx_mio_fus_prog_times_cn61xx cn63xx; 2267 struct cvmx_mio_fus_prog_times_cn61xx cn63xxp1; 2268 struct cvmx_mio_fus_prog_times_cn61xx cn66xx; 2269 struct cvmx_mio_fus_prog_times_cn61xx cn68xx; 2270 struct cvmx_mio_fus_prog_times_cn61xx cn68xxp1; 2271 struct cvmx_mio_fus_prog_times_cn61xx cnf71xx; 2272}; 2273 2274union cvmx_mio_fus_rcmd { 2275 uint64_t u64; 2276 struct cvmx_mio_fus_rcmd_s { 2277#ifdef __BIG_ENDIAN_BITFIELD 2278 uint64_t reserved_24_63:40; 2279 uint64_t dat:8; 2280 uint64_t reserved_13_15:3; 2281 uint64_t pend:1; 2282 uint64_t reserved_9_11:3; 2283 uint64_t efuse:1; 2284 uint64_t addr:8; 2285#else 2286 uint64_t addr:8; 2287 uint64_t efuse:1; 2288 uint64_t reserved_9_11:3; 2289 uint64_t pend:1; 2290 uint64_t reserved_13_15:3; 2291 uint64_t dat:8; 2292 uint64_t reserved_24_63:40; 2293#endif 2294 } s; 2295 struct cvmx_mio_fus_rcmd_cn30xx { 2296#ifdef __BIG_ENDIAN_BITFIELD 2297 uint64_t reserved_24_63:40; 2298 uint64_t dat:8; 2299 uint64_t reserved_13_15:3; 2300 uint64_t pend:1; 2301 uint64_t reserved_9_11:3; 2302 uint64_t efuse:1; 2303 uint64_t reserved_7_7:1; 2304 uint64_t addr:7; 2305#else 2306 uint64_t addr:7; 2307 uint64_t reserved_7_7:1; 2308 uint64_t efuse:1; 2309 uint64_t reserved_9_11:3; 2310 uint64_t pend:1; 2311 uint64_t reserved_13_15:3; 2312 uint64_t dat:8; 2313 uint64_t reserved_24_63:40; 2314#endif 2315 } cn30xx; 2316 struct cvmx_mio_fus_rcmd_cn30xx cn31xx; 2317 struct cvmx_mio_fus_rcmd_cn30xx cn38xx; 2318 struct cvmx_mio_fus_rcmd_cn30xx cn38xxp2; 2319 struct cvmx_mio_fus_rcmd_cn30xx cn50xx; 2320 struct cvmx_mio_fus_rcmd_s cn52xx; 2321 struct cvmx_mio_fus_rcmd_s cn52xxp1; 2322 struct cvmx_mio_fus_rcmd_s cn56xx; 2323 struct cvmx_mio_fus_rcmd_s cn56xxp1; 2324 struct cvmx_mio_fus_rcmd_cn30xx cn58xx; 2325 struct cvmx_mio_fus_rcmd_cn30xx cn58xxp1; 2326 struct cvmx_mio_fus_rcmd_s cn61xx; 2327 struct cvmx_mio_fus_rcmd_s cn63xx; 2328 struct cvmx_mio_fus_rcmd_s cn63xxp1; 2329 struct cvmx_mio_fus_rcmd_s cn66xx; 2330 struct cvmx_mio_fus_rcmd_s cn68xx; 2331 struct cvmx_mio_fus_rcmd_s cn68xxp1; 2332 struct cvmx_mio_fus_rcmd_s cnf71xx; 2333}; 2334 2335union cvmx_mio_fus_read_times { 2336 uint64_t u64; 2337 struct cvmx_mio_fus_read_times_s { 2338#ifdef __BIG_ENDIAN_BITFIELD 2339 uint64_t reserved_26_63:38; 2340 uint64_t sch:4; 2341 uint64_t fsh:4; 2342 uint64_t prh:4; 2343 uint64_t sdh:4; 2344 uint64_t setup:10; 2345#else 2346 uint64_t setup:10; 2347 uint64_t sdh:4; 2348 uint64_t prh:4; 2349 uint64_t fsh:4; 2350 uint64_t sch:4; 2351 uint64_t reserved_26_63:38; 2352#endif 2353 } s; 2354 struct cvmx_mio_fus_read_times_s cn61xx; 2355 struct cvmx_mio_fus_read_times_s cn63xx; 2356 struct cvmx_mio_fus_read_times_s cn63xxp1; 2357 struct cvmx_mio_fus_read_times_s cn66xx; 2358 struct cvmx_mio_fus_read_times_s cn68xx; 2359 struct cvmx_mio_fus_read_times_s cn68xxp1; 2360 struct cvmx_mio_fus_read_times_s cnf71xx; 2361}; 2362 2363union cvmx_mio_fus_repair_res0 { 2364 uint64_t u64; 2365 struct cvmx_mio_fus_repair_res0_s { 2366#ifdef __BIG_ENDIAN_BITFIELD 2367 uint64_t reserved_55_63:9; 2368 uint64_t too_many:1; 2369 uint64_t repair2:18; 2370 uint64_t repair1:18; 2371 uint64_t repair0:18; 2372#else 2373 uint64_t repair0:18; 2374 uint64_t repair1:18; 2375 uint64_t repair2:18; 2376 uint64_t too_many:1; 2377 uint64_t reserved_55_63:9; 2378#endif 2379 } s; 2380 struct cvmx_mio_fus_repair_res0_s cn61xx; 2381 struct cvmx_mio_fus_repair_res0_s cn63xx; 2382 struct cvmx_mio_fus_repair_res0_s cn63xxp1; 2383 struct cvmx_mio_fus_repair_res0_s cn66xx; 2384 struct cvmx_mio_fus_repair_res0_s cn68xx; 2385 struct cvmx_mio_fus_repair_res0_s cn68xxp1; 2386 struct cvmx_mio_fus_repair_res0_s cnf71xx; 2387}; 2388 2389union cvmx_mio_fus_repair_res1 { 2390 uint64_t u64; 2391 struct cvmx_mio_fus_repair_res1_s { 2392#ifdef __BIG_ENDIAN_BITFIELD 2393 uint64_t reserved_54_63:10; 2394 uint64_t repair5:18; 2395 uint64_t repair4:18; 2396 uint64_t repair3:18; 2397#else 2398 uint64_t repair3:18; 2399 uint64_t repair4:18; 2400 uint64_t repair5:18; 2401 uint64_t reserved_54_63:10; 2402#endif 2403 } s; 2404 struct cvmx_mio_fus_repair_res1_s cn61xx; 2405 struct cvmx_mio_fus_repair_res1_s cn63xx; 2406 struct cvmx_mio_fus_repair_res1_s cn63xxp1; 2407 struct cvmx_mio_fus_repair_res1_s cn66xx; 2408 struct cvmx_mio_fus_repair_res1_s cn68xx; 2409 struct cvmx_mio_fus_repair_res1_s cn68xxp1; 2410 struct cvmx_mio_fus_repair_res1_s cnf71xx; 2411}; 2412 2413union cvmx_mio_fus_repair_res2 { 2414 uint64_t u64; 2415 struct cvmx_mio_fus_repair_res2_s { 2416#ifdef __BIG_ENDIAN_BITFIELD 2417 uint64_t reserved_18_63:46; 2418 uint64_t repair6:18; 2419#else 2420 uint64_t repair6:18; 2421 uint64_t reserved_18_63:46; 2422#endif 2423 } s; 2424 struct cvmx_mio_fus_repair_res2_s cn61xx; 2425 struct cvmx_mio_fus_repair_res2_s cn63xx; 2426 struct cvmx_mio_fus_repair_res2_s cn63xxp1; 2427 struct cvmx_mio_fus_repair_res2_s cn66xx; 2428 struct cvmx_mio_fus_repair_res2_s cn68xx; 2429 struct cvmx_mio_fus_repair_res2_s cn68xxp1; 2430 struct cvmx_mio_fus_repair_res2_s cnf71xx; 2431}; 2432 2433union cvmx_mio_fus_spr_repair_res { 2434 uint64_t u64; 2435 struct cvmx_mio_fus_spr_repair_res_s { 2436#ifdef __BIG_ENDIAN_BITFIELD 2437 uint64_t reserved_42_63:22; 2438 uint64_t repair2:14; 2439 uint64_t repair1:14; 2440 uint64_t repair0:14; 2441#else 2442 uint64_t repair0:14; 2443 uint64_t repair1:14; 2444 uint64_t repair2:14; 2445 uint64_t reserved_42_63:22; 2446#endif 2447 } s; 2448 struct cvmx_mio_fus_spr_repair_res_s cn30xx; 2449 struct cvmx_mio_fus_spr_repair_res_s cn31xx; 2450 struct cvmx_mio_fus_spr_repair_res_s cn38xx; 2451 struct cvmx_mio_fus_spr_repair_res_s cn50xx; 2452 struct cvmx_mio_fus_spr_repair_res_s cn52xx; 2453 struct cvmx_mio_fus_spr_repair_res_s cn52xxp1; 2454 struct cvmx_mio_fus_spr_repair_res_s cn56xx; 2455 struct cvmx_mio_fus_spr_repair_res_s cn56xxp1; 2456 struct cvmx_mio_fus_spr_repair_res_s cn58xx; 2457 struct cvmx_mio_fus_spr_repair_res_s cn58xxp1; 2458 struct cvmx_mio_fus_spr_repair_res_s cn61xx; 2459 struct cvmx_mio_fus_spr_repair_res_s cn63xx; 2460 struct cvmx_mio_fus_spr_repair_res_s cn63xxp1; 2461 struct cvmx_mio_fus_spr_repair_res_s cn66xx; 2462 struct cvmx_mio_fus_spr_repair_res_s cn68xx; 2463 struct cvmx_mio_fus_spr_repair_res_s cn68xxp1; 2464 struct cvmx_mio_fus_spr_repair_res_s cnf71xx; 2465}; 2466 2467union cvmx_mio_fus_spr_repair_sum { 2468 uint64_t u64; 2469 struct cvmx_mio_fus_spr_repair_sum_s { 2470#ifdef __BIG_ENDIAN_BITFIELD 2471 uint64_t reserved_1_63:63; 2472 uint64_t too_many:1; 2473#else 2474 uint64_t too_many:1; 2475 uint64_t reserved_1_63:63; 2476#endif 2477 } s; 2478 struct cvmx_mio_fus_spr_repair_sum_s cn30xx; 2479 struct cvmx_mio_fus_spr_repair_sum_s cn31xx; 2480 struct cvmx_mio_fus_spr_repair_sum_s cn38xx; 2481 struct cvmx_mio_fus_spr_repair_sum_s cn50xx; 2482 struct cvmx_mio_fus_spr_repair_sum_s cn52xx; 2483 struct cvmx_mio_fus_spr_repair_sum_s cn52xxp1; 2484 struct cvmx_mio_fus_spr_repair_sum_s cn56xx; 2485 struct cvmx_mio_fus_spr_repair_sum_s cn56xxp1; 2486 struct cvmx_mio_fus_spr_repair_sum_s cn58xx; 2487 struct cvmx_mio_fus_spr_repair_sum_s cn58xxp1; 2488 struct cvmx_mio_fus_spr_repair_sum_s cn61xx; 2489 struct cvmx_mio_fus_spr_repair_sum_s cn63xx; 2490 struct cvmx_mio_fus_spr_repair_sum_s cn63xxp1; 2491 struct cvmx_mio_fus_spr_repair_sum_s cn66xx; 2492 struct cvmx_mio_fus_spr_repair_sum_s cn68xx; 2493 struct cvmx_mio_fus_spr_repair_sum_s cn68xxp1; 2494 struct cvmx_mio_fus_spr_repair_sum_s cnf71xx; 2495}; 2496 2497union cvmx_mio_fus_tgg { 2498 uint64_t u64; 2499 struct cvmx_mio_fus_tgg_s { 2500#ifdef __BIG_ENDIAN_BITFIELD 2501 uint64_t val:1; 2502 uint64_t dat:63; 2503#else 2504 uint64_t dat:63; 2505 uint64_t val:1; 2506#endif 2507 } s; 2508 struct cvmx_mio_fus_tgg_s cn61xx; 2509 struct cvmx_mio_fus_tgg_s cn66xx; 2510 struct cvmx_mio_fus_tgg_s cnf71xx; 2511}; 2512 2513union cvmx_mio_fus_unlock { 2514 uint64_t u64; 2515 struct cvmx_mio_fus_unlock_s { 2516#ifdef __BIG_ENDIAN_BITFIELD 2517 uint64_t reserved_24_63:40; 2518 uint64_t key:24; 2519#else 2520 uint64_t key:24; 2521 uint64_t reserved_24_63:40; 2522#endif 2523 } s; 2524 struct cvmx_mio_fus_unlock_s cn30xx; 2525 struct cvmx_mio_fus_unlock_s cn31xx; 2526}; 2527 2528union cvmx_mio_fus_wadr { 2529 uint64_t u64; 2530 struct cvmx_mio_fus_wadr_s { 2531#ifdef __BIG_ENDIAN_BITFIELD 2532 uint64_t reserved_10_63:54; 2533 uint64_t addr:10; 2534#else 2535 uint64_t addr:10; 2536 uint64_t reserved_10_63:54; 2537#endif 2538 } s; 2539 struct cvmx_mio_fus_wadr_s cn30xx; 2540 struct cvmx_mio_fus_wadr_s cn31xx; 2541 struct cvmx_mio_fus_wadr_s cn38xx; 2542 struct cvmx_mio_fus_wadr_s cn38xxp2; 2543 struct cvmx_mio_fus_wadr_cn50xx { 2544#ifdef __BIG_ENDIAN_BITFIELD 2545 uint64_t reserved_2_63:62; 2546 uint64_t addr:2; 2547#else 2548 uint64_t addr:2; 2549 uint64_t reserved_2_63:62; 2550#endif 2551 } cn50xx; 2552 struct cvmx_mio_fus_wadr_cn52xx { 2553#ifdef __BIG_ENDIAN_BITFIELD 2554 uint64_t reserved_3_63:61; 2555 uint64_t addr:3; 2556#else 2557 uint64_t addr:3; 2558 uint64_t reserved_3_63:61; 2559#endif 2560 } cn52xx; 2561 struct cvmx_mio_fus_wadr_cn52xx cn52xxp1; 2562 struct cvmx_mio_fus_wadr_cn52xx cn56xx; 2563 struct cvmx_mio_fus_wadr_cn52xx cn56xxp1; 2564 struct cvmx_mio_fus_wadr_cn50xx cn58xx; 2565 struct cvmx_mio_fus_wadr_cn50xx cn58xxp1; 2566 struct cvmx_mio_fus_wadr_cn61xx { 2567#ifdef __BIG_ENDIAN_BITFIELD 2568 uint64_t reserved_4_63:60; 2569 uint64_t addr:4; 2570#else 2571 uint64_t addr:4; 2572 uint64_t reserved_4_63:60; 2573#endif 2574 } cn61xx; 2575 struct cvmx_mio_fus_wadr_cn61xx cn63xx; 2576 struct cvmx_mio_fus_wadr_cn61xx cn63xxp1; 2577 struct cvmx_mio_fus_wadr_cn61xx cn66xx; 2578 struct cvmx_mio_fus_wadr_cn61xx cn68xx; 2579 struct cvmx_mio_fus_wadr_cn61xx cn68xxp1; 2580 struct cvmx_mio_fus_wadr_cn61xx cnf71xx; 2581}; 2582 2583union cvmx_mio_gpio_comp { 2584 uint64_t u64; 2585 struct cvmx_mio_gpio_comp_s { 2586#ifdef __BIG_ENDIAN_BITFIELD 2587 uint64_t reserved_12_63:52; 2588 uint64_t pctl:6; 2589 uint64_t nctl:6; 2590#else 2591 uint64_t nctl:6; 2592 uint64_t pctl:6; 2593 uint64_t reserved_12_63:52; 2594#endif 2595 } s; 2596 struct cvmx_mio_gpio_comp_s cn61xx; 2597 struct cvmx_mio_gpio_comp_s cn63xx; 2598 struct cvmx_mio_gpio_comp_s cn63xxp1; 2599 struct cvmx_mio_gpio_comp_s cn66xx; 2600 struct cvmx_mio_gpio_comp_s cn68xx; 2601 struct cvmx_mio_gpio_comp_s cn68xxp1; 2602 struct cvmx_mio_gpio_comp_s cnf71xx; 2603}; 2604 2605union cvmx_mio_ndf_dma_cfg { 2606 uint64_t u64; 2607 struct cvmx_mio_ndf_dma_cfg_s { 2608#ifdef __BIG_ENDIAN_BITFIELD 2609 uint64_t en:1; 2610 uint64_t rw:1; 2611 uint64_t clr:1; 2612 uint64_t reserved_60_60:1; 2613 uint64_t swap32:1; 2614 uint64_t swap16:1; 2615 uint64_t swap8:1; 2616 uint64_t endian:1; 2617 uint64_t size:20; 2618 uint64_t adr:36; 2619#else 2620 uint64_t adr:36; 2621 uint64_t size:20; 2622 uint64_t endian:1; 2623 uint64_t swap8:1; 2624 uint64_t swap16:1; 2625 uint64_t swap32:1; 2626 uint64_t reserved_60_60:1; 2627 uint64_t clr:1; 2628 uint64_t rw:1; 2629 uint64_t en:1; 2630#endif 2631 } s; 2632 struct cvmx_mio_ndf_dma_cfg_s cn52xx; 2633 struct cvmx_mio_ndf_dma_cfg_s cn61xx; 2634 struct cvmx_mio_ndf_dma_cfg_s cn63xx; 2635 struct cvmx_mio_ndf_dma_cfg_s cn63xxp1; 2636 struct cvmx_mio_ndf_dma_cfg_s cn66xx; 2637 struct cvmx_mio_ndf_dma_cfg_s cn68xx; 2638 struct cvmx_mio_ndf_dma_cfg_s cn68xxp1; 2639 struct cvmx_mio_ndf_dma_cfg_s cnf71xx; 2640}; 2641 2642union cvmx_mio_ndf_dma_int { 2643 uint64_t u64; 2644 struct cvmx_mio_ndf_dma_int_s { 2645#ifdef __BIG_ENDIAN_BITFIELD 2646 uint64_t reserved_1_63:63; 2647 uint64_t done:1; 2648#else 2649 uint64_t done:1; 2650 uint64_t reserved_1_63:63; 2651#endif 2652 } s; 2653 struct cvmx_mio_ndf_dma_int_s cn52xx; 2654 struct cvmx_mio_ndf_dma_int_s cn61xx; 2655 struct cvmx_mio_ndf_dma_int_s cn63xx; 2656 struct cvmx_mio_ndf_dma_int_s cn63xxp1; 2657 struct cvmx_mio_ndf_dma_int_s cn66xx; 2658 struct cvmx_mio_ndf_dma_int_s cn68xx; 2659 struct cvmx_mio_ndf_dma_int_s cn68xxp1; 2660 struct cvmx_mio_ndf_dma_int_s cnf71xx; 2661}; 2662 2663union cvmx_mio_ndf_dma_int_en { 2664 uint64_t u64; 2665 struct cvmx_mio_ndf_dma_int_en_s { 2666#ifdef __BIG_ENDIAN_BITFIELD 2667 uint64_t reserved_1_63:63; 2668 uint64_t done:1; 2669#else 2670 uint64_t done:1; 2671 uint64_t reserved_1_63:63; 2672#endif 2673 } s; 2674 struct cvmx_mio_ndf_dma_int_en_s cn52xx; 2675 struct cvmx_mio_ndf_dma_int_en_s cn61xx; 2676 struct cvmx_mio_ndf_dma_int_en_s cn63xx; 2677 struct cvmx_mio_ndf_dma_int_en_s cn63xxp1; 2678 struct cvmx_mio_ndf_dma_int_en_s cn66xx; 2679 struct cvmx_mio_ndf_dma_int_en_s cn68xx; 2680 struct cvmx_mio_ndf_dma_int_en_s cn68xxp1; 2681 struct cvmx_mio_ndf_dma_int_en_s cnf71xx; 2682}; 2683 2684union cvmx_mio_pll_ctl { 2685 uint64_t u64; 2686 struct cvmx_mio_pll_ctl_s { 2687#ifdef __BIG_ENDIAN_BITFIELD 2688 uint64_t reserved_5_63:59; 2689 uint64_t bw_ctl:5; 2690#else 2691 uint64_t bw_ctl:5; 2692 uint64_t reserved_5_63:59; 2693#endif 2694 } s; 2695 struct cvmx_mio_pll_ctl_s cn30xx; 2696 struct cvmx_mio_pll_ctl_s cn31xx; 2697}; 2698 2699union cvmx_mio_pll_setting { 2700 uint64_t u64; 2701 struct cvmx_mio_pll_setting_s { 2702#ifdef __BIG_ENDIAN_BITFIELD 2703 uint64_t reserved_17_63:47; 2704 uint64_t setting:17; 2705#else 2706 uint64_t setting:17; 2707 uint64_t reserved_17_63:47; 2708#endif 2709 } s; 2710 struct cvmx_mio_pll_setting_s cn30xx; 2711 struct cvmx_mio_pll_setting_s cn31xx; 2712}; 2713 2714union cvmx_mio_ptp_ckout_hi_incr { 2715 uint64_t u64; 2716 struct cvmx_mio_ptp_ckout_hi_incr_s { 2717#ifdef __BIG_ENDIAN_BITFIELD 2718 uint64_t nanosec:32; 2719 uint64_t frnanosec:32; 2720#else 2721 uint64_t frnanosec:32; 2722 uint64_t nanosec:32; 2723#endif 2724 } s; 2725 struct cvmx_mio_ptp_ckout_hi_incr_s cn61xx; 2726 struct cvmx_mio_ptp_ckout_hi_incr_s cn66xx; 2727 struct cvmx_mio_ptp_ckout_hi_incr_s cn68xx; 2728 struct cvmx_mio_ptp_ckout_hi_incr_s cnf71xx; 2729}; 2730 2731union cvmx_mio_ptp_ckout_lo_incr { 2732 uint64_t u64; 2733 struct cvmx_mio_ptp_ckout_lo_incr_s { 2734#ifdef __BIG_ENDIAN_BITFIELD 2735 uint64_t nanosec:32; 2736 uint64_t frnanosec:32; 2737#else 2738 uint64_t frnanosec:32; 2739 uint64_t nanosec:32; 2740#endif 2741 } s; 2742 struct cvmx_mio_ptp_ckout_lo_incr_s cn61xx; 2743 struct cvmx_mio_ptp_ckout_lo_incr_s cn66xx; 2744 struct cvmx_mio_ptp_ckout_lo_incr_s cn68xx; 2745 struct cvmx_mio_ptp_ckout_lo_incr_s cnf71xx; 2746}; 2747 2748union cvmx_mio_ptp_ckout_thresh_hi { 2749 uint64_t u64; 2750 struct cvmx_mio_ptp_ckout_thresh_hi_s { 2751#ifdef __BIG_ENDIAN_BITFIELD 2752 uint64_t nanosec:64; 2753#else 2754 uint64_t nanosec:64; 2755#endif 2756 } s; 2757 struct cvmx_mio_ptp_ckout_thresh_hi_s cn61xx; 2758 struct cvmx_mio_ptp_ckout_thresh_hi_s cn66xx; 2759 struct cvmx_mio_ptp_ckout_thresh_hi_s cn68xx; 2760 struct cvmx_mio_ptp_ckout_thresh_hi_s cnf71xx; 2761}; 2762 2763union cvmx_mio_ptp_ckout_thresh_lo { 2764 uint64_t u64; 2765 struct cvmx_mio_ptp_ckout_thresh_lo_s { 2766#ifdef __BIG_ENDIAN_BITFIELD 2767 uint64_t reserved_32_63:32; 2768 uint64_t frnanosec:32; 2769#else 2770 uint64_t frnanosec:32; 2771 uint64_t reserved_32_63:32; 2772#endif 2773 } s; 2774 struct cvmx_mio_ptp_ckout_thresh_lo_s cn61xx; 2775 struct cvmx_mio_ptp_ckout_thresh_lo_s cn66xx; 2776 struct cvmx_mio_ptp_ckout_thresh_lo_s cn68xx; 2777 struct cvmx_mio_ptp_ckout_thresh_lo_s cnf71xx; 2778}; 2779 2780union cvmx_mio_ptp_clock_cfg { 2781 uint64_t u64; 2782 struct cvmx_mio_ptp_clock_cfg_s { 2783#ifdef __BIG_ENDIAN_BITFIELD 2784 uint64_t reserved_42_63:22; 2785 uint64_t pps:1; 2786 uint64_t ckout:1; 2787 uint64_t ext_clk_edge:2; 2788 uint64_t ckout_out4:1; 2789 uint64_t pps_out:5; 2790 uint64_t pps_inv:1; 2791 uint64_t pps_en:1; 2792 uint64_t ckout_out:4; 2793 uint64_t ckout_inv:1; 2794 uint64_t ckout_en:1; 2795 uint64_t evcnt_in:6; 2796 uint64_t evcnt_edge:1; 2797 uint64_t evcnt_en:1; 2798 uint64_t tstmp_in:6; 2799 uint64_t tstmp_edge:1; 2800 uint64_t tstmp_en:1; 2801 uint64_t ext_clk_in:6; 2802 uint64_t ext_clk_en:1; 2803 uint64_t ptp_en:1; 2804#else 2805 uint64_t ptp_en:1; 2806 uint64_t ext_clk_en:1; 2807 uint64_t ext_clk_in:6; 2808 uint64_t tstmp_en:1; 2809 uint64_t tstmp_edge:1; 2810 uint64_t tstmp_in:6; 2811 uint64_t evcnt_en:1; 2812 uint64_t evcnt_edge:1; 2813 uint64_t evcnt_in:6; 2814 uint64_t ckout_en:1; 2815 uint64_t ckout_inv:1; 2816 uint64_t ckout_out:4; 2817 uint64_t pps_en:1; 2818 uint64_t pps_inv:1; 2819 uint64_t pps_out:5; 2820 uint64_t ckout_out4:1; 2821 uint64_t ext_clk_edge:2; 2822 uint64_t ckout:1; 2823 uint64_t pps:1; 2824 uint64_t reserved_42_63:22; 2825#endif 2826 } s; 2827 struct cvmx_mio_ptp_clock_cfg_s cn61xx; 2828 struct cvmx_mio_ptp_clock_cfg_cn63xx { 2829#ifdef __BIG_ENDIAN_BITFIELD 2830 uint64_t reserved_24_63:40; 2831 uint64_t evcnt_in:6; 2832 uint64_t evcnt_edge:1; 2833 uint64_t evcnt_en:1; 2834 uint64_t tstmp_in:6; 2835 uint64_t tstmp_edge:1; 2836 uint64_t tstmp_en:1; 2837 uint64_t ext_clk_in:6; 2838 uint64_t ext_clk_en:1; 2839 uint64_t ptp_en:1; 2840#else 2841 uint64_t ptp_en:1; 2842 uint64_t ext_clk_en:1; 2843 uint64_t ext_clk_in:6; 2844 uint64_t tstmp_en:1; 2845 uint64_t tstmp_edge:1; 2846 uint64_t tstmp_in:6; 2847 uint64_t evcnt_en:1; 2848 uint64_t evcnt_edge:1; 2849 uint64_t evcnt_in:6; 2850 uint64_t reserved_24_63:40; 2851#endif 2852 } cn63xx; 2853 struct cvmx_mio_ptp_clock_cfg_cn63xx cn63xxp1; 2854 struct cvmx_mio_ptp_clock_cfg_cn66xx { 2855#ifdef __BIG_ENDIAN_BITFIELD 2856 uint64_t reserved_40_63:24; 2857 uint64_t ext_clk_edge:2; 2858 uint64_t ckout_out4:1; 2859 uint64_t pps_out:5; 2860 uint64_t pps_inv:1; 2861 uint64_t pps_en:1; 2862 uint64_t ckout_out:4; 2863 uint64_t ckout_inv:1; 2864 uint64_t ckout_en:1; 2865 uint64_t evcnt_in:6; 2866 uint64_t evcnt_edge:1; 2867 uint64_t evcnt_en:1; 2868 uint64_t tstmp_in:6; 2869 uint64_t tstmp_edge:1; 2870 uint64_t tstmp_en:1; 2871 uint64_t ext_clk_in:6; 2872 uint64_t ext_clk_en:1; 2873 uint64_t ptp_en:1; 2874#else 2875 uint64_t ptp_en:1; 2876 uint64_t ext_clk_en:1; 2877 uint64_t ext_clk_in:6; 2878 uint64_t tstmp_en:1; 2879 uint64_t tstmp_edge:1; 2880 uint64_t tstmp_in:6; 2881 uint64_t evcnt_en:1; 2882 uint64_t evcnt_edge:1; 2883 uint64_t evcnt_in:6; 2884 uint64_t ckout_en:1; 2885 uint64_t ckout_inv:1; 2886 uint64_t ckout_out:4; 2887 uint64_t pps_en:1; 2888 uint64_t pps_inv:1; 2889 uint64_t pps_out:5; 2890 uint64_t ckout_out4:1; 2891 uint64_t ext_clk_edge:2; 2892 uint64_t reserved_40_63:24; 2893#endif 2894 } cn66xx; 2895 struct cvmx_mio_ptp_clock_cfg_s cn68xx; 2896 struct cvmx_mio_ptp_clock_cfg_cn63xx cn68xxp1; 2897 struct cvmx_mio_ptp_clock_cfg_s cnf71xx; 2898}; 2899 2900union cvmx_mio_ptp_clock_comp { 2901 uint64_t u64; 2902 struct cvmx_mio_ptp_clock_comp_s { 2903#ifdef __BIG_ENDIAN_BITFIELD 2904 uint64_t nanosec:32; 2905 uint64_t frnanosec:32; 2906#else 2907 uint64_t frnanosec:32; 2908 uint64_t nanosec:32; 2909#endif 2910 } s; 2911 struct cvmx_mio_ptp_clock_comp_s cn61xx; 2912 struct cvmx_mio_ptp_clock_comp_s cn63xx; 2913 struct cvmx_mio_ptp_clock_comp_s cn63xxp1; 2914 struct cvmx_mio_ptp_clock_comp_s cn66xx; 2915 struct cvmx_mio_ptp_clock_comp_s cn68xx; 2916 struct cvmx_mio_ptp_clock_comp_s cn68xxp1; 2917 struct cvmx_mio_ptp_clock_comp_s cnf71xx; 2918}; 2919 2920union cvmx_mio_ptp_clock_hi { 2921 uint64_t u64; 2922 struct cvmx_mio_ptp_clock_hi_s { 2923#ifdef __BIG_ENDIAN_BITFIELD 2924 uint64_t nanosec:64; 2925#else 2926 uint64_t nanosec:64; 2927#endif 2928 } s; 2929 struct cvmx_mio_ptp_clock_hi_s cn61xx; 2930 struct cvmx_mio_ptp_clock_hi_s cn63xx; 2931 struct cvmx_mio_ptp_clock_hi_s cn63xxp1; 2932 struct cvmx_mio_ptp_clock_hi_s cn66xx; 2933 struct cvmx_mio_ptp_clock_hi_s cn68xx; 2934 struct cvmx_mio_ptp_clock_hi_s cn68xxp1; 2935 struct cvmx_mio_ptp_clock_hi_s cnf71xx; 2936}; 2937 2938union cvmx_mio_ptp_clock_lo { 2939 uint64_t u64; 2940 struct cvmx_mio_ptp_clock_lo_s { 2941#ifdef __BIG_ENDIAN_BITFIELD 2942 uint64_t reserved_32_63:32; 2943 uint64_t frnanosec:32; 2944#else 2945 uint64_t frnanosec:32; 2946 uint64_t reserved_32_63:32; 2947#endif 2948 } s; 2949 struct cvmx_mio_ptp_clock_lo_s cn61xx; 2950 struct cvmx_mio_ptp_clock_lo_s cn63xx; 2951 struct cvmx_mio_ptp_clock_lo_s cn63xxp1; 2952 struct cvmx_mio_ptp_clock_lo_s cn66xx; 2953 struct cvmx_mio_ptp_clock_lo_s cn68xx; 2954 struct cvmx_mio_ptp_clock_lo_s cn68xxp1; 2955 struct cvmx_mio_ptp_clock_lo_s cnf71xx; 2956}; 2957 2958union cvmx_mio_ptp_evt_cnt { 2959 uint64_t u64; 2960 struct cvmx_mio_ptp_evt_cnt_s { 2961#ifdef __BIG_ENDIAN_BITFIELD 2962 uint64_t cntr:64; 2963#else 2964 uint64_t cntr:64; 2965#endif 2966 } s; 2967 struct cvmx_mio_ptp_evt_cnt_s cn61xx; 2968 struct cvmx_mio_ptp_evt_cnt_s cn63xx; 2969 struct cvmx_mio_ptp_evt_cnt_s cn63xxp1; 2970 struct cvmx_mio_ptp_evt_cnt_s cn66xx; 2971 struct cvmx_mio_ptp_evt_cnt_s cn68xx; 2972 struct cvmx_mio_ptp_evt_cnt_s cn68xxp1; 2973 struct cvmx_mio_ptp_evt_cnt_s cnf71xx; 2974}; 2975 2976union cvmx_mio_ptp_phy_1pps_in { 2977 uint64_t u64; 2978 struct cvmx_mio_ptp_phy_1pps_in_s { 2979#ifdef __BIG_ENDIAN_BITFIELD 2980 uint64_t reserved_5_63:59; 2981 uint64_t sel:5; 2982#else 2983 uint64_t sel:5; 2984 uint64_t reserved_5_63:59; 2985#endif 2986 } s; 2987 struct cvmx_mio_ptp_phy_1pps_in_s cnf71xx; 2988}; 2989 2990union cvmx_mio_ptp_pps_hi_incr { 2991 uint64_t u64; 2992 struct cvmx_mio_ptp_pps_hi_incr_s { 2993#ifdef __BIG_ENDIAN_BITFIELD 2994 uint64_t nanosec:32; 2995 uint64_t frnanosec:32; 2996#else 2997 uint64_t frnanosec:32; 2998 uint64_t nanosec:32; 2999#endif 3000 } s;
3001 struct cvmx_mio_ptp_pps_hi_incr_s cn61xx; 3002 struct cvmx_mio_ptp_pps_hi_incr_s cn66xx; 3003 struct cvmx_mio_ptp_pps_hi_incr_s cn68xx; 3004 struct cvmx_mio_ptp_pps_hi_incr_s cnf71xx; 3005}; 3006 3007union cvmx_mio_ptp_pps_lo_incr { 3008 uint64_t u64; 3009 struct cvmx_mio_ptp_pps_lo_incr_s { 3010#ifdef __BIG_ENDIAN_BITFIELD 3011 uint64_t nanosec:32; 3012 uint64_t frnanosec:32; 3013#else 3014 uint64_t frnanosec:32; 3015 uint64_t nanosec:32; 3016#endif 3017 } s; 3018 struct cvmx_mio_ptp_pps_lo_incr_s cn61xx; 3019 struct cvmx_mio_ptp_pps_lo_incr_s cn66xx; 3020 struct cvmx_mio_ptp_pps_lo_incr_s cn68xx; 3021 struct cvmx_mio_ptp_pps_lo_incr_s cnf71xx; 3022}; 3023 3024union cvmx_mio_ptp_pps_thresh_hi { 3025 uint64_t u64; 3026 struct cvmx_mio_ptp_pps_thresh_hi_s { 3027#ifdef __BIG_ENDIAN_BITFIELD 3028 uint64_t nanosec:64; 3029#else 3030 uint64_t nanosec:64; 3031#endif 3032 } s; 3033 struct cvmx_mio_ptp_pps_thresh_hi_s cn61xx; 3034 struct cvmx_mio_ptp_pps_thresh_hi_s cn66xx; 3035 struct cvmx_mio_ptp_pps_thresh_hi_s cn68xx; 3036 struct cvmx_mio_ptp_pps_thresh_hi_s cnf71xx; 3037}; 3038 3039union cvmx_mio_ptp_pps_thresh_lo { 3040 uint64_t u64; 3041 struct cvmx_mio_ptp_pps_thresh_lo_s { 3042#ifdef __BIG_ENDIAN_BITFIELD 3043 uint64_t reserved_32_63:32; 3044 uint64_t frnanosec:32; 3045#else 3046 uint64_t frnanosec:32; 3047 uint64_t reserved_32_63:32; 3048#endif 3049 } s; 3050 struct cvmx_mio_ptp_pps_thresh_lo_s cn61xx; 3051 struct cvmx_mio_ptp_pps_thresh_lo_s cn66xx; 3052 struct cvmx_mio_ptp_pps_thresh_lo_s cn68xx; 3053 struct cvmx_mio_ptp_pps_thresh_lo_s cnf71xx; 3054}; 3055 3056union cvmx_mio_ptp_timestamp { 3057 uint64_t u64; 3058 struct cvmx_mio_ptp_timestamp_s { 3059#ifdef __BIG_ENDIAN_BITFIELD 3060 uint64_t nanosec:64; 3061#else 3062 uint64_t nanosec:64; 3063#endif 3064 } s; 3065 struct cvmx_mio_ptp_timestamp_s cn61xx; 3066 struct cvmx_mio_ptp_timestamp_s cn63xx; 3067 struct cvmx_mio_ptp_timestamp_s cn63xxp1; 3068 struct cvmx_mio_ptp_timestamp_s cn66xx; 3069 struct cvmx_mio_ptp_timestamp_s cn68xx; 3070 struct cvmx_mio_ptp_timestamp_s cn68xxp1; 3071 struct cvmx_mio_ptp_timestamp_s cnf71xx; 3072}; 3073 3074union cvmx_mio_qlmx_cfg { 3075 uint64_t u64; 3076 struct cvmx_mio_qlmx_cfg_s { 3077#ifdef __BIG_ENDIAN_BITFIELD 3078 uint64_t reserved_15_63:49; 3079 uint64_t prtmode:1; 3080 uint64_t reserved_12_13:2; 3081 uint64_t qlm_spd:4; 3082 uint64_t reserved_4_7:4; 3083 uint64_t qlm_cfg:4; 3084#else 3085 uint64_t qlm_cfg:4; 3086 uint64_t reserved_4_7:4; 3087 uint64_t qlm_spd:4; 3088 uint64_t reserved_12_13:2; 3089 uint64_t prtmode:1; 3090 uint64_t reserved_15_63:49; 3091#endif 3092 } s; 3093 struct cvmx_mio_qlmx_cfg_cn61xx { 3094#ifdef __BIG_ENDIAN_BITFIELD 3095 uint64_t reserved_15_63:49; 3096 uint64_t prtmode:1; 3097 uint64_t reserved_12_13:2; 3098 uint64_t qlm_spd:4; 3099 uint64_t reserved_2_7:6; 3100 uint64_t qlm_cfg:2; 3101#else 3102 uint64_t qlm_cfg:2; 3103 uint64_t reserved_2_7:6; 3104 uint64_t qlm_spd:4; 3105 uint64_t reserved_12_13:2; 3106 uint64_t prtmode:1; 3107 uint64_t reserved_15_63:49; 3108#endif 3109 } cn61xx; 3110 struct cvmx_mio_qlmx_cfg_cn66xx { 3111#ifdef __BIG_ENDIAN_BITFIELD 3112 uint64_t reserved_12_63:52; 3113 uint64_t qlm_spd:4; 3114 uint64_t reserved_4_7:4; 3115 uint64_t qlm_cfg:4; 3116#else 3117 uint64_t qlm_cfg:4; 3118 uint64_t reserved_4_7:4; 3119 uint64_t qlm_spd:4; 3120 uint64_t reserved_12_63:52; 3121#endif 3122 } cn66xx; 3123 struct cvmx_mio_qlmx_cfg_cn68xx { 3124#ifdef __BIG_ENDIAN_BITFIELD 3125 uint64_t reserved_12_63:52; 3126 uint64_t qlm_spd:4; 3127 uint64_t reserved_3_7:5; 3128 uint64_t qlm_cfg:3; 3129#else 3130 uint64_t qlm_cfg:3; 3131 uint64_t reserved_3_7:5; 3132 uint64_t qlm_spd:4; 3133 uint64_t reserved_12_63:52; 3134#endif 3135 } cn68xx; 3136 struct cvmx_mio_qlmx_cfg_cn68xx cn68xxp1; 3137 struct cvmx_mio_qlmx_cfg_cn61xx cnf71xx; 3138}; 3139 3140union cvmx_mio_rst_boot { 3141 uint64_t u64; 3142 struct cvmx_mio_rst_boot_s { 3143#ifdef __BIG_ENDIAN_BITFIELD 3144 uint64_t chipkill:1; 3145 uint64_t jtcsrdis:1; 3146 uint64_t ejtagdis:1; 3147 uint64_t romen:1; 3148 uint64_t ckill_ppdis:1; 3149 uint64_t jt_tstmode:1; 3150 uint64_t reserved_50_57:8; 3151 uint64_t lboot_ext:2; 3152 uint64_t reserved_44_47:4; 3153 uint64_t qlm4_spd:4; 3154 uint64_t qlm3_spd:4; 3155 uint64_t c_mul:6; 3156 uint64_t pnr_mul:6; 3157 uint64_t qlm2_spd:4; 3158 uint64_t qlm1_spd:4; 3159 uint64_t qlm0_spd:4; 3160 uint64_t lboot:10; 3161 uint64_t rboot:1; 3162 uint64_t rboot_pin:1; 3163#else 3164 uint64_t rboot_pin:1; 3165 uint64_t rboot:1; 3166 uint64_t lboot:10; 3167 uint64_t qlm0_spd:4; 3168 uint64_t qlm1_spd:4; 3169 uint64_t qlm2_spd:4; 3170 uint64_t pnr_mul:6; 3171 uint64_t c_mul:6; 3172 uint64_t qlm3_spd:4; 3173 uint64_t qlm4_spd:4; 3174 uint64_t reserved_44_47:4; 3175 uint64_t lboot_ext:2; 3176 uint64_t reserved_50_57:8; 3177 uint64_t jt_tstmode:1; 3178 uint64_t ckill_ppdis:1; 3179 uint64_t romen:1; 3180 uint64_t ejtagdis:1; 3181 uint64_t jtcsrdis:1; 3182 uint64_t chipkill:1; 3183#endif 3184 } s; 3185 struct cvmx_mio_rst_boot_cn61xx { 3186#ifdef __BIG_ENDIAN_BITFIELD 3187 uint64_t chipkill:1; 3188 uint64_t jtcsrdis:1; 3189 uint64_t ejtagdis:1; 3190 uint64_t romen:1; 3191 uint64_t ckill_ppdis:1; 3192 uint64_t jt_tstmode:1; 3193 uint64_t reserved_50_57:8; 3194 uint64_t lboot_ext:2; 3195 uint64_t reserved_36_47:12; 3196 uint64_t c_mul:6; 3197 uint64_t pnr_mul:6; 3198 uint64_t qlm2_spd:4; 3199 uint64_t qlm1_spd:4; 3200 uint64_t qlm0_spd:4; 3201 uint64_t lboot:10; 3202 uint64_t rboot:1; 3203 uint64_t rboot_pin:1; 3204#else 3205 uint64_t rboot_pin:1; 3206 uint64_t rboot:1; 3207 uint64_t lboot:10; 3208 uint64_t qlm0_spd:4; 3209 uint64_t qlm1_spd:4; 3210 uint64_t qlm2_spd:4; 3211 uint64_t pnr_mul:6; 3212 uint64_t c_mul:6; 3213 uint64_t reserved_36_47:12; 3214 uint64_t lboot_ext:2; 3215 uint64_t reserved_50_57:8; 3216 uint64_t jt_tstmode:1; 3217 uint64_t ckill_ppdis:1; 3218 uint64_t romen:1; 3219 uint64_t ejtagdis:1; 3220 uint64_t jtcsrdis:1; 3221 uint64_t chipkill:1; 3222#endif 3223 } cn61xx; 3224 struct cvmx_mio_rst_boot_cn63xx { 3225#ifdef __BIG_ENDIAN_BITFIELD 3226 uint64_t reserved_36_63:28; 3227 uint64_t c_mul:6; 3228 uint64_t pnr_mul:6; 3229 uint64_t qlm2_spd:4; 3230 uint64_t qlm1_spd:4; 3231 uint64_t qlm0_spd:4; 3232 uint64_t lboot:10; 3233 uint64_t rboot:1; 3234 uint64_t rboot_pin:1; 3235#else 3236 uint64_t rboot_pin:1; 3237 uint64_t rboot:1; 3238 uint64_t lboot:10; 3239 uint64_t qlm0_spd:4; 3240 uint64_t qlm1_spd:4; 3241 uint64_t qlm2_spd:4; 3242 uint64_t pnr_mul:6; 3243 uint64_t c_mul:6; 3244 uint64_t reserved_36_63:28; 3245#endif 3246 } cn63xx; 3247 struct cvmx_mio_rst_boot_cn63xx cn63xxp1; 3248 struct cvmx_mio_rst_boot_cn66xx { 3249#ifdef __BIG_ENDIAN_BITFIELD 3250 uint64_t chipkill:1; 3251 uint64_t jtcsrdis:1; 3252 uint64_t ejtagdis:1; 3253 uint64_t romen:1; 3254 uint64_t ckill_ppdis:1; 3255 uint64_t reserved_50_58:9; 3256 uint64_t lboot_ext:2; 3257 uint64_t reserved_36_47:12; 3258 uint64_t c_mul:6; 3259 uint64_t pnr_mul:6; 3260 uint64_t qlm2_spd:4; 3261 uint64_t qlm1_spd:4; 3262 uint64_t qlm0_spd:4; 3263 uint64_t lboot:10; 3264 uint64_t rboot:1; 3265 uint64_t rboot_pin:1; 3266#else 3267 uint64_t rboot_pin:1; 3268 uint64_t rboot:1; 3269 uint64_t lboot:10; 3270 uint64_t qlm0_spd:4; 3271 uint64_t qlm1_spd:4; 3272 uint64_t qlm2_spd:4; 3273 uint64_t pnr_mul:6; 3274 uint64_t c_mul:6; 3275 uint64_t reserved_36_47:12; 3276 uint64_t lboot_ext:2; 3277 uint64_t reserved_50_58:9; 3278 uint64_t ckill_ppdis:1; 3279 uint64_t romen:1; 3280 uint64_t ejtagdis:1; 3281 uint64_t jtcsrdis:1; 3282 uint64_t chipkill:1; 3283#endif 3284 } cn66xx; 3285 struct cvmx_mio_rst_boot_cn68xx { 3286#ifdef __BIG_ENDIAN_BITFIELD 3287 uint64_t reserved_59_63:5; 3288 uint64_t jt_tstmode:1; 3289 uint64_t reserved_44_57:14; 3290 uint64_t qlm4_spd:4; 3291 uint64_t qlm3_spd:4; 3292 uint64_t c_mul:6; 3293 uint64_t pnr_mul:6; 3294 uint64_t qlm2_spd:4; 3295 uint64_t qlm1_spd:4; 3296 uint64_t qlm0_spd:4; 3297 uint64_t lboot:10; 3298 uint64_t rboot:1; 3299 uint64_t rboot_pin:1; 3300#else 3301 uint64_t rboot_pin:1; 3302 uint64_t rboot:1; 3303 uint64_t lboot:10; 3304 uint64_t qlm0_spd:4; 3305 uint64_t qlm1_spd:4; 3306 uint64_t qlm2_spd:4; 3307 uint64_t pnr_mul:6; 3308 uint64_t c_mul:6; 3309 uint64_t qlm3_spd:4; 3310 uint64_t qlm4_spd:4; 3311 uint64_t reserved_44_57:14; 3312 uint64_t jt_tstmode:1; 3313 uint64_t reserved_59_63:5; 3314#endif 3315 } cn68xx; 3316 struct cvmx_mio_rst_boot_cn68xxp1 { 3317#ifdef __BIG_ENDIAN_BITFIELD 3318 uint64_t reserved_44_63:20; 3319 uint64_t qlm4_spd:4; 3320 uint64_t qlm3_spd:4; 3321 uint64_t c_mul:6; 3322 uint64_t pnr_mul:6; 3323 uint64_t qlm2_spd:4; 3324 uint64_t qlm1_spd:4; 3325 uint64_t qlm0_spd:4; 3326 uint64_t lboot:10; 3327 uint64_t rboot:1; 3328 uint64_t rboot_pin:1; 3329#else 3330 uint64_t rboot_pin:1; 3331 uint64_t rboot:1; 3332 uint64_t lboot:10; 3333 uint64_t qlm0_spd:4; 3334 uint64_t qlm1_spd:4; 3335 uint64_t qlm2_spd:4; 3336 uint64_t pnr_mul:6; 3337 uint64_t c_mul:6; 3338 uint64_t qlm3_spd:4; 3339 uint64_t qlm4_spd:4; 3340 uint64_t reserved_44_63:20; 3341#endif 3342 } cn68xxp1; 3343 struct cvmx_mio_rst_boot_cn61xx cnf71xx; 3344}; 3345 3346union cvmx_mio_rst_cfg { 3347 uint64_t u64; 3348 struct cvmx_mio_rst_cfg_s { 3349#ifdef __BIG_ENDIAN_BITFIELD 3350 uint64_t reserved_3_63:61; 3351 uint64_t cntl_clr_bist:1; 3352 uint64_t warm_clr_bist:1; 3353 uint64_t soft_clr_bist:1; 3354#else 3355 uint64_t soft_clr_bist:1; 3356 uint64_t warm_clr_bist:1; 3357 uint64_t cntl_clr_bist:1; 3358 uint64_t reserved_3_63:61; 3359#endif 3360 } s; 3361 struct cvmx_mio_rst_cfg_cn61xx { 3362#ifdef __BIG_ENDIAN_BITFIELD 3363 uint64_t bist_delay:58; 3364 uint64_t reserved_3_5:3; 3365 uint64_t cntl_clr_bist:1; 3366 uint64_t warm_clr_bist:1; 3367 uint64_t soft_clr_bist:1; 3368#else 3369 uint64_t soft_clr_bist:1; 3370 uint64_t warm_clr_bist:1; 3371 uint64_t cntl_clr_bist:1; 3372 uint64_t reserved_3_5:3; 3373 uint64_t bist_delay:58; 3374#endif 3375 } cn61xx; 3376 struct cvmx_mio_rst_cfg_cn61xx cn63xx; 3377 struct cvmx_mio_rst_cfg_cn63xxp1 { 3378#ifdef __BIG_ENDIAN_BITFIELD 3379 uint64_t bist_delay:58; 3380 uint64_t reserved_2_5:4; 3381 uint64_t warm_clr_bist:1; 3382 uint64_t soft_clr_bist:1; 3383#else 3384 uint64_t soft_clr_bist:1; 3385 uint64_t warm_clr_bist:1; 3386 uint64_t reserved_2_5:4; 3387 uint64_t bist_delay:58; 3388#endif 3389 } cn63xxp1; 3390 struct cvmx_mio_rst_cfg_cn61xx cn66xx; 3391 struct cvmx_mio_rst_cfg_cn68xx { 3392#ifdef __BIG_ENDIAN_BITFIELD 3393 uint64_t bist_delay:56; 3394 uint64_t reserved_3_7:5; 3395 uint64_t cntl_clr_bist:1; 3396 uint64_t warm_clr_bist:1; 3397 uint64_t soft_clr_bist:1; 3398#else 3399 uint64_t soft_clr_bist:1; 3400 uint64_t warm_clr_bist:1; 3401 uint64_t cntl_clr_bist:1; 3402 uint64_t reserved_3_7:5; 3403 uint64_t bist_delay:56; 3404#endif 3405 } cn68xx; 3406 struct cvmx_mio_rst_cfg_cn68xx cn68xxp1; 3407 struct cvmx_mio_rst_cfg_cn61xx cnf71xx; 3408}; 3409 3410union cvmx_mio_rst_ckill { 3411 uint64_t u64; 3412 struct cvmx_mio_rst_ckill_s { 3413#ifdef __BIG_ENDIAN_BITFIELD 3414 uint64_t reserved_47_63:17; 3415 uint64_t timer:47; 3416#else 3417 uint64_t timer:47; 3418 uint64_t reserved_47_63:17; 3419#endif 3420 } s; 3421 struct cvmx_mio_rst_ckill_s cn61xx; 3422 struct cvmx_mio_rst_ckill_s cn66xx; 3423 struct cvmx_mio_rst_ckill_s cnf71xx; 3424}; 3425 3426union cvmx_mio_rst_cntlx { 3427 uint64_t u64; 3428 struct cvmx_mio_rst_cntlx_s { 3429#ifdef __BIG_ENDIAN_BITFIELD 3430 uint64_t reserved_13_63:51; 3431 uint64_t in_rev_ln:1; 3432 uint64_t rev_lanes:1; 3433 uint64_t gen1_only:1; 3434 uint64_t prst_link:1; 3435 uint64_t rst_done:1; 3436 uint64_t rst_link:1; 3437 uint64_t host_mode:1; 3438 uint64_t prtmode:2; 3439 uint64_t rst_drv:1; 3440 uint64_t rst_rcv:1; 3441 uint64_t rst_chip:1; 3442 uint64_t rst_val:1; 3443#else 3444 uint64_t rst_val:1; 3445 uint64_t rst_chip:1; 3446 uint64_t rst_rcv:1; 3447 uint64_t rst_drv:1; 3448 uint64_t prtmode:2; 3449 uint64_t host_mode:1; 3450 uint64_t rst_link:1; 3451 uint64_t rst_done:1; 3452 uint64_t prst_link:1; 3453 uint64_t gen1_only:1; 3454 uint64_t rev_lanes:1; 3455 uint64_t in_rev_ln:1; 3456 uint64_t reserved_13_63:51; 3457#endif 3458 } s; 3459 struct cvmx_mio_rst_cntlx_s cn61xx; 3460 struct cvmx_mio_rst_cntlx_cn66xx { 3461#ifdef __BIG_ENDIAN_BITFIELD 3462 uint64_t reserved_10_63:54; 3463 uint64_t prst_link:1; 3464 uint64_t rst_done:1; 3465 uint64_t rst_link:1; 3466 uint64_t host_mode:1; 3467 uint64_t prtmode:2; 3468 uint64_t rst_drv:1; 3469 uint64_t rst_rcv:1; 3470 uint64_t rst_chip:1; 3471 uint64_t rst_val:1; 3472#else 3473 uint64_t rst_val:1; 3474 uint64_t rst_chip:1; 3475 uint64_t rst_rcv:1; 3476 uint64_t rst_drv:1; 3477 uint64_t prtmode:2; 3478 uint64_t host_mode:1; 3479 uint64_t rst_link:1; 3480 uint64_t rst_done:1; 3481 uint64_t prst_link:1; 3482 uint64_t reserved_10_63:54; 3483#endif 3484 } cn66xx; 3485 struct cvmx_mio_rst_cntlx_cn66xx cn68xx; 3486 struct cvmx_mio_rst_cntlx_s cnf71xx; 3487}; 3488 3489union cvmx_mio_rst_ctlx { 3490 uint64_t u64; 3491 struct cvmx_mio_rst_ctlx_s { 3492#ifdef __BIG_ENDIAN_BITFIELD 3493 uint64_t reserved_13_63:51; 3494 uint64_t in_rev_ln:1; 3495 uint64_t rev_lanes:1; 3496 uint64_t gen1_only:1; 3497 uint64_t prst_link:1; 3498 uint64_t rst_done:1; 3499 uint64_t rst_link:1; 3500 uint64_t host_mode:1; 3501 uint64_t prtmode:2; 3502 uint64_t rst_drv:1; 3503 uint64_t rst_rcv:1; 3504 uint64_t rst_chip:1; 3505 uint64_t rst_val:1; 3506#else 3507 uint64_t rst_val:1; 3508 uint64_t rst_chip:1; 3509 uint64_t rst_rcv:1; 3510 uint64_t rst_drv:1; 3511 uint64_t prtmode:2; 3512 uint64_t host_mode:1; 3513 uint64_t rst_link:1; 3514 uint64_t rst_done:1; 3515 uint64_t prst_link:1; 3516 uint64_t gen1_only:1; 3517 uint64_t rev_lanes:1; 3518 uint64_t in_rev_ln:1; 3519 uint64_t reserved_13_63:51; 3520#endif 3521 } s; 3522 struct cvmx_mio_rst_ctlx_s cn61xx; 3523 struct cvmx_mio_rst_ctlx_cn63xx { 3524#ifdef __BIG_ENDIAN_BITFIELD 3525 uint64_t reserved_10_63:54; 3526 uint64_t prst_link:1; 3527 uint64_t rst_done:1; 3528 uint64_t rst_link:1; 3529 uint64_t host_mode:1; 3530 uint64_t prtmode:2; 3531 uint64_t rst_drv:1; 3532 uint64_t rst_rcv:1; 3533 uint64_t rst_chip:1; 3534 uint64_t rst_val:1; 3535#else 3536 uint64_t rst_val:1; 3537 uint64_t rst_chip:1; 3538 uint64_t rst_rcv:1; 3539 uint64_t rst_drv:1; 3540 uint64_t prtmode:2; 3541 uint64_t host_mode:1; 3542 uint64_t rst_link:1; 3543 uint64_t rst_done:1; 3544 uint64_t prst_link:1; 3545 uint64_t reserved_10_63:54; 3546#endif 3547 } cn63xx; 3548 struct cvmx_mio_rst_ctlx_cn63xxp1 { 3549#ifdef __BIG_ENDIAN_BITFIELD 3550 uint64_t reserved_9_63:55; 3551 uint64_t rst_done:1; 3552 uint64_t rst_link:1; 3553 uint64_t host_mode:1; 3554 uint64_t prtmode:2; 3555 uint64_t rst_drv:1; 3556 uint64_t rst_rcv:1; 3557 uint64_t rst_chip:1; 3558 uint64_t rst_val:1; 3559#else 3560 uint64_t rst_val:1; 3561 uint64_t rst_chip:1; 3562 uint64_t rst_rcv:1; 3563 uint64_t rst_drv:1; 3564 uint64_t prtmode:2; 3565 uint64_t host_mode:1; 3566 uint64_t rst_link:1; 3567 uint64_t rst_done:1; 3568 uint64_t reserved_9_63:55; 3569#endif 3570 } cn63xxp1; 3571 struct cvmx_mio_rst_ctlx_cn63xx cn66xx; 3572 struct cvmx_mio_rst_ctlx_cn63xx cn68xx; 3573 struct cvmx_mio_rst_ctlx_cn63xx cn68xxp1; 3574 struct cvmx_mio_rst_ctlx_s cnf71xx; 3575}; 3576 3577union cvmx_mio_rst_delay { 3578 uint64_t u64; 3579 struct cvmx_mio_rst_delay_s { 3580#ifdef __BIG_ENDIAN_BITFIELD 3581 uint64_t reserved_32_63:32; 3582 uint64_t warm_rst_dly:16; 3583 uint64_t soft_rst_dly:16; 3584#else 3585 uint64_t soft_rst_dly:16; 3586 uint64_t warm_rst_dly:16; 3587 uint64_t reserved_32_63:32; 3588#endif 3589 } s; 3590 struct cvmx_mio_rst_delay_s cn61xx; 3591 struct cvmx_mio_rst_delay_s cn63xx; 3592 struct cvmx_mio_rst_delay_s cn63xxp1; 3593 struct cvmx_mio_rst_delay_s cn66xx; 3594 struct cvmx_mio_rst_delay_s cn68xx; 3595 struct cvmx_mio_rst_delay_s cn68xxp1; 3596 struct cvmx_mio_rst_delay_s cnf71xx; 3597}; 3598 3599union cvmx_mio_rst_int { 3600 uint64_t u64; 3601 struct cvmx_mio_rst_int_s { 3602#ifdef __BIG_ENDIAN_BITFIELD 3603 uint64_t reserved_10_63:54; 3604 uint64_t perst1:1; 3605 uint64_t perst0:1; 3606 uint64_t reserved_4_7:4; 3607 uint64_t rst_link3:1; 3608 uint64_t rst_link2:1; 3609 uint64_t rst_link1:1; 3610 uint64_t rst_link0:1; 3611#else 3612 uint64_t rst_link0:1; 3613 uint64_t rst_link1:1; 3614 uint64_t rst_link2:1; 3615 uint64_t rst_link3:1; 3616 uint64_t reserved_4_7:4; 3617 uint64_t perst0:1; 3618 uint64_t perst1:1; 3619 uint64_t reserved_10_63:54; 3620#endif 3621 } s; 3622 struct cvmx_mio_rst_int_cn61xx { 3623#ifdef __BIG_ENDIAN_BITFIELD 3624 uint64_t reserved_10_63:54; 3625 uint64_t perst1:1; 3626 uint64_t perst0:1; 3627 uint64_t reserved_2_7:6; 3628 uint64_t rst_link1:1; 3629 uint64_t rst_link0:1; 3630#else 3631 uint64_t rst_link0:1; 3632 uint64_t rst_link1:1; 3633 uint64_t reserved_2_7:6; 3634 uint64_t perst0:1; 3635 uint64_t perst1:1; 3636 uint64_t reserved_10_63:54; 3637#endif 3638 } cn61xx; 3639 struct cvmx_mio_rst_int_cn61xx cn63xx; 3640 struct cvmx_mio_rst_int_cn61xx cn63xxp1; 3641 struct cvmx_mio_rst_int_s cn66xx; 3642 struct cvmx_mio_rst_int_cn61xx cn68xx; 3643 struct cvmx_mio_rst_int_cn61xx cn68xxp1; 3644 struct cvmx_mio_rst_int_cn61xx cnf71xx; 3645}; 3646 3647union cvmx_mio_rst_int_en { 3648 uint64_t u64; 3649 struct cvmx_mio_rst_int_en_s { 3650#ifdef __BIG_ENDIAN_BITFIELD 3651 uint64_t reserved_10_63:54; 3652 uint64_t perst1:1; 3653 uint64_t perst0:1; 3654 uint64_t reserved_4_7:4; 3655 uint64_t rst_link3:1; 3656 uint64_t rst_link2:1; 3657 uint64_t rst_link1:1; 3658 uint64_t rst_link0:1; 3659#else 3660 uint64_t rst_link0:1; 3661 uint64_t rst_link1:1; 3662 uint64_t rst_link2:1; 3663 uint64_t rst_link3:1; 3664 uint64_t reserved_4_7:4; 3665 uint64_t perst0:1; 3666 uint64_t perst1:1; 3667 uint64_t reserved_10_63:54; 3668#endif 3669 } s; 3670 struct cvmx_mio_rst_int_en_cn61xx { 3671#ifdef __BIG_ENDIAN_BITFIELD 3672 uint64_t reserved_10_63:54; 3673 uint64_t perst1:1; 3674 uint64_t perst0:1; 3675 uint64_t reserved_2_7:6; 3676 uint64_t rst_link1:1; 3677 uint64_t rst_link0:1; 3678#else 3679 uint64_t rst_link0:1; 3680 uint64_t rst_link1:1; 3681 uint64_t reserved_2_7:6; 3682 uint64_t perst0:1; 3683 uint64_t perst1:1; 3684 uint64_t reserved_10_63:54; 3685#endif 3686 } cn61xx; 3687 struct cvmx_mio_rst_int_en_cn61xx cn63xx; 3688 struct cvmx_mio_rst_int_en_cn61xx cn63xxp1; 3689 struct cvmx_mio_rst_int_en_s cn66xx; 3690 struct cvmx_mio_rst_int_en_cn61xx cn68xx; 3691 struct cvmx_mio_rst_int_en_cn61xx cn68xxp1; 3692 struct cvmx_mio_rst_int_en_cn61xx cnf71xx; 3693}; 3694 3695union cvmx_mio_twsx_int { 3696 uint64_t u64; 3697 struct cvmx_mio_twsx_int_s { 3698#ifdef __BIG_ENDIAN_BITFIELD 3699 uint64_t reserved_12_63:52; 3700 uint64_t scl:1; 3701 uint64_t sda:1; 3702 uint64_t scl_ovr:1; 3703 uint64_t sda_ovr:1; 3704 uint64_t reserved_7_7:1; 3705 uint64_t core_en:1; 3706 uint64_t ts_en:1; 3707 uint64_t st_en:1; 3708 uint64_t reserved_3_3:1; 3709 uint64_t core_int:1; 3710 uint64_t ts_int:1; 3711 uint64_t st_int:1; 3712#else 3713 uint64_t st_int:1; 3714 uint64_t ts_int:1; 3715 uint64_t core_int:1; 3716 uint64_t reserved_3_3:1; 3717 uint64_t st_en:1; 3718 uint64_t ts_en:1; 3719 uint64_t core_en:1; 3720 uint64_t reserved_7_7:1; 3721 uint64_t sda_ovr:1; 3722 uint64_t scl_ovr:1; 3723 uint64_t sda:1; 3724 uint64_t scl:1; 3725 uint64_t reserved_12_63:52; 3726#endif 3727 } s; 3728 struct cvmx_mio_twsx_int_s cn30xx; 3729 struct cvmx_mio_twsx_int_s cn31xx; 3730 struct cvmx_mio_twsx_int_s cn38xx; 3731 struct cvmx_mio_twsx_int_cn38xxp2 { 3732#ifdef __BIG_ENDIAN_BITFIELD 3733 uint64_t reserved_7_63:57; 3734 uint64_t core_en:1; 3735 uint64_t ts_en:1; 3736 uint64_t st_en:1; 3737 uint64_t reserved_3_3:1; 3738 uint64_t core_int:1; 3739 uint64_t ts_int:1; 3740 uint64_t st_int:1; 3741#else 3742 uint64_t st_int:1; 3743 uint64_t ts_int:1; 3744 uint64_t core_int:1; 3745 uint64_t reserved_3_3:1; 3746 uint64_t st_en:1; 3747 uint64_t ts_en:1; 3748 uint64_t core_en:1; 3749 uint64_t reserved_7_63:57; 3750#endif 3751 } cn38xxp2; 3752 struct cvmx_mio_twsx_int_s cn50xx; 3753 struct cvmx_mio_twsx_int_s cn52xx; 3754 struct cvmx_mio_twsx_int_s cn52xxp1; 3755 struct cvmx_mio_twsx_int_s cn56xx; 3756 struct cvmx_mio_twsx_int_s cn56xxp1; 3757 struct cvmx_mio_twsx_int_s cn58xx; 3758 struct cvmx_mio_twsx_int_s cn58xxp1; 3759 struct cvmx_mio_twsx_int_s cn61xx; 3760 struct cvmx_mio_twsx_int_s cn63xx; 3761 struct cvmx_mio_twsx_int_s cn63xxp1; 3762 struct cvmx_mio_twsx_int_s cn66xx; 3763 struct cvmx_mio_twsx_int_s cn68xx; 3764 struct cvmx_mio_twsx_int_s cn68xxp1; 3765 struct cvmx_mio_twsx_int_s cnf71xx; 3766}; 3767 3768union cvmx_mio_twsx_sw_twsi { 3769 uint64_t u64; 3770 struct cvmx_mio_twsx_sw_twsi_s { 3771#ifdef __BIG_ENDIAN_BITFIELD 3772 uint64_t v:1; 3773 uint64_t slonly:1; 3774 uint64_t eia:1; 3775 uint64_t op:4; 3776 uint64_t r:1; 3777 uint64_t sovr:1; 3778 uint64_t size:3; 3779 uint64_t scr:2; 3780 uint64_t a:10; 3781 uint64_t ia:5; 3782 uint64_t eop_ia:3; 3783 uint64_t d:32; 3784#else 3785 uint64_t d:32; 3786 uint64_t eop_ia:3; 3787 uint64_t ia:5; 3788 uint64_t a:10; 3789 uint64_t scr:2; 3790 uint64_t size:3; 3791 uint64_t sovr:1; 3792 uint64_t r:1; 3793 uint64_t op:4; 3794 uint64_t eia:1; 3795 uint64_t slonly:1; 3796 uint64_t v:1; 3797#endif 3798 } s; 3799 struct cvmx_mio_twsx_sw_twsi_s cn30xx; 3800 struct cvmx_mio_twsx_sw_twsi_s cn31xx; 3801 struct cvmx_mio_twsx_sw_twsi_s cn38xx; 3802 struct cvmx_mio_twsx_sw_twsi_s cn38xxp2; 3803 struct cvmx_mio_twsx_sw_twsi_s cn50xx; 3804 struct cvmx_mio_twsx_sw_twsi_s cn52xx; 3805 struct cvmx_mio_twsx_sw_twsi_s cn52xxp1; 3806 struct cvmx_mio_twsx_sw_twsi_s cn56xx; 3807 struct cvmx_mio_twsx_sw_twsi_s cn56xxp1; 3808 struct cvmx_mio_twsx_sw_twsi_s cn58xx; 3809 struct cvmx_mio_twsx_sw_twsi_s cn58xxp1; 3810 struct cvmx_mio_twsx_sw_twsi_s cn61xx; 3811 struct cvmx_mio_twsx_sw_twsi_s cn63xx; 3812 struct cvmx_mio_twsx_sw_twsi_s cn63xxp1; 3813 struct cvmx_mio_twsx_sw_twsi_s cn66xx; 3814 struct cvmx_mio_twsx_sw_twsi_s cn68xx; 3815 struct cvmx_mio_twsx_sw_twsi_s cn68xxp1; 3816 struct cvmx_mio_twsx_sw_twsi_s cnf71xx; 3817}; 3818 3819union cvmx_mio_twsx_sw_twsi_ext { 3820 uint64_t u64; 3821 struct cvmx_mio_twsx_sw_twsi_ext_s { 3822#ifdef __BIG_ENDIAN_BITFIELD 3823 uint64_t reserved_40_63:24; 3824 uint64_t ia:8; 3825 uint64_t d:32; 3826#else 3827 uint64_t d:32; 3828 uint64_t ia:8; 3829 uint64_t reserved_40_63:24; 3830#endif 3831 } s; 3832 struct cvmx_mio_twsx_sw_twsi_ext_s cn30xx; 3833 struct cvmx_mio_twsx_sw_twsi_ext_s cn31xx; 3834 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xx; 3835 struct cvmx_mio_twsx_sw_twsi_ext_s cn38xxp2; 3836 struct cvmx_mio_twsx_sw_twsi_ext_s cn50xx; 3837 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xx; 3838 struct cvmx_mio_twsx_sw_twsi_ext_s cn52xxp1; 3839 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xx; 3840 struct cvmx_mio_twsx_sw_twsi_ext_s cn56xxp1; 3841 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xx; 3842 struct cvmx_mio_twsx_sw_twsi_ext_s cn58xxp1; 3843 struct cvmx_mio_twsx_sw_twsi_ext_s cn61xx; 3844 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xx; 3845 struct cvmx_mio_twsx_sw_twsi_ext_s cn63xxp1; 3846 struct cvmx_mio_twsx_sw_twsi_ext_s cn66xx; 3847 struct cvmx_mio_twsx_sw_twsi_ext_s cn68xx; 3848 struct cvmx_mio_twsx_sw_twsi_ext_s cn68xxp1; 3849 struct cvmx_mio_twsx_sw_twsi_ext_s cnf71xx; 3850}; 3851 3852union cvmx_mio_twsx_twsi_sw { 3853 uint64_t u64; 3854 struct cvmx_mio_twsx_twsi_sw_s { 3855#ifdef __BIG_ENDIAN_BITFIELD 3856 uint64_t v:2; 3857 uint64_t reserved_32_61:30; 3858 uint64_t d:32; 3859#else 3860 uint64_t d:32; 3861 uint64_t reserved_32_61:30; 3862 uint64_t v:2; 3863#endif 3864 } s; 3865 struct cvmx_mio_twsx_twsi_sw_s cn30xx; 3866 struct cvmx_mio_twsx_twsi_sw_s cn31xx; 3867 struct cvmx_mio_twsx_twsi_sw_s cn38xx; 3868 struct cvmx_mio_twsx_twsi_sw_s cn38xxp2; 3869 struct cvmx_mio_twsx_twsi_sw_s cn50xx; 3870 struct cvmx_mio_twsx_twsi_sw_s cn52xx; 3871 struct cvmx_mio_twsx_twsi_sw_s cn52xxp1; 3872 struct cvmx_mio_twsx_twsi_sw_s cn56xx; 3873 struct cvmx_mio_twsx_twsi_sw_s cn56xxp1; 3874 struct cvmx_mio_twsx_twsi_sw_s cn58xx; 3875 struct cvmx_mio_twsx_twsi_sw_s cn58xxp1; 3876 struct cvmx_mio_twsx_twsi_sw_s cn61xx; 3877 struct cvmx_mio_twsx_twsi_sw_s cn63xx; 3878 struct cvmx_mio_twsx_twsi_sw_s cn63xxp1; 3879 struct cvmx_mio_twsx_twsi_sw_s cn66xx; 3880 struct cvmx_mio_twsx_twsi_sw_s cn68xx; 3881 struct cvmx_mio_twsx_twsi_sw_s cn68xxp1; 3882 struct cvmx_mio_twsx_twsi_sw_s cnf71xx; 3883}; 3884 3885union cvmx_mio_uartx_dlh { 3886 uint64_t u64; 3887 struct cvmx_mio_uartx_dlh_s { 3888#ifdef __BIG_ENDIAN_BITFIELD 3889 uint64_t reserved_8_63:56; 3890 uint64_t dlh:8; 3891#else 3892 uint64_t dlh:8; 3893 uint64_t reserved_8_63:56; 3894#endif 3895 } s; 3896 struct cvmx_mio_uartx_dlh_s cn30xx; 3897 struct cvmx_mio_uartx_dlh_s cn31xx; 3898 struct cvmx_mio_uartx_dlh_s cn38xx; 3899 struct cvmx_mio_uartx_dlh_s cn38xxp2; 3900 struct cvmx_mio_uartx_dlh_s cn50xx; 3901 struct cvmx_mio_uartx_dlh_s cn52xx; 3902 struct cvmx_mio_uartx_dlh_s cn52xxp1; 3903 struct cvmx_mio_uartx_dlh_s cn56xx; 3904 struct cvmx_mio_uartx_dlh_s cn56xxp1; 3905 struct cvmx_mio_uartx_dlh_s cn58xx; 3906 struct cvmx_mio_uartx_dlh_s cn58xxp1; 3907 struct cvmx_mio_uartx_dlh_s cn61xx; 3908 struct cvmx_mio_uartx_dlh_s cn63xx; 3909 struct cvmx_mio_uartx_dlh_s cn63xxp1; 3910 struct cvmx_mio_uartx_dlh_s cn66xx; 3911 struct cvmx_mio_uartx_dlh_s cn68xx; 3912 struct cvmx_mio_uartx_dlh_s cn68xxp1; 3913 struct cvmx_mio_uartx_dlh_s cnf71xx; 3914}; 3915 3916union cvmx_mio_uartx_dll { 3917 uint64_t u64; 3918 struct cvmx_mio_uartx_dll_s { 3919#ifdef __BIG_ENDIAN_BITFIELD 3920 uint64_t reserved_8_63:56; 3921 uint64_t dll:8; 3922#else 3923 uint64_t dll:8; 3924 uint64_t reserved_8_63:56; 3925#endif 3926 } s; 3927 struct cvmx_mio_uartx_dll_s cn30xx; 3928 struct cvmx_mio_uartx_dll_s cn31xx; 3929 struct cvmx_mio_uartx_dll_s cn38xx; 3930 struct cvmx_mio_uartx_dll_s cn38xxp2; 3931 struct cvmx_mio_uartx_dll_s cn50xx; 3932 struct cvmx_mio_uartx_dll_s cn52xx; 3933 struct cvmx_mio_uartx_dll_s cn52xxp1; 3934 struct cvmx_mio_uartx_dll_s cn56xx; 3935 struct cvmx_mio_uartx_dll_s cn56xxp1; 3936 struct cvmx_mio_uartx_dll_s cn58xx; 3937 struct cvmx_mio_uartx_dll_s cn58xxp1; 3938 struct cvmx_mio_uartx_dll_s cn61xx; 3939 struct cvmx_mio_uartx_dll_s cn63xx; 3940 struct cvmx_mio_uartx_dll_s cn63xxp1; 3941 struct cvmx_mio_uartx_dll_s cn66xx; 3942 struct cvmx_mio_uartx_dll_s cn68xx; 3943 struct cvmx_mio_uartx_dll_s cn68xxp1; 3944 struct cvmx_mio_uartx_dll_s cnf71xx; 3945}; 3946 3947union cvmx_mio_uartx_far { 3948 uint64_t u64; 3949 struct cvmx_mio_uartx_far_s { 3950#ifdef __BIG_ENDIAN_BITFIELD 3951 uint64_t reserved_1_63:63; 3952 uint64_t far:1; 3953#else 3954 uint64_t far:1; 3955 uint64_t reserved_1_63:63; 3956#endif 3957 } s; 3958 struct cvmx_mio_uartx_far_s cn30xx; 3959 struct cvmx_mio_uartx_far_s cn31xx; 3960 struct cvmx_mio_uartx_far_s cn38xx; 3961 struct cvmx_mio_uartx_far_s cn38xxp2; 3962 struct cvmx_mio_uartx_far_s cn50xx; 3963 struct cvmx_mio_uartx_far_s cn52xx; 3964 struct cvmx_mio_uartx_far_s cn52xxp1; 3965 struct cvmx_mio_uartx_far_s cn56xx; 3966 struct cvmx_mio_uartx_far_s cn56xxp1; 3967 struct cvmx_mio_uartx_far_s cn58xx; 3968 struct cvmx_mio_uartx_far_s cn58xxp1; 3969 struct cvmx_mio_uartx_far_s cn61xx; 3970 struct cvmx_mio_uartx_far_s cn63xx; 3971 struct cvmx_mio_uartx_far_s cn63xxp1; 3972 struct cvmx_mio_uartx_far_s cn66xx; 3973 struct cvmx_mio_uartx_far_s cn68xx; 3974 struct cvmx_mio_uartx_far_s cn68xxp1; 3975 struct cvmx_mio_uartx_far_s cnf71xx; 3976}; 3977 3978union cvmx_mio_uartx_fcr { 3979 uint64_t u64; 3980 struct cvmx_mio_uartx_fcr_s { 3981#ifdef __BIG_ENDIAN_BITFIELD 3982 uint64_t reserved_8_63:56; 3983 uint64_t rxtrig:2; 3984 uint64_t txtrig:2; 3985 uint64_t reserved_3_3:1; 3986 uint64_t txfr:1; 3987 uint64_t rxfr:1; 3988 uint64_t en:1; 3989#else 3990 uint64_t en:1; 3991 uint64_t rxfr:1; 3992 uint64_t txfr:1; 3993 uint64_t reserved_3_3:1; 3994 uint64_t txtrig:2; 3995 uint64_t rxtrig:2; 3996 uint64_t reserved_8_63:56; 3997#endif 3998 } s; 3999 struct cvmx_mio_uartx_fcr_s cn30xx; 4000 struct cvmx_mio_uartx_fcr_s cn31xx;
4001 struct cvmx_mio_uartx_fcr_s cn38xx; 4002 struct cvmx_mio_uartx_fcr_s cn38xxp2; 4003 struct cvmx_mio_uartx_fcr_s cn50xx; 4004 struct cvmx_mio_uartx_fcr_s cn52xx; 4005 struct cvmx_mio_uartx_fcr_s cn52xxp1; 4006 struct cvmx_mio_uartx_fcr_s cn56xx; 4007 struct cvmx_mio_uartx_fcr_s cn56xxp1; 4008 struct cvmx_mio_uartx_fcr_s cn58xx; 4009 struct cvmx_mio_uartx_fcr_s cn58xxp1; 4010 struct cvmx_mio_uartx_fcr_s cn61xx; 4011 struct cvmx_mio_uartx_fcr_s cn63xx; 4012 struct cvmx_mio_uartx_fcr_s cn63xxp1; 4013 struct cvmx_mio_uartx_fcr_s cn66xx; 4014 struct cvmx_mio_uartx_fcr_s cn68xx; 4015 struct cvmx_mio_uartx_fcr_s cn68xxp1; 4016 struct cvmx_mio_uartx_fcr_s cnf71xx; 4017}; 4018 4019union cvmx_mio_uartx_htx { 4020 uint64_t u64; 4021 struct cvmx_mio_uartx_htx_s { 4022#ifdef __BIG_ENDIAN_BITFIELD 4023 uint64_t reserved_1_63:63; 4024 uint64_t htx:1; 4025#else 4026 uint64_t htx:1; 4027 uint64_t reserved_1_63:63; 4028#endif 4029 } s; 4030 struct cvmx_mio_uartx_htx_s cn30xx; 4031 struct cvmx_mio_uartx_htx_s cn31xx; 4032 struct cvmx_mio_uartx_htx_s cn38xx; 4033 struct cvmx_mio_uartx_htx_s cn38xxp2; 4034 struct cvmx_mio_uartx_htx_s cn50xx; 4035 struct cvmx_mio_uartx_htx_s cn52xx; 4036 struct cvmx_mio_uartx_htx_s cn52xxp1; 4037 struct cvmx_mio_uartx_htx_s cn56xx; 4038 struct cvmx_mio_uartx_htx_s cn56xxp1; 4039 struct cvmx_mio_uartx_htx_s cn58xx; 4040 struct cvmx_mio_uartx_htx_s cn58xxp1; 4041 struct cvmx_mio_uartx_htx_s cn61xx; 4042 struct cvmx_mio_uartx_htx_s cn63xx; 4043 struct cvmx_mio_uartx_htx_s cn63xxp1; 4044 struct cvmx_mio_uartx_htx_s cn66xx; 4045 struct cvmx_mio_uartx_htx_s cn68xx; 4046 struct cvmx_mio_uartx_htx_s cn68xxp1; 4047 struct cvmx_mio_uartx_htx_s cnf71xx; 4048}; 4049 4050union cvmx_mio_uartx_ier { 4051 uint64_t u64; 4052 struct cvmx_mio_uartx_ier_s { 4053#ifdef __BIG_ENDIAN_BITFIELD 4054 uint64_t reserved_8_63:56; 4055 uint64_t ptime:1; 4056 uint64_t reserved_4_6:3; 4057 uint64_t edssi:1; 4058 uint64_t elsi:1; 4059 uint64_t etbei:1; 4060 uint64_t erbfi:1; 4061#else 4062 uint64_t erbfi:1; 4063 uint64_t etbei:1; 4064 uint64_t elsi:1; 4065 uint64_t edssi:1; 4066 uint64_t reserved_4_6:3; 4067 uint64_t ptime:1; 4068 uint64_t reserved_8_63:56; 4069#endif 4070 } s; 4071 struct cvmx_mio_uartx_ier_s cn30xx; 4072 struct cvmx_mio_uartx_ier_s cn31xx; 4073 struct cvmx_mio_uartx_ier_s cn38xx; 4074 struct cvmx_mio_uartx_ier_s cn38xxp2; 4075 struct cvmx_mio_uartx_ier_s cn50xx; 4076 struct cvmx_mio_uartx_ier_s cn52xx; 4077 struct cvmx_mio_uartx_ier_s cn52xxp1; 4078 struct cvmx_mio_uartx_ier_s cn56xx; 4079 struct cvmx_mio_uartx_ier_s cn56xxp1; 4080 struct cvmx_mio_uartx_ier_s cn58xx; 4081 struct cvmx_mio_uartx_ier_s cn58xxp1; 4082 struct cvmx_mio_uartx_ier_s cn61xx; 4083 struct cvmx_mio_uartx_ier_s cn63xx; 4084 struct cvmx_mio_uartx_ier_s cn63xxp1; 4085 struct cvmx_mio_uartx_ier_s cn66xx; 4086 struct cvmx_mio_uartx_ier_s cn68xx; 4087 struct cvmx_mio_uartx_ier_s cn68xxp1; 4088 struct cvmx_mio_uartx_ier_s cnf71xx; 4089}; 4090 4091union cvmx_mio_uartx_iir { 4092 uint64_t u64; 4093 struct cvmx_mio_uartx_iir_s { 4094#ifdef __BIG_ENDIAN_BITFIELD 4095 uint64_t reserved_8_63:56; 4096 uint64_t fen:2; 4097 uint64_t reserved_4_5:2; 4098 uint64_t iid:4; 4099#else 4100 uint64_t iid:4; 4101 uint64_t reserved_4_5:2; 4102 uint64_t fen:2; 4103 uint64_t reserved_8_63:56; 4104#endif 4105 } s; 4106 struct cvmx_mio_uartx_iir_s cn30xx; 4107 struct cvmx_mio_uartx_iir_s cn31xx; 4108 struct cvmx_mio_uartx_iir_s cn38xx; 4109 struct cvmx_mio_uartx_iir_s cn38xxp2; 4110 struct cvmx_mio_uartx_iir_s cn50xx; 4111 struct cvmx_mio_uartx_iir_s cn52xx; 4112 struct cvmx_mio_uartx_iir_s cn52xxp1; 4113 struct cvmx_mio_uartx_iir_s cn56xx; 4114 struct cvmx_mio_uartx_iir_s cn56xxp1; 4115 struct cvmx_mio_uartx_iir_s cn58xx; 4116 struct cvmx_mio_uartx_iir_s cn58xxp1; 4117 struct cvmx_mio_uartx_iir_s cn61xx; 4118 struct cvmx_mio_uartx_iir_s cn63xx; 4119 struct cvmx_mio_uartx_iir_s cn63xxp1; 4120 struct cvmx_mio_uartx_iir_s cn66xx; 4121 struct cvmx_mio_uartx_iir_s cn68xx; 4122 struct cvmx_mio_uartx_iir_s cn68xxp1; 4123 struct cvmx_mio_uartx_iir_s cnf71xx; 4124}; 4125 4126union cvmx_mio_uartx_lcr { 4127 uint64_t u64; 4128 struct cvmx_mio_uartx_lcr_s { 4129#ifdef __BIG_ENDIAN_BITFIELD 4130 uint64_t reserved_8_63:56; 4131 uint64_t dlab:1; 4132 uint64_t brk:1; 4133 uint64_t reserved_5_5:1; 4134 uint64_t eps:1; 4135 uint64_t pen:1; 4136 uint64_t stop:1; 4137 uint64_t cls:2; 4138#else 4139 uint64_t cls:2; 4140 uint64_t stop:1; 4141 uint64_t pen:1; 4142 uint64_t eps:1; 4143 uint64_t reserved_5_5:1; 4144 uint64_t brk:1; 4145 uint64_t dlab:1; 4146 uint64_t reserved_8_63:56; 4147#endif 4148 } s; 4149 struct cvmx_mio_uartx_lcr_s cn30xx; 4150 struct cvmx_mio_uartx_lcr_s cn31xx; 4151 struct cvmx_mio_uartx_lcr_s cn38xx; 4152 struct cvmx_mio_uartx_lcr_s cn38xxp2; 4153 struct cvmx_mio_uartx_lcr_s cn50xx; 4154 struct cvmx_mio_uartx_lcr_s cn52xx; 4155 struct cvmx_mio_uartx_lcr_s cn52xxp1; 4156 struct cvmx_mio_uartx_lcr_s cn56xx; 4157 struct cvmx_mio_uartx_lcr_s cn56xxp1; 4158 struct cvmx_mio_uartx_lcr_s cn58xx; 4159 struct cvmx_mio_uartx_lcr_s cn58xxp1; 4160 struct cvmx_mio_uartx_lcr_s cn61xx; 4161 struct cvmx_mio_uartx_lcr_s cn63xx; 4162 struct cvmx_mio_uartx_lcr_s cn63xxp1; 4163 struct cvmx_mio_uartx_lcr_s cn66xx; 4164 struct cvmx_mio_uartx_lcr_s cn68xx; 4165 struct cvmx_mio_uartx_lcr_s cn68xxp1; 4166 struct cvmx_mio_uartx_lcr_s cnf71xx; 4167}; 4168 4169union cvmx_mio_uartx_lsr { 4170 uint64_t u64; 4171 struct cvmx_mio_uartx_lsr_s { 4172#ifdef __BIG_ENDIAN_BITFIELD 4173 uint64_t reserved_8_63:56; 4174 uint64_t ferr:1; 4175 uint64_t temt:1; 4176 uint64_t thre:1; 4177 uint64_t bi:1; 4178 uint64_t fe:1; 4179 uint64_t pe:1; 4180 uint64_t oe:1; 4181 uint64_t dr:1; 4182#else 4183 uint64_t dr:1; 4184 uint64_t oe:1; 4185 uint64_t pe:1; 4186 uint64_t fe:1; 4187 uint64_t bi:1; 4188 uint64_t thre:1; 4189 uint64_t temt:1; 4190 uint64_t ferr:1; 4191 uint64_t reserved_8_63:56; 4192#endif 4193 } s; 4194 struct cvmx_mio_uartx_lsr_s cn30xx; 4195 struct cvmx_mio_uartx_lsr_s cn31xx; 4196 struct cvmx_mio_uartx_lsr_s cn38xx; 4197 struct cvmx_mio_uartx_lsr_s cn38xxp2; 4198 struct cvmx_mio_uartx_lsr_s cn50xx; 4199 struct cvmx_mio_uartx_lsr_s cn52xx; 4200 struct cvmx_mio_uartx_lsr_s cn52xxp1; 4201 struct cvmx_mio_uartx_lsr_s cn56xx; 4202 struct cvmx_mio_uartx_lsr_s cn56xxp1; 4203 struct cvmx_mio_uartx_lsr_s cn58xx; 4204 struct cvmx_mio_uartx_lsr_s cn58xxp1; 4205 struct cvmx_mio_uartx_lsr_s cn61xx; 4206 struct cvmx_mio_uartx_lsr_s cn63xx; 4207 struct cvmx_mio_uartx_lsr_s cn63xxp1; 4208 struct cvmx_mio_uartx_lsr_s cn66xx; 4209 struct cvmx_mio_uartx_lsr_s cn68xx; 4210 struct cvmx_mio_uartx_lsr_s cn68xxp1; 4211 struct cvmx_mio_uartx_lsr_s cnf71xx; 4212}; 4213 4214union cvmx_mio_uartx_mcr { 4215 uint64_t u64; 4216 struct cvmx_mio_uartx_mcr_s { 4217#ifdef __BIG_ENDIAN_BITFIELD 4218 uint64_t reserved_6_63:58; 4219 uint64_t afce:1; 4220 uint64_t loop:1; 4221 uint64_t out2:1; 4222 uint64_t out1:1; 4223 uint64_t rts:1; 4224 uint64_t dtr:1; 4225#else 4226 uint64_t dtr:1; 4227 uint64_t rts:1; 4228 uint64_t out1:1; 4229 uint64_t out2:1; 4230 uint64_t loop:1; 4231 uint64_t afce:1; 4232 uint64_t reserved_6_63:58; 4233#endif 4234 } s; 4235 struct cvmx_mio_uartx_mcr_s cn30xx; 4236 struct cvmx_mio_uartx_mcr_s cn31xx; 4237 struct cvmx_mio_uartx_mcr_s cn38xx; 4238 struct cvmx_mio_uartx_mcr_s cn38xxp2; 4239 struct cvmx_mio_uartx_mcr_s cn50xx; 4240 struct cvmx_mio_uartx_mcr_s cn52xx; 4241 struct cvmx_mio_uartx_mcr_s cn52xxp1; 4242 struct cvmx_mio_uartx_mcr_s cn56xx; 4243 struct cvmx_mio_uartx_mcr_s cn56xxp1; 4244 struct cvmx_mio_uartx_mcr_s cn58xx; 4245 struct cvmx_mio_uartx_mcr_s cn58xxp1; 4246 struct cvmx_mio_uartx_mcr_s cn61xx; 4247 struct cvmx_mio_uartx_mcr_s cn63xx; 4248 struct cvmx_mio_uartx_mcr_s cn63xxp1; 4249 struct cvmx_mio_uartx_mcr_s cn66xx; 4250 struct cvmx_mio_uartx_mcr_s cn68xx; 4251 struct cvmx_mio_uartx_mcr_s cn68xxp1; 4252 struct cvmx_mio_uartx_mcr_s cnf71xx; 4253}; 4254 4255union cvmx_mio_uartx_msr { 4256 uint64_t u64; 4257 struct cvmx_mio_uartx_msr_s { 4258#ifdef __BIG_ENDIAN_BITFIELD 4259 uint64_t reserved_8_63:56; 4260 uint64_t dcd:1; 4261 uint64_t ri:1; 4262 uint64_t dsr:1; 4263 uint64_t cts:1; 4264 uint64_t ddcd:1; 4265 uint64_t teri:1; 4266 uint64_t ddsr:1; 4267 uint64_t dcts:1; 4268#else 4269 uint64_t dcts:1; 4270 uint64_t ddsr:1; 4271 uint64_t teri:1; 4272 uint64_t ddcd:1; 4273 uint64_t cts:1; 4274 uint64_t dsr:1; 4275 uint64_t ri:1; 4276 uint64_t dcd:1; 4277 uint64_t reserved_8_63:56; 4278#endif 4279 } s; 4280 struct cvmx_mio_uartx_msr_s cn30xx; 4281 struct cvmx_mio_uartx_msr_s cn31xx; 4282 struct cvmx_mio_uartx_msr_s cn38xx; 4283 struct cvmx_mio_uartx_msr_s cn38xxp2; 4284 struct cvmx_mio_uartx_msr_s cn50xx; 4285 struct cvmx_mio_uartx_msr_s cn52xx; 4286 struct cvmx_mio_uartx_msr_s cn52xxp1; 4287 struct cvmx_mio_uartx_msr_s cn56xx; 4288 struct cvmx_mio_uartx_msr_s cn56xxp1; 4289 struct cvmx_mio_uartx_msr_s cn58xx; 4290 struct cvmx_mio_uartx_msr_s cn58xxp1; 4291 struct cvmx_mio_uartx_msr_s cn61xx; 4292 struct cvmx_mio_uartx_msr_s cn63xx; 4293 struct cvmx_mio_uartx_msr_s cn63xxp1; 4294 struct cvmx_mio_uartx_msr_s cn66xx; 4295 struct cvmx_mio_uartx_msr_s cn68xx; 4296 struct cvmx_mio_uartx_msr_s cn68xxp1; 4297 struct cvmx_mio_uartx_msr_s cnf71xx; 4298}; 4299 4300union cvmx_mio_uartx_rbr { 4301 uint64_t u64; 4302 struct cvmx_mio_uartx_rbr_s { 4303#ifdef __BIG_ENDIAN_BITFIELD 4304 uint64_t reserved_8_63:56; 4305 uint64_t rbr:8; 4306#else 4307 uint64_t rbr:8; 4308 uint64_t reserved_8_63:56; 4309#endif 4310 } s; 4311 struct cvmx_mio_uartx_rbr_s cn30xx; 4312 struct cvmx_mio_uartx_rbr_s cn31xx; 4313 struct cvmx_mio_uartx_rbr_s cn38xx; 4314 struct cvmx_mio_uartx_rbr_s cn38xxp2; 4315 struct cvmx_mio_uartx_rbr_s cn50xx; 4316 struct cvmx_mio_uartx_rbr_s cn52xx; 4317 struct cvmx_mio_uartx_rbr_s cn52xxp1; 4318 struct cvmx_mio_uartx_rbr_s cn56xx; 4319 struct cvmx_mio_uartx_rbr_s cn56xxp1; 4320 struct cvmx_mio_uartx_rbr_s cn58xx; 4321 struct cvmx_mio_uartx_rbr_s cn58xxp1; 4322 struct cvmx_mio_uartx_rbr_s cn61xx; 4323 struct cvmx_mio_uartx_rbr_s cn63xx; 4324 struct cvmx_mio_uartx_rbr_s cn63xxp1; 4325 struct cvmx_mio_uartx_rbr_s cn66xx; 4326 struct cvmx_mio_uartx_rbr_s cn68xx; 4327 struct cvmx_mio_uartx_rbr_s cn68xxp1; 4328 struct cvmx_mio_uartx_rbr_s cnf71xx; 4329}; 4330 4331union cvmx_mio_uartx_rfl { 4332 uint64_t u64; 4333 struct cvmx_mio_uartx_rfl_s { 4334#ifdef __BIG_ENDIAN_BITFIELD 4335 uint64_t reserved_7_63:57; 4336 uint64_t rfl:7; 4337#else 4338 uint64_t rfl:7; 4339 uint64_t reserved_7_63:57; 4340#endif 4341 } s; 4342 struct cvmx_mio_uartx_rfl_s cn30xx; 4343 struct cvmx_mio_uartx_rfl_s cn31xx; 4344 struct cvmx_mio_uartx_rfl_s cn38xx; 4345 struct cvmx_mio_uartx_rfl_s cn38xxp2; 4346 struct cvmx_mio_uartx_rfl_s cn50xx; 4347 struct cvmx_mio_uartx_rfl_s cn52xx; 4348 struct cvmx_mio_uartx_rfl_s cn52xxp1; 4349 struct cvmx_mio_uartx_rfl_s cn56xx; 4350 struct cvmx_mio_uartx_rfl_s cn56xxp1; 4351 struct cvmx_mio_uartx_rfl_s cn58xx; 4352 struct cvmx_mio_uartx_rfl_s cn58xxp1; 4353 struct cvmx_mio_uartx_rfl_s cn61xx; 4354 struct cvmx_mio_uartx_rfl_s cn63xx; 4355 struct cvmx_mio_uartx_rfl_s cn63xxp1; 4356 struct cvmx_mio_uartx_rfl_s cn66xx; 4357 struct cvmx_mio_uartx_rfl_s cn68xx; 4358 struct cvmx_mio_uartx_rfl_s cn68xxp1; 4359 struct cvmx_mio_uartx_rfl_s cnf71xx; 4360}; 4361 4362union cvmx_mio_uartx_rfw { 4363 uint64_t u64; 4364 struct cvmx_mio_uartx_rfw_s { 4365#ifdef __BIG_ENDIAN_BITFIELD 4366 uint64_t reserved_10_63:54; 4367 uint64_t rffe:1; 4368 uint64_t rfpe:1; 4369 uint64_t rfwd:8; 4370#else 4371 uint64_t rfwd:8; 4372 uint64_t rfpe:1; 4373 uint64_t rffe:1; 4374 uint64_t reserved_10_63:54; 4375#endif 4376 } s; 4377 struct cvmx_mio_uartx_rfw_s cn30xx; 4378 struct cvmx_mio_uartx_rfw_s cn31xx; 4379 struct cvmx_mio_uartx_rfw_s cn38xx; 4380 struct cvmx_mio_uartx_rfw_s cn38xxp2; 4381 struct cvmx_mio_uartx_rfw_s cn50xx; 4382 struct cvmx_mio_uartx_rfw_s cn52xx; 4383 struct cvmx_mio_uartx_rfw_s cn52xxp1; 4384 struct cvmx_mio_uartx_rfw_s cn56xx; 4385 struct cvmx_mio_uartx_rfw_s cn56xxp1; 4386 struct cvmx_mio_uartx_rfw_s cn58xx; 4387 struct cvmx_mio_uartx_rfw_s cn58xxp1; 4388 struct cvmx_mio_uartx_rfw_s cn61xx; 4389 struct cvmx_mio_uartx_rfw_s cn63xx; 4390 struct cvmx_mio_uartx_rfw_s cn63xxp1; 4391 struct cvmx_mio_uartx_rfw_s cn66xx; 4392 struct cvmx_mio_uartx_rfw_s cn68xx; 4393 struct cvmx_mio_uartx_rfw_s cn68xxp1; 4394 struct cvmx_mio_uartx_rfw_s cnf71xx; 4395}; 4396 4397union cvmx_mio_uartx_sbcr { 4398 uint64_t u64; 4399 struct cvmx_mio_uartx_sbcr_s { 4400#ifdef __BIG_ENDIAN_BITFIELD 4401 uint64_t reserved_1_63:63; 4402 uint64_t sbcr:1; 4403#else 4404 uint64_t sbcr:1; 4405 uint64_t reserved_1_63:63; 4406#endif 4407 } s; 4408 struct cvmx_mio_uartx_sbcr_s cn30xx; 4409 struct cvmx_mio_uartx_sbcr_s cn31xx; 4410 struct cvmx_mio_uartx_sbcr_s cn38xx; 4411 struct cvmx_mio_uartx_sbcr_s cn38xxp2; 4412 struct cvmx_mio_uartx_sbcr_s cn50xx; 4413 struct cvmx_mio_uartx_sbcr_s cn52xx; 4414 struct cvmx_mio_uartx_sbcr_s cn52xxp1; 4415 struct cvmx_mio_uartx_sbcr_s cn56xx; 4416 struct cvmx_mio_uartx_sbcr_s cn56xxp1; 4417 struct cvmx_mio_uartx_sbcr_s cn58xx; 4418 struct cvmx_mio_uartx_sbcr_s cn58xxp1; 4419 struct cvmx_mio_uartx_sbcr_s cn61xx; 4420 struct cvmx_mio_uartx_sbcr_s cn63xx; 4421 struct cvmx_mio_uartx_sbcr_s cn63xxp1; 4422 struct cvmx_mio_uartx_sbcr_s cn66xx; 4423 struct cvmx_mio_uartx_sbcr_s cn68xx; 4424 struct cvmx_mio_uartx_sbcr_s cn68xxp1; 4425 struct cvmx_mio_uartx_sbcr_s cnf71xx; 4426}; 4427 4428union cvmx_mio_uartx_scr { 4429 uint64_t u64; 4430 struct cvmx_mio_uartx_scr_s { 4431#ifdef __BIG_ENDIAN_BITFIELD 4432 uint64_t reserved_8_63:56; 4433 uint64_t scr:8; 4434#else 4435 uint64_t scr:8; 4436 uint64_t reserved_8_63:56; 4437#endif 4438 } s; 4439 struct cvmx_mio_uartx_scr_s cn30xx; 4440 struct cvmx_mio_uartx_scr_s cn31xx; 4441 struct cvmx_mio_uartx_scr_s cn38xx; 4442 struct cvmx_mio_uartx_scr_s cn38xxp2; 4443 struct cvmx_mio_uartx_scr_s cn50xx; 4444 struct cvmx_mio_uartx_scr_s cn52xx; 4445 struct cvmx_mio_uartx_scr_s cn52xxp1; 4446 struct cvmx_mio_uartx_scr_s cn56xx; 4447 struct cvmx_mio_uartx_scr_s cn56xxp1; 4448 struct cvmx_mio_uartx_scr_s cn58xx; 4449 struct cvmx_mio_uartx_scr_s cn58xxp1; 4450 struct cvmx_mio_uartx_scr_s cn61xx; 4451 struct cvmx_mio_uartx_scr_s cn63xx; 4452 struct cvmx_mio_uartx_scr_s cn63xxp1; 4453 struct cvmx_mio_uartx_scr_s cn66xx; 4454 struct cvmx_mio_uartx_scr_s cn68xx; 4455 struct cvmx_mio_uartx_scr_s cn68xxp1; 4456 struct cvmx_mio_uartx_scr_s cnf71xx; 4457}; 4458 4459union cvmx_mio_uartx_sfe { 4460 uint64_t u64; 4461 struct cvmx_mio_uartx_sfe_s { 4462#ifdef __BIG_ENDIAN_BITFIELD 4463 uint64_t reserved_1_63:63; 4464 uint64_t sfe:1; 4465#else 4466 uint64_t sfe:1; 4467 uint64_t reserved_1_63:63; 4468#endif 4469 } s; 4470 struct cvmx_mio_uartx_sfe_s cn30xx; 4471 struct cvmx_mio_uartx_sfe_s cn31xx; 4472 struct cvmx_mio_uartx_sfe_s cn38xx; 4473 struct cvmx_mio_uartx_sfe_s cn38xxp2; 4474 struct cvmx_mio_uartx_sfe_s cn50xx; 4475 struct cvmx_mio_uartx_sfe_s cn52xx; 4476 struct cvmx_mio_uartx_sfe_s cn52xxp1; 4477 struct cvmx_mio_uartx_sfe_s cn56xx; 4478 struct cvmx_mio_uartx_sfe_s cn56xxp1; 4479 struct cvmx_mio_uartx_sfe_s cn58xx; 4480 struct cvmx_mio_uartx_sfe_s cn58xxp1; 4481 struct cvmx_mio_uartx_sfe_s cn61xx; 4482 struct cvmx_mio_uartx_sfe_s cn63xx; 4483 struct cvmx_mio_uartx_sfe_s cn63xxp1; 4484 struct cvmx_mio_uartx_sfe_s cn66xx; 4485 struct cvmx_mio_uartx_sfe_s cn68xx; 4486 struct cvmx_mio_uartx_sfe_s cn68xxp1; 4487 struct cvmx_mio_uartx_sfe_s cnf71xx; 4488}; 4489 4490union cvmx_mio_uartx_srr { 4491 uint64_t u64; 4492 struct cvmx_mio_uartx_srr_s { 4493#ifdef __BIG_ENDIAN_BITFIELD 4494 uint64_t reserved_3_63:61; 4495 uint64_t stfr:1; 4496 uint64_t srfr:1; 4497 uint64_t usr:1; 4498#else 4499 uint64_t usr:1; 4500 uint64_t srfr:1; 4501 uint64_t stfr:1; 4502 uint64_t reserved_3_63:61; 4503#endif 4504 } s; 4505 struct cvmx_mio_uartx_srr_s cn30xx; 4506 struct cvmx_mio_uartx_srr_s cn31xx; 4507 struct cvmx_mio_uartx_srr_s cn38xx; 4508 struct cvmx_mio_uartx_srr_s cn38xxp2; 4509 struct cvmx_mio_uartx_srr_s cn50xx; 4510 struct cvmx_mio_uartx_srr_s cn52xx; 4511 struct cvmx_mio_uartx_srr_s cn52xxp1; 4512 struct cvmx_mio_uartx_srr_s cn56xx; 4513 struct cvmx_mio_uartx_srr_s cn56xxp1; 4514 struct cvmx_mio_uartx_srr_s cn58xx; 4515 struct cvmx_mio_uartx_srr_s cn58xxp1; 4516 struct cvmx_mio_uartx_srr_s cn61xx; 4517 struct cvmx_mio_uartx_srr_s cn63xx; 4518 struct cvmx_mio_uartx_srr_s cn63xxp1; 4519 struct cvmx_mio_uartx_srr_s cn66xx; 4520 struct cvmx_mio_uartx_srr_s cn68xx; 4521 struct cvmx_mio_uartx_srr_s cn68xxp1; 4522 struct cvmx_mio_uartx_srr_s cnf71xx; 4523}; 4524 4525union cvmx_mio_uartx_srt { 4526 uint64_t u64; 4527 struct cvmx_mio_uartx_srt_s { 4528#ifdef __BIG_ENDIAN_BITFIELD 4529 uint64_t reserved_2_63:62; 4530 uint64_t srt:2; 4531#else 4532 uint64_t srt:2; 4533 uint64_t reserved_2_63:62; 4534#endif 4535 } s; 4536 struct cvmx_mio_uartx_srt_s cn30xx; 4537 struct cvmx_mio_uartx_srt_s cn31xx; 4538 struct cvmx_mio_uartx_srt_s cn38xx; 4539 struct cvmx_mio_uartx_srt_s cn38xxp2; 4540 struct cvmx_mio_uartx_srt_s cn50xx; 4541 struct cvmx_mio_uartx_srt_s cn52xx; 4542 struct cvmx_mio_uartx_srt_s cn52xxp1; 4543 struct cvmx_mio_uartx_srt_s cn56xx; 4544 struct cvmx_mio_uartx_srt_s cn56xxp1; 4545 struct cvmx_mio_uartx_srt_s cn58xx; 4546 struct cvmx_mio_uartx_srt_s cn58xxp1; 4547 struct cvmx_mio_uartx_srt_s cn61xx; 4548 struct cvmx_mio_uartx_srt_s cn63xx; 4549 struct cvmx_mio_uartx_srt_s cn63xxp1; 4550 struct cvmx_mio_uartx_srt_s cn66xx; 4551 struct cvmx_mio_uartx_srt_s cn68xx; 4552 struct cvmx_mio_uartx_srt_s cn68xxp1; 4553 struct cvmx_mio_uartx_srt_s cnf71xx; 4554}; 4555 4556union cvmx_mio_uartx_srts { 4557 uint64_t u64; 4558 struct cvmx_mio_uartx_srts_s { 4559#ifdef __BIG_ENDIAN_BITFIELD 4560 uint64_t reserved_1_63:63; 4561 uint64_t srts:1; 4562#else 4563 uint64_t srts:1; 4564 uint64_t reserved_1_63:63; 4565#endif 4566 } s; 4567 struct cvmx_mio_uartx_srts_s cn30xx; 4568 struct cvmx_mio_uartx_srts_s cn31xx; 4569 struct cvmx_mio_uartx_srts_s cn38xx; 4570 struct cvmx_mio_uartx_srts_s cn38xxp2; 4571 struct cvmx_mio_uartx_srts_s cn50xx; 4572 struct cvmx_mio_uartx_srts_s cn52xx; 4573 struct cvmx_mio_uartx_srts_s cn52xxp1; 4574 struct cvmx_mio_uartx_srts_s cn56xx; 4575 struct cvmx_mio_uartx_srts_s cn56xxp1; 4576 struct cvmx_mio_uartx_srts_s cn58xx; 4577 struct cvmx_mio_uartx_srts_s cn58xxp1; 4578 struct cvmx_mio_uartx_srts_s cn61xx; 4579 struct cvmx_mio_uartx_srts_s cn63xx; 4580 struct cvmx_mio_uartx_srts_s cn63xxp1; 4581 struct cvmx_mio_uartx_srts_s cn66xx; 4582 struct cvmx_mio_uartx_srts_s cn68xx; 4583 struct cvmx_mio_uartx_srts_s cn68xxp1; 4584 struct cvmx_mio_uartx_srts_s cnf71xx; 4585}; 4586 4587union cvmx_mio_uartx_stt { 4588 uint64_t u64; 4589 struct cvmx_mio_uartx_stt_s { 4590#ifdef __BIG_ENDIAN_BITFIELD 4591 uint64_t reserved_2_63:62; 4592 uint64_t stt:2; 4593#else 4594 uint64_t stt:2; 4595 uint64_t reserved_2_63:62; 4596#endif 4597 } s; 4598 struct cvmx_mio_uartx_stt_s cn30xx; 4599 struct cvmx_mio_uartx_stt_s cn31xx; 4600 struct cvmx_mio_uartx_stt_s cn38xx; 4601 struct cvmx_mio_uartx_stt_s cn38xxp2; 4602 struct cvmx_mio_uartx_stt_s cn50xx; 4603 struct cvmx_mio_uartx_stt_s cn52xx; 4604 struct cvmx_mio_uartx_stt_s cn52xxp1; 4605 struct cvmx_mio_uartx_stt_s cn56xx; 4606 struct cvmx_mio_uartx_stt_s cn56xxp1; 4607 struct cvmx_mio_uartx_stt_s cn58xx; 4608 struct cvmx_mio_uartx_stt_s cn58xxp1; 4609 struct cvmx_mio_uartx_stt_s cn61xx; 4610 struct cvmx_mio_uartx_stt_s cn63xx; 4611 struct cvmx_mio_uartx_stt_s cn63xxp1; 4612 struct cvmx_mio_uartx_stt_s cn66xx; 4613 struct cvmx_mio_uartx_stt_s cn68xx; 4614 struct cvmx_mio_uartx_stt_s cn68xxp1; 4615 struct cvmx_mio_uartx_stt_s cnf71xx; 4616}; 4617 4618union cvmx_mio_uartx_tfl { 4619 uint64_t u64; 4620 struct cvmx_mio_uartx_tfl_s { 4621#ifdef __BIG_ENDIAN_BITFIELD 4622 uint64_t reserved_7_63:57; 4623 uint64_t tfl:7; 4624#else 4625 uint64_t tfl:7; 4626 uint64_t reserved_7_63:57; 4627#endif 4628 } s; 4629 struct cvmx_mio_uartx_tfl_s cn30xx; 4630 struct cvmx_mio_uartx_tfl_s cn31xx; 4631 struct cvmx_mio_uartx_tfl_s cn38xx; 4632 struct cvmx_mio_uartx_tfl_s cn38xxp2; 4633 struct cvmx_mio_uartx_tfl_s cn50xx; 4634 struct cvmx_mio_uartx_tfl_s cn52xx; 4635 struct cvmx_mio_uartx_tfl_s cn52xxp1; 4636 struct cvmx_mio_uartx_tfl_s cn56xx; 4637 struct cvmx_mio_uartx_tfl_s cn56xxp1; 4638 struct cvmx_mio_uartx_tfl_s cn58xx; 4639 struct cvmx_mio_uartx_tfl_s cn58xxp1; 4640 struct cvmx_mio_uartx_tfl_s cn61xx; 4641 struct cvmx_mio_uartx_tfl_s cn63xx; 4642 struct cvmx_mio_uartx_tfl_s cn63xxp1; 4643 struct cvmx_mio_uartx_tfl_s cn66xx; 4644 struct cvmx_mio_uartx_tfl_s cn68xx; 4645 struct cvmx_mio_uartx_tfl_s cn68xxp1; 4646 struct cvmx_mio_uartx_tfl_s cnf71xx; 4647}; 4648 4649union cvmx_mio_uartx_tfr { 4650 uint64_t u64; 4651 struct cvmx_mio_uartx_tfr_s { 4652#ifdef __BIG_ENDIAN_BITFIELD 4653 uint64_t reserved_8_63:56; 4654 uint64_t tfr:8; 4655#else 4656 uint64_t tfr:8; 4657 uint64_t reserved_8_63:56; 4658#endif 4659 } s; 4660 struct cvmx_mio_uartx_tfr_s cn30xx; 4661 struct cvmx_mio_uartx_tfr_s cn31xx; 4662 struct cvmx_mio_uartx_tfr_s cn38xx; 4663 struct cvmx_mio_uartx_tfr_s cn38xxp2; 4664 struct cvmx_mio_uartx_tfr_s cn50xx; 4665 struct cvmx_mio_uartx_tfr_s cn52xx; 4666 struct cvmx_mio_uartx_tfr_s cn52xxp1; 4667 struct cvmx_mio_uartx_tfr_s cn56xx; 4668 struct cvmx_mio_uartx_tfr_s cn56xxp1; 4669 struct cvmx_mio_uartx_tfr_s cn58xx; 4670 struct cvmx_mio_uartx_tfr_s cn58xxp1; 4671 struct cvmx_mio_uartx_tfr_s cn61xx; 4672 struct cvmx_mio_uartx_tfr_s cn63xx; 4673 struct cvmx_mio_uartx_tfr_s cn63xxp1; 4674 struct cvmx_mio_uartx_tfr_s cn66xx; 4675 struct cvmx_mio_uartx_tfr_s cn68xx; 4676 struct cvmx_mio_uartx_tfr_s cn68xxp1; 4677 struct cvmx_mio_uartx_tfr_s cnf71xx; 4678}; 4679 4680union cvmx_mio_uartx_thr { 4681 uint64_t u64; 4682 struct cvmx_mio_uartx_thr_s { 4683#ifdef __BIG_ENDIAN_BITFIELD 4684 uint64_t reserved_8_63:56; 4685 uint64_t thr:8; 4686#else 4687 uint64_t thr:8; 4688 uint64_t reserved_8_63:56; 4689#endif 4690 } s; 4691 struct cvmx_mio_uartx_thr_s cn30xx; 4692 struct cvmx_mio_uartx_thr_s cn31xx; 4693 struct cvmx_mio_uartx_thr_s cn38xx; 4694 struct cvmx_mio_uartx_thr_s cn38xxp2; 4695 struct cvmx_mio_uartx_thr_s cn50xx; 4696 struct cvmx_mio_uartx_thr_s cn52xx; 4697 struct cvmx_mio_uartx_thr_s cn52xxp1; 4698 struct cvmx_mio_uartx_thr_s cn56xx; 4699 struct cvmx_mio_uartx_thr_s cn56xxp1; 4700 struct cvmx_mio_uartx_thr_s cn58xx; 4701 struct cvmx_mio_uartx_thr_s cn58xxp1; 4702 struct cvmx_mio_uartx_thr_s cn61xx; 4703 struct cvmx_mio_uartx_thr_s cn63xx; 4704 struct cvmx_mio_uartx_thr_s cn63xxp1; 4705 struct cvmx_mio_uartx_thr_s cn66xx; 4706 struct cvmx_mio_uartx_thr_s cn68xx; 4707 struct cvmx_mio_uartx_thr_s cn68xxp1; 4708 struct cvmx_mio_uartx_thr_s cnf71xx; 4709}; 4710 4711union cvmx_mio_uartx_usr { 4712 uint64_t u64; 4713 struct cvmx_mio_uartx_usr_s { 4714#ifdef __BIG_ENDIAN_BITFIELD 4715 uint64_t reserved_5_63:59; 4716 uint64_t rff:1; 4717 uint64_t rfne:1; 4718 uint64_t tfe:1; 4719 uint64_t tfnf:1; 4720 uint64_t busy:1; 4721#else 4722 uint64_t busy:1; 4723 uint64_t tfnf:1; 4724 uint64_t tfe:1; 4725 uint64_t rfne:1; 4726 uint64_t rff:1; 4727 uint64_t reserved_5_63:59; 4728#endif 4729 } s; 4730 struct cvmx_mio_uartx_usr_s cn30xx; 4731 struct cvmx_mio_uartx_usr_s cn31xx; 4732 struct cvmx_mio_uartx_usr_s cn38xx; 4733 struct cvmx_mio_uartx_usr_s cn38xxp2; 4734 struct cvmx_mio_uartx_usr_s cn50xx; 4735 struct cvmx_mio_uartx_usr_s cn52xx; 4736 struct cvmx_mio_uartx_usr_s cn52xxp1; 4737 struct cvmx_mio_uartx_usr_s cn56xx; 4738 struct cvmx_mio_uartx_usr_s cn56xxp1; 4739 struct cvmx_mio_uartx_usr_s cn58xx; 4740 struct cvmx_mio_uartx_usr_s cn58xxp1; 4741 struct cvmx_mio_uartx_usr_s cn61xx; 4742 struct cvmx_mio_uartx_usr_s cn63xx; 4743 struct cvmx_mio_uartx_usr_s cn63xxp1; 4744 struct cvmx_mio_uartx_usr_s cn66xx; 4745 struct cvmx_mio_uartx_usr_s cn68xx; 4746 struct cvmx_mio_uartx_usr_s cn68xxp1; 4747 struct cvmx_mio_uartx_usr_s cnf71xx; 4748}; 4749 4750union cvmx_mio_uart2_dlh { 4751 uint64_t u64; 4752 struct cvmx_mio_uart2_dlh_s { 4753#ifdef __BIG_ENDIAN_BITFIELD 4754 uint64_t reserved_8_63:56; 4755 uint64_t dlh:8; 4756#else 4757 uint64_t dlh:8; 4758 uint64_t reserved_8_63:56; 4759#endif 4760 } s; 4761 struct cvmx_mio_uart2_dlh_s cn52xx; 4762 struct cvmx_mio_uart2_dlh_s cn52xxp1; 4763}; 4764 4765union cvmx_mio_uart2_dll { 4766 uint64_t u64; 4767 struct cvmx_mio_uart2_dll_s { 4768#ifdef __BIG_ENDIAN_BITFIELD 4769 uint64_t reserved_8_63:56; 4770 uint64_t dll:8; 4771#else 4772 uint64_t dll:8; 4773 uint64_t reserved_8_63:56; 4774#endif 4775 } s; 4776 struct cvmx_mio_uart2_dll_s cn52xx; 4777 struct cvmx_mio_uart2_dll_s cn52xxp1; 4778}; 4779 4780union cvmx_mio_uart2_far { 4781 uint64_t u64; 4782 struct cvmx_mio_uart2_far_s { 4783#ifdef __BIG_ENDIAN_BITFIELD 4784 uint64_t reserved_1_63:63; 4785 uint64_t far:1; 4786#else 4787 uint64_t far:1; 4788 uint64_t reserved_1_63:63; 4789#endif 4790 } s; 4791 struct cvmx_mio_uart2_far_s cn52xx; 4792 struct cvmx_mio_uart2_far_s cn52xxp1; 4793}; 4794 4795union cvmx_mio_uart2_fcr { 4796 uint64_t u64; 4797 struct cvmx_mio_uart2_fcr_s { 4798#ifdef __BIG_ENDIAN_BITFIELD 4799 uint64_t reserved_8_63:56; 4800 uint64_t rxtrig:2; 4801 uint64_t txtrig:2; 4802 uint64_t reserved_3_3:1; 4803 uint64_t txfr:1; 4804 uint64_t rxfr:1; 4805 uint64_t en:1; 4806#else 4807 uint64_t en:1; 4808 uint64_t rxfr:1; 4809 uint64_t txfr:1; 4810 uint64_t reserved_3_3:1; 4811 uint64_t txtrig:2; 4812 uint64_t rxtrig:2; 4813 uint64_t reserved_8_63:56; 4814#endif 4815 } s; 4816 struct cvmx_mio_uart2_fcr_s cn52xx; 4817 struct cvmx_mio_uart2_fcr_s cn52xxp1; 4818}; 4819 4820union cvmx_mio_uart2_htx { 4821 uint64_t u64; 4822 struct cvmx_mio_uart2_htx_s { 4823#ifdef __BIG_ENDIAN_BITFIELD 4824 uint64_t reserved_1_63:63; 4825 uint64_t htx:1; 4826#else 4827 uint64_t htx:1; 4828 uint64_t reserved_1_63:63; 4829#endif 4830 } s; 4831 struct cvmx_mio_uart2_htx_s cn52xx; 4832 struct cvmx_mio_uart2_htx_s cn52xxp1; 4833}; 4834 4835union cvmx_mio_uart2_ier { 4836 uint64_t u64; 4837 struct cvmx_mio_uart2_ier_s { 4838#ifdef __BIG_ENDIAN_BITFIELD 4839 uint64_t reserved_8_63:56; 4840 uint64_t ptime:1; 4841 uint64_t reserved_4_6:3; 4842 uint64_t edssi:1; 4843 uint64_t elsi:1; 4844 uint64_t etbei:1; 4845 uint64_t erbfi:1; 4846#else 4847 uint64_t erbfi:1; 4848 uint64_t etbei:1; 4849 uint64_t elsi:1; 4850 uint64_t edssi:1; 4851 uint64_t reserved_4_6:3; 4852 uint64_t ptime:1; 4853 uint64_t reserved_8_63:56; 4854#endif 4855 } s; 4856 struct cvmx_mio_uart2_ier_s cn52xx; 4857 struct cvmx_mio_uart2_ier_s cn52xxp1; 4858}; 4859 4860union cvmx_mio_uart2_iir { 4861 uint64_t u64; 4862 struct cvmx_mio_uart2_iir_s { 4863#ifdef __BIG_ENDIAN_BITFIELD 4864 uint64_t reserved_8_63:56; 4865 uint64_t fen:2; 4866 uint64_t reserved_4_5:2; 4867 uint64_t iid:4; 4868#else 4869 uint64_t iid:4; 4870 uint64_t reserved_4_5:2; 4871 uint64_t fen:2; 4872 uint64_t reserved_8_63:56; 4873#endif 4874 } s; 4875 struct cvmx_mio_uart2_iir_s cn52xx; 4876 struct cvmx_mio_uart2_iir_s cn52xxp1; 4877}; 4878 4879union cvmx_mio_uart2_lcr { 4880 uint64_t u64; 4881 struct cvmx_mio_uart2_lcr_s { 4882#ifdef __BIG_ENDIAN_BITFIELD 4883 uint64_t reserved_8_63:56; 4884 uint64_t dlab:1; 4885 uint64_t brk:1; 4886 uint64_t reserved_5_5:1; 4887 uint64_t eps:1; 4888 uint64_t pen:1; 4889 uint64_t stop:1; 4890 uint64_t cls:2; 4891#else 4892 uint64_t cls:2; 4893 uint64_t stop:1; 4894 uint64_t pen:1; 4895 uint64_t eps:1; 4896 uint64_t reserved_5_5:1; 4897 uint64_t brk:1; 4898 uint64_t dlab:1; 4899 uint64_t reserved_8_63:56; 4900#endif 4901 } s; 4902 struct cvmx_mio_uart2_lcr_s cn52xx; 4903 struct cvmx_mio_uart2_lcr_s cn52xxp1; 4904}; 4905 4906union cvmx_mio_uart2_lsr { 4907 uint64_t u64; 4908 struct cvmx_mio_uart2_lsr_s { 4909#ifdef __BIG_ENDIAN_BITFIELD 4910 uint64_t reserved_8_63:56; 4911 uint64_t ferr:1; 4912 uint64_t temt:1; 4913 uint64_t thre:1; 4914 uint64_t bi:1; 4915 uint64_t fe:1; 4916 uint64_t pe:1; 4917 uint64_t oe:1; 4918 uint64_t dr:1; 4919#else 4920 uint64_t dr:1; 4921 uint64_t oe:1; 4922 uint64_t pe:1; 4923 uint64_t fe:1; 4924 uint64_t bi:1; 4925 uint64_t thre:1; 4926 uint64_t temt:1; 4927 uint64_t ferr:1; 4928 uint64_t reserved_8_63:56; 4929#endif 4930 } s; 4931 struct cvmx_mio_uart2_lsr_s cn52xx; 4932 struct cvmx_mio_uart2_lsr_s cn52xxp1; 4933}; 4934 4935union cvmx_mio_uart2_mcr { 4936 uint64_t u64; 4937 struct cvmx_mio_uart2_mcr_s { 4938#ifdef __BIG_ENDIAN_BITFIELD 4939 uint64_t reserved_6_63:58; 4940 uint64_t afce:1; 4941 uint64_t loop:1; 4942 uint64_t out2:1; 4943 uint64_t out1:1; 4944 uint64_t rts:1; 4945 uint64_t dtr:1; 4946#else 4947 uint64_t dtr:1; 4948 uint64_t rts:1; 4949 uint64_t out1:1; 4950 uint64_t out2:1; 4951 uint64_t loop:1; 4952 uint64_t afce:1; 4953 uint64_t reserved_6_63:58; 4954#endif 4955 } s; 4956 struct cvmx_mio_uart2_mcr_s cn52xx; 4957 struct cvmx_mio_uart2_mcr_s cn52xxp1; 4958}; 4959 4960union cvmx_mio_uart2_msr { 4961 uint64_t u64; 4962 struct cvmx_mio_uart2_msr_s { 4963#ifdef __BIG_ENDIAN_BITFIELD 4964 uint64_t reserved_8_63:56; 4965 uint64_t dcd:1; 4966 uint64_t ri:1; 4967 uint64_t dsr:1; 4968 uint64_t cts:1; 4969 uint64_t ddcd:1; 4970 uint64_t teri:1; 4971 uint64_t ddsr:1; 4972 uint64_t dcts:1; 4973#else 4974 uint64_t dcts:1; 4975 uint64_t ddsr:1; 4976 uint64_t teri:1; 4977 uint64_t ddcd:1; 4978 uint64_t cts:1; 4979 uint64_t dsr:1; 4980 uint64_t ri:1; 4981 uint64_t dcd:1; 4982 uint64_t reserved_8_63:56; 4983#endif 4984 } s; 4985 struct cvmx_mio_uart2_msr_s cn52xx; 4986 struct cvmx_mio_uart2_msr_s cn52xxp1; 4987}; 4988 4989union cvmx_mio_uart2_rbr { 4990 uint64_t u64; 4991 struct cvmx_mio_uart2_rbr_s { 4992#ifdef __BIG_ENDIAN_BITFIELD 4993 uint64_t reserved_8_63:56; 4994 uint64_t rbr:8; 4995#else 4996 uint64_t rbr:8; 4997 uint64_t reserved_8_63:56; 4998#endif 4999 } s; 5000 struct cvmx_mio_uart2_rbr_s cn52xx;
5001 struct cvmx_mio_uart2_rbr_s cn52xxp1; 5002}; 5003 5004union cvmx_mio_uart2_rfl { 5005 uint64_t u64; 5006 struct cvmx_mio_uart2_rfl_s { 5007#ifdef __BIG_ENDIAN_BITFIELD 5008 uint64_t reserved_7_63:57; 5009 uint64_t rfl:7; 5010#else 5011 uint64_t rfl:7; 5012 uint64_t reserved_7_63:57; 5013#endif 5014 } s; 5015 struct cvmx_mio_uart2_rfl_s cn52xx; 5016 struct cvmx_mio_uart2_rfl_s cn52xxp1; 5017}; 5018 5019union cvmx_mio_uart2_rfw { 5020 uint64_t u64; 5021 struct cvmx_mio_uart2_rfw_s { 5022#ifdef __BIG_ENDIAN_BITFIELD 5023 uint64_t reserved_10_63:54; 5024 uint64_t rffe:1; 5025 uint64_t rfpe:1; 5026 uint64_t rfwd:8; 5027#else 5028 uint64_t rfwd:8; 5029 uint64_t rfpe:1; 5030 uint64_t rffe:1; 5031 uint64_t reserved_10_63:54; 5032#endif 5033 } s; 5034 struct cvmx_mio_uart2_rfw_s cn52xx; 5035 struct cvmx_mio_uart2_rfw_s cn52xxp1; 5036}; 5037 5038union cvmx_mio_uart2_sbcr { 5039 uint64_t u64; 5040 struct cvmx_mio_uart2_sbcr_s { 5041#ifdef __BIG_ENDIAN_BITFIELD 5042 uint64_t reserved_1_63:63; 5043 uint64_t sbcr:1; 5044#else 5045 uint64_t sbcr:1; 5046 uint64_t reserved_1_63:63; 5047#endif 5048 } s; 5049 struct cvmx_mio_uart2_sbcr_s cn52xx; 5050 struct cvmx_mio_uart2_sbcr_s cn52xxp1; 5051}; 5052 5053union cvmx_mio_uart2_scr { 5054 uint64_t u64; 5055 struct cvmx_mio_uart2_scr_s { 5056#ifdef __BIG_ENDIAN_BITFIELD 5057 uint64_t reserved_8_63:56; 5058 uint64_t scr:8; 5059#else 5060 uint64_t scr:8; 5061 uint64_t reserved_8_63:56; 5062#endif 5063 } s; 5064 struct cvmx_mio_uart2_scr_s cn52xx; 5065 struct cvmx_mio_uart2_scr_s cn52xxp1; 5066}; 5067 5068union cvmx_mio_uart2_sfe { 5069 uint64_t u64; 5070 struct cvmx_mio_uart2_sfe_s { 5071#ifdef __BIG_ENDIAN_BITFIELD 5072 uint64_t reserved_1_63:63; 5073 uint64_t sfe:1; 5074#else 5075 uint64_t sfe:1; 5076 uint64_t reserved_1_63:63; 5077#endif 5078 } s; 5079 struct cvmx_mio_uart2_sfe_s cn52xx; 5080 struct cvmx_mio_uart2_sfe_s cn52xxp1; 5081}; 5082 5083union cvmx_mio_uart2_srr { 5084 uint64_t u64; 5085 struct cvmx_mio_uart2_srr_s { 5086#ifdef __BIG_ENDIAN_BITFIELD 5087 uint64_t reserved_3_63:61; 5088 uint64_t stfr:1; 5089 uint64_t srfr:1; 5090 uint64_t usr:1; 5091#else 5092 uint64_t usr:1; 5093 uint64_t srfr:1; 5094 uint64_t stfr:1; 5095 uint64_t reserved_3_63:61; 5096#endif 5097 } s; 5098 struct cvmx_mio_uart2_srr_s cn52xx; 5099 struct cvmx_mio_uart2_srr_s cn52xxp1; 5100}; 5101 5102union cvmx_mio_uart2_srt { 5103 uint64_t u64; 5104 struct cvmx_mio_uart2_srt_s { 5105#ifdef __BIG_ENDIAN_BITFIELD 5106 uint64_t reserved_2_63:62; 5107 uint64_t srt:2; 5108#else 5109 uint64_t srt:2; 5110 uint64_t reserved_2_63:62; 5111#endif 5112 } s; 5113 struct cvmx_mio_uart2_srt_s cn52xx; 5114 struct cvmx_mio_uart2_srt_s cn52xxp1; 5115}; 5116 5117union cvmx_mio_uart2_srts { 5118 uint64_t u64; 5119 struct cvmx_mio_uart2_srts_s { 5120#ifdef __BIG_ENDIAN_BITFIELD 5121 uint64_t reserved_1_63:63; 5122 uint64_t srts:1; 5123#else 5124 uint64_t srts:1; 5125 uint64_t reserved_1_63:63; 5126#endif 5127 } s; 5128 struct cvmx_mio_uart2_srts_s cn52xx; 5129 struct cvmx_mio_uart2_srts_s cn52xxp1; 5130}; 5131 5132union cvmx_mio_uart2_stt { 5133 uint64_t u64; 5134 struct cvmx_mio_uart2_stt_s { 5135#ifdef __BIG_ENDIAN_BITFIELD 5136 uint64_t reserved_2_63:62; 5137 uint64_t stt:2; 5138#else 5139 uint64_t stt:2; 5140 uint64_t reserved_2_63:62; 5141#endif 5142 } s; 5143 struct cvmx_mio_uart2_stt_s cn52xx; 5144 struct cvmx_mio_uart2_stt_s cn52xxp1; 5145}; 5146 5147union cvmx_mio_uart2_tfl { 5148 uint64_t u64; 5149 struct cvmx_mio_uart2_tfl_s { 5150#ifdef __BIG_ENDIAN_BITFIELD 5151 uint64_t reserved_7_63:57; 5152 uint64_t tfl:7; 5153#else 5154 uint64_t tfl:7; 5155 uint64_t reserved_7_63:57; 5156#endif 5157 } s; 5158 struct cvmx_mio_uart2_tfl_s cn52xx; 5159 struct cvmx_mio_uart2_tfl_s cn52xxp1; 5160}; 5161 5162union cvmx_mio_uart2_tfr { 5163 uint64_t u64; 5164 struct cvmx_mio_uart2_tfr_s { 5165#ifdef __BIG_ENDIAN_BITFIELD 5166 uint64_t reserved_8_63:56; 5167 uint64_t tfr:8; 5168#else 5169 uint64_t tfr:8; 5170 uint64_t reserved_8_63:56; 5171#endif 5172 } s; 5173 struct cvmx_mio_uart2_tfr_s cn52xx; 5174 struct cvmx_mio_uart2_tfr_s cn52xxp1; 5175}; 5176 5177union cvmx_mio_uart2_thr { 5178 uint64_t u64; 5179 struct cvmx_mio_uart2_thr_s { 5180#ifdef __BIG_ENDIAN_BITFIELD 5181 uint64_t reserved_8_63:56; 5182 uint64_t thr:8; 5183#else 5184 uint64_t thr:8; 5185 uint64_t reserved_8_63:56; 5186#endif 5187 } s; 5188 struct cvmx_mio_uart2_thr_s cn52xx; 5189 struct cvmx_mio_uart2_thr_s cn52xxp1; 5190}; 5191 5192union cvmx_mio_uart2_usr { 5193 uint64_t u64; 5194 struct cvmx_mio_uart2_usr_s { 5195#ifdef __BIG_ENDIAN_BITFIELD 5196 uint64_t reserved_5_63:59; 5197 uint64_t rff:1; 5198 uint64_t rfne:1; 5199 uint64_t tfe:1; 5200 uint64_t tfnf:1; 5201 uint64_t busy:1; 5202#else 5203 uint64_t busy:1; 5204 uint64_t tfnf:1; 5205 uint64_t tfe:1; 5206 uint64_t rfne:1; 5207 uint64_t rff:1; 5208 uint64_t reserved_5_63:59; 5209#endif 5210 } s; 5211 struct cvmx_mio_uart2_usr_s cn52xx; 5212 struct cvmx_mio_uart2_usr_s cn52xxp1; 5213}; 5214 5215#endif 5216