1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_MIXX_DEFS_H__ 29#define __CVMX_MIXX_DEFS_H__ 30 31#define CVMX_MIXX_BIST(offset) (CVMX_ADD_IO_SEG(0x0001070000100078ull) + ((offset) & 1) * 2048) 32#define CVMX_MIXX_CTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100020ull) + ((offset) & 1) * 2048) 33#define CVMX_MIXX_INTENA(offset) (CVMX_ADD_IO_SEG(0x0001070000100050ull) + ((offset) & 1) * 2048) 34#define CVMX_MIXX_IRCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100030ull) + ((offset) & 1) * 2048) 35#define CVMX_MIXX_IRHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100028ull) + ((offset) & 1) * 2048) 36#define CVMX_MIXX_IRING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100010ull) + ((offset) & 1) * 2048) 37#define CVMX_MIXX_IRING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100018ull) + ((offset) & 1) * 2048) 38#define CVMX_MIXX_ISR(offset) (CVMX_ADD_IO_SEG(0x0001070000100048ull) + ((offset) & 1) * 2048) 39#define CVMX_MIXX_ORCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100040ull) + ((offset) & 1) * 2048) 40#define CVMX_MIXX_ORHWM(offset) (CVMX_ADD_IO_SEG(0x0001070000100038ull) + ((offset) & 1) * 2048) 41#define CVMX_MIXX_ORING1(offset) (CVMX_ADD_IO_SEG(0x0001070000100000ull) + ((offset) & 1) * 2048) 42#define CVMX_MIXX_ORING2(offset) (CVMX_ADD_IO_SEG(0x0001070000100008ull) + ((offset) & 1) * 2048) 43#define CVMX_MIXX_REMCNT(offset) (CVMX_ADD_IO_SEG(0x0001070000100058ull) + ((offset) & 1) * 2048) 44#define CVMX_MIXX_TSCTL(offset) (CVMX_ADD_IO_SEG(0x0001070000100068ull) + ((offset) & 1) * 2048) 45#define CVMX_MIXX_TSTAMP(offset) (CVMX_ADD_IO_SEG(0x0001070000100060ull) + ((offset) & 1) * 2048) 46 47union cvmx_mixx_bist { 48 uint64_t u64; 49 struct cvmx_mixx_bist_s { 50#ifdef __BIG_ENDIAN_BITFIELD 51 uint64_t reserved_6_63:58; 52 uint64_t opfdat:1; 53 uint64_t mrgdat:1; 54 uint64_t mrqdat:1; 55 uint64_t ipfdat:1; 56 uint64_t irfdat:1; 57 uint64_t orfdat:1; 58#else 59 uint64_t orfdat:1; 60 uint64_t irfdat:1; 61 uint64_t ipfdat:1; 62 uint64_t mrqdat:1; 63 uint64_t mrgdat:1; 64 uint64_t opfdat:1; 65 uint64_t reserved_6_63:58; 66#endif 67 } s; 68 struct cvmx_mixx_bist_cn52xx { 69#ifdef __BIG_ENDIAN_BITFIELD 70 uint64_t reserved_4_63:60; 71 uint64_t mrqdat:1; 72 uint64_t ipfdat:1; 73 uint64_t irfdat:1; 74 uint64_t orfdat:1; 75#else 76 uint64_t orfdat:1; 77 uint64_t irfdat:1; 78 uint64_t ipfdat:1; 79 uint64_t mrqdat:1; 80 uint64_t reserved_4_63:60; 81#endif 82 } cn52xx; 83 struct cvmx_mixx_bist_cn52xx cn52xxp1; 84 struct cvmx_mixx_bist_cn52xx cn56xx; 85 struct cvmx_mixx_bist_cn52xx cn56xxp1; 86 struct cvmx_mixx_bist_s cn61xx; 87 struct cvmx_mixx_bist_s cn63xx; 88 struct cvmx_mixx_bist_s cn63xxp1; 89 struct cvmx_mixx_bist_s cn66xx; 90 struct cvmx_mixx_bist_s cn68xx; 91 struct cvmx_mixx_bist_s cn68xxp1; 92}; 93 94union cvmx_mixx_ctl { 95 uint64_t u64; 96 struct cvmx_mixx_ctl_s { 97#ifdef __BIG_ENDIAN_BITFIELD 98 uint64_t reserved_12_63:52; 99 uint64_t ts_thresh:4; 100 uint64_t crc_strip:1; 101 uint64_t busy:1; 102 uint64_t en:1; 103 uint64_t reset:1; 104 uint64_t lendian:1; 105 uint64_t nbtarb:1; 106 uint64_t mrq_hwm:2; 107#else 108 uint64_t mrq_hwm:2; 109 uint64_t nbtarb:1; 110 uint64_t lendian:1; 111 uint64_t reset:1; 112 uint64_t en:1; 113 uint64_t busy:1; 114 uint64_t crc_strip:1; 115 uint64_t ts_thresh:4; 116 uint64_t reserved_12_63:52; 117#endif 118 } s; 119 struct cvmx_mixx_ctl_cn52xx { 120#ifdef __BIG_ENDIAN_BITFIELD 121 uint64_t reserved_8_63:56; 122 uint64_t crc_strip:1; 123 uint64_t busy:1; 124 uint64_t en:1; 125 uint64_t reset:1; 126 uint64_t lendian:1; 127 uint64_t nbtarb:1; 128 uint64_t mrq_hwm:2; 129#else 130 uint64_t mrq_hwm:2; 131 uint64_t nbtarb:1; 132 uint64_t lendian:1; 133 uint64_t reset:1; 134 uint64_t en:1; 135 uint64_t busy:1; 136 uint64_t crc_strip:1; 137 uint64_t reserved_8_63:56; 138#endif 139 } cn52xx; 140 struct cvmx_mixx_ctl_cn52xx cn52xxp1; 141 struct cvmx_mixx_ctl_cn52xx cn56xx; 142 struct cvmx_mixx_ctl_cn52xx cn56xxp1; 143 struct cvmx_mixx_ctl_s cn61xx; 144 struct cvmx_mixx_ctl_s cn63xx; 145 struct cvmx_mixx_ctl_s cn63xxp1; 146 struct cvmx_mixx_ctl_s cn66xx; 147 struct cvmx_mixx_ctl_s cn68xx; 148 struct cvmx_mixx_ctl_s cn68xxp1; 149}; 150 151union cvmx_mixx_intena { 152 uint64_t u64; 153 struct cvmx_mixx_intena_s { 154#ifdef __BIG_ENDIAN_BITFIELD 155 uint64_t reserved_8_63:56; 156 uint64_t tsena:1; 157 uint64_t orunena:1; 158 uint64_t irunena:1; 159 uint64_t data_drpena:1; 160 uint64_t ithena:1; 161 uint64_t othena:1; 162 uint64_t ivfena:1; 163 uint64_t ovfena:1; 164#else 165 uint64_t ovfena:1; 166 uint64_t ivfena:1; 167 uint64_t othena:1; 168 uint64_t ithena:1; 169 uint64_t data_drpena:1; 170 uint64_t irunena:1; 171 uint64_t orunena:1; 172 uint64_t tsena:1; 173 uint64_t reserved_8_63:56; 174#endif 175 } s; 176 struct cvmx_mixx_intena_cn52xx { 177#ifdef __BIG_ENDIAN_BITFIELD 178 uint64_t reserved_7_63:57; 179 uint64_t orunena:1; 180 uint64_t irunena:1; 181 uint64_t data_drpena:1; 182 uint64_t ithena:1; 183 uint64_t othena:1; 184 uint64_t ivfena:1; 185 uint64_t ovfena:1; 186#else 187 uint64_t ovfena:1; 188 uint64_t ivfena:1; 189 uint64_t othena:1; 190 uint64_t ithena:1; 191 uint64_t data_drpena:1; 192 uint64_t irunena:1; 193 uint64_t orunena:1; 194 uint64_t reserved_7_63:57; 195#endif 196 } cn52xx; 197 struct cvmx_mixx_intena_cn52xx cn52xxp1; 198 struct cvmx_mixx_intena_cn52xx cn56xx; 199 struct cvmx_mixx_intena_cn52xx cn56xxp1; 200 struct cvmx_mixx_intena_s cn61xx; 201 struct cvmx_mixx_intena_s cn63xx; 202 struct cvmx_mixx_intena_s cn63xxp1; 203 struct cvmx_mixx_intena_s cn66xx; 204 struct cvmx_mixx_intena_s cn68xx; 205 struct cvmx_mixx_intena_s cn68xxp1; 206}; 207 208union cvmx_mixx_ircnt { 209 uint64_t u64; 210 struct cvmx_mixx_ircnt_s { 211#ifdef __BIG_ENDIAN_BITFIELD 212 uint64_t reserved_20_63:44; 213 uint64_t ircnt:20; 214#else 215 uint64_t ircnt:20; 216 uint64_t reserved_20_63:44; 217#endif 218 } s; 219 struct cvmx_mixx_ircnt_s cn52xx; 220 struct cvmx_mixx_ircnt_s cn52xxp1; 221 struct cvmx_mixx_ircnt_s cn56xx; 222 struct cvmx_mixx_ircnt_s cn56xxp1; 223 struct cvmx_mixx_ircnt_s cn61xx; 224 struct cvmx_mixx_ircnt_s cn63xx; 225 struct cvmx_mixx_ircnt_s cn63xxp1; 226 struct cvmx_mixx_ircnt_s cn66xx; 227 struct cvmx_mixx_ircnt_s cn68xx; 228 struct cvmx_mixx_ircnt_s cn68xxp1; 229}; 230 231union cvmx_mixx_irhwm { 232 uint64_t u64; 233 struct cvmx_mixx_irhwm_s { 234#ifdef __BIG_ENDIAN_BITFIELD 235 uint64_t reserved_40_63:24; 236 uint64_t ibplwm:20; 237 uint64_t irhwm:20; 238#else 239 uint64_t irhwm:20; 240 uint64_t ibplwm:20; 241 uint64_t reserved_40_63:24; 242#endif 243 } s; 244 struct cvmx_mixx_irhwm_s cn52xx; 245 struct cvmx_mixx_irhwm_s cn52xxp1; 246 struct cvmx_mixx_irhwm_s cn56xx; 247 struct cvmx_mixx_irhwm_s cn56xxp1; 248 struct cvmx_mixx_irhwm_s cn61xx; 249 struct cvmx_mixx_irhwm_s cn63xx; 250 struct cvmx_mixx_irhwm_s cn63xxp1; 251 struct cvmx_mixx_irhwm_s cn66xx; 252 struct cvmx_mixx_irhwm_s cn68xx; 253 struct cvmx_mixx_irhwm_s cn68xxp1; 254}; 255 256union cvmx_mixx_iring1 { 257 uint64_t u64; 258 struct cvmx_mixx_iring1_s { 259#ifdef __BIG_ENDIAN_BITFIELD 260 uint64_t reserved_60_63:4; 261 uint64_t isize:20; 262 uint64_t ibase:37; 263 uint64_t reserved_0_2:3; 264#else 265 uint64_t reserved_0_2:3; 266 uint64_t ibase:37; 267 uint64_t isize:20; 268 uint64_t reserved_60_63:4; 269#endif 270 } s; 271 struct cvmx_mixx_iring1_cn52xx { 272#ifdef __BIG_ENDIAN_BITFIELD 273 uint64_t reserved_60_63:4; 274 uint64_t isize:20; 275 uint64_t reserved_36_39:4; 276 uint64_t ibase:33; 277 uint64_t reserved_0_2:3; 278#else 279 uint64_t reserved_0_2:3; 280 uint64_t ibase:33; 281 uint64_t reserved_36_39:4; 282 uint64_t isize:20; 283 uint64_t reserved_60_63:4; 284#endif 285 } cn52xx; 286 struct cvmx_mixx_iring1_cn52xx cn52xxp1; 287 struct cvmx_mixx_iring1_cn52xx cn56xx; 288 struct cvmx_mixx_iring1_cn52xx cn56xxp1; 289 struct cvmx_mixx_iring1_s cn61xx; 290 struct cvmx_mixx_iring1_s cn63xx; 291 struct cvmx_mixx_iring1_s cn63xxp1; 292 struct cvmx_mixx_iring1_s cn66xx; 293 struct cvmx_mixx_iring1_s cn68xx; 294 struct cvmx_mixx_iring1_s cn68xxp1; 295}; 296 297union cvmx_mixx_iring2 { 298 uint64_t u64; 299 struct cvmx_mixx_iring2_s { 300#ifdef __BIG_ENDIAN_BITFIELD 301 uint64_t reserved_52_63:12; 302 uint64_t itlptr:20; 303 uint64_t reserved_20_31:12; 304 uint64_t idbell:20; 305#else 306 uint64_t idbell:20; 307 uint64_t reserved_20_31:12; 308 uint64_t itlptr:20; 309 uint64_t reserved_52_63:12; 310#endif 311 } s; 312 struct cvmx_mixx_iring2_s cn52xx; 313 struct cvmx_mixx_iring2_s cn52xxp1; 314 struct cvmx_mixx_iring2_s cn56xx; 315 struct cvmx_mixx_iring2_s cn56xxp1; 316 struct cvmx_mixx_iring2_s cn61xx; 317 struct cvmx_mixx_iring2_s cn63xx; 318 struct cvmx_mixx_iring2_s cn63xxp1; 319 struct cvmx_mixx_iring2_s cn66xx; 320 struct cvmx_mixx_iring2_s cn68xx; 321 struct cvmx_mixx_iring2_s cn68xxp1; 322}; 323 324union cvmx_mixx_isr { 325 uint64_t u64; 326 struct cvmx_mixx_isr_s { 327#ifdef __BIG_ENDIAN_BITFIELD 328 uint64_t reserved_8_63:56; 329 uint64_t ts:1; 330 uint64_t orun:1; 331 uint64_t irun:1; 332 uint64_t data_drp:1; 333 uint64_t irthresh:1; 334 uint64_t orthresh:1; 335 uint64_t idblovf:1; 336 uint64_t odblovf:1; 337#else 338 uint64_t odblovf:1; 339 uint64_t idblovf:1; 340 uint64_t orthresh:1; 341 uint64_t irthresh:1; 342 uint64_t data_drp:1; 343 uint64_t irun:1; 344 uint64_t orun:1; 345 uint64_t ts:1; 346 uint64_t reserved_8_63:56; 347#endif 348 } s; 349 struct cvmx_mixx_isr_cn52xx { 350#ifdef __BIG_ENDIAN_BITFIELD 351 uint64_t reserved_7_63:57; 352 uint64_t orun:1; 353 uint64_t irun:1; 354 uint64_t data_drp:1; 355 uint64_t irthresh:1; 356 uint64_t orthresh:1; 357 uint64_t idblovf:1; 358 uint64_t odblovf:1; 359#else 360 uint64_t odblovf:1; 361 uint64_t idblovf:1; 362 uint64_t orthresh:1; 363 uint64_t irthresh:1; 364 uint64_t data_drp:1; 365 uint64_t irun:1; 366 uint64_t orun:1; 367 uint64_t reserved_7_63:57; 368#endif 369 } cn52xx; 370 struct cvmx_mixx_isr_cn52xx cn52xxp1; 371 struct cvmx_mixx_isr_cn52xx cn56xx; 372 struct cvmx_mixx_isr_cn52xx cn56xxp1; 373 struct cvmx_mixx_isr_s cn61xx; 374 struct cvmx_mixx_isr_s cn63xx; 375 struct cvmx_mixx_isr_s cn63xxp1; 376 struct cvmx_mixx_isr_s cn66xx; 377 struct cvmx_mixx_isr_s cn68xx; 378 struct cvmx_mixx_isr_s cn68xxp1; 379}; 380 381union cvmx_mixx_orcnt { 382 uint64_t u64; 383 struct cvmx_mixx_orcnt_s { 384#ifdef __BIG_ENDIAN_BITFIELD 385 uint64_t reserved_20_63:44; 386 uint64_t orcnt:20; 387#else 388 uint64_t orcnt:20; 389 uint64_t reserved_20_63:44; 390#endif 391 } s; 392 struct cvmx_mixx_orcnt_s cn52xx; 393 struct cvmx_mixx_orcnt_s cn52xxp1; 394 struct cvmx_mixx_orcnt_s cn56xx; 395 struct cvmx_mixx_orcnt_s cn56xxp1; 396 struct cvmx_mixx_orcnt_s cn61xx; 397 struct cvmx_mixx_orcnt_s cn63xx; 398 struct cvmx_mixx_orcnt_s cn63xxp1; 399 struct cvmx_mixx_orcnt_s cn66xx; 400 struct cvmx_mixx_orcnt_s cn68xx; 401 struct cvmx_mixx_orcnt_s cn68xxp1; 402}; 403 404union cvmx_mixx_orhwm { 405 uint64_t u64; 406 struct cvmx_mixx_orhwm_s { 407#ifdef __BIG_ENDIAN_BITFIELD 408 uint64_t reserved_20_63:44; 409 uint64_t orhwm:20; 410#else 411 uint64_t orhwm:20; 412 uint64_t reserved_20_63:44; 413#endif 414 } s; 415 struct cvmx_mixx_orhwm_s cn52xx; 416 struct cvmx_mixx_orhwm_s cn52xxp1; 417 struct cvmx_mixx_orhwm_s cn56xx; 418 struct cvmx_mixx_orhwm_s cn56xxp1; 419 struct cvmx_mixx_orhwm_s cn61xx; 420 struct cvmx_mixx_orhwm_s cn63xx; 421 struct cvmx_mixx_orhwm_s cn63xxp1; 422 struct cvmx_mixx_orhwm_s cn66xx; 423 struct cvmx_mixx_orhwm_s cn68xx; 424 struct cvmx_mixx_orhwm_s cn68xxp1; 425}; 426 427union cvmx_mixx_oring1 { 428 uint64_t u64; 429 struct cvmx_mixx_oring1_s { 430#ifdef __BIG_ENDIAN_BITFIELD 431 uint64_t reserved_60_63:4; 432 uint64_t osize:20; 433 uint64_t obase:37; 434 uint64_t reserved_0_2:3; 435#else 436 uint64_t reserved_0_2:3; 437 uint64_t obase:37; 438 uint64_t osize:20; 439 uint64_t reserved_60_63:4; 440#endif 441 } s; 442 struct cvmx_mixx_oring1_cn52xx { 443#ifdef __BIG_ENDIAN_BITFIELD 444 uint64_t reserved_60_63:4; 445 uint64_t osize:20; 446 uint64_t reserved_36_39:4; 447 uint64_t obase:33; 448 uint64_t reserved_0_2:3; 449#else 450 uint64_t reserved_0_2:3; 451 uint64_t obase:33; 452 uint64_t reserved_36_39:4; 453 uint64_t osize:20; 454 uint64_t reserved_60_63:4; 455#endif 456 } cn52xx; 457 struct cvmx_mixx_oring1_cn52xx cn52xxp1; 458 struct cvmx_mixx_oring1_cn52xx cn56xx; 459 struct cvmx_mixx_oring1_cn52xx cn56xxp1; 460 struct cvmx_mixx_oring1_s cn61xx; 461 struct cvmx_mixx_oring1_s cn63xx; 462 struct cvmx_mixx_oring1_s cn63xxp1; 463 struct cvmx_mixx_oring1_s cn66xx; 464 struct cvmx_mixx_oring1_s cn68xx; 465 struct cvmx_mixx_oring1_s cn68xxp1; 466}; 467 468union cvmx_mixx_oring2 { 469 uint64_t u64; 470 struct cvmx_mixx_oring2_s { 471#ifdef __BIG_ENDIAN_BITFIELD 472 uint64_t reserved_52_63:12; 473 uint64_t otlptr:20; 474 uint64_t reserved_20_31:12; 475 uint64_t odbell:20; 476#else 477 uint64_t odbell:20; 478 uint64_t reserved_20_31:12; 479 uint64_t otlptr:20; 480 uint64_t reserved_52_63:12; 481#endif 482 } s; 483 struct cvmx_mixx_oring2_s cn52xx; 484 struct cvmx_mixx_oring2_s cn52xxp1; 485 struct cvmx_mixx_oring2_s cn56xx; 486 struct cvmx_mixx_oring2_s cn56xxp1; 487 struct cvmx_mixx_oring2_s cn61xx; 488 struct cvmx_mixx_oring2_s cn63xx; 489 struct cvmx_mixx_oring2_s cn63xxp1; 490 struct cvmx_mixx_oring2_s cn66xx; 491 struct cvmx_mixx_oring2_s cn68xx; 492 struct cvmx_mixx_oring2_s cn68xxp1; 493}; 494 495union cvmx_mixx_remcnt { 496 uint64_t u64; 497 struct cvmx_mixx_remcnt_s { 498#ifdef __BIG_ENDIAN_BITFIELD 499 uint64_t reserved_52_63:12; 500 uint64_t iremcnt:20; 501 uint64_t reserved_20_31:12; 502 uint64_t oremcnt:20; 503#else 504 uint64_t oremcnt:20; 505 uint64_t reserved_20_31:12; 506 uint64_t iremcnt:20; 507 uint64_t reserved_52_63:12; 508#endif 509 } s; 510 struct cvmx_mixx_remcnt_s cn52xx; 511 struct cvmx_mixx_remcnt_s cn52xxp1; 512 struct cvmx_mixx_remcnt_s cn56xx; 513 struct cvmx_mixx_remcnt_s cn56xxp1; 514 struct cvmx_mixx_remcnt_s cn61xx; 515 struct cvmx_mixx_remcnt_s cn63xx; 516 struct cvmx_mixx_remcnt_s cn63xxp1; 517 struct cvmx_mixx_remcnt_s cn66xx; 518 struct cvmx_mixx_remcnt_s cn68xx; 519 struct cvmx_mixx_remcnt_s cn68xxp1; 520}; 521 522union cvmx_mixx_tsctl { 523 uint64_t u64; 524 struct cvmx_mixx_tsctl_s { 525#ifdef __BIG_ENDIAN_BITFIELD 526 uint64_t reserved_21_63:43; 527 uint64_t tsavl:5; 528 uint64_t reserved_13_15:3; 529 uint64_t tstot:5; 530 uint64_t reserved_5_7:3; 531 uint64_t tscnt:5; 532#else 533 uint64_t tscnt:5; 534 uint64_t reserved_5_7:3; 535 uint64_t tstot:5; 536 uint64_t reserved_13_15:3; 537 uint64_t tsavl:5; 538 uint64_t reserved_21_63:43; 539#endif 540 } s; 541 struct cvmx_mixx_tsctl_s cn61xx; 542 struct cvmx_mixx_tsctl_s cn63xx; 543 struct cvmx_mixx_tsctl_s cn63xxp1; 544 struct cvmx_mixx_tsctl_s cn66xx; 545 struct cvmx_mixx_tsctl_s cn68xx; 546 struct cvmx_mixx_tsctl_s cn68xxp1; 547}; 548 549union cvmx_mixx_tstamp { 550 uint64_t u64; 551 struct cvmx_mixx_tstamp_s { 552#ifdef __BIG_ENDIAN_BITFIELD 553 uint64_t tstamp:64; 554#else 555 uint64_t tstamp:64; 556#endif 557 } s; 558 struct cvmx_mixx_tstamp_s cn61xx; 559 struct cvmx_mixx_tstamp_s cn63xx; 560 struct cvmx_mixx_tstamp_s cn63xxp1; 561 struct cvmx_mixx_tstamp_s cn66xx; 562 struct cvmx_mixx_tstamp_s cn68xx; 563 struct cvmx_mixx_tstamp_s cn68xxp1; 564}; 565 566#endif 567