LXR linux/arch/mips/include/asm/octeon/cvmx-pcsx-defs.h

   1/***********************license start***************
   2 * Author: Cavium Networks
   3 *
   4 * Contact: support@caviumnetworks.com
   5 * This file is part of the OCTEON SDK
   6 *
   7 * Copyright (c) 2003-2012 Cavium Networks
   8 *
   9 * This file is free software; you can redistribute it and/or modify
  10 * it under the terms of the GNU General Public License, Version 2, as
  11 * published by the Free Software Foundation.
  12 *
  13 * This file is distributed in the hope that it will be useful, but
  14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
  15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
  16 * NONINFRINGEMENT.  See the GNU General Public License for more
  17 * details.
  18 *
  19 * You should have received a copy of the GNU General Public License
  20 * along with this file; if not, write to the Free Software
  21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  22 * or visit http://www.gnu.org/licenses/.
  23 *
  24 * This file may also be available under a different license from Cavium.
  25 * Contact Cavium Networks for more information
  26 ***********************license end**************************************/
  27
  28#ifndef __CVMX_PCSX_DEFS_H__
  29#define __CVMX_PCSX_DEFS_H__
  30
  31static inline uint64_t CVMX_PCSX_ANX_ADV_REG(unsigned long offset, unsigned long block_id)
  32{
  33        switch (cvmx_get_octeon_family()) {
  34        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  35                return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  36        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  37        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  38                return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  39        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  40        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  41        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  42                return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  43        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  44                return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
  45        }
  46        return CVMX_ADD_IO_SEG(0x00011800B0001010ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  47}
  48
  49static inline uint64_t CVMX_PCSX_ANX_EXT_ST_REG(unsigned long offset, unsigned long block_id)
  50{
  51        switch (cvmx_get_octeon_family()) {
  52        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  53                return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  54        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  55        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  56                return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  57        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  58        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  59        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  60                return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  61        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  62                return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
  63        }
  64        return CVMX_ADD_IO_SEG(0x00011800B0001028ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  65}
  66
  67static inline uint64_t CVMX_PCSX_ANX_LP_ABIL_REG(unsigned long offset, unsigned long block_id)
  68{
  69        switch (cvmx_get_octeon_family()) {
  70        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  71                return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  72        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  73        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  74                return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  75        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  76        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  77        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  78                return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  79        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  80                return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
  81        }
  82        return CVMX_ADD_IO_SEG(0x00011800B0001018ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  83}
  84
  85static inline uint64_t CVMX_PCSX_ANX_RESULTS_REG(unsigned long offset, unsigned long block_id)
  86{
  87        switch (cvmx_get_octeon_family()) {
  88        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
  89                return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  90        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
  91        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
  92                return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  93        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
  94        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
  95        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
  96                return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
  97        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
  98                return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
  99        }
 100        return CVMX_ADD_IO_SEG(0x00011800B0001020ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 101}
 102
 103static inline uint64_t CVMX_PCSX_INTX_EN_REG(unsigned long offset, unsigned long block_id)
 104{
 105        switch (cvmx_get_octeon_family()) {
 106        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 107                return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 108        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 109        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 110                return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 111        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 112        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 113        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 114                return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 115        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 116                return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
 117        }
 118        return CVMX_ADD_IO_SEG(0x00011800B0001088ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 119}
 120
 121static inline uint64_t CVMX_PCSX_INTX_REG(unsigned long offset, unsigned long block_id)
 122{
 123        switch (cvmx_get_octeon_family()) {
 124        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 125                return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 126        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 127        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 128                return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 129        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 130        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 131        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 132                return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 133        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 134                return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
 135        }
 136        return CVMX_ADD_IO_SEG(0x00011800B0001080ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 137}
 138
 139static inline uint64_t CVMX_PCSX_LINKX_TIMER_COUNT_REG(unsigned long offset, unsigned long block_id)
 140{
 141        switch (cvmx_get_octeon_family()) {
 142        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 143                return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 144        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 145        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 146                return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 147        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 148        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 149        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 150                return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 151        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 152                return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
 153        }
 154        return CVMX_ADD_IO_SEG(0x00011800B0001040ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 155}
 156
 157static inline uint64_t CVMX_PCSX_LOG_ANLX_REG(unsigned long offset, unsigned long block_id)
 158{
 159        switch (cvmx_get_octeon_family()) {
 160        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 161                return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 162        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 163        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 164                return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 165        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 166        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 167        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 168                return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 169        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 170                return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
 171        }
 172        return CVMX_ADD_IO_SEG(0x00011800B0001090ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 173}
 174
 175static inline uint64_t CVMX_PCSX_MISCX_CTL_REG(unsigned long offset, unsigned long block_id)
 176{
 177        switch (cvmx_get_octeon_family()) {
 178        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 179                return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 180        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 181        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 182                return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 183        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 184        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 185        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 186                return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 187        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 188                return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
 189        }
 190        return CVMX_ADD_IO_SEG(0x00011800B0001078ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 191}
 192
 193static inline uint64_t CVMX_PCSX_MRX_CONTROL_REG(unsigned long offset, unsigned long block_id)
 194{
 195        switch (cvmx_get_octeon_family()) {
 196        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 197                return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 198        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 199        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 200                return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 201        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 202        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 203        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 204                return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 205        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 206                return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
 207        }
 208        return CVMX_ADD_IO_SEG(0x00011800B0001000ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 209}
 210
 211static inline uint64_t CVMX_PCSX_MRX_STATUS_REG(unsigned long offset, unsigned long block_id)
 212{
 213        switch (cvmx_get_octeon_family()) {
 214        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 215                return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 216        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 217        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 218                return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 219        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 220        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 221        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 222                return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 223        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 224                return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
 225        }
 226        return CVMX_ADD_IO_SEG(0x00011800B0001008ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 227}
 228
 229static inline uint64_t CVMX_PCSX_RXX_STATES_REG(unsigned long offset, unsigned long block_id)
 230{
 231        switch (cvmx_get_octeon_family()) {
 232        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 233                return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 234        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 235        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 236                return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 237        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 238        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 239        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 240                return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 241        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 242                return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
 243        }
 244        return CVMX_ADD_IO_SEG(0x00011800B0001058ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 245}
 246
 247static inline uint64_t CVMX_PCSX_RXX_SYNC_REG(unsigned long offset, unsigned long block_id)
 248{
 249        switch (cvmx_get_octeon_family()) {
 250        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 251                return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 252        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 253        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 254                return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 255        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 256        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 257        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 258                return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 259        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 260                return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
 261        }
 262        return CVMX_ADD_IO_SEG(0x00011800B0001050ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 263}
 264
 265static inline uint64_t CVMX_PCSX_SGMX_AN_ADV_REG(unsigned long offset, unsigned long block_id)
 266{
 267        switch (cvmx_get_octeon_family()) {
 268        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 269                return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 270        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 271        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 272                return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 273        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 274        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 275        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 276                return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 277        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 278                return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
 279        }
 280        return CVMX_ADD_IO_SEG(0x00011800B0001068ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 281}
 282
 283static inline uint64_t CVMX_PCSX_SGMX_LP_ADV_REG(unsigned long offset, unsigned long block_id)
 284{
 285        switch (cvmx_get_octeon_family()) {
 286        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 287                return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 288        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 289        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 290                return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 291        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 292        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 293        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 294                return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 295        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 296                return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
 297        }
 298        return CVMX_ADD_IO_SEG(0x00011800B0001070ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 299}
 300
 301static inline uint64_t CVMX_PCSX_TXX_STATES_REG(unsigned long offset, unsigned long block_id)
 302{
 303        switch (cvmx_get_octeon_family()) {
 304        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 305                return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 306        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 307        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 308                return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 309        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 310        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 311        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 312                return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 313        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 314                return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
 315        }
 316        return CVMX_ADD_IO_SEG(0x00011800B0001060ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 317}
 318
 319static inline uint64_t CVMX_PCSX_TX_RXX_POLARITY_REG(unsigned long offset, unsigned long block_id)
 320{
 321        switch (cvmx_get_octeon_family()) {
 322        case OCTEON_CNF71XX & OCTEON_FAMILY_MASK:
 323                return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 324        case OCTEON_CN63XX & OCTEON_FAMILY_MASK:
 325        case OCTEON_CN52XX & OCTEON_FAMILY_MASK:
 326                return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 327        case OCTEON_CN56XX & OCTEON_FAMILY_MASK:
 328        case OCTEON_CN66XX & OCTEON_FAMILY_MASK:
 329        case OCTEON_CN61XX & OCTEON_FAMILY_MASK:
 330                return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 331        case OCTEON_CN68XX & OCTEON_FAMILY_MASK:
 332                return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x4000ull) * 1024;
 333        }
 334        return CVMX_ADD_IO_SEG(0x00011800B0001048ull) + ((offset) + (block_id) * 0x20000ull) * 1024;
 335}
 336
 337union cvmx_pcsx_anx_adv_reg {
 338        uint64_t u64;
 339        struct cvmx_pcsx_anx_adv_reg_s {
 340#ifdef __BIG_ENDIAN_BITFIELD
 341                uint64_t reserved_16_63:48;
 342                uint64_t np:1;
 343                uint64_t reserved_14_14:1;
 344                uint64_t rem_flt:2;
 345                uint64_t reserved_9_11:3;
 346                uint64_t pause:2;
 347                uint64_t hfd:1;
 348                uint64_t fd:1;
 349                uint64_t reserved_0_4:5;
 350#else
 351                uint64_t reserved_0_4:5;
 352                uint64_t fd:1;
 353                uint64_t hfd:1;
 354                uint64_t pause:2;
 355                uint64_t reserved_9_11:3;
 356                uint64_t rem_flt:2;
 357                uint64_t reserved_14_14:1;
 358                uint64_t np:1;
 359                uint64_t reserved_16_63:48;
 360#endif
 361        } s;
 362        struct cvmx_pcsx_anx_adv_reg_s cn52xx;
 363        struct cvmx_pcsx_anx_adv_reg_s cn52xxp1;
 364        struct cvmx_pcsx_anx_adv_reg_s cn56xx;
 365        struct cvmx_pcsx_anx_adv_reg_s cn56xxp1;
 366        struct cvmx_pcsx_anx_adv_reg_s cn61xx;
 367        struct cvmx_pcsx_anx_adv_reg_s cn63xx;
 368        struct cvmx_pcsx_anx_adv_reg_s cn63xxp1;
 369        struct cvmx_pcsx_anx_adv_reg_s cn66xx;
 370        struct cvmx_pcsx_anx_adv_reg_s cn68xx;
 371        struct cvmx_pcsx_anx_adv_reg_s cn68xxp1;
 372        struct cvmx_pcsx_anx_adv_reg_s cnf71xx;
 373};
 374
 375union cvmx_pcsx_anx_ext_st_reg {
 376        uint64_t u64;
 377        struct cvmx_pcsx_anx_ext_st_reg_s {
 378#ifdef __BIG_ENDIAN_BITFIELD
 379                uint64_t reserved_16_63:48;
 380                uint64_t thou_xfd:1;
 381                uint64_t thou_xhd:1;
 382                uint64_t thou_tfd:1;
 383                uint64_t thou_thd:1;
 384                uint64_t reserved_0_11:12;
 385#else
 386                uint64_t reserved_0_11:12;
 387                uint64_t thou_thd:1;
 388                uint64_t thou_tfd:1;
 389                uint64_t thou_xhd:1;
 390                uint64_t thou_xfd:1;
 391                uint64_t reserved_16_63:48;
 392#endif
 393        } s;
 394        struct cvmx_pcsx_anx_ext_st_reg_s cn52xx;
 395        struct cvmx_pcsx_anx_ext_st_reg_s cn52xxp1;
 396        struct cvmx_pcsx_anx_ext_st_reg_s cn56xx;
 397        struct cvmx_pcsx_anx_ext_st_reg_s cn56xxp1;
 398        struct cvmx_pcsx_anx_ext_st_reg_s cn61xx;
 399        struct cvmx_pcsx_anx_ext_st_reg_s cn63xx;
 400        struct cvmx_pcsx_anx_ext_st_reg_s cn63xxp1;
 401        struct cvmx_pcsx_anx_ext_st_reg_s cn66xx;
 402        struct cvmx_pcsx_anx_ext_st_reg_s cn68xx;
 403        struct cvmx_pcsx_anx_ext_st_reg_s cn68xxp1;
 404        struct cvmx_pcsx_anx_ext_st_reg_s cnf71xx;
 405};
 406
 407union cvmx_pcsx_anx_lp_abil_reg {
 408        uint64_t u64;
 409        struct cvmx_pcsx_anx_lp_abil_reg_s {
 410#ifdef __BIG_ENDIAN_BITFIELD
 411                uint64_t reserved_16_63:48;
 412                uint64_t np:1;
 413                uint64_t ack:1;
 414                uint64_t rem_flt:2;
 415                uint64_t reserved_9_11:3;
 416                uint64_t pause:2;
 417                uint64_t hfd:1;
 418                uint64_t fd:1;
 419                uint64_t reserved_0_4:5;
 420#else
 421                uint64_t reserved_0_4:5;
 422                uint64_t fd:1;
 423                uint64_t hfd:1;
 424                uint64_t pause:2;
 425                uint64_t reserved_9_11:3;
 426                uint64_t rem_flt:2;
 427                uint64_t ack:1;
 428                uint64_t np:1;
 429                uint64_t reserved_16_63:48;
 430#endif
 431        } s;
 432        struct cvmx_pcsx_anx_lp_abil_reg_s cn52xx;
 433        struct cvmx_pcsx_anx_lp_abil_reg_s cn52xxp1;
 434        struct cvmx_pcsx_anx_lp_abil_reg_s cn56xx;
 435        struct cvmx_pcsx_anx_lp_abil_reg_s cn56xxp1;
 436        struct cvmx_pcsx_anx_lp_abil_reg_s cn61xx;
 437        struct cvmx_pcsx_anx_lp_abil_reg_s cn63xx;
 438        struct cvmx_pcsx_anx_lp_abil_reg_s cn63xxp1;
 439        struct cvmx_pcsx_anx_lp_abil_reg_s cn66xx;
 440        struct cvmx_pcsx_anx_lp_abil_reg_s cn68xx;
 441        struct cvmx_pcsx_anx_lp_abil_reg_s cn68xxp1;
 442        struct cvmx_pcsx_anx_lp_abil_reg_s cnf71xx;
 443};
 444
 445union cvmx_pcsx_anx_results_reg {
 446        uint64_t u64;
 447        struct cvmx_pcsx_anx_results_reg_s {
 448#ifdef __BIG_ENDIAN_BITFIELD
 449                uint64_t reserved_7_63:57;
 450                uint64_t pause:2;
 451                uint64_t spd:2;
 452                uint64_t an_cpt:1;
 453                uint64_t dup:1;
 454                uint64_t link_ok:1;
 455#else
 456                uint64_t link_ok:1;
 457                uint64_t dup:1;
 458                uint64_t an_cpt:1;
 459                uint64_t spd:2;
 460                uint64_t pause:2;
 461                uint64_t reserved_7_63:57;
 462#endif
 463        } s;
 464        struct cvmx_pcsx_anx_results_reg_s cn52xx;
 465        struct cvmx_pcsx_anx_results_reg_s cn52xxp1;
 466        struct cvmx_pcsx_anx_results_reg_s cn56xx;
 467        struct cvmx_pcsx_anx_results_reg_s cn56xxp1;
 468        struct cvmx_pcsx_anx_results_reg_s cn61xx;
 469        struct cvmx_pcsx_anx_results_reg_s cn63xx;
 470        struct cvmx_pcsx_anx_results_reg_s cn63xxp1;
 471        struct cvmx_pcsx_anx_results_reg_s cn66xx;
 472        struct cvmx_pcsx_anx_results_reg_s cn68xx;
 473        struct cvmx_pcsx_anx_results_reg_s cn68xxp1;
 474        struct cvmx_pcsx_anx_results_reg_s cnf71xx;
 475};
 476
 477union cvmx_pcsx_intx_en_reg {
 478        uint64_t u64;
 479        struct cvmx_pcsx_intx_en_reg_s {
 480#ifdef __BIG_ENDIAN_BITFIELD
 481                uint64_t reserved_13_63:51;
 482                uint64_t dbg_sync_en:1;
 483                uint64_t dup:1;
 484                uint64_t sync_bad_en:1;
 485                uint64_t an_bad_en:1;
 486                uint64_t rxlock_en:1;
 487                uint64_t rxbad_en:1;
 488                uint64_t rxerr_en:1;
 489                uint64_t txbad_en:1;
 490                uint64_t txfifo_en:1;
 491                uint64_t txfifu_en:1;
 492                uint64_t an_err_en:1;
 493                uint64_t xmit_en:1;
 494                uint64_t lnkspd_en:1;
 495#else
 496                uint64_t lnkspd_en:1;
 497                uint64_t xmit_en:1;
 498                uint64_t an_err_en:1;
 499                uint64_t txfifu_en:1;
 500                uint64_t txfifo_en:1;
 501                uint64_t txbad_en:1;
 502                uint64_t rxerr_en:1;
 503                uint64_t rxbad_en:1;
 504                uint64_t rxlock_en:1;
 505                uint64_t an_bad_en:1;
 506                uint64_t sync_bad_en:1;
 507                uint64_t dup:1;
 508                uint64_t dbg_sync_en:1;
 509                uint64_t reserved_13_63:51;
 510#endif
 511        } s;
 512        struct cvmx_pcsx_intx_en_reg_cn52xx {
 513#ifdef __BIG_ENDIAN_BITFIELD
 514                uint64_t reserved_12_63:52;
 515                uint64_t dup:1;
 516                uint64_t sync_bad_en:1;
 517                uint64_t an_bad_en:1;
 518                uint64_t rxlock_en:1;
 519                uint64_t rxbad_en:1;
 520                uint64_t rxerr_en:1;
 521                uint64_t txbad_en:1;
 522                uint64_t txfifo_en:1;
 523                uint64_t txfifu_en:1;
 524                uint64_t an_err_en:1;
 525                uint64_t xmit_en:1;
 526                uint64_t lnkspd_en:1;
 527#else
 528                uint64_t lnkspd_en:1;
 529                uint64_t xmit_en:1;
 530                uint64_t an_err_en:1;
 531                uint64_t txfifu_en:1;
 532                uint64_t txfifo_en:1;
 533                uint64_t txbad_en:1;
 534                uint64_t rxerr_en:1;
 535                uint64_t rxbad_en:1;
 536                uint64_t rxlock_en:1;
 537                uint64_t an_bad_en:1;
 538                uint64_t sync_bad_en:1;
 539                uint64_t dup:1;
 540                uint64_t reserved_12_63:52;
 541#endif
 542        } cn52xx;
 543        struct cvmx_pcsx_intx_en_reg_cn52xx cn52xxp1;
 544        struct cvmx_pcsx_intx_en_reg_cn52xx cn56xx;
 545        struct cvmx_pcsx_intx_en_reg_cn52xx cn56xxp1;
 546        struct cvmx_pcsx_intx_en_reg_s cn61xx;
 547        struct cvmx_pcsx_intx_en_reg_s cn63xx;
 548        struct cvmx_pcsx_intx_en_reg_s cn63xxp1;
 549        struct cvmx_pcsx_intx_en_reg_s cn66xx;
 550        struct cvmx_pcsx_intx_en_reg_s cn68xx;
 551        struct cvmx_pcsx_intx_en_reg_s cn68xxp1;
 552        struct cvmx_pcsx_intx_en_reg_s cnf71xx;
 553};
 554
 555union cvmx_pcsx_intx_reg {
 556        uint64_t u64;
 557        struct cvmx_pcsx_intx_reg_s {
 558#ifdef __BIG_ENDIAN_BITFIELD
 559                uint64_t reserved_13_63:51;
 560                uint64_t dbg_sync:1;
 561                uint64_t dup:1;
 562                uint64_t sync_bad:1;
 563                uint64_t an_bad:1;
 564                uint64_t rxlock:1;
 565                uint64_t rxbad:1;
 566                uint64_t rxerr:1;
 567                uint64_t txbad:1;
 568                uint64_t txfifo:1;
 569                uint64_t txfifu:1;
 570                uint64_t an_err:1;
 571                uint64_t xmit:1;
 572                uint64_t lnkspd:1;
 573#else
 574                uint64_t lnkspd:1;
 575                uint64_t xmit:1;
 576                uint64_t an_err:1;
 577                uint64_t txfifu:1;
 578                uint64_t txfifo:1;
 579                uint64_t txbad:1;
 580                uint64_t rxerr:1;
 581                uint64_t rxbad:1;
 582                uint64_t rxlock:1;
 583                uint64_t an_bad:1;
 584                uint64_t sync_bad:1;
 585                uint64_t dup:1;
 586                uint64_t dbg_sync:1;
 587                uint64_t reserved_13_63:51;
 588#endif
 589        } s;
 590        struct cvmx_pcsx_intx_reg_cn52xx {
 591#ifdef __BIG_ENDIAN_BITFIELD
 592                uint64_t reserved_12_63:52;
 593                uint64_t dup:1;
 594                uint64_t sync_bad:1;
 595                uint64_t an_bad:1;
 596                uint64_t rxlock:1;
 597                uint64_t rxbad:1;
 598                uint64_t rxerr:1;
 599                uint64_t txbad:1;
 600                uint64_t txfifo:1;
 601                uint64_t txfifu:1;
 602                uint64_t an_err:1;
 603                uint64_t xmit:1;
 604                uint64_t lnkspd:1;
 605#else
 606                uint64_t lnkspd:1;
 607                uint64_t xmit:1;
 608                uint64_t an_err:1;
 609                uint64_t txfifu:1;
 610                uint64_t txfifo:1;
 611                uint64_t txbad:1;
 612                uint64_t rxerr:1;
 613                uint64_t rxbad:1;
 614                uint64_t rxlock:1;
 615                uint64_t an_bad:1;
 616                uint64_t sync_bad:1;
 617                uint64_t dup:1;
 618                uint64_t reserved_12_63:52;
 619#endif
 620        } cn52xx;
 621        struct cvmx_pcsx_intx_reg_cn52xx cn52xxp1;
 622        struct cvmx_pcsx_intx_reg_cn52xx cn56xx;
 623        struct cvmx_pcsx_intx_reg_cn52xx cn56xxp1;
 624        struct cvmx_pcsx_intx_reg_s cn61xx;
 625        struct cvmx_pcsx_intx_reg_s cn63xx;
 626        struct cvmx_pcsx_intx_reg_s cn63xxp1;
 627        struct cvmx_pcsx_intx_reg_s cn66xx;
 628        struct cvmx_pcsx_intx_reg_s cn68xx;
 629        struct cvmx_pcsx_intx_reg_s cn68xxp1;
 630        struct cvmx_pcsx_intx_reg_s cnf71xx;
 631};
 632
 633union cvmx_pcsx_linkx_timer_count_reg {
 634        uint64_t u64;
 635        struct cvmx_pcsx_linkx_timer_count_reg_s {
 636#ifdef __BIG_ENDIAN_BITFIELD
 637                uint64_t reserved_16_63:48;
 638                uint64_t count:16;
 639#else
 640                uint64_t count:16;
 641                uint64_t reserved_16_63:48;
 642#endif
 643        } s;
 644        struct cvmx_pcsx_linkx_timer_count_reg_s cn52xx;
 645        struct cvmx_pcsx_linkx_timer_count_reg_s cn52xxp1;
 646        struct cvmx_pcsx_linkx_timer_count_reg_s cn56xx;
 647        struct cvmx_pcsx_linkx_timer_count_reg_s cn56xxp1;
 648        struct cvmx_pcsx_linkx_timer_count_reg_s cn61xx;
 649        struct cvmx_pcsx_linkx_timer_count_reg_s cn63xx;
 650        struct cvmx_pcsx_linkx_timer_count_reg_s cn63xxp1;
 651        struct cvmx_pcsx_linkx_timer_count_reg_s cn66xx;
 652        struct cvmx_pcsx_linkx_timer_count_reg_s cn68xx;
 653        struct cvmx_pcsx_linkx_timer_count_reg_s cn68xxp1;
 654        struct cvmx_pcsx_linkx_timer_count_reg_s cnf71xx;
 655};
 656
 657union cvmx_pcsx_log_anlx_reg {
 658        uint64_t u64;
 659        struct cvmx_pcsx_log_anlx_reg_s {
 660#ifdef __BIG_ENDIAN_BITFIELD
 661                uint64_t reserved_4_63:60;
 662                uint64_t lafifovfl:1;
 663                uint64_t la_en:1;
 664                uint64_t pkt_sz:2;
 665#else
 666                uint64_t pkt_sz:2;
 667                uint64_t la_en:1;
 668                uint64_t lafifovfl:1;
 669                uint64_t reserved_4_63:60;
 670#endif
 671        } s;
 672        struct cvmx_pcsx_log_anlx_reg_s cn52xx;
 673        struct cvmx_pcsx_log_anlx_reg_s cn52xxp1;
 674        struct cvmx_pcsx_log_anlx_reg_s cn56xx;
 675        struct cvmx_pcsx_log_anlx_reg_s cn56xxp1;
 676        struct cvmx_pcsx_log_anlx_reg_s cn61xx;
 677        struct cvmx_pcsx_log_anlx_reg_s cn63xx;
 678        struct cvmx_pcsx_log_anlx_reg_s cn63xxp1;
 679        struct cvmx_pcsx_log_anlx_reg_s cn66xx;
 680        struct cvmx_pcsx_log_anlx_reg_s cn68xx;
 681        struct cvmx_pcsx_log_anlx_reg_s cn68xxp1;
 682        struct cvmx_pcsx_log_anlx_reg_s cnf71xx;
 683};
 684
 685union cvmx_pcsx_miscx_ctl_reg {
 686        uint64_t u64;
 687        struct cvmx_pcsx_miscx_ctl_reg_s {
 688#ifdef __BIG_ENDIAN_BITFIELD
 689                uint64_t reserved_13_63:51;
 690                uint64_t sgmii:1;
 691                uint64_t gmxeno:1;
 692                uint64_t loopbck2:1;
 693                uint64_t mac_phy:1;
 694                uint64_t mode:1;
 695                uint64_t an_ovrd:1;
 696                uint64_t samp_pt:7;
 697#else
 698                uint64_t samp_pt:7;
 699                uint64_t an_ovrd:1;
 700                uint64_t mode:1;
 701                uint64_t mac_phy:1;
 702                uint64_t loopbck2:1;
 703                uint64_t gmxeno:1;
 704                uint64_t sgmii:1;
 705                uint64_t reserved_13_63:51;
 706#endif
 707        } s;
 708        struct cvmx_pcsx_miscx_ctl_reg_s cn52xx;
 709        struct cvmx_pcsx_miscx_ctl_reg_s cn52xxp1;
 710        struct cvmx_pcsx_miscx_ctl_reg_s cn56xx;
 711        struct cvmx_pcsx_miscx_ctl_reg_s cn56xxp1;
 712        struct cvmx_pcsx_miscx_ctl_reg_s cn61xx;
 713        struct cvmx_pcsx_miscx_ctl_reg_s cn63xx;
 714        struct cvmx_pcsx_miscx_ctl_reg_s cn63xxp1;
 715        struct cvmx_pcsx_miscx_ctl_reg_s cn66xx;
 716        struct cvmx_pcsx_miscx_ctl_reg_s cn68xx;
 717        struct cvmx_pcsx_miscx_ctl_reg_s cn68xxp1;
 718        struct cvmx_pcsx_miscx_ctl_reg_s cnf71xx;
 719};
 720
 721union cvmx_pcsx_mrx_control_reg {
 722        uint64_t u64;
 723        struct cvmx_pcsx_mrx_control_reg_s {
 724#ifdef __BIG_ENDIAN_BITFIELD
 725                uint64_t reserved_16_63:48;
 726                uint64_t reset:1;
 727                uint64_t loopbck1:1;
 728                uint64_t spdlsb:1;
 729                uint64_t an_en:1;
 730                uint64_t pwr_dn:1;
 731                uint64_t reserved_10_10:1;
 732                uint64_t rst_an:1;
 733                uint64_t dup:1;
 734                uint64_t coltst:1;
 735                uint64_t spdmsb:1;
 736                uint64_t uni:1;
 737                uint64_t reserved_0_4:5;
 738#else
 739                uint64_t reserved_0_4:5;
 740                uint64_t uni:1;
 741                uint64_t spdmsb:1;
 742                uint64_t coltst:1;
 743                uint64_t dup:1;
 744                uint64_t rst_an:1;
 745                uint64_t reserved_10_10:1;
 746                uint64_t pwr_dn:1;
 747                uint64_t an_en:1;
 748                uint64_t spdlsb:1;
 749                uint64_t loopbck1:1;
 750                uint64_t reset:1;
 751                uint64_t reserved_16_63:48;
 752#endif
 753        } s;
 754        struct cvmx_pcsx_mrx_control_reg_s cn52xx;
 755        struct cvmx_pcsx_mrx_control_reg_s cn52xxp1;
 756        struct cvmx_pcsx_mrx_control_reg_s cn56xx;
 757        struct cvmx_pcsx_mrx_control_reg_s cn56xxp1;
 758        struct cvmx_pcsx_mrx_control_reg_s cn61xx;
 759        struct cvmx_pcsx_mrx_control_reg_s cn63xx;
 760        struct cvmx_pcsx_mrx_control_reg_s cn63xxp1;
 761        struct cvmx_pcsx_mrx_control_reg_s cn66xx;
 762        struct cvmx_pcsx_mrx_control_reg_s cn68xx;
 763        struct cvmx_pcsx_mrx_control_reg_s cn68xxp1;
 764        struct cvmx_pcsx_mrx_control_reg_s cnf71xx;
 765};
 766
 767union cvmx_pcsx_mrx_status_reg {
 768        uint64_t u64;
 769        struct cvmx_pcsx_mrx_status_reg_s {
 770#ifdef __BIG_ENDIAN_BITFIELD
 771                uint64_t reserved_16_63:48;
 772                uint64_t hun_t4:1;
 773                uint64_t hun_xfd:1;
 774                uint64_t hun_xhd:1;
 775                uint64_t ten_fd:1;
 776                uint64_t ten_hd:1;
 777                uint64_t hun_t2fd:1;
 778                uint64_t hun_t2hd:1;
 779                uint64_t ext_st:1;
 780                uint64_t reserved_7_7:1;
 781                uint64_t prb_sup:1;
 782                uint64_t an_cpt:1;
 783                uint64_t rm_flt:1;
 784                uint64_t an_abil:1;
 785                uint64_t lnk_st:1;
 786                uint64_t reserved_1_1:1;
 787                uint64_t extnd:1;
 788#else
 789                uint64_t extnd:1;
 790                uint64_t reserved_1_1:1;
 791                uint64_t lnk_st:1;
 792                uint64_t an_abil:1;
 793                uint64_t rm_flt:1;
 794                uint64_t an_cpt:1;
 795                uint64_t prb_sup:1;
 796                uint64_t reserved_7_7:1;
 797                uint64_t ext_st:1;
 798                uint64_t hun_t2hd:1;
 799                uint64_t hun_t2fd:1;
 800                uint64_t ten_hd:1;
 801                uint64_t ten_fd:1;
 802                uint64_t hun_xhd:1;
 803                uint64_t hun_xfd:1;
 804                uint64_t hun_t4:1;
 805                uint64_t reserved_16_63:48;
 806#endif
 807        } s;
 808        struct cvmx_pcsx_mrx_status_reg_s cn52xx;
 809        struct cvmx_pcsx_mrx_status_reg_s cn52xxp1;
 810        struct cvmx_pcsx_mrx_status_reg_s cn56xx;
 811        struct cvmx_pcsx_mrx_status_reg_s cn56xxp1;
 812        struct cvmx_pcsx_mrx_status_reg_s cn61xx;
 813        struct cvmx_pcsx_mrx_status_reg_s cn63xx;
 814        struct cvmx_pcsx_mrx_status_reg_s cn63xxp1;
 815        struct cvmx_pcsx_mrx_status_reg_s cn66xx;
 816        struct cvmx_pcsx_mrx_status_reg_s cn68xx;
 817        struct cvmx_pcsx_mrx_status_reg_s cn68xxp1;
 818        struct cvmx_pcsx_mrx_status_reg_s cnf71xx;
 819};
 820
 821union cvmx_pcsx_rxx_states_reg {
 822        uint64_t u64;
 823        struct cvmx_pcsx_rxx_states_reg_s {
 824#ifdef __BIG_ENDIAN_BITFIELD
 825                uint64_t reserved_16_63:48;
 826                uint64_t rx_bad:1;
 827                uint64_t rx_st:5;
 828                uint64_t sync_bad:1;
 829                uint64_t sync:4;
 830                uint64_t an_bad:1;
 831                uint64_t an_st:4;
 832#else
 833                uint64_t an_st:4;
 834                uint64_t an_bad:1;
 835                uint64_t sync:4;
 836                uint64_t sync_bad:1;
 837                uint64_t rx_st:5;
 838                uint64_t rx_bad:1;
 839                uint64_t reserved_16_63:48;
 840#endif
 841        } s;
 842        struct cvmx_pcsx_rxx_states_reg_s cn52xx;
 843        struct cvmx_pcsx_rxx_states_reg_s cn52xxp1;
 844        struct cvmx_pcsx_rxx_states_reg_s cn56xx;
 845        struct cvmx_pcsx_rxx_states_reg_s cn56xxp1;
 846        struct cvmx_pcsx_rxx_states_reg_s cn61xx;
 847        struct cvmx_pcsx_rxx_states_reg_s cn63xx;
 848        struct cvmx_pcsx_rxx_states_reg_s cn63xxp1;
 849        struct cvmx_pcsx_rxx_states_reg_s cn66xx;
 850        struct cvmx_pcsx_rxx_states_reg_s cn68xx;
 851        struct cvmx_pcsx_rxx_states_reg_s cn68xxp1;
 852        struct cvmx_pcsx_rxx_states_reg_s cnf71xx;
 853};
 854
 855union cvmx_pcsx_rxx_sync_reg {
 856        uint64_t u64;
 857        struct cvmx_pcsx_rxx_sync_reg_s {
 858#ifdef __BIG_ENDIAN_BITFIELD
 859                uint64_t reserved_2_63:62;
 860                uint64_t sync:1;
 861                uint64_t bit_lock:1;
 862#else
 863                uint64_t bit_lock:1;
 864                uint64_t sync:1;
 865                uint64_t reserved_2_63:62;
 866#endif
 867        } s;
 868        struct cvmx_pcsx_rxx_sync_reg_s cn52xx;
 869        struct cvmx_pcsx_rxx_sync_reg_s cn52xxp1;
 870        struct cvmx_pcsx_rxx_sync_reg_s cn56xx;
 871        struct cvmx_pcsx_rxx_sync_reg_s cn56xxp1;
 872        struct cvmx_pcsx_rxx_sync_reg_s cn61xx;
 873        struct cvmx_pcsx_rxx_sync_reg_s cn63xx;
 874        struct cvmx_pcsx_rxx_sync_reg_s cn63xxp1;
 875        struct cvmx_pcsx_rxx_sync_reg_s cn66xx;
 876        struct cvmx_pcsx_rxx_sync_reg_s cn68xx;
 877        struct cvmx_pcsx_rxx_sync_reg_s cn68xxp1;
 878        struct cvmx_pcsx_rxx_sync_reg_s cnf71xx;
 879};
 880
 881union cvmx_pcsx_sgmx_an_adv_reg {
 882        uint64_t u64;
 883        struct cvmx_pcsx_sgmx_an_adv_reg_s {
 884#ifdef __BIG_ENDIAN_BITFIELD
 885                uint64_t reserved_16_63:48;
 886                uint64_t link:1;
 887                uint64_t ack:1;
 888                uint64_t reserved_13_13:1;
 889                uint64_t dup:1;
 890                uint64_t speed:2;
 891                uint64_t reserved_1_9:9;
 892                uint64_t one:1;
 893#else
 894                uint64_t one:1;
 895                uint64_t reserved_1_9:9;
 896                uint64_t speed:2;
 897                uint64_t dup:1;
 898                uint64_t reserved_13_13:1;
 899                uint64_t ack:1;
 900                uint64_t link:1;
 901                uint64_t reserved_16_63:48;
 902#endif
 903        } s;
 904        struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xx;
 905        struct cvmx_pcsx_sgmx_an_adv_reg_s cn52xxp1;
 906        struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xx;
 907        struct cvmx_pcsx_sgmx_an_adv_reg_s cn56xxp1;
 908        struct cvmx_pcsx_sgmx_an_adv_reg_s cn61xx;
 909        struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xx;
 910        struct cvmx_pcsx_sgmx_an_adv_reg_s cn63xxp1;
 911        struct cvmx_pcsx_sgmx_an_adv_reg_s cn66xx;
 912        struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xx;
 913        struct cvmx_pcsx_sgmx_an_adv_reg_s cn68xxp1;
 914        struct cvmx_pcsx_sgmx_an_adv_reg_s cnf71xx;
 915};
 916
 917union cvmx_pcsx_sgmx_lp_adv_reg {
 918        uint64_t u64;
 919        struct cvmx_pcsx_sgmx_lp_adv_reg_s {
 920#ifdef __BIG_ENDIAN_BITFIELD
 921                uint64_t reserved_16_63:48;
 922                uint64_t link:1;
 923                uint64_t reserved_13_14:2;
 924                uint64_t dup:1;
 925                uint64_t speed:2;
 926                uint64_t reserved_1_9:9;
 927                uint64_t one:1;
 928#else
 929                uint64_t one:1;
 930                uint64_t reserved_1_9:9;
 931                uint64_t speed:2;
 932                uint64_t dup:1;
 933                uint64_t reserved_13_14:2;
 934                uint64_t link:1;
 935                uint64_t reserved_16_63:48;
 936#endif
 937        } s;
 938        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xx;
 939        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn52xxp1;
 940        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xx;
 941        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn56xxp1;
 942        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn61xx;
 943        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xx;
 944        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn63xxp1;
 945        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn66xx;
 946        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xx;
 947        struct cvmx_pcsx_sgmx_lp_adv_reg_s cn68xxp1;
 948        struct cvmx_pcsx_sgmx_lp_adv_reg_s cnf71xx;
 949};
 950
 951union cvmx_pcsx_txx_states_reg {
 952        uint64_t u64;
 953        struct cvmx_pcsx_txx_states_reg_s {
 954#ifdef __BIG_ENDIAN_BITFIELD
 955                uint64_t reserved_7_63:57;
 956                uint64_t xmit:2;
 957                uint64_t tx_bad:1;
 958                uint64_t ord_st:4;
 959#else
 960                uint64_t ord_st:4;
 961                uint64_t tx_bad:1;
 962                uint64_t xmit:2;
 963                uint64_t reserved_7_63:57;
 964#endif
 965        } s;
 966        struct cvmx_pcsx_txx_states_reg_s cn52xx;
 967        struct cvmx_pcsx_txx_states_reg_s cn52xxp1;
 968        struct cvmx_pcsx_txx_states_reg_s cn56xx;
 969        struct cvmx_pcsx_txx_states_reg_s cn56xxp1;
 970        struct cvmx_pcsx_txx_states_reg_s cn61xx;
 971        struct cvmx_pcsx_txx_states_reg_s cn63xx;
 972        struct cvmx_pcsx_txx_states_reg_s cn63xxp1;
 973        struct cvmx_pcsx_txx_states_reg_s cn66xx;
 974        struct cvmx_pcsx_txx_states_reg_s cn68xx;
 975        struct cvmx_pcsx_txx_states_reg_s cn68xxp1;
 976        struct cvmx_pcsx_txx_states_reg_s cnf71xx;
 977};
 978
 979union cvmx_pcsx_tx_rxx_polarity_reg {
 980        uint64_t u64;
 981        struct cvmx_pcsx_tx_rxx_polarity_reg_s {
 982#ifdef __BIG_ENDIAN_BITFIELD
 983                uint64_t reserved_4_63:60;
 984                uint64_t rxovrd:1;
 985                uint64_t autorxpl:1;
 986                uint64_t rxplrt:1;
 987                uint64_t txplrt:1;
 988#else
 989                uint64_t txplrt:1;
 990                uint64_t rxplrt:1;
 991                uint64_t autorxpl:1;
 992                uint64_t rxovrd:1;
 993                uint64_t reserved_4_63:60;
 994#endif
 995        } s;
 996        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xx;
 997        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn52xxp1;
 998        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xx;
 999        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn56xxp1;
1000        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn61xx;

1001        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xx;
1002        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn63xxp1;
1003        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn66xx;
1004        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xx;
1005        struct cvmx_pcsx_tx_rxx_polarity_reg_s cn68xxp1;
1006        struct cvmx_pcsx_tx_rxx_polarity_reg_s cnf71xx;
1007};
1008
1009#endif
1010