1/***********************license start*************** 2 * Author: Cavium Networks 3 * 4 * Contact: support@caviumnetworks.com 5 * This file is part of the OCTEON SDK 6 * 7 * Copyright (c) 2003-2012 Cavium Networks 8 * 9 * This file is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License, Version 2, as 11 * published by the Free Software Foundation. 12 * 13 * This file is distributed in the hope that it will be useful, but 14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty 15 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or 16 * NONINFRINGEMENT. See the GNU General Public License for more 17 * details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this file; if not, write to the Free Software 21 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 22 * or visit http://www.gnu.org/licenses/. 23 * 24 * This file may also be available under a different license from Cavium. 25 * Contact Cavium Networks for more information 26 ***********************license end**************************************/ 27 28#ifndef __CVMX_PESCX_DEFS_H__ 29#define __CVMX_PESCX_DEFS_H__ 30 31#define CVMX_PESCX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000018ull) + ((block_id) & 1) * 0x8000000ull) 32#define CVMX_PESCX_BIST_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000418ull) + ((block_id) & 1) * 0x8000000ull) 33#define CVMX_PESCX_CFG_RD(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000030ull) + ((block_id) & 1) * 0x8000000ull) 34#define CVMX_PESCX_CFG_WR(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000028ull) + ((block_id) & 1) * 0x8000000ull) 35#define CVMX_PESCX_CPL_LUT_VALID(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000098ull) + ((block_id) & 1) * 0x8000000ull) 36#define CVMX_PESCX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000000ull) + ((block_id) & 1) * 0x8000000ull) 37#define CVMX_PESCX_CTL_STATUS2(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000400ull) + ((block_id) & 1) * 0x8000000ull) 38#define CVMX_PESCX_DBG_INFO(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000008ull) + ((block_id) & 1) * 0x8000000ull) 39#define CVMX_PESCX_DBG_INFO_EN(block_id) (CVMX_ADD_IO_SEG(0x00011800C80000A0ull) + ((block_id) & 1) * 0x8000000ull) 40#define CVMX_PESCX_DIAG_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000020ull) + ((block_id) & 1) * 0x8000000ull) 41#define CVMX_PESCX_P2N_BAR0_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000080ull) + ((block_id) & 1) * 0x8000000ull) 42#define CVMX_PESCX_P2N_BAR1_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000088ull) + ((block_id) & 1) * 0x8000000ull) 43#define CVMX_PESCX_P2N_BAR2_START(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000090ull) + ((block_id) & 1) * 0x8000000ull) 44#define CVMX_PESCX_P2P_BARX_END(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000048ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16) 45#define CVMX_PESCX_P2P_BARX_START(offset, block_id) (CVMX_ADD_IO_SEG(0x00011800C8000040ull) + (((offset) & 3) + ((block_id) & 1) * 0x800000ull) * 16) 46#define CVMX_PESCX_TLP_CREDITS(block_id) (CVMX_ADD_IO_SEG(0x00011800C8000038ull) + ((block_id) & 1) * 0x8000000ull) 47 48union cvmx_pescx_bist_status { 49 uint64_t u64; 50 struct cvmx_pescx_bist_status_s { 51#ifdef __BIG_ENDIAN_BITFIELD 52 uint64_t reserved_13_63:51; 53 uint64_t rqdata5:1; 54 uint64_t ctlp_or:1; 55 uint64_t ntlp_or:1; 56 uint64_t ptlp_or:1; 57 uint64_t retry:1; 58 uint64_t rqdata0:1; 59 uint64_t rqdata1:1; 60 uint64_t rqdata2:1; 61 uint64_t rqdata3:1; 62 uint64_t rqdata4:1; 63 uint64_t rqhdr1:1; 64 uint64_t rqhdr0:1; 65 uint64_t sot:1; 66#else 67 uint64_t sot:1; 68 uint64_t rqhdr0:1; 69 uint64_t rqhdr1:1; 70 uint64_t rqdata4:1; 71 uint64_t rqdata3:1; 72 uint64_t rqdata2:1; 73 uint64_t rqdata1:1; 74 uint64_t rqdata0:1; 75 uint64_t retry:1; 76 uint64_t ptlp_or:1; 77 uint64_t ntlp_or:1; 78 uint64_t ctlp_or:1; 79 uint64_t rqdata5:1; 80 uint64_t reserved_13_63:51; 81#endif 82 } s; 83 struct cvmx_pescx_bist_status_s cn52xx; 84 struct cvmx_pescx_bist_status_cn52xxp1 { 85#ifdef __BIG_ENDIAN_BITFIELD 86 uint64_t reserved_12_63:52; 87 uint64_t ctlp_or:1; 88 uint64_t ntlp_or:1; 89 uint64_t ptlp_or:1; 90 uint64_t retry:1; 91 uint64_t rqdata0:1; 92 uint64_t rqdata1:1; 93 uint64_t rqdata2:1; 94 uint64_t rqdata3:1; 95 uint64_t rqdata4:1; 96 uint64_t rqhdr1:1; 97 uint64_t rqhdr0:1; 98 uint64_t sot:1; 99#else 100 uint64_t sot:1; 101 uint64_t rqhdr0:1; 102 uint64_t rqhdr1:1; 103 uint64_t rqdata4:1; 104 uint64_t rqdata3:1; 105 uint64_t rqdata2:1; 106 uint64_t rqdata1:1; 107 uint64_t rqdata0:1; 108 uint64_t retry:1; 109 uint64_t ptlp_or:1; 110 uint64_t ntlp_or:1; 111 uint64_t ctlp_or:1; 112 uint64_t reserved_12_63:52; 113#endif 114 } cn52xxp1; 115 struct cvmx_pescx_bist_status_s cn56xx; 116 struct cvmx_pescx_bist_status_cn52xxp1 cn56xxp1; 117}; 118 119union cvmx_pescx_bist_status2 { 120 uint64_t u64; 121 struct cvmx_pescx_bist_status2_s { 122#ifdef __BIG_ENDIAN_BITFIELD 123 uint64_t reserved_14_63:50; 124 uint64_t cto_p2e:1; 125 uint64_t e2p_cpl:1; 126 uint64_t e2p_n:1; 127 uint64_t e2p_p:1; 128 uint64_t e2p_rsl:1; 129 uint64_t dbg_p2e:1; 130 uint64_t peai_p2e:1; 131 uint64_t rsl_p2e:1; 132 uint64_t pef_tpf1:1; 133 uint64_t pef_tpf0:1; 134 uint64_t pef_tnf:1; 135 uint64_t pef_tcf1:1; 136 uint64_t pef_tc0:1; 137 uint64_t ppf:1; 138#else 139 uint64_t ppf:1; 140 uint64_t pef_tc0:1; 141 uint64_t pef_tcf1:1; 142 uint64_t pef_tnf:1; 143 uint64_t pef_tpf0:1; 144 uint64_t pef_tpf1:1; 145 uint64_t rsl_p2e:1; 146 uint64_t peai_p2e:1; 147 uint64_t dbg_p2e:1; 148 uint64_t e2p_rsl:1; 149 uint64_t e2p_p:1; 150 uint64_t e2p_n:1; 151 uint64_t e2p_cpl:1; 152 uint64_t cto_p2e:1; 153 uint64_t reserved_14_63:50; 154#endif 155 } s; 156 struct cvmx_pescx_bist_status2_s cn52xx; 157 struct cvmx_pescx_bist_status2_s cn52xxp1; 158 struct cvmx_pescx_bist_status2_s cn56xx; 159 struct cvmx_pescx_bist_status2_s cn56xxp1; 160}; 161 162union cvmx_pescx_cfg_rd { 163 uint64_t u64; 164 struct cvmx_pescx_cfg_rd_s { 165#ifdef __BIG_ENDIAN_BITFIELD 166 uint64_t data:32; 167 uint64_t addr:32; 168#else 169 uint64_t addr:32; 170 uint64_t data:32; 171#endif 172 } s; 173 struct cvmx_pescx_cfg_rd_s cn52xx; 174 struct cvmx_pescx_cfg_rd_s cn52xxp1; 175 struct cvmx_pescx_cfg_rd_s cn56xx; 176 struct cvmx_pescx_cfg_rd_s cn56xxp1; 177}; 178 179union cvmx_pescx_cfg_wr { 180 uint64_t u64; 181 struct cvmx_pescx_cfg_wr_s { 182#ifdef __BIG_ENDIAN_BITFIELD 183 uint64_t data:32; 184 uint64_t addr:32; 185#else 186 uint64_t addr:32; 187 uint64_t data:32; 188#endif 189 } s; 190 struct cvmx_pescx_cfg_wr_s cn52xx; 191 struct cvmx_pescx_cfg_wr_s cn52xxp1; 192 struct cvmx_pescx_cfg_wr_s cn56xx; 193 struct cvmx_pescx_cfg_wr_s cn56xxp1; 194}; 195 196union cvmx_pescx_cpl_lut_valid { 197 uint64_t u64; 198 struct cvmx_pescx_cpl_lut_valid_s { 199#ifdef __BIG_ENDIAN_BITFIELD 200 uint64_t reserved_32_63:32; 201 uint64_t tag:32; 202#else 203 uint64_t tag:32; 204 uint64_t reserved_32_63:32; 205#endif 206 } s; 207 struct cvmx_pescx_cpl_lut_valid_s cn52xx; 208 struct cvmx_pescx_cpl_lut_valid_s cn52xxp1; 209 struct cvmx_pescx_cpl_lut_valid_s cn56xx; 210 struct cvmx_pescx_cpl_lut_valid_s cn56xxp1; 211}; 212 213union cvmx_pescx_ctl_status { 214 uint64_t u64; 215 struct cvmx_pescx_ctl_status_s { 216#ifdef __BIG_ENDIAN_BITFIELD 217 uint64_t reserved_28_63:36; 218 uint64_t dnum:5; 219 uint64_t pbus:8; 220 uint64_t qlm_cfg:2; 221 uint64_t lane_swp:1; 222 uint64_t pm_xtoff:1; 223 uint64_t pm_xpme:1; 224 uint64_t ob_p_cmd:1; 225 uint64_t reserved_7_8:2; 226 uint64_t nf_ecrc:1; 227 uint64_t dly_one:1; 228 uint64_t lnk_enb:1; 229 uint64_t ro_ctlp:1; 230 uint64_t reserved_2_2:1; 231 uint64_t inv_ecrc:1; 232 uint64_t inv_lcrc:1; 233#else 234 uint64_t inv_lcrc:1; 235 uint64_t inv_ecrc:1; 236 uint64_t reserved_2_2:1; 237 uint64_t ro_ctlp:1; 238 uint64_t lnk_enb:1; 239 uint64_t dly_one:1; 240 uint64_t nf_ecrc:1; 241 uint64_t reserved_7_8:2; 242 uint64_t ob_p_cmd:1; 243 uint64_t pm_xpme:1; 244 uint64_t pm_xtoff:1; 245 uint64_t lane_swp:1; 246 uint64_t qlm_cfg:2; 247 uint64_t pbus:8; 248 uint64_t dnum:5; 249 uint64_t reserved_28_63:36; 250#endif 251 } s; 252 struct cvmx_pescx_ctl_status_s cn52xx; 253 struct cvmx_pescx_ctl_status_s cn52xxp1; 254 struct cvmx_pescx_ctl_status_cn56xx { 255#ifdef __BIG_ENDIAN_BITFIELD 256 uint64_t reserved_28_63:36; 257 uint64_t dnum:5; 258 uint64_t pbus:8; 259 uint64_t qlm_cfg:2; 260 uint64_t reserved_12_12:1; 261 uint64_t pm_xtoff:1; 262 uint64_t pm_xpme:1; 263 uint64_t ob_p_cmd:1; 264 uint64_t reserved_7_8:2; 265 uint64_t nf_ecrc:1; 266 uint64_t dly_one:1; 267 uint64_t lnk_enb:1; 268 uint64_t ro_ctlp:1; 269 uint64_t reserved_2_2:1; 270 uint64_t inv_ecrc:1; 271 uint64_t inv_lcrc:1; 272#else 273 uint64_t inv_lcrc:1; 274 uint64_t inv_ecrc:1; 275 uint64_t reserved_2_2:1; 276 uint64_t ro_ctlp:1; 277 uint64_t lnk_enb:1; 278 uint64_t dly_one:1; 279 uint64_t nf_ecrc:1; 280 uint64_t reserved_7_8:2; 281 uint64_t ob_p_cmd:1; 282 uint64_t pm_xpme:1; 283 uint64_t pm_xtoff:1; 284 uint64_t reserved_12_12:1; 285 uint64_t qlm_cfg:2; 286 uint64_t pbus:8; 287 uint64_t dnum:5; 288 uint64_t reserved_28_63:36; 289#endif 290 } cn56xx; 291 struct cvmx_pescx_ctl_status_cn56xx cn56xxp1; 292}; 293 294union cvmx_pescx_ctl_status2 { 295 uint64_t u64; 296 struct cvmx_pescx_ctl_status2_s { 297#ifdef __BIG_ENDIAN_BITFIELD 298 uint64_t reserved_2_63:62; 299 uint64_t pclk_run:1; 300 uint64_t pcierst:1; 301#else 302 uint64_t pcierst:1; 303 uint64_t pclk_run:1; 304 uint64_t reserved_2_63:62; 305#endif 306 } s; 307 struct cvmx_pescx_ctl_status2_s cn52xx; 308 struct cvmx_pescx_ctl_status2_cn52xxp1 { 309#ifdef __BIG_ENDIAN_BITFIELD 310 uint64_t reserved_1_63:63; 311 uint64_t pcierst:1; 312#else 313 uint64_t pcierst:1; 314 uint64_t reserved_1_63:63; 315#endif 316 } cn52xxp1; 317 struct cvmx_pescx_ctl_status2_s cn56xx; 318 struct cvmx_pescx_ctl_status2_cn52xxp1 cn56xxp1; 319}; 320 321union cvmx_pescx_dbg_info { 322 uint64_t u64; 323 struct cvmx_pescx_dbg_info_s { 324#ifdef __BIG_ENDIAN_BITFIELD 325 uint64_t reserved_31_63:33; 326 uint64_t ecrc_e:1; 327 uint64_t rawwpp:1; 328 uint64_t racpp:1; 329 uint64_t ramtlp:1; 330 uint64_t rarwdns:1; 331 uint64_t caar:1; 332 uint64_t racca:1; 333 uint64_t racur:1; 334 uint64_t rauc:1; 335 uint64_t rqo:1; 336 uint64_t fcuv:1; 337 uint64_t rpe:1; 338 uint64_t fcpvwt:1; 339 uint64_t dpeoosd:1; 340 uint64_t rtwdle:1; 341 uint64_t rdwdle:1; 342 uint64_t mre:1; 343 uint64_t rte:1; 344 uint64_t acto:1; 345 uint64_t rvdm:1; 346 uint64_t rumep:1; 347 uint64_t rptamrc:1; 348 uint64_t rpmerc:1; 349 uint64_t rfemrc:1; 350 uint64_t rnfemrc:1; 351 uint64_t rcemrc:1; 352 uint64_t rpoison:1; 353 uint64_t recrce:1; 354 uint64_t rtlplle:1; 355 uint64_t rtlpmal:1; 356 uint64_t spoison:1; 357#else 358 uint64_t spoison:1; 359 uint64_t rtlpmal:1; 360 uint64_t rtlplle:1; 361 uint64_t recrce:1; 362 uint64_t rpoison:1; 363 uint64_t rcemrc:1; 364 uint64_t rnfemrc:1; 365 uint64_t rfemrc:1; 366 uint64_t rpmerc:1; 367 uint64_t rptamrc:1; 368 uint64_t rumep:1; 369 uint64_t rvdm:1; 370 uint64_t acto:1; 371 uint64_t rte:1; 372 uint64_t mre:1; 373 uint64_t rdwdle:1; 374 uint64_t rtwdle:1; 375 uint64_t dpeoosd:1; 376 uint64_t fcpvwt:1; 377 uint64_t rpe:1; 378 uint64_t fcuv:1; 379 uint64_t rqo:1; 380 uint64_t rauc:1; 381 uint64_t racur:1; 382 uint64_t racca:1; 383 uint64_t caar:1; 384 uint64_t rarwdns:1; 385 uint64_t ramtlp:1; 386 uint64_t racpp:1; 387 uint64_t rawwpp:1; 388 uint64_t ecrc_e:1; 389 uint64_t reserved_31_63:33; 390#endif 391 } s; 392 struct cvmx_pescx_dbg_info_s cn52xx; 393 struct cvmx_pescx_dbg_info_s cn52xxp1; 394 struct cvmx_pescx_dbg_info_s cn56xx; 395 struct cvmx_pescx_dbg_info_s cn56xxp1; 396}; 397 398union cvmx_pescx_dbg_info_en { 399 uint64_t u64; 400 struct cvmx_pescx_dbg_info_en_s { 401#ifdef __BIG_ENDIAN_BITFIELD 402 uint64_t reserved_31_63:33; 403 uint64_t ecrc_e:1; 404 uint64_t rawwpp:1; 405 uint64_t racpp:1; 406 uint64_t ramtlp:1; 407 uint64_t rarwdns:1; 408 uint64_t caar:1; 409 uint64_t racca:1; 410 uint64_t racur:1; 411 uint64_t rauc:1; 412 uint64_t rqo:1; 413 uint64_t fcuv:1; 414 uint64_t rpe:1; 415 uint64_t fcpvwt:1; 416 uint64_t dpeoosd:1; 417 uint64_t rtwdle:1; 418 uint64_t rdwdle:1; 419 uint64_t mre:1; 420 uint64_t rte:1; 421 uint64_t acto:1; 422 uint64_t rvdm:1; 423 uint64_t rumep:1; 424 uint64_t rptamrc:1; 425 uint64_t rpmerc:1; 426 uint64_t rfemrc:1; 427 uint64_t rnfemrc:1; 428 uint64_t rcemrc:1; 429 uint64_t rpoison:1; 430 uint64_t recrce:1; 431 uint64_t rtlplle:1; 432 uint64_t rtlpmal:1; 433 uint64_t spoison:1; 434#else 435 uint64_t spoison:1; 436 uint64_t rtlpmal:1; 437 uint64_t rtlplle:1; 438 uint64_t recrce:1; 439 uint64_t rpoison:1; 440 uint64_t rcemrc:1; 441 uint64_t rnfemrc:1; 442 uint64_t rfemrc:1; 443 uint64_t rpmerc:1; 444 uint64_t rptamrc:1; 445 uint64_t rumep:1; 446 uint64_t rvdm:1; 447 uint64_t acto:1; 448 uint64_t rte:1; 449 uint64_t mre:1; 450 uint64_t rdwdle:1; 451 uint64_t rtwdle:1; 452 uint64_t dpeoosd:1; 453 uint64_t fcpvwt:1; 454 uint64_t rpe:1; 455 uint64_t fcuv:1; 456 uint64_t rqo:1; 457 uint64_t rauc:1; 458 uint64_t racur:1; 459 uint64_t racca:1; 460 uint64_t caar:1; 461 uint64_t rarwdns:1; 462 uint64_t ramtlp:1; 463 uint64_t racpp:1; 464 uint64_t rawwpp:1; 465 uint64_t ecrc_e:1; 466 uint64_t reserved_31_63:33; 467#endif 468 } s; 469 struct cvmx_pescx_dbg_info_en_s cn52xx; 470 struct cvmx_pescx_dbg_info_en_s cn52xxp1; 471 struct cvmx_pescx_dbg_info_en_s cn56xx; 472 struct cvmx_pescx_dbg_info_en_s cn56xxp1; 473}; 474 475union cvmx_pescx_diag_status { 476 uint64_t u64; 477 struct cvmx_pescx_diag_status_s { 478#ifdef __BIG_ENDIAN_BITFIELD 479 uint64_t reserved_4_63:60; 480 uint64_t pm_dst:1; 481 uint64_t pm_stat:1; 482 uint64_t pm_en:1; 483 uint64_t aux_en:1; 484#else 485 uint64_t aux_en:1; 486 uint64_t pm_en:1; 487 uint64_t pm_stat:1; 488 uint64_t pm_dst:1; 489 uint64_t reserved_4_63:60; 490#endif 491 } s; 492 struct cvmx_pescx_diag_status_s cn52xx; 493 struct cvmx_pescx_diag_status_s cn52xxp1; 494 struct cvmx_pescx_diag_status_s cn56xx; 495 struct cvmx_pescx_diag_status_s cn56xxp1; 496}; 497 498union cvmx_pescx_p2n_bar0_start { 499 uint64_t u64; 500 struct cvmx_pescx_p2n_bar0_start_s { 501#ifdef __BIG_ENDIAN_BITFIELD 502 uint64_t addr:50; 503 uint64_t reserved_0_13:14; 504#else 505 uint64_t reserved_0_13:14; 506 uint64_t addr:50; 507#endif 508 } s; 509 struct cvmx_pescx_p2n_bar0_start_s cn52xx; 510 struct cvmx_pescx_p2n_bar0_start_s cn52xxp1; 511 struct cvmx_pescx_p2n_bar0_start_s cn56xx; 512 struct cvmx_pescx_p2n_bar0_start_s cn56xxp1; 513}; 514 515union cvmx_pescx_p2n_bar1_start { 516 uint64_t u64; 517 struct cvmx_pescx_p2n_bar1_start_s { 518#ifdef __BIG_ENDIAN_BITFIELD 519 uint64_t addr:38; 520 uint64_t reserved_0_25:26; 521#else 522 uint64_t reserved_0_25:26; 523 uint64_t addr:38; 524#endif 525 } s; 526 struct cvmx_pescx_p2n_bar1_start_s cn52xx; 527 struct cvmx_pescx_p2n_bar1_start_s cn52xxp1; 528 struct cvmx_pescx_p2n_bar1_start_s cn56xx; 529 struct cvmx_pescx_p2n_bar1_start_s cn56xxp1; 530}; 531 532union cvmx_pescx_p2n_bar2_start { 533 uint64_t u64; 534 struct cvmx_pescx_p2n_bar2_start_s { 535#ifdef __BIG_ENDIAN_BITFIELD 536 uint64_t addr:25; 537 uint64_t reserved_0_38:39; 538#else 539 uint64_t reserved_0_38:39; 540 uint64_t addr:25; 541#endif 542 } s; 543 struct cvmx_pescx_p2n_bar2_start_s cn52xx; 544 struct cvmx_pescx_p2n_bar2_start_s cn52xxp1; 545 struct cvmx_pescx_p2n_bar2_start_s cn56xx; 546 struct cvmx_pescx_p2n_bar2_start_s cn56xxp1; 547}; 548 549union cvmx_pescx_p2p_barx_end { 550 uint64_t u64; 551 struct cvmx_pescx_p2p_barx_end_s { 552#ifdef __BIG_ENDIAN_BITFIELD 553 uint64_t addr:52; 554 uint64_t reserved_0_11:12; 555#else 556 uint64_t reserved_0_11:12; 557 uint64_t addr:52; 558#endif 559 } s; 560 struct cvmx_pescx_p2p_barx_end_s cn52xx; 561 struct cvmx_pescx_p2p_barx_end_s cn52xxp1; 562 struct cvmx_pescx_p2p_barx_end_s cn56xx; 563 struct cvmx_pescx_p2p_barx_end_s cn56xxp1; 564}; 565 566union cvmx_pescx_p2p_barx_start { 567 uint64_t u64; 568 struct cvmx_pescx_p2p_barx_start_s { 569#ifdef __BIG_ENDIAN_BITFIELD 570 uint64_t addr:52; 571 uint64_t reserved_0_11:12; 572#else 573 uint64_t reserved_0_11:12; 574 uint64_t addr:52; 575#endif 576 } s; 577 struct cvmx_pescx_p2p_barx_start_s cn52xx; 578 struct cvmx_pescx_p2p_barx_start_s cn52xxp1; 579 struct cvmx_pescx_p2p_barx_start_s cn56xx; 580 struct cvmx_pescx_p2p_barx_start_s cn56xxp1; 581}; 582 583union cvmx_pescx_tlp_credits { 584 uint64_t u64; 585 struct cvmx_pescx_tlp_credits_s { 586#ifdef __BIG_ENDIAN_BITFIELD 587 uint64_t reserved_0_63:64; 588#else 589 uint64_t reserved_0_63:64; 590#endif 591 } s; 592 struct cvmx_pescx_tlp_credits_cn52xx { 593#ifdef __BIG_ENDIAN_BITFIELD 594 uint64_t reserved_56_63:8; 595 uint64_t peai_ppf:8; 596 uint64_t pesc_cpl:8; 597 uint64_t pesc_np:8; 598 uint64_t pesc_p:8; 599 uint64_t npei_cpl:8; 600 uint64_t npei_np:8; 601 uint64_t npei_p:8; 602#else 603 uint64_t npei_p:8; 604 uint64_t npei_np:8; 605 uint64_t npei_cpl:8; 606 uint64_t pesc_p:8; 607 uint64_t pesc_np:8; 608 uint64_t pesc_cpl:8; 609 uint64_t peai_ppf:8; 610 uint64_t reserved_56_63:8; 611#endif 612 } cn52xx; 613 struct cvmx_pescx_tlp_credits_cn52xxp1 { 614#ifdef __BIG_ENDIAN_BITFIELD 615 uint64_t reserved_38_63:26; 616 uint64_t peai_ppf:8; 617 uint64_t pesc_cpl:5; 618 uint64_t pesc_np:5; 619 uint64_t pesc_p:5; 620 uint64_t npei_cpl:5; 621 uint64_t npei_np:5; 622 uint64_t npei_p:5; 623#else 624 uint64_t npei_p:5; 625 uint64_t npei_np:5; 626 uint64_t npei_cpl:5; 627 uint64_t pesc_p:5; 628 uint64_t pesc_np:5; 629 uint64_t pesc_cpl:5; 630 uint64_t peai_ppf:8; 631 uint64_t reserved_38_63:26; 632#endif 633 } cn52xxp1; 634 struct cvmx_pescx_tlp_credits_cn52xx cn56xx; 635 struct cvmx_pescx_tlp_credits_cn52xxp1 cn56xxp1; 636}; 637 638#endif 639