LXR linux/arch/powerpc/boot/cuboot-pq2.c

   1/*
   2 * Old U-boot compatibility for PowerQUICC II
   3 * (a.k.a. 82xx with CPM, not the 8240 family of chips)
   4 *
   5 * Author: Scott Wood <scottwood@freescale.com>
   6 *
   7 * Copyright (c) 2007 Freescale Semiconductor, Inc.
   8 *
   9 * This program is free software; you can redistribute it and/or modify it
  10 * under the terms of the GNU General Public License version 2 as published
  11 * by the Free Software Foundation.
  12 */
  13
  14#include "ops.h"
  15#include "stdio.h"
  16#include "cuboot.h"
  17#include "io.h"
  18#include "fsl-soc.h"
  19
  20#define TARGET_CPM2
  21#define TARGET_HAS_ETH1
  22#include "ppcboot.h"
  23
  24static bd_t bd;
  25
  26struct cs_range {
  27        u32 csnum;
  28        u32 base; /* must be zero */
  29        u32 addr;
  30        u32 size;
  31};
  32
  33struct pci_range {
  34        u32 flags;
  35        u32 pci_addr[2];
  36        u32 phys_addr;
  37        u32 size[2];
  38};
  39
  40struct cs_range cs_ranges_buf[MAX_PROP_LEN / sizeof(struct cs_range)];
  41struct pci_range pci_ranges_buf[MAX_PROP_LEN / sizeof(struct pci_range)];
  42
  43/* Different versions of u-boot put the BCSR in different places, and
  44 * some don't set up the PCI PIC at all, so we assume the device tree is
  45 * sane and update the BRx registers appropriately.
  46 *
  47 * For any node defined as compatible with fsl,pq2-localbus,
  48 * #address/#size must be 2/1 for the localbus, and 1/1 for the parent bus.
  49 * Ranges must be for whole chip selects.
  50 */
  51static void update_cs_ranges(void)
  52{
  53        void *bus_node, *parent_node;
  54        u32 *ctrl_addr;
  55        unsigned long ctrl_size;
  56        u32 naddr, nsize;
  57        int len;
  58        int i;
  59
  60        bus_node = finddevice("/localbus");
  61        if (!bus_node || !dt_is_compatible(bus_node, "fsl,pq2-localbus"))
  62                return;
  63
  64        dt_get_reg_format(bus_node, &naddr, &nsize);
  65        if (naddr != 2 || nsize != 1)
  66                goto err;
  67
  68        parent_node = get_parent(bus_node);
  69        if (!parent_node)
  70                goto err;
  71
  72        dt_get_reg_format(parent_node, &naddr, &nsize);
  73        if (naddr != 1 || nsize != 1)
  74                goto err;
  75
  76        if (!dt_xlate_reg(bus_node, 0, (unsigned long *)&ctrl_addr,
  77                          &ctrl_size))
  78                goto err;
  79
  80        len = getprop(bus_node, "ranges", cs_ranges_buf, sizeof(cs_ranges_buf));
  81
  82        for (i = 0; i < len / sizeof(struct cs_range); i++) {
  83                u32 base, option;
  84                int cs = cs_ranges_buf[i].csnum;
  85                if (cs >= ctrl_size / 8)
  86                        goto err;
  87
  88                if (cs_ranges_buf[i].base != 0)
  89                        goto err;
  90
  91                base = in_be32(&ctrl_addr[cs * 2]);
  92
  93                /* If CS is already valid, use the existing flags.
  94                 * Otherwise, guess a sane default.
  95                 */
  96                if (base & 1) {
  97                        base &= 0x7fff;
  98                        option = in_be32(&ctrl_addr[cs * 2 + 1]) & 0x7fff;
  99                } else {
 100                        base = 0x1801;
 101                        option = 0x10;
 102                }
 103
 104                out_be32(&ctrl_addr[cs * 2], 0);
 105                out_be32(&ctrl_addr[cs * 2 + 1],
 106                         option | ~(cs_ranges_buf[i].size - 1));
 107                out_be32(&ctrl_addr[cs * 2], base | cs_ranges_buf[i].addr);
 108        }
 109
 110        return;
 111
 112err:
 113        printf("Bad /localbus node\r\n");
 114}
 115
 116/* Older u-boots don't set PCI up properly.  Update the hardware to match
 117 * the device tree.  The prefetch mem region and non-prefetch mem region
 118 * must be contiguous in the host bus.  As required by the PCI binding,
 119 * PCI #addr/#size must be 3/2.  The parent bus must be 1/1.  Only
 120 * 32-bit PCI is supported.  All three region types (prefetchable mem,
 121 * non-prefetchable mem, and I/O) must be present.
 122 */
 123static void fixup_pci(void)
 124{
 125        struct pci_range *mem = NULL, *mmio = NULL,
 126                         *io = NULL, *mem_base = NULL;
 127        u32 *pci_regs[3];
 128        u8 *soc_regs;
 129        int i, len;
 130        void *node, *parent_node;
 131        u32 naddr, nsize, mem_pow2, mem_mask;
 132
 133        node = finddevice("/pci");
 134        if (!node || !dt_is_compatible(node, "fsl,pq2-pci"))
 135                return;
 136
 137        for (i = 0; i < 3; i++)
 138                if (!dt_xlate_reg(node, i,
 139                                  (unsigned long *)&pci_regs[i], NULL))
 140                        goto err;
 141
 142        soc_regs = (u8 *)fsl_get_immr();
 143        if (!soc_regs)
 144                goto unhandled;
 145
 146        dt_get_reg_format(node, &naddr, &nsize);
 147        if (naddr != 3 || nsize != 2)
 148                goto err;
 149
 150        parent_node = get_parent(node);
 151        if (!parent_node)
 152                goto err;
 153
 154        dt_get_reg_format(parent_node, &naddr, &nsize);
 155        if (naddr != 1 || nsize != 1)
 156                goto unhandled;
 157
 158        len = getprop(node, "ranges", pci_ranges_buf,
 159                      sizeof(pci_ranges_buf));
 160
 161        for (i = 0; i < len / sizeof(struct pci_range); i++) {
 162                u32 flags = pci_ranges_buf[i].flags & 0x43000000;
 163
 164                if (flags == 0x42000000)
 165                        mem = &pci_ranges_buf[i];
 166                else if (flags == 0x02000000)
 167                        mmio = &pci_ranges_buf[i];
 168                else if (flags == 0x01000000)
 169                        io = &pci_ranges_buf[i];
 170        }
 171
 172        if (!mem || !mmio || !io)
 173                goto unhandled;
 174        if (mem->size[1] != mmio->size[1])
 175                goto unhandled;
 176        if (mem->size[1] & (mem->size[1] - 1))
 177                goto unhandled;
 178        if (io->size[1] & (io->size[1] - 1))
 179                goto unhandled;
 180
 181        if (mem->phys_addr + mem->size[1] == mmio->phys_addr)
 182                mem_base = mem;
 183        else if (mmio->phys_addr + mmio->size[1] == mem->phys_addr)
 184                mem_base = mmio;
 185        else
 186                goto unhandled;
 187
 188        out_be32(&pci_regs[1][0], mem_base->phys_addr | 1);
 189        out_be32(&pci_regs[2][0], ~(mem->size[1] + mmio->size[1] - 1));
 190
 191        out_be32(&pci_regs[1][1], io->phys_addr | 1);
 192        out_be32(&pci_regs[2][1], ~(io->size[1] - 1));
 193
 194        out_le32(&pci_regs[0][0], mem->pci_addr[1] >> 12);
 195        out_le32(&pci_regs[0][2], mem->phys_addr >> 12);
 196        out_le32(&pci_regs[0][4], (~(mem->size[1] - 1) >> 12) | 0xa0000000);
 197
 198        out_le32(&pci_regs[0][6], mmio->pci_addr[1] >> 12);
 199        out_le32(&pci_regs[0][8], mmio->phys_addr >> 12);
 200        out_le32(&pci_regs[0][10], (~(mmio->size[1] - 1) >> 12) | 0x80000000);
 201
 202        out_le32(&pci_regs[0][12], io->pci_addr[1] >> 12);
 203        out_le32(&pci_regs[0][14], io->phys_addr >> 12);
 204        out_le32(&pci_regs[0][16], (~(io->size[1] - 1) >> 12) | 0xc0000000);
 205
 206        /* Inbound translation */
 207        out_le32(&pci_regs[0][58], 0);
 208        out_le32(&pci_regs[0][60], 0);
 209
 210        mem_pow2 = 1 << (__ilog2_u32(bd.bi_memsize - 1) + 1);
 211        mem_mask = ~(mem_pow2 - 1) >> 12;
 212        out_le32(&pci_regs[0][62], 0xa0000000 | mem_mask);
 213
 214        /* If PCI is disabled, drive RST high to enable. */
 215        if (!(in_le32(&pci_regs[0][32]) & 1)) {
 216                 /* Tpvrh (Power valid to RST# high) 100 ms */
 217                udelay(100000);
 218
 219                out_le32(&pci_regs[0][32], 1);
 220
 221                /* Trhfa (RST# high to first cfg access) 2^25 clocks */
 222                udelay(1020000);
 223        }
 224
 225        /* Enable bus master and memory access */
 226        out_le32(&pci_regs[0][64], 0x80000004);
 227        out_le32(&pci_regs[0][65], in_le32(&pci_regs[0][65]) | 6);
 228
 229        /* Park the bus on PCI, and elevate PCI's arbitration priority,
 230         * as required by section 9.6 of the user's manual.
 231         */
 232        out_8(&soc_regs[0x10028], 3);
 233        out_be32((u32 *)&soc_regs[0x1002c], 0x01236745);
 234
 235        return;
 236
 237err:
 238        printf("Bad PCI node -- using existing firmware setup.\r\n");
 239        return;
 240
 241unhandled:
 242        printf("Unsupported PCI node -- using existing firmware setup.\r\n");
 243}
 244
 245static void pq2_platform_fixups(void)
 246{
 247        void *node;
 248
 249        dt_fixup_memory(bd.bi_memstart, bd.bi_memsize);
 250        dt_fixup_mac_addresses(bd.bi_enetaddr, bd.bi_enet1addr);
 251        dt_fixup_cpu_clocks(bd.bi_intfreq, bd.bi_busfreq / 4, bd.bi_busfreq);
 252
 253        node = finddevice("/soc/cpm");
 254        if (node)
 255                setprop(node, "clock-frequency", &bd.bi_cpmfreq, 4);
 256
 257        node = finddevice("/soc/cpm/brg");
 258        if (node)
 259                setprop(node, "clock-frequency",  &bd.bi_brgfreq, 4);
 260
 261        update_cs_ranges();
 262        fixup_pci();
 263}
 264
 265void platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 266                   unsigned long r6, unsigned long r7)
 267{
 268        CUBOOT_INIT();
 269        fdt_init(_dtb_start);
 270        serial_console_init();
 271        platform_ops.fixups = pq2_platform_fixups;
 272}
 273