LXR linux/arch/powerpc/include/asm/processor.h

   1#ifndef _ASM_POWERPC_PROCESSOR_H
   2#define _ASM_POWERPC_PROCESSOR_H
   3
   4/*
   5 * Copyright (C) 2001 PPC 64 Team, IBM Corp
   6 *
   7 * This program is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU General Public License
   9 * as published by the Free Software Foundation; either version
  10 * 2 of the License, or (at your option) any later version.
  11 */
  12
  13#include <asm/reg.h>
  14
  15#ifdef CONFIG_VSX
  16#define TS_FPRWIDTH 2
  17#else
  18#define TS_FPRWIDTH 1
  19#endif
  20
  21#ifdef CONFIG_PPC64
  22/* Default SMT priority is set to 3. Use 11- 13bits to save priority. */
  23#define PPR_PRIORITY 3
  24#ifdef __ASSEMBLY__
  25#define INIT_PPR (PPR_PRIORITY << 50)
  26#else
  27#define INIT_PPR ((u64)PPR_PRIORITY << 50)
  28#endif /* __ASSEMBLY__ */
  29#endif /* CONFIG_PPC64 */
  30
  31#ifndef __ASSEMBLY__
  32#include <linux/compiler.h>
  33#include <linux/cache.h>
  34#include <asm/ptrace.h>
  35#include <asm/types.h>
  36#include <asm/hw_breakpoint.h>
  37
  38/* We do _not_ want to define new machine types at all, those must die
  39 * in favor of using the device-tree
  40 * -- BenH.
  41 */
  42
  43/* PREP sub-platform types. Unused */
  44#define _PREP_Motorola  0x01    /* motorola prep */
  45#define _PREP_Firm      0x02    /* firmworks prep */
  46#define _PREP_IBM       0x00    /* ibm prep */
  47#define _PREP_Bull      0x03    /* bull prep */
  48
  49/* CHRP sub-platform types. These are arbitrary */
  50#define _CHRP_Motorola  0x04    /* motorola chrp, the cobra */
  51#define _CHRP_IBM       0x05    /* IBM chrp, the longtrail and longtrail 2 */
  52#define _CHRP_Pegasos   0x06    /* Genesi/bplan's Pegasos and Pegasos2 */
  53#define _CHRP_briq      0x07    /* TotalImpact's briQ */
  54
  55#if defined(__KERNEL__) && defined(CONFIG_PPC32)
  56
  57extern int _chrp_type;
  58
  59#endif /* defined(__KERNEL__) && defined(CONFIG_PPC32) */
  60
  61/*
  62 * Default implementation of macro that returns current
  63 * instruction pointer ("program counter").
  64 */
  65#define current_text_addr() ({ __label__ _l; _l: &&_l;})
  66
  67/* Macros for adjusting thread priority (hardware multi-threading) */
  68#define HMT_very_low()   asm volatile("or 31,31,31   # very low priority")
  69#define HMT_low()        asm volatile("or 1,1,1      # low priority")
  70#define HMT_medium_low() asm volatile("or 6,6,6      # medium low priority")
  71#define HMT_medium()     asm volatile("or 2,2,2      # medium priority")
  72#define HMT_medium_high() asm volatile("or 5,5,5      # medium high priority")
  73#define HMT_high()       asm volatile("or 3,3,3      # high priority")
  74
  75#ifdef __KERNEL__
  76
  77struct task_struct;
  78void start_thread(struct pt_regs *regs, unsigned long fdptr, unsigned long sp);
  79void release_thread(struct task_struct *);
  80
  81/* Lazy FPU handling on uni-processor */
  82extern struct task_struct *last_task_used_math;
  83extern struct task_struct *last_task_used_altivec;
  84extern struct task_struct *last_task_used_vsx;
  85extern struct task_struct *last_task_used_spe;
  86
  87#ifdef CONFIG_PPC32
  88
  89#if CONFIG_TASK_SIZE > CONFIG_KERNEL_START
  90#error User TASK_SIZE overlaps with KERNEL_START address
  91#endif
  92#define TASK_SIZE       (CONFIG_TASK_SIZE)
  93
  94/* This decides where the kernel will search for a free chunk of vm
  95 * space during mmap's.
  96 */
  97#define TASK_UNMAPPED_BASE      (TASK_SIZE / 8 * 3)
  98#endif
  99
 100#ifdef CONFIG_PPC64
 101/* 64-bit user address space is 46-bits (64TB user VM) */
 102#define TASK_SIZE_USER64 (0x0000400000000000UL)
 103
 104/* 
 105 * 32-bit user address space is 4GB - 1 page 
 106 * (this 1 page is needed so referencing of 0xFFFFFFFF generates EFAULT
 107 */
 108#define TASK_SIZE_USER32 (0x0000000100000000UL - (1*PAGE_SIZE))
 109
 110#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
 111                TASK_SIZE_USER32 : TASK_SIZE_USER64)
 112#define TASK_SIZE         TASK_SIZE_OF(current)
 113
 114/* This decides where the kernel will search for a free chunk of vm
 115 * space during mmap's.
 116 */
 117#define TASK_UNMAPPED_BASE_USER32 (PAGE_ALIGN(TASK_SIZE_USER32 / 4))
 118#define TASK_UNMAPPED_BASE_USER64 (PAGE_ALIGN(TASK_SIZE_USER64 / 4))
 119
 120#define TASK_UNMAPPED_BASE ((is_32bit_task()) ? \
 121                TASK_UNMAPPED_BASE_USER32 : TASK_UNMAPPED_BASE_USER64 )
 122#endif
 123
 124#ifdef __powerpc64__
 125
 126#define STACK_TOP_USER64 TASK_SIZE_USER64
 127#define STACK_TOP_USER32 TASK_SIZE_USER32
 128
 129#define STACK_TOP (is_32bit_task() ? \
 130                   STACK_TOP_USER32 : STACK_TOP_USER64)
 131
 132#define STACK_TOP_MAX STACK_TOP_USER64
 133
 134#else /* __powerpc64__ */
 135
 136#define STACK_TOP TASK_SIZE
 137#define STACK_TOP_MAX   STACK_TOP
 138
 139#endif /* __powerpc64__ */
 140
 141typedef struct {
 142        unsigned long seg;
 143} mm_segment_t;
 144
 145#define TS_FPROFFSET 0
 146#define TS_VSRLOWOFFSET 1
 147#define TS_FPR(i) fpr[i][TS_FPROFFSET]
 148#define TS_TRANS_FPR(i) transact_fpr[i][TS_FPROFFSET]
 149
 150struct thread_struct {
 151        unsigned long   ksp;            /* Kernel stack pointer */
 152#ifdef CONFIG_PPC64
 153        unsigned long   ksp_vsid;
 154#endif
 155        struct pt_regs  *regs;          /* Pointer to saved register state */
 156        mm_segment_t    fs;             /* for get_fs() validation */
 157#ifdef CONFIG_BOOKE
 158        /* BookE base exception scratch space; align on cacheline */
 159        unsigned long   normsave[8] ____cacheline_aligned;
 160#endif
 161#ifdef CONFIG_PPC32
 162        void            *pgdir;         /* root of page-table tree */
 163        unsigned long   ksp_limit;      /* if ksp <= ksp_limit stack overflow */
 164#endif
 165#ifdef CONFIG_PPC_ADV_DEBUG_REGS
 166        /*
 167         * The following help to manage the use of Debug Control Registers
 168         * om the BookE platforms.
 169         */
 170        uint32_t        dbcr0;
 171        uint32_t        dbcr1;
 172#ifdef CONFIG_BOOKE
 173        uint32_t        dbcr2;
 174#endif
 175        /*
 176         * The stored value of the DBSR register will be the value at the
 177         * last debug interrupt. This register can only be read from the
 178         * user (will never be written to) and has value while helping to
 179         * describe the reason for the last debug trap.  Torez
 180         */
 181        uint32_t        dbsr;
 182        /*
 183         * The following will contain addresses used by debug applications
 184         * to help trace and trap on particular address locations.
 185         * The bits in the Debug Control Registers above help define which
 186         * of the following registers will contain valid data and/or addresses.
 187         */
 188        unsigned long   iac1;
 189        unsigned long   iac2;
 190#if CONFIG_PPC_ADV_DEBUG_IACS > 2
 191        unsigned long   iac3;
 192        unsigned long   iac4;
 193#endif
 194        unsigned long   dac1;
 195        unsigned long   dac2;
 196#if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 197        unsigned long   dvc1;
 198        unsigned long   dvc2;
 199#endif
 200#endif
 201        /* FP and VSX 0-31 register set */
 202        double          fpr[32][TS_FPRWIDTH] __attribute__((aligned(16)));
 203        struct {
 204
 205                unsigned int pad;
 206                unsigned int val;       /* Floating point status */
 207        } fpscr;
 208        int             fpexc_mode;     /* floating-point exception mode */
 209        unsigned int    align_ctl;      /* alignment handling control */
 210#ifdef CONFIG_PPC64
 211        unsigned long   start_tb;       /* Start purr when proc switched in */
 212        unsigned long   accum_tb;       /* Total accumilated purr for process */
 213#ifdef CONFIG_HAVE_HW_BREAKPOINT
 214        struct perf_event *ptrace_bps[HBP_NUM];
 215        /*
 216         * Helps identify source of single-step exception and subsequent
 217         * hw-breakpoint enablement
 218         */
 219        struct perf_event *last_hit_ubp;
 220#endif /* CONFIG_HAVE_HW_BREAKPOINT */
 221#endif
 222        struct arch_hw_breakpoint hw_brk; /* info on the hardware breakpoint */
 223        unsigned long   trap_nr;        /* last trap # on this thread */
 224#ifdef CONFIG_ALTIVEC
 225        /* Complete AltiVec register set */
 226        vector128       vr[32] __attribute__((aligned(16)));
 227        /* AltiVec status */
 228        vector128       vscr __attribute__((aligned(16)));
 229        unsigned long   vrsave;
 230        int             used_vr;        /* set if process has used altivec */
 231#endif /* CONFIG_ALTIVEC */
 232#ifdef CONFIG_VSX
 233        /* VSR status */
 234        int             used_vsr;       /* set if process has used altivec */
 235#endif /* CONFIG_VSX */
 236#ifdef CONFIG_SPE
 237        unsigned long   evr[32];        /* upper 32-bits of SPE regs */
 238        u64             acc;            /* Accumulator */
 239        unsigned long   spefscr;        /* SPE & eFP status */
 240        int             used_spe;       /* set if process has used spe */
 241#endif /* CONFIG_SPE */
 242#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 243        u64             tm_tfhar;       /* Transaction fail handler addr */
 244        u64             tm_texasr;      /* Transaction exception & summary */
 245        u64             tm_tfiar;       /* Transaction fail instr address reg */
 246        unsigned long   tm_orig_msr;    /* Thread's MSR on ctx switch */
 247        struct pt_regs  ckpt_regs;      /* Checkpointed registers */
 248
 249        unsigned long   tm_tar;
 250        unsigned long   tm_ppr;
 251        unsigned long   tm_dscr;
 252
 253        /*
 254         * Transactional FP and VSX 0-31 register set.
 255         * NOTE: the sense of these is the opposite of the integer ckpt_regs!
 256         *
 257         * When a transaction is active/signalled/scheduled etc., *regs is the
 258         * most recent set of/speculated GPRs with ckpt_regs being the older
 259         * checkpointed regs to which we roll back if transaction aborts.
 260         *
 261         * However, fpr[] is the checkpointed 'base state' of FP regs, and
 262         * transact_fpr[] is the new set of transactional values.
 263         * VRs work the same way.
 264         */
 265        double          transact_fpr[32][TS_FPRWIDTH];
 266        struct {
 267                unsigned int pad;
 268                unsigned int val;       /* Floating point status */
 269        } transact_fpscr;
 270        vector128       transact_vr[32] __attribute__((aligned(16)));
 271        vector128       transact_vscr __attribute__((aligned(16)));
 272        unsigned long   transact_vrsave;
 273#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 274#ifdef CONFIG_KVM_BOOK3S_32_HANDLER
 275        void*           kvm_shadow_vcpu; /* KVM internal data */
 276#endif /* CONFIG_KVM_BOOK3S_32_HANDLER */
 277#if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
 278        struct kvm_vcpu *kvm_vcpu;
 279#endif
 280#ifdef CONFIG_PPC64
 281        unsigned long   dscr;
 282        int             dscr_inherit;
 283        unsigned long   ppr;    /* used to save/restore SMT priority */
 284#endif
 285#ifdef CONFIG_PPC_BOOK3S_64
 286        unsigned long   tar;
 287        unsigned long   ebbrr;
 288        unsigned long   ebbhr;
 289        unsigned long   bescr;
 290        unsigned long   siar;
 291        unsigned long   sdar;
 292        unsigned long   sier;
 293        unsigned long   mmcr2;
 294        unsigned        mmcr0;
 295        unsigned        used_ebb;
 296#endif
 297};
 298
 299#define ARCH_MIN_TASKALIGN 16
 300
 301#define INIT_SP         (sizeof(init_stack) + (unsigned long) &init_stack)
 302#define INIT_SP_LIMIT \
 303        (_ALIGN_UP(sizeof(init_thread_info), 16) + (unsigned long) &init_stack)
 304
 305#ifdef CONFIG_SPE
 306#define SPEFSCR_INIT .spefscr = SPEFSCR_FINVE | SPEFSCR_FDBZE | SPEFSCR_FUNFE | SPEFSCR_FOVFE,
 307#else
 308#define SPEFSCR_INIT
 309#endif
 310
 311#ifdef CONFIG_PPC32
 312#define INIT_THREAD { \
 313        .ksp = INIT_SP, \
 314        .ksp_limit = INIT_SP_LIMIT, \
 315        .fs = KERNEL_DS, \
 316        .pgdir = swapper_pg_dir, \
 317        .fpexc_mode = MSR_FE0 | MSR_FE1, \
 318        SPEFSCR_INIT \
 319}
 320#else
 321#define INIT_THREAD  { \
 322        .ksp = INIT_SP, \
 323        .regs = (struct pt_regs *)INIT_SP - 1, /* XXX bogus, I think */ \
 324        .fs = KERNEL_DS, \
 325        .fpr = {{0}}, \
 326        .fpscr = { .val = 0, }, \
 327        .fpexc_mode = 0, \
 328        .ppr = INIT_PPR, \
 329}
 330#endif
 331
 332/*
 333 * Return saved PC of a blocked thread. For now, this is the "user" PC
 334 */
 335#define thread_saved_pc(tsk)    \
 336        ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 337
 338#define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.regs)
 339
 340unsigned long get_wchan(struct task_struct *p);
 341
 342#define KSTK_EIP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
 343#define KSTK_ESP(tsk)  ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
 344
 345/* Get/set floating-point exception mode */
 346#define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
 347#define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
 348
 349extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
 350extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
 351
 352#define GET_ENDIAN(tsk, adr) get_endian((tsk), (adr))
 353#define SET_ENDIAN(tsk, val) set_endian((tsk), (val))
 354
 355extern int get_endian(struct task_struct *tsk, unsigned long adr);
 356extern int set_endian(struct task_struct *tsk, unsigned int val);
 357
 358#define GET_UNALIGN_CTL(tsk, adr)       get_unalign_ctl((tsk), (adr))
 359#define SET_UNALIGN_CTL(tsk, val)       set_unalign_ctl((tsk), (val))
 360
 361extern int get_unalign_ctl(struct task_struct *tsk, unsigned long adr);
 362extern int set_unalign_ctl(struct task_struct *tsk, unsigned int val);
 363
 364static inline unsigned int __unpack_fe01(unsigned long msr_bits)
 365{
 366        return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8);
 367}
 368
 369static inline unsigned long __pack_fe01(unsigned int fpmode)
 370{
 371        return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1);
 372}
 373
 374#ifdef CONFIG_PPC64
 375#define cpu_relax()     do { HMT_low(); HMT_medium(); barrier(); } while (0)
 376#else
 377#define cpu_relax()     barrier()
 378#endif
 379
 380/* Check that a certain kernel stack pointer is valid in task_struct p */
 381int validate_sp(unsigned long sp, struct task_struct *p,
 382                       unsigned long nbytes);
 383
 384/*
 385 * Prefetch macros.
 386 */
 387#define ARCH_HAS_PREFETCH
 388#define ARCH_HAS_PREFETCHW
 389#define ARCH_HAS_SPINLOCK_PREFETCH
 390
 391static inline void prefetch(const void *x)
 392{
 393        if (unlikely(!x))
 394                return;
 395
 396        __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
 397}
 398
 399static inline void prefetchw(const void *x)
 400{
 401        if (unlikely(!x))
 402                return;
 403
 404        __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
 405}
 406
 407#define spin_lock_prefetch(x)   prefetchw(x)
 408
 409#define HAVE_ARCH_PICK_MMAP_LAYOUT
 410
 411#ifdef CONFIG_PPC64
 412static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
 413{
 414        if (is_32)
 415                return sp & 0x0ffffffffUL;
 416        return sp;
 417}
 418#else
 419static inline unsigned long get_clean_sp(unsigned long sp, int is_32)
 420{
 421        return sp;
 422}
 423#endif
 424
 425extern unsigned long cpuidle_disable;
 426enum idle_boot_override {IDLE_NO_OVERRIDE = 0, IDLE_POWERSAVE_OFF};
 427
 428extern int powersave_nap;       /* set if nap mode can be used in idle loop */
 429extern void power7_nap(void);
 430
 431#ifdef CONFIG_PSERIES_IDLE
 432extern void update_smt_snooze_delay(int cpu, int residency);
 433#else
 434static inline void update_smt_snooze_delay(int cpu, int residency) {}
 435#endif
 436
 437extern void flush_instruction_cache(void);
 438extern void hard_reset_now(void);
 439extern void poweroff_now(void);
 440extern int fix_alignment(struct pt_regs *);
 441extern void cvt_fd(float *from, double *to);
 442extern void cvt_df(double *from, float *to);
 443extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
 444
 445#ifdef CONFIG_PPC64
 446/*
 447 * We handle most unaligned accesses in hardware. On the other hand 
 448 * unaligned DMA can be very expensive on some ppc64 IO chips (it does
 449 * powers of 2 writes until it reaches sufficient alignment).
 450 *
 451 * Based on this we disable the IP header alignment in network drivers.
 452 */
 453#define NET_IP_ALIGN    0
 454#endif
 455
 456#endif /* __KERNEL__ */
 457#endif /* __ASSEMBLY__ */
 458#endif /* _ASM_POWERPC_PROCESSOR_H */
 459