LXR linux/arch/powerpc/include/asm/smp.h

   1/* 
   2 * smp.h: PowerPC-specific SMP code.
   3 *
   4 * Original was a copy of sparc smp.h.  Now heavily modified
   5 * for PPC.
   6 *
   7 * Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
   8 * Copyright (C) 1996-2001 Cort Dougan <cort@fsmlabs.com>
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License
  12 * as published by the Free Software Foundation; either version
  13 * 2 of the License, or (at your option) any later version.
  14 */
  15
  16#ifndef _ASM_POWERPC_SMP_H
  17#define _ASM_POWERPC_SMP_H
  18#ifdef __KERNEL__
  19
  20#include <linux/threads.h>
  21#include <linux/cpumask.h>
  22#include <linux/kernel.h>
  23#include <linux/irqreturn.h>
  24
  25#ifndef __ASSEMBLY__
  26
  27#ifdef CONFIG_PPC64
  28#include <asm/paca.h>
  29#endif
  30#include <asm/percpu.h>
  31
  32extern int boot_cpuid;
  33extern int spinning_secondaries;
  34
  35extern void cpu_die(void);
  36
  37#ifdef CONFIG_SMP
  38
  39struct smp_ops_t {
  40        void  (*message_pass)(int cpu, int msg);
  41#ifdef CONFIG_PPC_SMP_MUXED_IPI
  42        void  (*cause_ipi)(int cpu, unsigned long data);
  43#endif
  44        int   (*probe)(void);
  45        int   (*kick_cpu)(int nr);
  46        void  (*setup_cpu)(int nr);
  47        void  (*bringup_done)(void);
  48        void  (*take_timebase)(void);
  49        void  (*give_timebase)(void);
  50        int   (*cpu_disable)(void);
  51        void  (*cpu_die)(unsigned int nr);
  52        int   (*cpu_bootable)(unsigned int nr);
  53};
  54
  55extern void smp_send_debugger_break(void);
  56extern void start_secondary_resume(void);
  57extern void smp_generic_give_timebase(void);
  58extern void smp_generic_take_timebase(void);
  59
  60DECLARE_PER_CPU(unsigned int, cpu_pvr);
  61
  62#ifdef CONFIG_HOTPLUG_CPU
  63extern void migrate_irqs(void);
  64int generic_cpu_disable(void);
  65void generic_cpu_die(unsigned int cpu);
  66void generic_mach_cpu_die(void);
  67void generic_set_cpu_dead(unsigned int cpu);
  68void generic_set_cpu_up(unsigned int cpu);
  69int generic_check_cpu_restart(unsigned int cpu);
  70
  71extern void inhibit_secondary_onlining(void);
  72extern void uninhibit_secondary_onlining(void);
  73
  74#else /* HOTPLUG_CPU */
  75static inline void inhibit_secondary_onlining(void) {}
  76static inline void uninhibit_secondary_onlining(void) {}
  77
  78#endif
  79
  80#ifdef CONFIG_PPC64
  81#define raw_smp_processor_id()  (local_paca->paca_index)
  82#define hard_smp_processor_id() (get_paca()->hw_cpu_id)
  83#else
  84/* 32-bit */
  85extern int smp_hw_index[];
  86
  87#define raw_smp_processor_id()  (current_thread_info()->cpu)
  88#define hard_smp_processor_id()         (smp_hw_index[smp_processor_id()])
  89
  90static inline int get_hard_smp_processor_id(int cpu)
  91{
  92        return smp_hw_index[cpu];
  93}
  94
  95static inline void set_hard_smp_processor_id(int cpu, int phys)
  96{
  97        smp_hw_index[cpu] = phys;
  98}
  99#endif
 100
 101DECLARE_PER_CPU(cpumask_var_t, cpu_sibling_map);
 102DECLARE_PER_CPU(cpumask_var_t, cpu_core_map);
 103
 104static inline struct cpumask *cpu_sibling_mask(int cpu)
 105{
 106        return per_cpu(cpu_sibling_map, cpu);
 107}
 108
 109static inline struct cpumask *cpu_core_mask(int cpu)
 110{
 111        return per_cpu(cpu_core_map, cpu);
 112}
 113
 114extern int cpu_to_core_id(int cpu);
 115extern int cpu_to_chip_id(int cpu);
 116
 117/* Since OpenPIC has only 4 IPIs, we use slightly different message numbers.
 118 *
 119 * Make sure this matches openpic_request_IPIs in open_pic.c, or what shows up
 120 * in /proc/interrupts will be wrong!!! --Troy */
 121#define PPC_MSG_CALL_FUNCTION   0
 122#define PPC_MSG_RESCHEDULE      1
 123#define PPC_MSG_CALL_FUNC_SINGLE        2
 124#define PPC_MSG_DEBUGGER_BREAK  3
 125
 126/* for irq controllers that have dedicated ipis per message (4) */
 127extern int smp_request_message_ipi(int virq, int message);
 128extern const char *smp_ipi_name[];
 129
 130/* for irq controllers with only a single ipi */
 131extern void smp_muxed_ipi_set_data(int cpu, unsigned long data);
 132extern void smp_muxed_ipi_message_pass(int cpu, int msg);
 133extern irqreturn_t smp_ipi_demux(void);
 134
 135void smp_init_pSeries(void);
 136void smp_init_cell(void);
 137void smp_init_celleb(void);
 138void smp_setup_cpu_maps(void);
 139
 140extern int __cpu_disable(void);
 141extern void __cpu_die(unsigned int cpu);
 142
 143#else
 144/* for UP */
 145#define hard_smp_processor_id()         get_hard_smp_processor_id(0)
 146#define smp_setup_cpu_maps()
 147static inline void inhibit_secondary_onlining(void) {}
 148static inline void uninhibit_secondary_onlining(void) {}
 149static inline const struct cpumask *cpu_sibling_mask(int cpu)
 150{
 151        return cpumask_of(cpu);
 152}
 153
 154#endif /* CONFIG_SMP */
 155
 156#ifdef CONFIG_PPC64
 157static inline int get_hard_smp_processor_id(int cpu)
 158{
 159        return paca[cpu].hw_cpu_id;
 160}
 161
 162static inline void set_hard_smp_processor_id(int cpu, int phys)
 163{
 164        paca[cpu].hw_cpu_id = phys;
 165}
 166
 167extern void smp_release_cpus(void);
 168
 169#else
 170/* 32-bit */
 171#ifndef CONFIG_SMP
 172extern int boot_cpuid_phys;
 173static inline int get_hard_smp_processor_id(int cpu)
 174{
 175        return boot_cpuid_phys;
 176}
 177
 178static inline void set_hard_smp_processor_id(int cpu, int phys)
 179{
 180        boot_cpuid_phys = phys;
 181}
 182#endif /* !CONFIG_SMP */
 183#endif /* !CONFIG_PPC64 */
 184
 185extern int smt_enabled_at_boot;
 186
 187extern int smp_mpic_probe(void);
 188extern void smp_mpic_setup_cpu(int cpu);
 189extern int smp_generic_kick_cpu(int nr);
 190extern int smp_generic_cpu_bootable(unsigned int nr);
 191
 192
 193extern void smp_generic_give_timebase(void);
 194extern void smp_generic_take_timebase(void);
 195
 196extern struct smp_ops_t *smp_ops;
 197
 198extern void arch_send_call_function_single_ipi(int cpu);
 199extern void arch_send_call_function_ipi_mask(const struct cpumask *mask);
 200
 201/* Definitions relative to the secondary CPU spin loop
 202 * and entry point. Not all of them exist on both 32 and
 203 * 64-bit but defining them all here doesn't harm
 204 */
 205extern void generic_secondary_smp_init(void);
 206extern void generic_secondary_thread_init(void);
 207extern unsigned long __secondary_hold_spinloop;
 208extern unsigned long __secondary_hold_acknowledge;
 209extern char __secondary_hold;
 210
 211extern void __early_start(void);
 212#endif /* __ASSEMBLY__ */
 213
 214#endif /* __KERNEL__ */
 215#endif /* _ASM_POWERPC_SMP_H) */
 216