LXR linux/arch/powerpc/kernel/head

   1/*
   2 *    Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
   3 *      Initial PowerPC version.
   4 *    Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
   5 *      Rewritten for PReP
   6 *    Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
   7 *      Low-level exception handers, MMU support, and rewrite.
   8 *    Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
   9 *      PowerPC 8xx modifications.
  10 *    Copyright (c) 1998-1999 TiVo, Inc.
  11 *      PowerPC 403GCX modifications.
  12 *    Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
  13 *      PowerPC 403GCX/405GP modifications.
  14 *    Copyright 2000 MontaVista Software Inc.
  15 *      PPC405 modifications
  16 *      PowerPC 403GCX/405GP modifications.
  17 *      Author: MontaVista Software, Inc.
  18 *              frank_rowand@mvista.com or source@mvista.com
  19 *              debbie_chu@mvista.com
  20 *
  21 *
  22 *    Module name: head_4xx.S
  23 *
  24 *    Description:
  25 *      Kernel execution entry point code.
  26 *
  27 *    This program is free software; you can redistribute it and/or
  28 *    modify it under the terms of the GNU General Public License
  29 *    as published by the Free Software Foundation; either version
  30 *    2 of the License, or (at your option) any later version.
  31 *
  32 */
  33
  34#include <linux/init.h>
  35#include <asm/processor.h>
  36#include <asm/page.h>
  37#include <asm/mmu.h>
  38#include <asm/pgtable.h>
  39#include <asm/cputable.h>
  40#include <asm/thread_info.h>
  41#include <asm/ppc_asm.h>
  42#include <asm/asm-offsets.h>
  43#include <asm/ptrace.h>
  44
  45/* As with the other PowerPC ports, it is expected that when code
  46 * execution begins here, the following registers contain valid, yet
  47 * optional, information:
  48 *
  49 *   r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
  50 *   r4 - Starting address of the init RAM disk
  51 *   r5 - Ending address of the init RAM disk
  52 *   r6 - Start of kernel command line string (e.g. "mem=96m")
  53 *   r7 - End of kernel command line string
  54 *
  55 * This is all going to change RSN when we add bi_recs.......  -- Dan
  56 */
  57        __HEAD
  58_ENTRY(_stext);
  59_ENTRY(_start);
  60
  61        mr      r31,r3                  /* save device tree ptr */
  62
  63        /* We have to turn on the MMU right away so we get cache modes
  64         * set correctly.
  65         */
  66        bl      initial_mmu
  67
  68/* We now have the lower 16 Meg mapped into TLB entries, and the caches
  69 * ready to work.
  70 */
  71turn_on_mmu:
  72        lis     r0,MSR_KERNEL@h
  73        ori     r0,r0,MSR_KERNEL@l
  74        mtspr   SPRN_SRR1,r0
  75        lis     r0,start_here@h
  76        ori     r0,r0,start_here@l
  77        mtspr   SPRN_SRR0,r0
  78        SYNC
  79        rfi                             /* enables MMU */
  80        b       .                       /* prevent prefetch past rfi */
  81
  82/*
  83 * This area is used for temporarily saving registers during the
  84 * critical exception prolog.
  85 */
  86        . = 0xc0
  87crit_save:
  88_ENTRY(crit_r10)
  89        .space  4
  90_ENTRY(crit_r11)
  91        .space  4
  92_ENTRY(crit_srr0)
  93        .space  4
  94_ENTRY(crit_srr1)
  95        .space  4
  96_ENTRY(saved_ksp_limit)
  97        .space  4
  98
  99/*
 100 * Exception vector entry code. This code runs with address translation
 101 * turned off (i.e. using physical addresses). We assume SPRG_THREAD has
 102 * the physical address of the current task thread_struct.
 103 * Note that we have to have decremented r1 before we write to any fields
 104 * of the exception frame, since a critical interrupt could occur at any
 105 * time, and it will write to the area immediately below the current r1.
 106 */
 107#define NORMAL_EXCEPTION_PROLOG                                              \
 108        mtspr   SPRN_SPRG_SCRATCH0,r10; /* save two registers to work with */\
 109        mtspr   SPRN_SPRG_SCRATCH1,r11;                                      \
 110        mtspr   SPRN_SPRG_SCRATCH2,r1;                                       \
 111        mfcr    r10;                    /* save CR in r10 for now          */\
 112        mfspr   r11,SPRN_SRR1;          /* check whether user or kernel    */\
 113        andi.   r11,r11,MSR_PR;                                              \
 114        beq     1f;                                                          \
 115        mfspr   r1,SPRN_SPRG_THREAD;    /* if from user, start at top of   */\
 116        lwz     r1,THREAD_INFO-THREAD(r1); /* this thread's kernel stack   */\
 117        addi    r1,r1,THREAD_SIZE;                                           \
 1181:      subi    r1,r1,INT_FRAME_SIZE;   /* Allocate an exception frame     */\
 119        tophys(r11,r1);                                                      \
 120        stw     r10,_CCR(r11);          /* save various registers          */\
 121        stw     r12,GPR12(r11);                                              \
 122        stw     r9,GPR9(r11);                                                \
 123        mfspr   r10,SPRN_SPRG_SCRATCH0;                                      \
 124        stw     r10,GPR10(r11);                                              \
 125        mfspr   r12,SPRN_SPRG_SCRATCH1;                                      \
 126        stw     r12,GPR11(r11);                                              \
 127        mflr    r10;                                                         \
 128        stw     r10,_LINK(r11);                                              \
 129        mfspr   r10,SPRN_SPRG_SCRATCH2;                                      \
 130        mfspr   r12,SPRN_SRR0;                                               \
 131        stw     r10,GPR1(r11);                                               \
 132        mfspr   r9,SPRN_SRR1;                                                \
 133        stw     r10,0(r11);                                                  \
 134        rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 135        stw     r0,GPR0(r11);                                                \
 136        SAVE_4GPRS(3, r11);                                                  \
 137        SAVE_2GPRS(7, r11)
 138
 139/*
 140 * Exception prolog for critical exceptions.  This is a little different
 141 * from the normal exception prolog above since a critical exception
 142 * can potentially occur at any point during normal exception processing.
 143 * Thus we cannot use the same SPRG registers as the normal prolog above.
 144 * Instead we use a couple of words of memory at low physical addresses.
 145 * This is OK since we don't support SMP on these processors.
 146 */
 147#define CRITICAL_EXCEPTION_PROLOG                                            \
 148        stw     r10,crit_r10@l(0);      /* save two registers to work with */\
 149        stw     r11,crit_r11@l(0);                                           \
 150        mfcr    r10;                    /* save CR in r10 for now          */\
 151        mfspr   r11,SPRN_SRR3;          /* check whether user or kernel    */\
 152        andi.   r11,r11,MSR_PR;                                              \
 153        lis     r11,critirq_ctx@ha;                                          \
 154        tophys(r11,r11);                                                     \
 155        lwz     r11,critirq_ctx@l(r11);                                      \
 156        beq     1f;                                                          \
 157        /* COMING FROM USER MODE */                                          \
 158        mfspr   r11,SPRN_SPRG_THREAD;   /* if from user, start at top of   */\
 159        lwz     r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
 1601:      addi    r11,r11,THREAD_SIZE-INT_FRAME_SIZE; /* Alloc an excpt frm  */\
 161        tophys(r11,r11);                                                     \
 162        stw     r10,_CCR(r11);          /* save various registers          */\
 163        stw     r12,GPR12(r11);                                              \
 164        stw     r9,GPR9(r11);                                                \
 165        mflr    r10;                                                         \
 166        stw     r10,_LINK(r11);                                              \
 167        mfspr   r12,SPRN_DEAR;          /* save DEAR and ESR in the frame  */\
 168        stw     r12,_DEAR(r11);         /* since they may have had stuff   */\
 169        mfspr   r9,SPRN_ESR;            /* in them at the point where the  */\
 170        stw     r9,_ESR(r11);           /* exception was taken             */\
 171        mfspr   r12,SPRN_SRR2;                                               \
 172        stw     r1,GPR1(r11);                                                \
 173        mfspr   r9,SPRN_SRR3;                                                \
 174        stw     r1,0(r11);                                                   \
 175        tovirt(r1,r11);                                                      \
 176        rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 177        stw     r0,GPR0(r11);                                                \
 178        SAVE_4GPRS(3, r11);                                                  \
 179        SAVE_2GPRS(7, r11)
 180
 181        /*
 182         * State at this point:
 183         * r9 saved in stack frame, now saved SRR3 & ~MSR_WE
 184         * r10 saved in crit_r10 and in stack frame, trashed
 185         * r11 saved in crit_r11 and in stack frame,
 186         *      now phys stack/exception frame pointer
 187         * r12 saved in stack frame, now saved SRR2
 188         * CR saved in stack frame, CR0.EQ = !SRR3.PR
 189         * LR, DEAR, ESR in stack frame
 190         * r1 saved in stack frame, now virt stack/excframe pointer
 191         * r0, r3-r8 saved in stack frame
 192         */
 193
 194/*
 195 * Exception vectors.
 196 */
 197#define START_EXCEPTION(n, label)                                            \
 198        . = n;                                                               \
 199label:
 200
 201#define EXCEPTION(n, label, hdlr, xfer)                         \
 202        START_EXCEPTION(n, label);                              \
 203        NORMAL_EXCEPTION_PROLOG;                                \
 204        addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 205        xfer(n, hdlr)
 206
 207#define CRITICAL_EXCEPTION(n, label, hdlr)                      \
 208        START_EXCEPTION(n, label);                              \
 209        CRITICAL_EXCEPTION_PROLOG;                              \
 210        addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 211        EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 212                          NOCOPY, crit_transfer_to_handler,     \
 213                          ret_from_crit_exc)
 214
 215#define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret)   \
 216        li      r10,trap;                                       \
 217        stw     r10,_TRAP(r11);                                 \
 218        lis     r10,msr@h;                                      \
 219        ori     r10,r10,msr@l;                                  \
 220        copyee(r10, r9);                                        \
 221        bl      tfer;                                           \
 222        .long   hdlr;                                           \
 223        .long   ret
 224
 225#define COPY_EE(d, s)           rlwimi d,s,0,16,16
 226#define NOCOPY(d, s)
 227
 228#define EXC_XFER_STD(n, hdlr)           \
 229        EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
 230                          ret_from_except_full)
 231
 232#define EXC_XFER_LITE(n, hdlr)          \
 233        EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
 234                          ret_from_except)
 235
 236#define EXC_XFER_EE(n, hdlr)            \
 237        EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
 238                          ret_from_except_full)
 239
 240#define EXC_XFER_EE_LITE(n, hdlr)       \
 241        EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
 242                          ret_from_except)
 243
 244
 245/*
 246 * 0x0100 - Critical Interrupt Exception
 247 */
 248        CRITICAL_EXCEPTION(0x0100, CriticalInterrupt, unknown_exception)
 249
 250/*
 251 * 0x0200 - Machine Check Exception
 252 */
 253        CRITICAL_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
 254
 255/*
 256 * 0x0300 - Data Storage Exception
 257 * This happens for just a few reasons.  U0 set (but we don't do that),
 258 * or zone protection fault (user violation, write to protected page).
 259 * If this is just an update of modified status, we do that quickly
 260 * and exit.  Otherwise, we call heavywight functions to do the work.
 261 */
 262        START_EXCEPTION(0x0300, DataStorage)
 263        mtspr   SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
 264        mtspr   SPRN_SPRG_SCRATCH1, r11
 265#ifdef CONFIG_403GCX
 266        stw     r12, 0(r0)
 267        stw     r9, 4(r0)
 268        mfcr    r11
 269        mfspr   r12, SPRN_PID
 270        stw     r11, 8(r0)
 271        stw     r12, 12(r0)
 272#else
 273        mtspr   SPRN_SPRG_SCRATCH3, r12
 274        mtspr   SPRN_SPRG_SCRATCH4, r9
 275        mfcr    r11
 276        mfspr   r12, SPRN_PID
 277        mtspr   SPRN_SPRG_SCRATCH6, r11
 278        mtspr   SPRN_SPRG_SCRATCH5, r12
 279#endif
 280
 281        /* First, check if it was a zone fault (which means a user
 282        * tried to access a kernel or read-protected page - always
 283        * a SEGV).  All other faults here must be stores, so no
 284        * need to check ESR_DST as well. */
 285        mfspr   r10, SPRN_ESR
 286        andis.  r10, r10, ESR_DIZ@h
 287        bne     2f
 288
 289        mfspr   r10, SPRN_DEAR          /* Get faulting address */
 290
 291        /* If we are faulting a kernel address, we have to use the
 292         * kernel page tables.
 293         */
 294        lis     r11, PAGE_OFFSET@h
 295        cmplw   r10, r11
 296        blt+    3f
 297        lis     r11, swapper_pg_dir@h
 298        ori     r11, r11, swapper_pg_dir@l
 299        li      r9, 0
 300        mtspr   SPRN_PID, r9            /* TLB will have 0 TID */
 301        b       4f
 302
 303        /* Get the PGD for the current thread.
 304         */
 3053:
 306        mfspr   r11,SPRN_SPRG_THREAD
 307        lwz     r11,PGDIR(r11)
 3084:
 309        tophys(r11, r11)
 310        rlwimi  r11, r10, 12, 20, 29    /* Create L1 (pgdir/pmd) address */
 311        lwz     r11, 0(r11)             /* Get L1 entry */
 312        rlwinm. r12, r11, 0, 0, 19      /* Extract L2 (pte) base address */
 313        beq     2f                      /* Bail if no table */
 314
 315        rlwimi  r12, r10, 22, 20, 29    /* Compute PTE address */
 316        lwz     r11, 0(r12)             /* Get Linux PTE */
 317
 318        andi.   r9, r11, _PAGE_RW       /* Is it writeable? */
 319        beq     2f                      /* Bail if not */
 320
 321        /* Update 'changed'.
 322        */
 323        ori     r11, r11, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE
 324        stw     r11, 0(r12)             /* Update Linux page table */
 325
 326        /* Most of the Linux PTE is ready to load into the TLB LO.
 327         * We set ZSEL, where only the LS-bit determines user access.
 328         * We set execute, because we don't have the granularity to
 329         * properly set this at the page level (Linux problem).
 330         * If shared is set, we cause a zero PID->TID load.
 331         * Many of these bits are software only.  Bits we don't set
 332         * here we (properly should) assume have the appropriate value.
 333         */
 334        li      r12, 0x0ce2
 335        andc    r11, r11, r12           /* Make sure 20, 21 are zero */
 336
 337        /* find the TLB index that caused the fault.  It has to be here.
 338        */
 339        tlbsx   r9, 0, r10
 340
 341        tlbwe   r11, r9, TLB_DATA               /* Load TLB LO */
 342
 343        /* Done...restore registers and get out of here.
 344        */
 345#ifdef CONFIG_403GCX
 346        lwz     r12, 12(r0)
 347        lwz     r11, 8(r0)
 348        mtspr   SPRN_PID, r12
 349        mtcr    r11
 350        lwz     r9, 4(r0)
 351        lwz     r12, 0(r0)
 352#else
 353        mfspr   r12, SPRN_SPRG_SCRATCH5
 354        mfspr   r11, SPRN_SPRG_SCRATCH6
 355        mtspr   SPRN_PID, r12
 356        mtcr    r11
 357        mfspr   r9, SPRN_SPRG_SCRATCH4
 358        mfspr   r12, SPRN_SPRG_SCRATCH3
 359#endif
 360        mfspr   r11, SPRN_SPRG_SCRATCH1
 361        mfspr   r10, SPRN_SPRG_SCRATCH0
 362        PPC405_ERR77_SYNC
 363        rfi                     /* Should sync shadow TLBs */
 364        b       .               /* prevent prefetch past rfi */
 365
 3662:
 367        /* The bailout.  Restore registers to pre-exception conditions
 368         * and call the heavyweights to help us out.
 369         */
 370#ifdef CONFIG_403GCX
 371        lwz     r12, 12(r0)
 372        lwz     r11, 8(r0)
 373        mtspr   SPRN_PID, r12
 374        mtcr    r11
 375        lwz     r9, 4(r0)
 376        lwz     r12, 0(r0)
 377#else
 378        mfspr   r12, SPRN_SPRG_SCRATCH5
 379        mfspr   r11, SPRN_SPRG_SCRATCH6
 380        mtspr   SPRN_PID, r12
 381        mtcr    r11
 382        mfspr   r9, SPRN_SPRG_SCRATCH4
 383        mfspr   r12, SPRN_SPRG_SCRATCH3
 384#endif
 385        mfspr   r11, SPRN_SPRG_SCRATCH1
 386        mfspr   r10, SPRN_SPRG_SCRATCH0
 387        b       DataAccess
 388
 389/*
 390 * 0x0400 - Instruction Storage Exception
 391 * This is caused by a fetch from non-execute or guarded pages.
 392 */
 393        START_EXCEPTION(0x0400, InstructionAccess)
 394        NORMAL_EXCEPTION_PROLOG
 395        mr      r4,r12                  /* Pass SRR0 as arg2 */
 396        li      r5,0                    /* Pass zero as arg3 */
 397        EXC_XFER_LITE(0x400, handle_page_fault)
 398
 399/* 0x0500 - External Interrupt Exception */
 400        EXCEPTION(0x0500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
 401
 402/* 0x0600 - Alignment Exception */
 403        START_EXCEPTION(0x0600, Alignment)
 404        NORMAL_EXCEPTION_PROLOG
 405        mfspr   r4,SPRN_DEAR            /* Grab the DEAR and save it */
 406        stw     r4,_DEAR(r11)
 407        addi    r3,r1,STACK_FRAME_OVERHEAD
 408        EXC_XFER_EE(0x600, alignment_exception)
 409
 410/* 0x0700 - Program Exception */
 411        START_EXCEPTION(0x0700, ProgramCheck)
 412        NORMAL_EXCEPTION_PROLOG
 413        mfspr   r4,SPRN_ESR             /* Grab the ESR and save it */
 414        stw     r4,_ESR(r11)
 415        addi    r3,r1,STACK_FRAME_OVERHEAD
 416        EXC_XFER_STD(0x700, program_check_exception)
 417
 418        EXCEPTION(0x0800, Trap_08, unknown_exception, EXC_XFER_EE)
 419        EXCEPTION(0x0900, Trap_09, unknown_exception, EXC_XFER_EE)
 420        EXCEPTION(0x0A00, Trap_0A, unknown_exception, EXC_XFER_EE)
 421        EXCEPTION(0x0B00, Trap_0B, unknown_exception, EXC_XFER_EE)
 422
 423/* 0x0C00 - System Call Exception */
 424        START_EXCEPTION(0x0C00, SystemCall)
 425        NORMAL_EXCEPTION_PROLOG
 426        EXC_XFER_EE_LITE(0xc00, DoSyscall)
 427
 428        EXCEPTION(0x0D00, Trap_0D, unknown_exception, EXC_XFER_EE)
 429        EXCEPTION(0x0E00, Trap_0E, unknown_exception, EXC_XFER_EE)
 430        EXCEPTION(0x0F00, Trap_0F, unknown_exception, EXC_XFER_EE)
 431
 432/* 0x1000 - Programmable Interval Timer (PIT) Exception */
 433        . = 0x1000
 434        b Decrementer
 435
 436/* 0x1010 - Fixed Interval Timer (FIT) Exception
 437*/
 438        . = 0x1010
 439        b FITException
 440
 441/* 0x1020 - Watchdog Timer (WDT) Exception
 442*/
 443        . = 0x1020
 444        b WDTException
 445
 446/* 0x1100 - Data TLB Miss Exception
 447 * As the name implies, translation is not in the MMU, so search the
 448 * page tables and fix it.  The only purpose of this function is to
 449 * load TLB entries from the page table if they exist.
 450 */
 451        START_EXCEPTION(0x1100, DTLBMiss)
 452        mtspr   SPRN_SPRG_SCRATCH0, r10 /* Save some working registers */
 453        mtspr   SPRN_SPRG_SCRATCH1, r11
 454#ifdef CONFIG_403GCX
 455        stw     r12, 0(r0)
 456        stw     r9, 4(r0)
 457        mfcr    r11
 458        mfspr   r12, SPRN_PID
 459        stw     r11, 8(r0)
 460        stw     r12, 12(r0)
 461#else
 462        mtspr   SPRN_SPRG_SCRATCH3, r12
 463        mtspr   SPRN_SPRG_SCRATCH4, r9
 464        mfcr    r11
 465        mfspr   r12, SPRN_PID
 466        mtspr   SPRN_SPRG_SCRATCH6, r11
 467        mtspr   SPRN_SPRG_SCRATCH5, r12
 468#endif
 469        mfspr   r10, SPRN_DEAR          /* Get faulting address */
 470
 471        /* If we are faulting a kernel address, we have to use the
 472         * kernel page tables.
 473         */
 474        lis     r11, PAGE_OFFSET@h
 475        cmplw   r10, r11
 476        blt+    3f
 477        lis     r11, swapper_pg_dir@h
 478        ori     r11, r11, swapper_pg_dir@l
 479        li      r9, 0
 480        mtspr   SPRN_PID, r9            /* TLB will have 0 TID */
 481        b       4f
 482
 483        /* Get the PGD for the current thread.
 484         */
 4853:
 486        mfspr   r11,SPRN_SPRG_THREAD
 487        lwz     r11,PGDIR(r11)
 4884:
 489        tophys(r11, r11)
 490        rlwimi  r11, r10, 12, 20, 29    /* Create L1 (pgdir/pmd) address */
 491        lwz     r12, 0(r11)             /* Get L1 entry */
 492        andi.   r9, r12, _PMD_PRESENT   /* Check if it points to a PTE page */
 493        beq     2f                      /* Bail if no table */
 494
 495        rlwimi  r12, r10, 22, 20, 29    /* Compute PTE address */
 496        lwz     r11, 0(r12)             /* Get Linux PTE */
 497        andi.   r9, r11, _PAGE_PRESENT
 498        beq     5f
 499
 500        ori     r11, r11, _PAGE_ACCESSED
 501        stw     r11, 0(r12)
 502
 503        /* Create TLB tag.  This is the faulting address plus a static
 504         * set of bits.  These are size, valid, E, U0.
 505        */
 506        li      r12, 0x00c0
 507        rlwimi  r10, r12, 0, 20, 31
 508
 509        b       finish_tlb_load
 510
 5112:      /* Check for possible large-page pmd entry */
 512        rlwinm. r9, r12, 2, 22, 24
 513        beq     5f
 514
 515        /* Create TLB tag.  This is the faulting address, plus a static
 516         * set of bits (valid, E, U0) plus the size from the PMD.
 517         */
 518        ori     r9, r9, 0x40
 519        rlwimi  r10, r9, 0, 20, 31
 520        mr      r11, r12
 521
 522        b       finish_tlb_load
 523
 5245:
 525        /* The bailout.  Restore registers to pre-exception conditions
 526         * and call the heavyweights to help us out.
 527         */
 528#ifdef CONFIG_403GCX
 529        lwz     r12, 12(r0)
 530        lwz     r11, 8(r0)
 531        mtspr   SPRN_PID, r12
 532        mtcr    r11
 533        lwz     r9, 4(r0)
 534        lwz     r12, 0(r0)
 535#else
 536        mfspr   r12, SPRN_SPRG_SCRATCH5
 537        mfspr   r11, SPRN_SPRG_SCRATCH6
 538        mtspr   SPRN_PID, r12
 539        mtcr    r11
 540        mfspr   r9, SPRN_SPRG_SCRATCH4
 541        mfspr   r12, SPRN_SPRG_SCRATCH3
 542#endif
 543        mfspr   r11, SPRN_SPRG_SCRATCH1
 544        mfspr   r10, SPRN_SPRG_SCRATCH0
 545        b       DataAccess
 546
 547/* 0x1200 - Instruction TLB Miss Exception
 548 * Nearly the same as above, except we get our information from different
 549 * registers and bailout to a different point.
 550 */
 551        START_EXCEPTION(0x1200, ITLBMiss)
 552        mtspr   SPRN_SPRG_SCRATCH0, r10  /* Save some working registers */
 553        mtspr   SPRN_SPRG_SCRATCH1, r11
 554#ifdef CONFIG_403GCX
 555        stw     r12, 0(r0)
 556        stw     r9, 4(r0)
 557        mfcr    r11
 558        mfspr   r12, SPRN_PID
 559        stw     r11, 8(r0)
 560        stw     r12, 12(r0)
 561#else
 562        mtspr   SPRN_SPRG_SCRATCH3, r12
 563        mtspr   SPRN_SPRG_SCRATCH4, r9
 564        mfcr    r11
 565        mfspr   r12, SPRN_PID
 566        mtspr   SPRN_SPRG_SCRATCH6, r11
 567        mtspr   SPRN_SPRG_SCRATCH5, r12
 568#endif
 569        mfspr   r10, SPRN_SRR0          /* Get faulting address */
 570
 571        /* If we are faulting a kernel address, we have to use the
 572         * kernel page tables.
 573         */
 574        lis     r11, PAGE_OFFSET@h
 575        cmplw   r10, r11
 576        blt+    3f
 577        lis     r11, swapper_pg_dir@h
 578        ori     r11, r11, swapper_pg_dir@l
 579        li      r9, 0
 580        mtspr   SPRN_PID, r9            /* TLB will have 0 TID */
 581        b       4f
 582
 583        /* Get the PGD for the current thread.
 584         */
 5853:
 586        mfspr   r11,SPRN_SPRG_THREAD
 587        lwz     r11,PGDIR(r11)
 5884:
 589        tophys(r11, r11)
 590        rlwimi  r11, r10, 12, 20, 29    /* Create L1 (pgdir/pmd) address */
 591        lwz     r12, 0(r11)             /* Get L1 entry */
 592        andi.   r9, r12, _PMD_PRESENT   /* Check if it points to a PTE page */
 593        beq     2f                      /* Bail if no table */
 594
 595        rlwimi  r12, r10, 22, 20, 29    /* Compute PTE address */
 596        lwz     r11, 0(r12)             /* Get Linux PTE */
 597        andi.   r9, r11, _PAGE_PRESENT
 598        beq     5f
 599
 600        ori     r11, r11, _PAGE_ACCESSED
 601        stw     r11, 0(r12)
 602
 603        /* Create TLB tag.  This is the faulting address plus a static
 604         * set of bits.  These are size, valid, E, U0.
 605        */
 606        li      r12, 0x00c0
 607        rlwimi  r10, r12, 0, 20, 31
 608
 609        b       finish_tlb_load
 610
 6112:      /* Check for possible large-page pmd entry */
 612        rlwinm. r9, r12, 2, 22, 24
 613        beq     5f
 614
 615        /* Create TLB tag.  This is the faulting address, plus a static
 616         * set of bits (valid, E, U0) plus the size from the PMD.
 617         */
 618        ori     r9, r9, 0x40
 619        rlwimi  r10, r9, 0, 20, 31
 620        mr      r11, r12
 621
 622        b       finish_tlb_load
 623
 6245:
 625        /* The bailout.  Restore registers to pre-exception conditions
 626         * and call the heavyweights to help us out.
 627         */
 628#ifdef CONFIG_403GCX
 629        lwz     r12, 12(r0)
 630        lwz     r11, 8(r0)
 631        mtspr   SPRN_PID, r12
 632        mtcr    r11
 633        lwz     r9, 4(r0)
 634        lwz     r12, 0(r0)
 635#else
 636        mfspr   r12, SPRN_SPRG_SCRATCH5
 637        mfspr   r11, SPRN_SPRG_SCRATCH6
 638        mtspr   SPRN_PID, r12
 639        mtcr    r11
 640        mfspr   r9, SPRN_SPRG_SCRATCH4
 641        mfspr   r12, SPRN_SPRG_SCRATCH3
 642#endif
 643        mfspr   r11, SPRN_SPRG_SCRATCH1
 644        mfspr   r10, SPRN_SPRG_SCRATCH0
 645        b       InstructionAccess
 646
 647        EXCEPTION(0x1300, Trap_13, unknown_exception, EXC_XFER_EE)
 648        EXCEPTION(0x1400, Trap_14, unknown_exception, EXC_XFER_EE)
 649        EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
 650        EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
 651#ifdef CONFIG_IBM405_ERR51
 652        /* 405GP errata 51 */
 653        START_EXCEPTION(0x1700, Trap_17)
 654        b DTLBMiss
 655#else
 656        EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
 657#endif
 658        EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
 659        EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
 660        EXCEPTION(0x1A00, Trap_1A, unknown_exception, EXC_XFER_EE)
 661        EXCEPTION(0x1B00, Trap_1B, unknown_exception, EXC_XFER_EE)
 662        EXCEPTION(0x1C00, Trap_1C, unknown_exception, EXC_XFER_EE)
 663        EXCEPTION(0x1D00, Trap_1D, unknown_exception, EXC_XFER_EE)
 664        EXCEPTION(0x1E00, Trap_1E, unknown_exception, EXC_XFER_EE)
 665        EXCEPTION(0x1F00, Trap_1F, unknown_exception, EXC_XFER_EE)
 666
 667/* Check for a single step debug exception while in an exception
 668 * handler before state has been saved.  This is to catch the case
 669 * where an instruction that we are trying to single step causes
 670 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
 671 * the exception handler generates a single step debug exception.
 672 *
 673 * If we get a debug trap on the first instruction of an exception handler,
 674 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
 675 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
 676 * The exception handler was handling a non-critical interrupt, so it will
 677 * save (and later restore) the MSR via SPRN_SRR1, which will still have
 678 * the MSR_DE bit set.
 679 */
 680        /* 0x2000 - Debug Exception */
 681        START_EXCEPTION(0x2000, DebugTrap)
 682        CRITICAL_EXCEPTION_PROLOG
 683
 684        /*
 685         * If this is a single step or branch-taken exception in an
 686         * exception entry sequence, it was probably meant to apply to
 687         * the code where the exception occurred (since exception entry
 688         * doesn't turn off DE automatically).  We simulate the effect
 689         * of turning off DE on entry to an exception handler by turning
 690         * off DE in the SRR3 value and clearing the debug status.
 691         */
 692        mfspr   r10,SPRN_DBSR           /* check single-step/branch taken */
 693        andis.  r10,r10,DBSR_IC@h
 694        beq+    2f
 695
 696        andi.   r10,r9,MSR_IR|MSR_PR    /* check supervisor + MMU off */
 697        beq     1f                      /* branch and fix it up */
 698
 699        mfspr   r10,SPRN_SRR2           /* Faulting instruction address */
 700        cmplwi  r10,0x2100
 701        bgt+    2f                      /* address above exception vectors */
 702
 703        /* here it looks like we got an inappropriate debug exception. */
 7041:      rlwinm  r9,r9,0,~MSR_DE         /* clear DE in the SRR3 value */
 705        lis     r10,DBSR_IC@h           /* clear the IC event */
 706        mtspr   SPRN_DBSR,r10
 707        /* restore state and get out */
 708        lwz     r10,_CCR(r11)
 709        lwz     r0,GPR0(r11)
 710        lwz     r1,GPR1(r11)
 711        mtcrf   0x80,r10
 712        mtspr   SPRN_SRR2,r12
 713        mtspr   SPRN_SRR3,r9
 714        lwz     r9,GPR9(r11)
 715        lwz     r12,GPR12(r11)
 716        lwz     r10,crit_r10@l(0)
 717        lwz     r11,crit_r11@l(0)
 718        PPC405_ERR77_SYNC
 719        rfci
 720        b       .
 721
 722        /* continue normal handling for a critical exception... */
 7232:      mfspr   r4,SPRN_DBSR
 724        addi    r3,r1,STACK_FRAME_OVERHEAD
 725        EXC_XFER_TEMPLATE(DebugException, 0x2002, \
 726                (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 727                NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
 728
 729        /* Programmable Interval Timer (PIT) Exception. (from 0x1000) */
 730Decrementer:
 731        NORMAL_EXCEPTION_PROLOG
 732        lis     r0,TSR_PIS@h
 733        mtspr   SPRN_TSR,r0             /* Clear the PIT exception */
 734        addi    r3,r1,STACK_FRAME_OVERHEAD
 735        EXC_XFER_LITE(0x1000, timer_interrupt)
 736
 737        /* Fixed Interval Timer (FIT) Exception. (from 0x1010) */
 738FITException:
 739        NORMAL_EXCEPTION_PROLOG
 740        addi    r3,r1,STACK_FRAME_OVERHEAD;
 741        EXC_XFER_EE(0x1010, unknown_exception)
 742
 743        /* Watchdog Timer (WDT) Exception. (from 0x1020) */
 744WDTException:
 745        CRITICAL_EXCEPTION_PROLOG;
 746        addi    r3,r1,STACK_FRAME_OVERHEAD;
 747        EXC_XFER_TEMPLATE(WatchdogException, 0x1020+2,
 748                          (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)),
 749                          NOCOPY, crit_transfer_to_handler,
 750                          ret_from_crit_exc)
 751
 752/*
 753 * The other Data TLB exceptions bail out to this point
 754 * if they can't resolve the lightweight TLB fault.
 755 */
 756DataAccess:
 757        NORMAL_EXCEPTION_PROLOG
 758        mfspr   r5,SPRN_ESR             /* Grab the ESR, save it, pass arg3 */
 759        stw     r5,_ESR(r11)
 760        mfspr   r4,SPRN_DEAR            /* Grab the DEAR, save it, pass arg2 */
 761        EXC_XFER_LITE(0x300, handle_page_fault)
 762
 763/* Other PowerPC processors, namely those derived from the 6xx-series
 764 * have vectors from 0x2100 through 0x2F00 defined, but marked as reserved.
 765 * However, for the 4xx-series processors these are neither defined nor
 766 * reserved.
 767 */
 768
 769        /* Damn, I came up one instruction too many to fit into the
 770         * exception space :-).  Both the instruction and data TLB
 771         * miss get to this point to load the TLB.
 772         *      r10 - TLB_TAG value
 773         *      r11 - Linux PTE
 774         *      r12, r9 - available to use
 775         *      PID - loaded with proper value when we get here
 776         *      Upon exit, we reload everything and RFI.
 777         * Actually, it will fit now, but oh well.....a common place
 778         * to load the TLB.
 779         */
 780tlb_4xx_index:
 781        .long   0
 782finish_tlb_load:
 783        /* load the next available TLB index.
 784        */
 785        lwz     r9, tlb_4xx_index@l(0)
 786        addi    r9, r9, 1
 787        andi.   r9, r9, (PPC40X_TLB_SIZE-1)
 788        stw     r9, tlb_4xx_index@l(0)
 789
 7906:
 791        /*
 792         * Clear out the software-only bits in the PTE to generate the
 793         * TLB_DATA value.  These are the bottom 2 bits of the RPM, the
 794         * top 3 bits of the zone field, and M.
 795         */
 796        li      r12, 0x0ce2
 797        andc    r11, r11, r12
 798
 799        tlbwe   r11, r9, TLB_DATA               /* Load TLB LO */
 800        tlbwe   r10, r9, TLB_TAG                /* Load TLB HI */
 801
 802        /* Done...restore registers and get out of here.
 803        */
 804#ifdef CONFIG_403GCX
 805        lwz     r12, 12(r0)
 806        lwz     r11, 8(r0)
 807        mtspr   SPRN_PID, r12
 808        mtcr    r11
 809        lwz     r9, 4(r0)
 810        lwz     r12, 0(r0)
 811#else
 812        mfspr   r12, SPRN_SPRG_SCRATCH5
 813        mfspr   r11, SPRN_SPRG_SCRATCH6
 814        mtspr   SPRN_PID, r12
 815        mtcr    r11
 816        mfspr   r9, SPRN_SPRG_SCRATCH4
 817        mfspr   r12, SPRN_SPRG_SCRATCH3
 818#endif
 819        mfspr   r11, SPRN_SPRG_SCRATCH1
 820        mfspr   r10, SPRN_SPRG_SCRATCH0
 821        PPC405_ERR77_SYNC
 822        rfi                     /* Should sync shadow TLBs */
 823        b       .               /* prevent prefetch past rfi */
 824
 825/* This is where the main kernel code starts.
 826 */
 827start_here:
 828
 829        /* ptr to current */
 830        lis     r2,init_task@h
 831        ori     r2,r2,init_task@l
 832
 833        /* ptr to phys current thread */
 834        tophys(r4,r2)
 835        addi    r4,r4,THREAD    /* init task's THREAD */
 836        mtspr   SPRN_SPRG_THREAD,r4
 837
 838        /* stack */
 839        lis     r1,init_thread_union@ha
 840        addi    r1,r1,init_thread_union@l
 841        li      r0,0
 842        stwu    r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
 843
 844        bl      early_init      /* We have to do this with MMU on */
 845
 846/*
 847 * Decide what sort of machine this is and initialize the MMU.
 848 */
 849        li      r3,0
 850        mr      r4,r31
 851        bl      machine_init
 852        bl      MMU_init
 853
 854/* Go back to running unmapped so we can load up new values
 855 * and change to using our exception vectors.
 856 * On the 4xx, all we have to do is invalidate the TLB to clear
 857 * the old 16M byte TLB mappings.
 858 */
 859        lis     r4,2f@h
 860        ori     r4,r4,2f@l
 861        tophys(r4,r4)
 862        lis     r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@h
 863        ori     r3,r3,(MSR_KERNEL & ~(MSR_IR|MSR_DR))@l
 864        mtspr   SPRN_SRR0,r4
 865        mtspr   SPRN_SRR1,r3
 866        rfi
 867        b       .               /* prevent prefetch past rfi */
 868
 869/* Load up the kernel context */
 8702:
 871        sync                    /* Flush to memory before changing TLB */
 872        tlbia
 873        isync                   /* Flush shadow TLBs */
 874
 875        /* set up the PTE pointers for the Abatron bdiGDB.
 876        */
 877        lis     r6, swapper_pg_dir@h
 878        ori     r6, r6, swapper_pg_dir@l
 879        lis     r5, abatron_pteptrs@h
 880        ori     r5, r5, abatron_pteptrs@l
 881        stw     r5, 0xf0(r0)    /* Must match your Abatron config file */
 882        tophys(r5,r5)
 883        stw     r6, 0(r5)
 884
 885/* Now turn on the MMU for real! */
 886        lis     r4,MSR_KERNEL@h
 887        ori     r4,r4,MSR_KERNEL@l
 888        lis     r3,start_kernel@h
 889        ori     r3,r3,start_kernel@l
 890        mtspr   SPRN_SRR0,r3
 891        mtspr   SPRN_SRR1,r4
 892        rfi                     /* enable MMU and jump to start_kernel */
 893        b       .               /* prevent prefetch past rfi */
 894
 895/* Set up the initial MMU state so we can do the first level of
 896 * kernel initialization.  This maps the first 16 MBytes of memory 1:1
 897 * virtual to physical and more importantly sets the cache mode.
 898 */
 899initial_mmu:
 900        tlbia                   /* Invalidate all TLB entries */
 901        isync
 902
 903        /* We should still be executing code at physical address 0x0000xxxx
 904         * at this point. However, start_here is at virtual address
 905         * 0xC000xxxx. So, set up a TLB mapping to cover this once
 906         * translation is enabled.
 907         */
 908
 909        lis     r3,KERNELBASE@h         /* Load the kernel virtual address */
 910        ori     r3,r3,KERNELBASE@l
 911        tophys(r4,r3)                   /* Load the kernel physical address */
 912
 913        iccci   r0,r3                   /* Invalidate the i-cache before use */
 914
 915        /* Load the kernel PID.
 916        */
 917        li      r0,0
 918        mtspr   SPRN_PID,r0
 919        sync
 920
 921        /* Configure and load one entry into TLB slots 63 */
 922        clrrwi  r4,r4,10                /* Mask off the real page number */
 923        ori     r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
 924
 925        clrrwi  r3,r3,10                /* Mask off the effective page number */
 926        ori     r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_16M))
 927
 928        li      r0,63                    /* TLB slot 63 */
 929
 930        tlbwe   r4,r0,TLB_DATA          /* Load the data portion of the entry */
 931        tlbwe   r3,r0,TLB_TAG           /* Load the tag portion of the entry */
 932
 933#if defined(CONFIG_SERIAL_TEXT_DEBUG) && defined(SERIAL_DEBUG_IO_BASE)
 934
 935        /* Load a TLB entry for the UART, so that ppc4xx_progress() can use
 936         * the UARTs nice and early.  We use a 4k real==virtual mapping. */
 937
 938        lis     r3,SERIAL_DEBUG_IO_BASE@h
 939        ori     r3,r3,SERIAL_DEBUG_IO_BASE@l
 940        mr      r4,r3
 941        clrrwi  r4,r4,12
 942        ori     r4,r4,(TLB_WR|TLB_I|TLB_M|TLB_G)
 943
 944        clrrwi  r3,r3,12
 945        ori     r3,r3,(TLB_VALID | TLB_PAGESZ(PAGESZ_4K))
 946
 947        li      r0,0                    /* TLB slot 0 */
 948        tlbwe   r4,r0,TLB_DATA
 949        tlbwe   r3,r0,TLB_TAG
 950#endif /* CONFIG_SERIAL_DEBUG_TEXT && SERIAL_DEBUG_IO_BASE */
 951
 952        isync
 953
 954        /* Establish the exception vector base
 955        */
 956        lis     r4,KERNELBASE@h         /* EVPR only uses the high 16-bits */
 957        tophys(r0,r4)                   /* Use the physical address */
 958        mtspr   SPRN_EVPR,r0
 959
 960        blr
 961
 962_GLOBAL(abort)
 963        mfspr   r13,SPRN_DBCR0
 964        oris    r13,r13,DBCR0_RST_SYSTEM@h
 965        mtspr   SPRN_DBCR0,r13
 966
 967_GLOBAL(set_context)
 968
 969#ifdef CONFIG_BDI_SWITCH
 970        /* Context switch the PTE pointer for the Abatron BDI2000.
 971         * The PGDIR is the second parameter.
 972         */
 973        lis     r5, KERNELBASE@h
 974        lwz     r5, 0xf0(r5)
 975        stw     r4, 0x4(r5)
 976#endif
 977        sync
 978        mtspr   SPRN_PID,r3
 979        isync                           /* Need an isync to flush shadow */
 980                                        /* TLBs after changing PID */
 981        blr
 982
 983/* We put a few things here that have to be page-aligned. This stuff
 984 * goes at the beginning of the data segment, which is page-aligned.
 985 */
 986        .data
 987        .align  12
 988        .globl  sdata
 989sdata:
 990        .globl  empty_zero_page
 991empty_zero_page:
 992        .space  4096
 993        .globl  swapper_pg_dir
 994swapper_pg_dir:
 995        .space  PGD_TABLE_SIZE
 996
 997/* Room for two PTE pointers, usually the kernel and current user pointers
 998 * to their respective root page table.
 999 */
1000abatron_pteptrs:

1001        .space  8
1002