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30
31#include <linux/init.h>
32#include <asm/processor.h>
33#include <asm/page.h>
34#include <asm/mmu.h>
35#include <asm/pgtable.h>
36#include <asm/cputable.h>
37#include <asm/thread_info.h>
38#include <asm/ppc_asm.h>
39#include <asm/asm-offsets.h>
40#include <asm/ptrace.h>
41#include <asm/synch.h>
42#include "head_booke.h"
43
44
45
46
47
48
49
50
51
52
53
54
55
56 __HEAD
57_ENTRY(_stext);
58_ENTRY(_start);
59
60
61
62
63 nop
64 mr r31,r3
65 li r24,0
66
67#ifdef CONFIG_RELOCATABLE
68
69
70
71
72
73
74
75 bl 0f
760: mflr r21
77 addis r21,r21,(_stext - 0b)@ha
78 addi r21,r21,(_stext - 0b)@l
79
80
81
82
83
84
85
86 lis r4,KERNELBASE@h
87 ori r4,r4,KERNELBASE@l
88 rlwinm r6,r21,0,4,31
89 rlwinm r5,r4,0,4,31
90 subf r3,r5,r6
91 add r3,r4,r3
92
93 bl relocate
94#endif
95
96 bl init_cpu_state
97
98
99
100
101
102
103 lis r2,init_task@h
104 ori r2,r2,init_task@l
105
106
107 addi r4,r2,THREAD
108 mtspr SPRN_SPRG_THREAD,r4
109
110
111 lis r1,init_thread_union@h
112 ori r1,r1,init_thread_union@l
113 li r0,0
114 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
115
116 bl early_init
117
118#ifdef CONFIG_RELOCATABLE
119
120
121
122
123
124
125
126 lis r3,kernstart_addr@ha
127 la r3,kernstart_addr@l(r3)
128
129
130
131
132
133
134 rlwinm r6,r25,0,28,31
135 rlwinm r7,r25,0,0,3
136 rlwinm r8,r21,0,4,31
137 or r8,r7,r8
138
139
140 stw r6,0(r3)
141 stw r8,4(r3)
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158 li r4, 0
159 lis r5,KERNELBASE@h
160 rlwinm r5,r5,0,0,3
161
162
163
164
165 subfc r5,r7,r5
166 subfe r4,r6,r4
167
168
169 lis r3,virt_phys_offset@ha
170 la r3,virt_phys_offset@l(r3)
171
172 stw r4,0(r3)
173 stw r5,4(r3)
174
175
176
177
178
179
180
181
182
183
184 lis r3,kernstart_addr@ha
185 la r3,kernstart_addr@l(r3)
186
187 lis r4,KERNELBASE@h
188 ori r4,r4,KERNELBASE@l
189 lis r5,PAGE_OFFSET@h
190 ori r5,r5,PAGE_OFFSET@l
191 subf r4,r5,r4
192
193 rlwinm r6,r25,0,28,31
194 rlwinm r7,r25,0,0,3
195 add r7,r7,r4
196
197 stw r6,0(r3)
198 stw r7,4(r3)
199#endif
200
201
202
203
204 li r3,0
205 mr r4,r31
206 bl machine_init
207 bl MMU_init
208
209
210 lis r6, swapper_pg_dir@h
211 ori r6, r6, swapper_pg_dir@l
212 lis r5, abatron_pteptrs@h
213 ori r5, r5, abatron_pteptrs@l
214 lis r4, KERNELBASE@h
215 ori r4, r4, KERNELBASE@l
216 stw r5, 0(r4)
217 stw r6, 0(r5)
218
219
220 li r0,0
221 mtspr SPRN_MCSR,r0
222
223
224 lis r4,start_kernel@h
225 ori r4,r4,start_kernel@l
226 lis r3,MSR_KERNEL@h
227 ori r3,r3,MSR_KERNEL@l
228 mtspr SPRN_SRR0,r4
229 mtspr SPRN_SRR1,r3
230 rfi
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249interrupt_base:
250
251 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
252
253
254 CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
255 machine_check_exception)
256 MCHECK_EXCEPTION(0x0210, MachineCheckA, machine_check_exception)
257
258
259 DATA_STORAGE_EXCEPTION
260
261
262 INSTRUCTION_STORAGE_EXCEPTION
263
264
265 EXCEPTION(0x0500, BOOKE_INTERRUPT_EXTERNAL, ExternalInput, \
266 do_IRQ, EXC_XFER_LITE)
267
268
269 ALIGNMENT_EXCEPTION
270
271
272 PROGRAM_EXCEPTION
273
274
275#ifdef CONFIG_PPC_FPU
276 FP_UNAVAILABLE_EXCEPTION
277#else
278 EXCEPTION(0x2010, BOOKE_INTERRUPT_FP_UNAVAIL, \
279 FloatingPointUnavailable, unknown_exception, EXC_XFER_EE)
280#endif
281
282 START_EXCEPTION(SystemCall)
283 NORMAL_EXCEPTION_PROLOG(BOOKE_INTERRUPT_SYSCALL)
284 EXC_XFER_EE_LITE(0x0c00, DoSyscall)
285
286
287 EXCEPTION(0x2020, BOOKE_INTERRUPT_AP_UNAVAIL, \
288 AuxillaryProcessorUnavailable, unknown_exception, EXC_XFER_EE)
289
290
291 DECREMENTER_EXCEPTION
292
293
294
295 EXCEPTION(0x1010, BOOKE_INTERRUPT_FIT, FixedIntervalTimer, \
296 unknown_exception, EXC_XFER_EE)
297
298
299
300#ifdef CONFIG_BOOKE_WDT
301 CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, WatchdogException)
302#else
303 CRITICAL_EXCEPTION(0x1020, WATCHDOG, WatchdogTimer, unknown_exception)
304#endif
305
306
307 START_EXCEPTION(DataTLBError44x)
308 mtspr SPRN_SPRG_WSCRATCH0, r10
309 mtspr SPRN_SPRG_WSCRATCH1, r11
310 mtspr SPRN_SPRG_WSCRATCH2, r12
311 mtspr SPRN_SPRG_WSCRATCH3, r13
312 mfcr r11
313 mtspr SPRN_SPRG_WSCRATCH4, r11
314 mfspr r10, SPRN_DEAR
315
316
317
318
319 lis r11, PAGE_OFFSET@h
320 cmplw r10, r11
321 blt+ 3f
322 lis r11, swapper_pg_dir@h
323 ori r11, r11, swapper_pg_dir@l
324
325 mfspr r12,SPRN_MMUCR
326 rlwinm r12,r12,0,0,23
327
328 b 4f
329
330
3313:
332 mfspr r11,SPRN_SPRG_THREAD
333 lwz r11,PGDIR(r11)
334
335
336 mfspr r12,SPRN_MMUCR
337 mfspr r13,SPRN_PID
338 rlwimi r12,r13,0,24,31
339
3404:
341 mtspr SPRN_MMUCR,r12
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356 mfspr r12,SPRN_ESR
357 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
358 rlwimi r13,r12,10,30,30
359
360
361
362 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
363 lwzx r11, r12, r11
364 rlwinm. r12, r11, 0, 0, 20
365 beq 2f
366
367
368 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
369 lwz r11, 0(r12)
370 lwz r12, 4(r12)
371
372 lis r10,tlb_44x_index@ha
373
374 andc. r13,r13,r12
375
376
377 lwz r13,tlb_44x_index@l(r10)
378
379 bne 2f
380
381
382 addi r13,r13,1
383
384
385 .globl tlb_44x_patch_hwater_D
386tlb_44x_patch_hwater_D:
387 cmpwi 0,r13,1
388 ble 5f
389 li r13,0
3905:
391
392 stw r13,tlb_44x_index@l(r10)
393
394
395 mfspr r10,SPRN_DEAR
396
397
398 b finish_tlb_load_44x
399
4002:
401
402
403
404 mfspr r11, SPRN_SPRG_RSCRATCH4
405 mtcr r11
406 mfspr r13, SPRN_SPRG_RSCRATCH3
407 mfspr r12, SPRN_SPRG_RSCRATCH2
408 mfspr r11, SPRN_SPRG_RSCRATCH1
409 mfspr r10, SPRN_SPRG_RSCRATCH0
410 b DataStorage
411
412
413
414
415
416
417
418 START_EXCEPTION(InstructionTLBError44x)
419 mtspr SPRN_SPRG_WSCRATCH0, r10
420 mtspr SPRN_SPRG_WSCRATCH1, r11
421 mtspr SPRN_SPRG_WSCRATCH2, r12
422 mtspr SPRN_SPRG_WSCRATCH3, r13
423 mfcr r11
424 mtspr SPRN_SPRG_WSCRATCH4, r11
425 mfspr r10, SPRN_SRR0
426
427
428
429
430 lis r11, PAGE_OFFSET@h
431 cmplw r10, r11
432 blt+ 3f
433 lis r11, swapper_pg_dir@h
434 ori r11, r11, swapper_pg_dir@l
435
436 mfspr r12,SPRN_MMUCR
437 rlwinm r12,r12,0,0,23
438
439 b 4f
440
441
4423:
443 mfspr r11,SPRN_SPRG_THREAD
444 lwz r11,PGDIR(r11)
445
446
447 mfspr r12,SPRN_MMUCR
448 mfspr r13,SPRN_PID
449 rlwimi r12,r13,0,24,31
450
4514:
452 mtspr SPRN_MMUCR,r12
453
454
455 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
456
457
458 rlwinm r12, r10, PPC44x_PGD_OFF_SHIFT, PPC44x_PGD_OFF_MASK_BIT, 29
459 lwzx r11, r12, r11
460 rlwinm. r12, r11, 0, 0, 20
461 beq 2f
462
463
464 rlwimi r12, r10, PPC44x_PTE_ADD_SHIFT, PPC44x_PTE_ADD_MASK_BIT, 28
465 lwz r11, 0(r12)
466 lwz r12, 4(r12)
467
468 lis r10,tlb_44x_index@ha
469
470 andc. r13,r13,r12
471
472
473 lwz r13,tlb_44x_index@l(r10)
474
475 bne 2f
476
477
478 addi r13,r13,1
479
480
481 .globl tlb_44x_patch_hwater_I
482tlb_44x_patch_hwater_I:
483 cmpwi 0,r13,1
484 ble 5f
485 li r13,0
4865:
487
488 stw r13,tlb_44x_index@l(r10)
489
490
491 mfspr r10,SPRN_SRR0
492
493
494 b finish_tlb_load_44x
495
4962:
497
498
499
500 mfspr r11, SPRN_SPRG_RSCRATCH4
501 mtcr r11
502 mfspr r13, SPRN_SPRG_RSCRATCH3
503 mfspr r12, SPRN_SPRG_RSCRATCH2
504 mfspr r11, SPRN_SPRG_RSCRATCH1
505 mfspr r10, SPRN_SPRG_RSCRATCH0
506 b InstructionStorage
507
508
509
510
511
512
513
514
515
516
517
518finish_tlb_load_44x:
519
520 rlwimi r11,r12,0,0,31-PAGE_SHIFT
521 tlbwe r11,r13,PPC44x_TLB_XLAT
522
523
524
525
526
527 li r11,PPC44x_TLB_VALID | PPC44x_TLBE_SIZE
528
529 rlwimi r10,r11,0,PPC44x_PTE_ADD_MASK_BIT,31
530 tlbwe r10,r13,PPC44x_TLB_PAGEID
531
532
533 li r10,0xf85
534 rlwimi r10,r12,29,30,30
535 and r11,r12,r10
536 andi. r10,r12,_PAGE_USER
537 beq 1f
538 rlwimi r11,r11,3,26,28
5391: tlbwe r11,r13,PPC44x_TLB_ATTRIB
540
541
542
543 mfspr r11, SPRN_SPRG_RSCRATCH4
544 mtcr r11
545 mfspr r13, SPRN_SPRG_RSCRATCH3
546 mfspr r12, SPRN_SPRG_RSCRATCH2
547 mfspr r11, SPRN_SPRG_RSCRATCH1
548 mfspr r10, SPRN_SPRG_RSCRATCH0
549 rfi
550
551
552
553#ifdef CONFIG_PPC_47x
554 START_EXCEPTION(DataTLBError47x)
555 mtspr SPRN_SPRG_WSCRATCH0,r10
556 mtspr SPRN_SPRG_WSCRATCH1,r11
557 mtspr SPRN_SPRG_WSCRATCH2,r12
558 mtspr SPRN_SPRG_WSCRATCH3,r13
559 mfcr r11
560 mtspr SPRN_SPRG_WSCRATCH4,r11
561 mfspr r10,SPRN_DEAR
562
563
564
565
566 lis r11,PAGE_OFFSET@h
567 cmplw cr0,r10,r11
568 blt+ 3f
569 lis r11,swapper_pg_dir@h
570 ori r11,r11, swapper_pg_dir@l
571 li r12,0
572 b 4f
573
574
5753: mfspr r11,SPRN_SPRG3
576 lwz r11,PGDIR(r11)
577 mfspr r12,SPRN_PID
5784: mtspr SPRN_MMUCR,r12
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593 mfspr r12,SPRN_ESR
594 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
595 rlwimi r13,r12,10,30,30
596
597
598
599 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
600 lwzx r11,r12,r11
601
602
603 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
604 rlwimi r10,r12,0,32-PAGE_SHIFT,31
605 li r12,0
606 tlbwe r10,r12,0
607
608
609
610#ifdef CONFIG_SMP
611 isync
612#endif
613
614 rlwinm. r12,r11,0,0,20
615
616 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
617 beq 2f
618 lwz r11,0(r12)
619
620
621
622
623
624#ifdef CONFIG_SMP
625 lwsync
626#endif
627 lwz r12,4(r12)
628
629 andc. r13,r13,r12
630
631
632 beq finish_tlb_load_47x
633
6342:
635
636
637 mfspr r11,SPRN_SPRG_RSCRATCH4
638 mtcr r11
639 mfspr r13,SPRN_SPRG_RSCRATCH3
640 mfspr r12,SPRN_SPRG_RSCRATCH2
641 mfspr r11,SPRN_SPRG_RSCRATCH1
642 mfspr r10,SPRN_SPRG_RSCRATCH0
643 b DataStorage
644
645
646
647
648
649
650
651 START_EXCEPTION(InstructionTLBError47x)
652 mtspr SPRN_SPRG_WSCRATCH0,r10
653 mtspr SPRN_SPRG_WSCRATCH1,r11
654 mtspr SPRN_SPRG_WSCRATCH2,r12
655 mtspr SPRN_SPRG_WSCRATCH3,r13
656 mfcr r11
657 mtspr SPRN_SPRG_WSCRATCH4,r11
658 mfspr r10,SPRN_SRR0
659
660
661
662
663 lis r11,PAGE_OFFSET@h
664 cmplw cr0,r10,r11
665 blt+ 3f
666 lis r11,swapper_pg_dir@h
667 ori r11,r11, swapper_pg_dir@l
668 li r12,0
669 b 4f
670
671
6723: mfspr r11,SPRN_SPRG_THREAD
673 lwz r11,PGDIR(r11)
674 mfspr r12,SPRN_PID
6754: mtspr SPRN_MMUCR,r12
676
677
678 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
679
680
681
682 rlwinm r12,r10,PPC44x_PGD_OFF_SHIFT,PPC44x_PGD_OFF_MASK_BIT,29
683 lwzx r11,r12,r11
684
685
686 li r12,PPC47x_TLB0_VALID | PPC47x_TLBE_SIZE
687 rlwimi r10,r12,0,32-PAGE_SHIFT,31
688 li r12,0
689 tlbwe r10,r12,0
690
691
692
693#ifdef CONFIG_SMP
694 isync
695#endif
696
697 rlwinm. r12,r11,0,0,20
698
699 rlwimi r12,r10,PPC44x_PTE_ADD_SHIFT,PPC44x_PTE_ADD_MASK_BIT,28
700 beq 2f
701
702 lwz r11,0(r12)
703
704
705
706
707#ifdef CONFIG_SMP
708 lwsync
709#endif
710 lwz r12,4(r12)
711
712 andc. r13,r13,r12
713
714
715 beq finish_tlb_load_47x
716
7172:
718
719
720 mfspr r11, SPRN_SPRG_RSCRATCH4
721 mtcr r11
722 mfspr r13, SPRN_SPRG_RSCRATCH3
723 mfspr r12, SPRN_SPRG_RSCRATCH2
724 mfspr r11, SPRN_SPRG_RSCRATCH1
725 mfspr r10, SPRN_SPRG_RSCRATCH0
726 b InstructionStorage
727
728
729
730
731
732
733
734
735
736
737
738finish_tlb_load_47x:
739
740 rlwimi r11,r12,0,0,31-PAGE_SHIFT
741 tlbwe r11,r13,1
742
743
744 li r10,0xf85
745 rlwimi r10,r12,29,30,30
746 and r11,r12,r10
747 andi. r10,r12,_PAGE_USER
748 beq 1f
749 rlwimi r11,r11,3,26,28
7501: tlbwe r11,r13,2
751
752
753
754 mfspr r11, SPRN_SPRG_RSCRATCH4
755 mtcr r11
756 mfspr r13, SPRN_SPRG_RSCRATCH3
757 mfspr r12, SPRN_SPRG_RSCRATCH2
758 mfspr r11, SPRN_SPRG_RSCRATCH1
759 mfspr r10, SPRN_SPRG_RSCRATCH0
760 rfi
761
762#endif
763
764
765
766
767
768
769
770 DEBUG_CRIT_EXCEPTION
771
772interrupt_end:
773
774
775
776
777
778
779
780
781_GLOBAL(__fixup_440A_mcheck)
782 li r3,MachineCheckA@l
783 mtspr SPRN_IVOR1,r3
784 sync
785 blr
786
787_GLOBAL(set_context)
788
789#ifdef CONFIG_BDI_SWITCH
790
791
792
793 lis r5, abatron_pteptrs@h
794 ori r5, r5, abatron_pteptrs@l
795 stw r4, 0x4(r5)
796#endif
797 mtspr SPRN_PID,r3
798 isync
799 blr
800
801
802
803
804
805
806_GLOBAL(init_cpu_state)
807 mflr r22
808#ifdef CONFIG_PPC_47x
809
810 mfspr r3,SPRN_PVR
811 srwi r3,r3,16
812 cmplwi cr0,r3,PVR_476FPE@h
813 beq head_start_47x
814 cmplwi cr0,r3,PVR_476@h
815 beq head_start_47x
816 cmplwi cr0,r3,PVR_476_ISS@h
817 beq head_start_47x
818#endif
819
820
821
822
823
824 mfspr r3,SPRN_CCR0
825 rlwinm r3,r3,0,0,27
826 isync
827 mtspr SPRN_CCR0,r3
828 isync
829 sync
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858 mfspr r3,SPRN_PID
859 mfmsr r4
860 andi. r4,r4,MSR_IS@l
861 beq wmmucr
862 oris r3,r3,PPC44x_MMUCR_STS@h
863wmmucr: mtspr SPRN_MMUCR,r3
864 sync
865
866 bl invstr
867invstr: mflr r5
868 tlbsx r23,0,r5
869 li r4,0
870 li r3,0
8711: cmpw r23,r4
872 beq skpinv
873 tlbwe r3,r4,PPC44x_TLB_PAGEID
874skpinv: addi r4,r4,1
875 cmpwi r4,64
876 bne 1b
877 isync
878
879
880
881
882#ifdef CONFIG_NONSTATIC_KERNEL
883
884
885
886
887
888
889
890 tlbre r25,r23,PPC44x_TLB_XLAT
891
892 lis r3,KERNELBASE@h
893 ori r3,r3,KERNELBASE@l
894
895
896 mr r4,r25
897#else
898
899 lis r3,PAGE_OFFSET@h
900 ori r3,r3,PAGE_OFFSET@l
901
902
903 li r4, 0
904#endif
905
906
907 li r0,0
908 mtspr SPRN_PID,r0
909 sync
910
911
912 li r5,0
913 mtspr SPRN_MMUCR,r5
914 sync
915
916
917 clrrwi r3,r3,10
918 ori r3,r3,PPC44x_TLB_VALID | PPC44x_TLB_256M
919
920
921 clrrwi r4,r4,10
922
923
924
925
926 li r5,0
927 ori r5,r5,(PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
928
929 li r0,63
930
931 tlbwe r3,r0,PPC44x_TLB_PAGEID
932 tlbwe r4,r0,PPC44x_TLB_XLAT
933 tlbwe r5,r0,PPC44x_TLB_ATTRIB
934
935
936 mfmsr r0
937 mtspr SPRN_SRR1, r0
938 lis r0,3f@h
939 ori r0,r0,3f@l
940 mtspr SPRN_SRR0,r0
941 sync
942 rfi
943
944
9453: cmpwi r23,63
946 beq 4f
947 li r6,0
948 tlbwe r6,r23,PPC44x_TLB_PAGEID
949 isync
950
9514:
952#ifdef CONFIG_PPC_EARLY_DEBUG_44x
953
954
955
956 lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h
957 ori r3,r3,PPC44x_TLB_VALID|PPC44x_TLB_TS|PPC44x_TLB_64K
958
959
960 lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
961 ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
962
963
964 li r5,(PPC44x_TLB_SW|PPC44x_TLB_SR|PPC44x_TLB_I|PPC44x_TLB_G)
965 li r0,62
966
967 tlbwe r3,r0,PPC44x_TLB_PAGEID
968 tlbwe r4,r0,PPC44x_TLB_XLAT
969 tlbwe r5,r0,PPC44x_TLB_ATTRIB
970
971
972 isync
973#endif
974
975
976 SET_IVOR(0, CriticalInput);
977 SET_IVOR(1, MachineCheck);
978 SET_IVOR(2, DataStorage);
979 SET_IVOR(3, InstructionStorage);
980 SET_IVOR(4, ExternalInput);
981 SET_IVOR(5, Alignment);
982 SET_IVOR(6, Program);
983 SET_IVOR(7, FloatingPointUnavailable);
984 SET_IVOR(8, SystemCall);
985 SET_IVOR(9, AuxillaryProcessorUnavailable);
986 SET_IVOR(10, Decrementer);
987 SET_IVOR(11, FixedIntervalTimer);
988 SET_IVOR(12, WatchdogTimer);
989 SET_IVOR(13, DataTLBError44x);
990 SET_IVOR(14, InstructionTLBError44x);
991 SET_IVOR(15, DebugCrit);
992
993 b head_start_common
994
995
996#ifdef CONFIG_PPC_47x
997
998#ifdef CONFIG_SMP
999
1000
1001_GLOBAL(start_secondary_47x)
1002 mr r24,r3
1003
1004 bl init_cpu_state
1005
1006
1007
1008
1009
1010
1011
1012
1013 lis r1,temp_boot_stack@h
1014 ori r1,r1,temp_boot_stack@l
1015 addi r1,r1,1024-STACK_FRAME_OVERHEAD
1016 li r0,0
1017 stw r0,0(r1)
1018 bl mmu_init_secondary
1019
1020
1021
1022
1023 lis r1,secondary_ti@ha
1024 lwz r1,secondary_ti@l(r1)
1025 lwz r2,TI_TASK(r1)
1026
1027
1028 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1029 li r0,0
1030 stw r0,0(r1)
1031
1032
1033 addi r4,r2,THREAD
1034 mtspr SPRN_SPRG3,r4
1035
1036 b start_secondary
1037
1038#endif
1039
1040
1041
1042
1043
1044
1045
1046
1047head_start_47x:
1048
1049 mfspr r3,SPRN_PID
1050 mfmsr r4
1051 andi. r4,r4,MSR_IS@l
1052 beq 1f
1053 oris r3,r3,PPC47x_MMUCR_STS@h
10541: mtspr SPRN_MMUCR,r3
1055 sync
1056
1057
1058 bl 1f
10591: mflr r23
1060 tlbsx r23,0,r23
1061 tlbre r24,r23,0
1062 tlbre r25,r23,1
1063 tlbre r26,r23,2
1064
1065
1066
1067
1068
1069
1070 li r5,0
1071 mtspr SPRN_MMUCR,r5
1072 sync
1073
1074clear_all_utlb_entries:
1075
1076
1077
1078 addis r3,0,0x8000
1079 addi r4,0,0
1080 addi r5,0,0
1081 b clear_utlb_entry
1082
1083
1084
1085 .align 6
1086
1087clear_utlb_entry:
1088
1089 tlbwe r4,r3,0
1090 tlbwe r5,r3,1
1091 tlbwe r5,r3,2
1092 addis r3,r3,0x2000
1093 cmpwi r3,0
1094 bne clear_utlb_entry
1095 addis r3,0,0x8000
1096 addis r4,r4,0x100
1097 cmpwi r4,0
1098 bne clear_utlb_entry
1099
1100
1101
1102 oris r23,r23,0x8000
1103 tlbwe r24,r23,0
1104 tlbwe r25,r23,1
1105 tlbwe r26,r23,2
1106
1107
1108
1109
1110
1111 lis r3,PAGE_OFFSET@h
1112 ori r3,r3,PAGE_OFFSET@l
1113
1114
1115 li r0,0
1116 mtspr SPRN_PID,r0
1117 sync
1118
1119
1120 clrrwi r3,r3,12
1121 ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_256M
1122
1123
1124
1125
1126 li r5,0
1127 ori r5,r5,PPC47x_TLB2_S_RWX
1128#ifdef CONFIG_SMP
1129 ori r5,r5,PPC47x_TLB2_M
1130#endif
1131
1132
1133 lis r0,0x8800
1134 tlbwe r3,r0,0
1135 tlbwe r25,r0,1
1136 tlbwe r5,r0,2
1137
1138
1139
1140
1141
1142 LOAD_REG_IMMEDIATE(r3, 0x9abcdef0)
1143 mtspr SPRN_SSPCR,r3
1144 mtspr SPRN_USPCR,r3
1145 LOAD_REG_IMMEDIATE(r3, 0x12345670)
1146 mtspr SPRN_ISPCR,r3
1147
1148
1149 mfmsr r0
1150 mtspr SPRN_SRR1, r0
1151 lis r0,3f@h
1152 ori r0,r0,3f@l
1153 mtspr SPRN_SRR0,r0
1154 sync
1155 rfi
1156
1157
11583:
1159 rlwinm r24,r24,0,21,19
1160 tlbwe r24,r23,0
1161 addi r24,0,0
1162 tlbwe r24,r23,1
1163 tlbwe r24,r23,2
1164 isync
1165
1166#ifdef CONFIG_PPC_EARLY_DEBUG_44x
1167
1168
1169
1170 lis r3,PPC44x_EARLY_DEBUG_VIRTADDR@h
1171 ori r3,r3,PPC47x_TLB0_VALID | PPC47x_TLB0_TS | PPC47x_TLB0_1M
1172
1173
1174 lis r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW@h
1175 ori r4,r4,CONFIG_PPC_EARLY_DEBUG_44x_PHYSHIGH
1176
1177
1178 li r5,(PPC47x_TLB2_S_RW | PPC47x_TLB2_IMG)
1179
1180
1181
1182
1183
1184 lis r0,0x8d00
1185 tlbwe r3,r0,0
1186 tlbwe r4,r0,1
1187 tlbwe r5,r0,2
1188
1189
1190 isync
1191#endif
1192
1193
1194 SET_IVOR(0, CriticalInput);
1195 SET_IVOR(1, MachineCheckA);
1196 SET_IVOR(2, DataStorage);
1197 SET_IVOR(3, InstructionStorage);
1198 SET_IVOR(4, ExternalInput);
1199 SET_IVOR(5, Alignment);
1200 SET_IVOR(6, Program);
1201 SET_IVOR(7, FloatingPointUnavailable);
1202 SET_IVOR(8, SystemCall);
1203 SET_IVOR(9, AuxillaryProcessorUnavailable);
1204 SET_IVOR(10, Decrementer);
1205 SET_IVOR(11, FixedIntervalTimer);
1206 SET_IVOR(12, WatchdogTimer);
1207 SET_IVOR(13, DataTLBError47x);
1208 SET_IVOR(14, InstructionTLBError47x);
1209 SET_IVOR(15, DebugCrit);
1210
1211
1212
1213
1214
1215 mfspr r3,SPRN_CCR0
1216 oris r3,r3,0x0020
1217 mtspr SPRN_CCR0,r3
1218 isync
1219
1220#endif
1221
1222
1223
1224
1225
1226
1227
1228head_start_common:
1229
1230 lis r4,interrupt_base@h
1231 mtspr SPRN_IVPR,r4
1232
1233
1234
1235
1236
1237
1238 rlwinm r22,r22,0,4,31
1239 addis r22,r22,PAGE_OFFSET@h
1240 mtlr r22
1241 isync
1242 blr
1243
1244
1245
1246
1247
1248 .data
1249 .align PAGE_SHIFT
1250 .globl sdata
1251sdata:
1252 .globl empty_zero_page
1253empty_zero_page:
1254 .space PAGE_SIZE
1255
1256
1257
1258
1259 .globl swapper_pg_dir
1260swapper_pg_dir:
1261 .space PGD_TABLE_SIZE
1262
1263
1264
1265
1266
1267abatron_pteptrs:
1268 .space 8
1269
1270#ifdef CONFIG_SMP
1271 .align 12
1272temp_boot_stack:
1273 .space 1024
1274#endif
1275