LXR linux/arch/powerpc/platforms/85xx/b4

   1/*
   2 * B4 QDS Setup
   3 * Should apply for QDS platform of B4860 and it's personalities.
   4 * viz B4860/B4420/B4220QDS
   5 *
   6 * Copyright 2012 Freescale Semiconductor Inc.
   7 *
   8 * This program is free software; you can redistribute  it and/or modify it
   9 * under  the terms of  the GNU General  Public License as published by the
  10 * Free Software Foundation;  either version 2 of the  License, or (at your
  11 * option) any later version.
  12 */
  13
  14#include <linux/kernel.h>
  15#include <linux/pci.h>
  16#include <linux/kdev_t.h>
  17#include <linux/delay.h>
  18#include <linux/interrupt.h>
  19#include <linux/phy.h>
  20
  21#include <asm/time.h>
  22#include <asm/machdep.h>
  23#include <asm/pci-bridge.h>
  24#include <mm/mmu_decl.h>
  25#include <asm/prom.h>
  26#include <asm/udbg.h>
  27#include <asm/mpic.h>
  28
  29#include <linux/of_platform.h>
  30#include <sysdev/fsl_soc.h>
  31#include <sysdev/fsl_pci.h>
  32#include <asm/ehv_pic.h>
  33
  34#include "corenet_ds.h"
  35
  36/*
  37 * Called very early, device-tree isn't unflattened
  38 */
  39static int __init b4_qds_probe(void)
  40{
  41        unsigned long root = of_get_flat_dt_root();
  42#ifdef CONFIG_SMP
  43        extern struct smp_ops_t smp_85xx_ops;
  44#endif
  45
  46        if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
  47                (of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
  48                        (of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
  49                return 1;
  50
  51        /* Check if we're running under the Freescale hypervisor */
  52        if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
  53                (of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
  54                        (of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
  55                ppc_md.init_IRQ = ehv_pic_init;
  56                ppc_md.get_irq = ehv_pic_get_irq;
  57                ppc_md.restart = fsl_hv_restart;
  58                ppc_md.power_off = fsl_hv_halt;
  59                ppc_md.halt = fsl_hv_halt;
  60#ifdef CONFIG_SMP
  61                /*
  62                 * Disable the timebase sync operations because we can't write
  63                 * to the timebase registers under the hypervisor.
  64                  */
  65                smp_85xx_ops.give_timebase = NULL;
  66                smp_85xx_ops.take_timebase = NULL;
  67#endif
  68                return 1;
  69        }
  70
  71        return 0;
  72}
  73
  74define_machine(b4_qds) {
  75        .name                   = "B4 QDS",
  76        .probe                  = b4_qds_probe,
  77        .setup_arch             = corenet_ds_setup_arch,
  78        .init_IRQ               = corenet_ds_pic_init,
  79#ifdef CONFIG_PCI
  80        .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
  81#endif
  82/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
  83#ifdef CONFIG_PPC64
  84        .get_irq                = mpic_get_irq,
  85#else
  86        .get_irq                = mpic_get_coreint_irq,
  87#endif
  88        .restart                = fsl_rstcr_restart,
  89        .calibrate_decr         = generic_calibrate_decr,
  90        .progress               = udbg_progress,
  91#ifdef CONFIG_PPC64
  92        .power_save             = book3e_idle,
  93#else
  94        .power_save             = e500_idle,
  95#endif
  96};
  97
  98machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
  99
 100#ifdef CONFIG_SWIOTLB
 101machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier);
 102#endif
 103