linux/arch/s390/include/asm/processor.h
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   1/*
   2 *  S390 version
   3 *    Copyright IBM Corp. 1999
   4 *    Author(s): Hartmut Penner (hp@de.ibm.com),
   5 *               Martin Schwidefsky (schwidefsky@de.ibm.com)
   6 *
   7 *  Derived from "include/asm-i386/processor.h"
   8 *    Copyright (C) 1994, Linus Torvalds
   9 */
  10
  11#ifndef __ASM_S390_PROCESSOR_H
  12#define __ASM_S390_PROCESSOR_H
  13
  14#ifndef __ASSEMBLY__
  15
  16#include <linux/linkage.h>
  17#include <linux/irqflags.h>
  18#include <asm/cpu.h>
  19#include <asm/page.h>
  20#include <asm/ptrace.h>
  21#include <asm/setup.h>
  22#include <asm/runtime_instr.h>
  23
  24/*
  25 * Default implementation of macro that returns current
  26 * instruction pointer ("program counter").
  27 */
  28#define current_text_addr() ({ void *pc; asm("basr %0,0" : "=a" (pc)); pc; })
  29
  30static inline void get_cpu_id(struct cpuid *ptr)
  31{
  32        asm volatile("stidp %0" : "=Q" (*ptr));
  33}
  34
  35extern void s390_adjust_jiffies(void);
  36extern const struct seq_operations cpuinfo_op;
  37extern int sysctl_ieee_emulation_warnings;
  38extern void execve_tail(void);
  39
  40/*
  41 * User space process size: 2GB for 31 bit, 4TB or 8PT for 64 bit.
  42 */
  43#ifndef CONFIG_64BIT
  44
  45#define TASK_SIZE               (1UL << 31)
  46#define TASK_MAX_SIZE           (1UL << 31)
  47#define TASK_UNMAPPED_BASE      (1UL << 30)
  48
  49#else /* CONFIG_64BIT */
  50
  51#define TASK_SIZE_OF(tsk)       ((tsk)->mm->context.asce_limit)
  52#define TASK_UNMAPPED_BASE      (test_thread_flag(TIF_31BIT) ? \
  53                                        (1UL << 30) : (1UL << 41))
  54#define TASK_SIZE               TASK_SIZE_OF(current)
  55#define TASK_MAX_SIZE           (1UL << 53)
  56
  57#endif /* CONFIG_64BIT */
  58
  59#ifndef CONFIG_64BIT
  60#define STACK_TOP               (1UL << 31)
  61#define STACK_TOP_MAX           (1UL << 31)
  62#else /* CONFIG_64BIT */
  63#define STACK_TOP               (1UL << (test_thread_flag(TIF_31BIT) ? 31:42))
  64#define STACK_TOP_MAX           (1UL << 42)
  65#endif /* CONFIG_64BIT */
  66
  67#define HAVE_ARCH_PICK_MMAP_LAYOUT
  68
  69typedef struct {
  70        __u32 ar4;
  71} mm_segment_t;
  72
  73/*
  74 * Thread structure
  75 */
  76struct thread_struct {
  77        s390_fp_regs fp_regs;
  78        unsigned int  acrs[NUM_ACRS];
  79        unsigned long ksp;              /* kernel stack pointer             */
  80        mm_segment_t mm_segment;
  81        unsigned long gmap_addr;        /* address of last gmap fault. */
  82        struct per_regs per_user;       /* User specified PER registers */
  83        struct per_event per_event;     /* Cause of the last PER trap */
  84        unsigned long per_flags;        /* Flags to control debug behavior */
  85        /* pfault_wait is used to block the process on a pfault event */
  86        unsigned long pfault_wait;
  87        struct list_head list;
  88        /* cpu runtime instrumentation */
  89        struct runtime_instr_cb *ri_cb;
  90        int ri_signum;
  91#ifdef CONFIG_64BIT
  92        unsigned char trap_tdb[256];    /* Transaction abort diagnose block */
  93#endif
  94};
  95
  96/* Flag to disable transactions. */
  97#define PER_FLAG_NO_TE                  1UL
  98/* Flag to enable random transaction aborts. */
  99#define PER_FLAG_TE_ABORT_RAND          2UL
 100/* Flag to specify random transaction abort mode:
 101 * - abort each transaction at a random instruction before TEND if set.
 102 * - abort random transactions at a random instruction if cleared.
 103 */
 104#define PER_FLAG_TE_ABORT_RAND_TEND     4UL
 105
 106typedef struct thread_struct thread_struct;
 107
 108/*
 109 * Stack layout of a C stack frame.
 110 */
 111#ifndef __PACK_STACK
 112struct stack_frame {
 113        unsigned long back_chain;
 114        unsigned long empty1[5];
 115        unsigned long gprs[10];
 116        unsigned int  empty2[8];
 117};
 118#else
 119struct stack_frame {
 120        unsigned long empty1[5];
 121        unsigned int  empty2[8];
 122        unsigned long gprs[10];
 123        unsigned long back_chain;
 124};
 125#endif
 126
 127#define ARCH_MIN_TASKALIGN      8
 128
 129#define INIT_THREAD {                                                   \
 130        .ksp = sizeof(init_stack) + (unsigned long) &init_stack,        \
 131}
 132
 133/*
 134 * Do necessary setup to start up a new thread.
 135 */
 136#define start_thread(regs, new_psw, new_stackp) do {                    \
 137        regs->psw.mask  = psw_user_bits | PSW_MASK_EA | PSW_MASK_BA;    \
 138        regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 139        regs->gprs[15]  = new_stackp;                                   \
 140        execve_tail();                                                  \
 141} while (0)
 142
 143#define start_thread31(regs, new_psw, new_stackp) do {                  \
 144        regs->psw.mask  = psw_user_bits | PSW_MASK_BA;                  \
 145        regs->psw.addr  = new_psw | PSW_ADDR_AMODE;                     \
 146        regs->gprs[15]  = new_stackp;                                   \
 147        __tlb_flush_mm(current->mm);                                    \
 148        crst_table_downgrade(current->mm, 1UL << 31);                   \
 149        update_mm(current->mm, current);                                \
 150        execve_tail();                                                  \
 151} while (0)
 152
 153/* Forward declaration, a strange C thing */
 154struct task_struct;
 155struct mm_struct;
 156struct seq_file;
 157
 158#ifdef CONFIG_64BIT
 159extern void show_cacheinfo(struct seq_file *m);
 160#else
 161static inline void show_cacheinfo(struct seq_file *m) { }
 162#endif
 163
 164/* Free all resources held by a thread. */
 165extern void release_thread(struct task_struct *);
 166
 167/*
 168 * Return saved PC of a blocked thread.
 169 */
 170extern unsigned long thread_saved_pc(struct task_struct *t);
 171
 172extern void show_code(struct pt_regs *regs);
 173extern void print_fn_code(unsigned char *code, unsigned long len);
 174extern int insn_to_mnemonic(unsigned char *instruction, char *buf,
 175                            unsigned int len);
 176
 177unsigned long get_wchan(struct task_struct *p);
 178#define task_pt_regs(tsk) ((struct pt_regs *) \
 179        (task_stack_page(tsk) + THREAD_SIZE) - 1)
 180#define KSTK_EIP(tsk)   (task_pt_regs(tsk)->psw.addr)
 181#define KSTK_ESP(tsk)   (task_pt_regs(tsk)->gprs[15])
 182
 183static inline unsigned short stap(void)
 184{
 185        unsigned short cpu_address;
 186
 187        asm volatile("stap %0" : "=m" (cpu_address));
 188        return cpu_address;
 189}
 190
 191/*
 192 * Give up the time slice of the virtual PU.
 193 */
 194static inline void cpu_relax(void)
 195{
 196        if (MACHINE_HAS_DIAG44)
 197                asm volatile("diag 0,0,68");
 198        barrier();
 199}
 200
 201#define arch_mutex_cpu_relax()  barrier()
 202
 203static inline void psw_set_key(unsigned int key)
 204{
 205        asm volatile("spka 0(%0)" : : "d" (key));
 206}
 207
 208/*
 209 * Set PSW to specified value.
 210 */
 211static inline void __load_psw(psw_t psw)
 212{
 213#ifndef CONFIG_64BIT
 214        asm volatile("lpsw  %0" : : "Q" (psw) : "cc");
 215#else
 216        asm volatile("lpswe %0" : : "Q" (psw) : "cc");
 217#endif
 218}
 219
 220/*
 221 * Set PSW mask to specified value, while leaving the
 222 * PSW addr pointing to the next instruction.
 223 */
 224static inline void __load_psw_mask (unsigned long mask)
 225{
 226        unsigned long addr;
 227        psw_t psw;
 228
 229        psw.mask = mask;
 230
 231#ifndef CONFIG_64BIT
 232        asm volatile(
 233                "       basr    %0,0\n"
 234                "0:     ahi     %0,1f-0b\n"
 235                "       st      %0,%O1+4(%R1)\n"
 236                "       lpsw    %1\n"
 237                "1:"
 238                : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 239#else /* CONFIG_64BIT */
 240        asm volatile(
 241                "       larl    %0,1f\n"
 242                "       stg     %0,%O1+8(%R1)\n"
 243                "       lpswe   %1\n"
 244                "1:"
 245                : "=&d" (addr), "=Q" (psw) : "Q" (psw) : "memory", "cc");
 246#endif /* CONFIG_64BIT */
 247}
 248
 249/*
 250 * Rewind PSW instruction address by specified number of bytes.
 251 */
 252static inline unsigned long __rewind_psw(psw_t psw, unsigned long ilc)
 253{
 254#ifndef CONFIG_64BIT
 255        if (psw.addr & PSW_ADDR_AMODE)
 256                /* 31 bit mode */
 257                return (psw.addr - ilc) | PSW_ADDR_AMODE;
 258        /* 24 bit mode */
 259        return (psw.addr - ilc) & ((1UL << 24) - 1);
 260#else
 261        unsigned long mask;
 262
 263        mask = (psw.mask & PSW_MASK_EA) ? -1UL :
 264               (psw.mask & PSW_MASK_BA) ? (1UL << 31) - 1 :
 265                                          (1UL << 24) - 1;
 266        return (psw.addr - ilc) & mask;
 267#endif
 268}
 269 
 270/*
 271 * Function to drop a processor into disabled wait state
 272 */
 273static inline void __noreturn disabled_wait(unsigned long code)
 274{
 275        unsigned long ctl_buf;
 276        psw_t dw_psw;
 277
 278        dw_psw.mask = PSW_MASK_BASE | PSW_MASK_WAIT | PSW_MASK_BA | PSW_MASK_EA;
 279        dw_psw.addr = code;
 280        /* 
 281         * Store status and then load disabled wait psw,
 282         * the processor is dead afterwards
 283         */
 284#ifndef CONFIG_64BIT
 285        asm volatile(
 286                "       stctl   0,0,0(%2)\n"
 287                "       ni      0(%2),0xef\n"   /* switch off protection */
 288                "       lctl    0,0,0(%2)\n"
 289                "       stpt    0xd8\n"         /* store timer */
 290                "       stckc   0xe0\n"         /* store clock comparator */
 291                "       stpx    0x108\n"        /* store prefix register */
 292                "       stam    0,15,0x120\n"   /* store access registers */
 293                "       std     0,0x160\n"      /* store f0 */
 294                "       std     2,0x168\n"      /* store f2 */
 295                "       std     4,0x170\n"      /* store f4 */
 296                "       std     6,0x178\n"      /* store f6 */
 297                "       stm     0,15,0x180\n"   /* store general registers */
 298                "       stctl   0,15,0x1c0\n"   /* store control registers */
 299                "       oi      0x1c0,0x10\n"   /* fake protection bit */
 300                "       lpsw    0(%1)"
 301                : "=m" (ctl_buf)
 302                : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc");
 303#else /* CONFIG_64BIT */
 304        asm volatile(
 305                "       stctg   0,0,0(%2)\n"
 306                "       ni      4(%2),0xef\n"   /* switch off protection */
 307                "       lctlg   0,0,0(%2)\n"
 308                "       lghi    1,0x1000\n"
 309                "       stpt    0x328(1)\n"     /* store timer */
 310                "       stckc   0x330(1)\n"     /* store clock comparator */
 311                "       stpx    0x318(1)\n"     /* store prefix register */
 312                "       stam    0,15,0x340(1)\n"/* store access registers */
 313                "       stfpc   0x31c(1)\n"     /* store fpu control */
 314                "       std     0,0x200(1)\n"   /* store f0 */
 315                "       std     1,0x208(1)\n"   /* store f1 */
 316                "       std     2,0x210(1)\n"   /* store f2 */
 317                "       std     3,0x218(1)\n"   /* store f3 */
 318                "       std     4,0x220(1)\n"   /* store f4 */
 319                "       std     5,0x228(1)\n"   /* store f5 */
 320                "       std     6,0x230(1)\n"   /* store f6 */
 321                "       std     7,0x238(1)\n"   /* store f7 */
 322                "       std     8,0x240(1)\n"   /* store f8 */
 323                "       std     9,0x248(1)\n"   /* store f9 */
 324                "       std     10,0x250(1)\n"  /* store f10 */
 325                "       std     11,0x258(1)\n"  /* store f11 */
 326                "       std     12,0x260(1)\n"  /* store f12 */
 327                "       std     13,0x268(1)\n"  /* store f13 */
 328                "       std     14,0x270(1)\n"  /* store f14 */
 329                "       std     15,0x278(1)\n"  /* store f15 */
 330                "       stmg    0,15,0x280(1)\n"/* store general registers */
 331                "       stctg   0,15,0x380(1)\n"/* store control registers */
 332                "       oi      0x384(1),0x10\n"/* fake protection bit */
 333                "       lpswe   0(%1)"
 334                : "=m" (ctl_buf)
 335                : "a" (&dw_psw), "a" (&ctl_buf), "m" (dw_psw) : "cc", "0", "1");
 336#endif /* CONFIG_64BIT */
 337        while (1);
 338}
 339
 340/*
 341 * Use to set psw mask except for the first byte which
 342 * won't be changed by this function.
 343 */
 344static inline void
 345__set_psw_mask(unsigned long mask)
 346{
 347        __load_psw_mask(mask | (arch_local_save_flags() & ~(-1UL >> 8)));
 348}
 349
 350#define local_mcck_enable() \
 351        __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT | PSW_MASK_MCHECK)
 352#define local_mcck_disable() \
 353        __set_psw_mask(psw_kernel_bits | PSW_MASK_DAT)
 354
 355/*
 356 * Basic Machine Check/Program Check Handler.
 357 */
 358
 359extern void s390_base_mcck_handler(void);
 360extern void s390_base_pgm_handler(void);
 361extern void s390_base_ext_handler(void);
 362
 363extern void (*s390_base_mcck_handler_fn)(void);
 364extern void (*s390_base_pgm_handler_fn)(void);
 365extern void (*s390_base_ext_handler_fn)(void);
 366
 367#define ARCH_LOW_ADDRESS_LIMIT  0x7fffffffUL
 368
 369extern int memcpy_real(void *, void *, size_t);
 370extern void memcpy_absolute(void *, void *, size_t);
 371
 372#define mem_assign_absolute(dest, val) {                        \
 373        __typeof__(dest) __tmp = (val);                         \
 374                                                                \
 375        BUILD_BUG_ON(sizeof(__tmp) != sizeof(val));             \
 376        memcpy_absolute(&(dest), &__tmp, sizeof(__tmp));        \
 377}
 378
 379/*
 380 * Helper macro for exception table entries
 381 */
 382#define EX_TABLE(_fault, _target)       \
 383        ".section __ex_table,\"a\"\n"   \
 384        ".align 4\n"                    \
 385        ".long  (" #_fault ") - .\n"    \
 386        ".long  (" #_target ") - .\n"   \
 387        ".previous\n"
 388
 389#else /* __ASSEMBLY__ */
 390
 391#define EX_TABLE(_fault, _target)       \
 392        .section __ex_table,"a" ;       \
 393        .align  4 ;                     \
 394        .long   (_fault) - . ;          \
 395        .long   (_target) - . ;         \
 396        .previous
 397
 398#endif /* __ASSEMBLY__ */
 399
 400#endif /* __ASM_S390_PROCESSOR_H */
 401