LXR linux/arch/sparc/include/asm/tsb.h

   1#ifndef _SPARC64_TSB_H
   2#define _SPARC64_TSB_H
   3
   4/* The sparc64 TSB is similar to the powerpc hashtables.  It's a
   5 * power-of-2 sized table of TAG/PTE pairs.  The cpu precomputes
   6 * pointers into this table for 8K and 64K page sizes, and also a
   7 * comparison TAG based upon the virtual address and context which
   8 * faults.
   9 *
  10 * TLB miss trap handler software does the actual lookup via something
  11 * of the form:
  12 *
  13 *      ldxa            [%g0] ASI_{D,I}MMU_TSB_8KB_PTR, %g1
  14 *      ldxa            [%g0] ASI_{D,I}MMU, %g6
  15 *      sllx            %g6, 22, %g6
  16 *      srlx            %g6, 22, %g6
  17 *      ldda            [%g1] ASI_NUCLEUS_QUAD_LDD, %g4
  18 *      cmp             %g4, %g6
  19 *      bne,pn  %xcc, tsb_miss_{d,i}tlb
  20 *       mov            FAULT_CODE_{D,I}TLB, %g3
  21 *      stxa            %g5, [%g0] ASI_{D,I}TLB_DATA_IN
  22 *      retry
  23 *
  24 *
  25 * Each 16-byte slot of the TSB is the 8-byte tag and then the 8-byte
  26 * PTE.  The TAG is of the same layout as the TLB TAG TARGET mmu
  27 * register which is:
  28 *
  29 * -------------------------------------------------
  30 * |  -  |  CONTEXT |  -  |    VADDR bits 63:22    |
  31 * -------------------------------------------------
  32 *  63 61 60      48 47 42 41                     0
  33 *
  34 * But actually, since we use per-mm TSB's, we zero out the CONTEXT
  35 * field.
  36 *
  37 * Like the powerpc hashtables we need to use locking in order to
  38 * synchronize while we update the entries.  PTE updates need locking
  39 * as well.
  40 *
  41 * We need to carefully choose a lock bits for the TSB entry.  We
  42 * choose to use bit 47 in the tag.  Also, since we never map anything
  43 * at page zero in context zero, we use zero as an invalid tag entry.
  44 * When the lock bit is set, this forces a tag comparison failure.
  45 */
  46
  47#define TSB_TAG_LOCK_BIT        47
  48#define TSB_TAG_LOCK_HIGH       (1 << (TSB_TAG_LOCK_BIT - 32))
  49
  50#define TSB_TAG_INVALID_BIT     46
  51#define TSB_TAG_INVALID_HIGH    (1 << (TSB_TAG_INVALID_BIT - 32))
  52
  53/* Some cpus support physical address quad loads.  We want to use
  54 * those if possible so we don't need to hard-lock the TSB mapping
  55 * into the TLB.  We encode some instruction patching in order to
  56 * support this.
  57 *
  58 * The kernel TSB is locked into the TLB by virtue of being in the
  59 * kernel image, so we don't play these games for swapper_tsb access.
  60 */
  61#ifndef __ASSEMBLY__
  62struct tsb_ldquad_phys_patch_entry {
  63        unsigned int    addr;
  64        unsigned int    sun4u_insn;
  65        unsigned int    sun4v_insn;
  66};
  67extern struct tsb_ldquad_phys_patch_entry __tsb_ldquad_phys_patch,
  68        __tsb_ldquad_phys_patch_end;
  69
  70struct tsb_phys_patch_entry {
  71        unsigned int    addr;
  72        unsigned int    insn;
  73};
  74extern struct tsb_phys_patch_entry __tsb_phys_patch, __tsb_phys_patch_end;
  75#endif
  76#define TSB_LOAD_QUAD(TSB, REG) \
  77661:    ldda            [TSB] ASI_NUCLEUS_QUAD_LDD, REG; \
  78        .section        .tsb_ldquad_phys_patch, "ax"; \
  79        .word           661b; \
  80        ldda            [TSB] ASI_QUAD_LDD_PHYS, REG; \
  81        ldda            [TSB] ASI_QUAD_LDD_PHYS_4V, REG; \
  82        .previous
  83
  84#define TSB_LOAD_TAG_HIGH(TSB, REG) \
  85661:    lduwa           [TSB] ASI_N, REG; \
  86        .section        .tsb_phys_patch, "ax"; \
  87        .word           661b; \
  88        lduwa           [TSB] ASI_PHYS_USE_EC, REG; \
  89        .previous
  90
  91#define TSB_LOAD_TAG(TSB, REG) \
  92661:    ldxa            [TSB] ASI_N, REG; \
  93        .section        .tsb_phys_patch, "ax"; \
  94        .word           661b; \
  95        ldxa            [TSB] ASI_PHYS_USE_EC, REG; \
  96        .previous
  97
  98#define TSB_CAS_TAG_HIGH(TSB, REG1, REG2) \
  99661:    casa            [TSB] ASI_N, REG1, REG2; \
 100        .section        .tsb_phys_patch, "ax"; \
 101        .word           661b; \
 102        casa            [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
 103        .previous
 104
 105#define TSB_CAS_TAG(TSB, REG1, REG2) \
 106661:    casxa           [TSB] ASI_N, REG1, REG2; \
 107        .section        .tsb_phys_patch, "ax"; \
 108        .word           661b; \
 109        casxa           [TSB] ASI_PHYS_USE_EC, REG1, REG2; \
 110        .previous
 111
 112#define TSB_STORE(ADDR, VAL) \
 113661:    stxa            VAL, [ADDR] ASI_N; \
 114        .section        .tsb_phys_patch, "ax"; \
 115        .word           661b; \
 116        stxa            VAL, [ADDR] ASI_PHYS_USE_EC; \
 117        .previous
 118
 119#define TSB_LOCK_TAG(TSB, REG1, REG2)   \
 12099:     TSB_LOAD_TAG_HIGH(TSB, REG1);   \
 121        sethi   %hi(TSB_TAG_LOCK_HIGH), REG2;\
 122        andcc   REG1, REG2, %g0;        \
 123        bne,pn  %icc, 99b;              \
 124         nop;                           \
 125        TSB_CAS_TAG_HIGH(TSB, REG1, REG2);      \
 126        cmp     REG1, REG2;             \
 127        bne,pn  %icc, 99b;              \
 128         nop;                           \
 129
 130#define TSB_WRITE(TSB, TTE, TAG) \
 131        add     TSB, 0x8, TSB;   \
 132        TSB_STORE(TSB, TTE);     \
 133        sub     TSB, 0x8, TSB;   \
 134        TSB_STORE(TSB, TAG);
 135
 136        /* Do a kernel page table walk.  Leaves physical PTE pointer in
 137         * REG1.  Jumps to FAIL_LABEL on early page table walk termination.
 138         * VADDR will not be clobbered, but REG2 will.
 139         */
 140#define KERN_PGTABLE_WALK(VADDR, REG1, REG2, FAIL_LABEL)        \
 141        sethi           %hi(swapper_pg_dir), REG1; \
 142        or              REG1, %lo(swapper_pg_dir), REG1; \
 143        sllx            VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
 144        srlx            REG2, 64 - PAGE_SHIFT, REG2; \
 145        andn            REG2, 0x3, REG2; \
 146        lduw            [REG1 + REG2], REG1; \
 147        brz,pn          REG1, FAIL_LABEL; \
 148         sllx           VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
 149        srlx            REG2, 64 - PAGE_SHIFT, REG2; \
 150        sllx            REG1, PGD_PADDR_SHIFT, REG1; \
 151        andn            REG2, 0x3, REG2; \
 152        lduwa           [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
 153        brz,pn          REG1, FAIL_LABEL; \
 154         sllx           VADDR, 64 - PMD_SHIFT, REG2; \
 155        srlx            REG2, 64 - (PAGE_SHIFT - 1), REG2; \
 156        sllx            REG1, PMD_PADDR_SHIFT, REG1; \
 157        andn            REG2, 0x7, REG2; \
 158        add             REG1, REG2, REG1;
 159
 160        /* These macros exists only to make the PMD translator below
 161         * easier to read.  It hides the ELF section switch for the
 162         * sun4v code patching.
 163         */
 164#define OR_PTE_BIT_1INSN(REG, NAME)                     \
 165661:    or              REG, _PAGE_##NAME##_4U, REG;    \
 166        .section        .sun4v_1insn_patch, "ax";       \
 167        .word           661b;                           \
 168        or              REG, _PAGE_##NAME##_4V, REG;    \
 169        .previous;
 170
 171#define OR_PTE_BIT_2INSN(REG, TMP, NAME)                \
 172661:    sethi           %hi(_PAGE_##NAME##_4U), TMP;    \
 173        or              REG, TMP, REG;                  \
 174        .section        .sun4v_2insn_patch, "ax";       \
 175        .word           661b;                           \
 176        mov             -1, TMP;                        \
 177        or              REG, _PAGE_##NAME##_4V, REG;    \
 178        .previous;
 179
 180        /* Load into REG the PTE value for VALID, CACHE, and SZHUGE.  */
 181#define BUILD_PTE_VALID_SZHUGE_CACHE(REG)                                  \
 182661:    sethi           %uhi(_PAGE_VALID|_PAGE_SZHUGE_4U), REG;            \
 183        .section        .sun4v_1insn_patch, "ax";                          \
 184        .word           661b;                                              \
 185        sethi           %uhi(_PAGE_VALID), REG;                            \
 186        .previous;                                                         \
 187        sllx            REG, 32, REG;                                      \
 188661:    or              REG, _PAGE_CP_4U|_PAGE_CV_4U, REG;                 \
 189        .section        .sun4v_1insn_patch, "ax";                          \
 190        .word           661b;                                              \
 191        or              REG, _PAGE_CP_4V|_PAGE_CV_4V|_PAGE_SZHUGE_4V, REG; \
 192        .previous;
 193
 194        /* PMD has been loaded into REG1, interpret the value, seeing
 195         * if it is a HUGE PMD or a normal one.  If it is not valid
 196         * then jump to FAIL_LABEL.  If it is a HUGE PMD, and it
 197         * translates to a valid PTE, branch to PTE_LABEL.
 198         *
 199         * We translate the PMD by hand, one bit at a time,
 200         * constructing the huge PTE.
 201         *
 202         * So we construct the PTE in REG2 as follows:
 203         *
 204         * 1) Extract the PMD PFN from REG1 and place it into REG2.
 205         *
 206         * 2) Translate PMD protection bits in REG1 into REG2, one bit
 207         *    at a time using andcc tests on REG1 and OR's into REG2.
 208         *
 209         *    Only two bits to be concerned with here, EXEC and WRITE.
 210         *    Now REG1 is freed up and we can use it as a temporary.
 211         *
 212         * 3) Construct the VALID, CACHE, and page size PTE bits in
 213         *    REG1, OR with REG2 to form final PTE.
 214         */
 215#ifdef CONFIG_TRANSPARENT_HUGEPAGE
 216#define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
 217        brz,pn          REG1, FAIL_LABEL;                                     \
 218         andcc          REG1, PMD_ISHUGE, %g0;                                \
 219        be,pt           %xcc, 700f;                                           \
 220         and            REG1, PMD_HUGE_PRESENT|PMD_HUGE_ACCESSED, REG2;       \
 221        cmp             REG2, PMD_HUGE_PRESENT|PMD_HUGE_ACCESSED;             \
 222        bne,pn          %xcc, FAIL_LABEL;                                     \
 223         andn           REG1, PMD_HUGE_PROTBITS, REG2;                        \
 224        sllx            REG2, PMD_PADDR_SHIFT, REG2;                          \
 225        /* REG2 now holds PFN << PAGE_SHIFT */                                \
 226        andcc           REG1, PMD_HUGE_WRITE, %g0;                            \
 227        bne,a,pt        %xcc, 1f;                                             \
 228         OR_PTE_BIT_1INSN(REG2, W);                                           \
 2291:      andcc           REG1, PMD_HUGE_EXEC, %g0;                             \
 230        be,pt           %xcc, 1f;                                             \
 231         nop;                                                                 \
 232        OR_PTE_BIT_2INSN(REG2, REG1, EXEC);                                   \
 233        /* REG1 can now be clobbered, build final PTE */                      \
 2341:      BUILD_PTE_VALID_SZHUGE_CACHE(REG1);                                   \
 235        ba,pt           %xcc, PTE_LABEL;                                      \
 236         or             REG1, REG2, REG1;                                     \
 237700:
 238#else
 239#define USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, PTE_LABEL) \
 240        brz,pn          REG1, FAIL_LABEL; \
 241         nop;
 242#endif
 243
 244        /* Do a user page table walk in MMU globals.  Leaves final,
 245         * valid, PTE value in REG1.  Jumps to FAIL_LABEL on early
 246         * page table walk termination or if the PTE is not valid.
 247         *
 248         * Physical base of page tables is in PHYS_PGD which will not
 249         * be modified.
 250         *
 251         * VADDR will not be clobbered, but REG1 and REG2 will.
 252         */
 253#define USER_PGTABLE_WALK_TL1(VADDR, PHYS_PGD, REG1, REG2, FAIL_LABEL)  \
 254        sllx            VADDR, 64 - (PGDIR_SHIFT + PGDIR_BITS), REG2; \
 255        srlx            REG2, 64 - PAGE_SHIFT, REG2; \
 256        andn            REG2, 0x3, REG2; \
 257        lduwa           [PHYS_PGD + REG2] ASI_PHYS_USE_EC, REG1; \
 258        brz,pn          REG1, FAIL_LABEL; \
 259         sllx           VADDR, 64 - (PMD_SHIFT + PMD_BITS), REG2; \
 260        srlx            REG2, 64 - PAGE_SHIFT, REG2; \
 261        sllx            REG1, PGD_PADDR_SHIFT, REG1; \
 262        andn            REG2, 0x3, REG2; \
 263        lduwa           [REG1 + REG2] ASI_PHYS_USE_EC, REG1; \
 264        USER_PGTABLE_CHECK_PMD_HUGE(VADDR, REG1, REG2, FAIL_LABEL, 800f) \
 265        sllx            VADDR, 64 - PMD_SHIFT, REG2; \
 266        srlx            REG2, 64 - (PAGE_SHIFT - 1), REG2; \
 267        sllx            REG1, PMD_PADDR_SHIFT, REG1; \
 268        andn            REG2, 0x7, REG2; \
 269        add             REG1, REG2, REG1; \
 270        ldxa            [REG1] ASI_PHYS_USE_EC, REG1; \
 271        brgez,pn        REG1, FAIL_LABEL; \
 272         nop; \
 273800:
 274
 275/* Lookup a OBP mapping on VADDR in the prom_trans[] table at TL>0.
 276 * If no entry is found, FAIL_LABEL will be branched to.  On success
 277 * the resulting PTE value will be left in REG1.  VADDR is preserved
 278 * by this routine.
 279 */
 280#define OBP_TRANS_LOOKUP(VADDR, REG1, REG2, REG3, FAIL_LABEL) \
 281        sethi           %hi(prom_trans), REG1; \
 282        or              REG1, %lo(prom_trans), REG1; \
 28397:     ldx             [REG1 + 0x00], REG2; \
 284        brz,pn          REG2, FAIL_LABEL; \
 285         nop; \
 286        ldx             [REG1 + 0x08], REG3; \
 287        add             REG2, REG3, REG3; \
 288        cmp             REG2, VADDR; \
 289        bgu,pt          %xcc, 98f; \
 290         cmp            VADDR, REG3; \
 291        bgeu,pt         %xcc, 98f; \
 292         ldx            [REG1 + 0x10], REG3; \
 293        sub             VADDR, REG2, REG2; \
 294        ba,pt           %xcc, 99f; \
 295         add            REG3, REG2, REG1; \
 29698:     ba,pt           %xcc, 97b; \
 297         add            REG1, (3 * 8), REG1; \
 29899:
 299
 300        /* We use a 32K TSB for the whole kernel, this allows to
 301         * handle about 16MB of modules and vmalloc mappings without
 302         * incurring many hash conflicts.
 303         */
 304#define KERNEL_TSB_SIZE_BYTES   (32 * 1024)
 305#define KERNEL_TSB_NENTRIES     \
 306        (KERNEL_TSB_SIZE_BYTES / 16)
 307#define KERNEL_TSB4M_NENTRIES   4096
 308
 309#define KTSB_PHYS_SHIFT         15
 310
 311        /* Do a kernel TSB lookup at tl>0 on VADDR+TAG, branch to OK_LABEL
 312         * on TSB hit.  REG1, REG2, REG3, and REG4 are used as temporaries
 313         * and the found TTE will be left in REG1.  REG3 and REG4 must
 314         * be an even/odd pair of registers.
 315         *
 316         * VADDR and TAG will be preserved and not clobbered by this macro.
 317         */
 318#define KERN_TSB_LOOKUP_TL1(VADDR, TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
 319661:    sethi           %hi(swapper_tsb), REG1;                 \
 320        or              REG1, %lo(swapper_tsb), REG1; \
 321        .section        .swapper_tsb_phys_patch, "ax"; \
 322        .word           661b; \
 323        .previous; \
 324661:    nop; \
 325        .section        .tsb_ldquad_phys_patch, "ax"; \
 326        .word           661b; \
 327        sllx            REG1, KTSB_PHYS_SHIFT, REG1; \
 328        sllx            REG1, KTSB_PHYS_SHIFT, REG1; \
 329        .previous; \
 330        srlx            VADDR, PAGE_SHIFT, REG2; \
 331        and             REG2, (KERNEL_TSB_NENTRIES - 1), REG2; \
 332        sllx            REG2, 4, REG2; \
 333        add             REG1, REG2, REG2; \
 334        TSB_LOAD_QUAD(REG2, REG3); \
 335        cmp             REG3, TAG; \
 336        be,a,pt         %xcc, OK_LABEL; \
 337         mov            REG4, REG1;
 338
 339#ifndef CONFIG_DEBUG_PAGEALLOC
 340        /* This version uses a trick, the TAG is already (VADDR >> 22) so
 341         * we can make use of that for the index computation.
 342         */
 343#define KERN_TSB4M_LOOKUP_TL1(TAG, REG1, REG2, REG3, REG4, OK_LABEL) \
 344661:    sethi           %hi(swapper_4m_tsb), REG1;           \
 345        or              REG1, %lo(swapper_4m_tsb), REG1; \
 346        .section        .swapper_4m_tsb_phys_patch, "ax"; \
 347        .word           661b; \
 348        .previous; \
 349661:    nop; \
 350        .section        .tsb_ldquad_phys_patch, "ax"; \
 351        .word           661b; \
 352        sllx            REG1, KTSB_PHYS_SHIFT, REG1; \
 353        sllx            REG1, KTSB_PHYS_SHIFT, REG1; \
 354        .previous; \
 355        and             TAG, (KERNEL_TSB4M_NENTRIES - 1), REG2; \
 356        sllx            REG2, 4, REG2; \
 357        add             REG1, REG2, REG2; \
 358        TSB_LOAD_QUAD(REG2, REG3); \
 359        cmp             REG3, TAG; \
 360        be,a,pt         %xcc, OK_LABEL; \
 361         mov            REG4, REG1;
 362#endif
 363
 364#endif /* !(_SPARC64_TSB_H) */
 365