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6#include <linux/string.h>
7#include <linux/slab.h>
8#include <linux/init.h>
9#include <linux/pci.h>
10#include <linux/device.h>
11#include <linux/of_device.h>
12
13#include <asm/prom.h>
14#include <asm/oplib.h>
15
16#include "pci_impl.h"
17#include "pci_sun4v.h"
18
19static int config_out_of_range(struct pci_pbm_info *pbm,
20 unsigned long bus,
21 unsigned long devfn,
22 unsigned long reg)
23{
24 if (bus < pbm->pci_first_busno ||
25 bus > pbm->pci_last_busno)
26 return 1;
27 return 0;
28}
29
30static void *sun4u_config_mkaddr(struct pci_pbm_info *pbm,
31 unsigned long bus,
32 unsigned long devfn,
33 unsigned long reg)
34{
35 unsigned long rbits = pbm->config_space_reg_bits;
36
37 if (config_out_of_range(pbm, bus, devfn, reg))
38 return NULL;
39
40 reg = (reg & ((1 << rbits) - 1));
41 devfn <<= rbits;
42 bus <<= rbits + 8;
43
44 return (void *) (pbm->config_space | bus | devfn | reg);
45}
46
47
48
49
50
51
52static int sun4u_read_pci_cfg_host(struct pci_pbm_info *pbm,
53 unsigned char bus, unsigned int devfn,
54 int where, int size, u32 *value)
55{
56 u32 tmp32, *addr;
57 u16 tmp16;
58 u8 tmp8;
59
60 addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
61 if (!addr)
62 return PCIBIOS_SUCCESSFUL;
63
64 switch (size) {
65 case 1:
66 if (where < 8) {
67 unsigned long align = (unsigned long) addr;
68
69 align &= ~1;
70 pci_config_read16((u16 *)align, &tmp16);
71 if (where & 1)
72 *value = tmp16 >> 8;
73 else
74 *value = tmp16 & 0xff;
75 } else {
76 pci_config_read8((u8 *)addr, &tmp8);
77 *value = (u32) tmp8;
78 }
79 break;
80
81 case 2:
82 if (where < 8) {
83 pci_config_read16((u16 *)addr, &tmp16);
84 *value = (u32) tmp16;
85 } else {
86 pci_config_read8((u8 *)addr, &tmp8);
87 *value = (u32) tmp8;
88 pci_config_read8(((u8 *)addr) + 1, &tmp8);
89 *value |= ((u32) tmp8) << 8;
90 }
91 break;
92
93 case 4:
94 tmp32 = 0xffffffff;
95 sun4u_read_pci_cfg_host(pbm, bus, devfn,
96 where, 2, &tmp32);
97 *value = tmp32;
98
99 tmp32 = 0xffffffff;
100 sun4u_read_pci_cfg_host(pbm, bus, devfn,
101 where + 2, 2, &tmp32);
102 *value |= tmp32 << 16;
103 break;
104 }
105 return PCIBIOS_SUCCESSFUL;
106}
107
108static int sun4u_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
109 int where, int size, u32 *value)
110{
111 struct pci_pbm_info *pbm = bus_dev->sysdata;
112 unsigned char bus = bus_dev->number;
113 u32 *addr;
114 u16 tmp16;
115 u8 tmp8;
116
117 switch (size) {
118 case 1:
119 *value = 0xff;
120 break;
121 case 2:
122 *value = 0xffff;
123 break;
124 case 4:
125 *value = 0xffffffff;
126 break;
127 }
128
129 if (!bus_dev->number && !PCI_SLOT(devfn))
130 return sun4u_read_pci_cfg_host(pbm, bus, devfn, where,
131 size, value);
132
133 addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
134 if (!addr)
135 return PCIBIOS_SUCCESSFUL;
136
137 switch (size) {
138 case 1:
139 pci_config_read8((u8 *)addr, &tmp8);
140 *value = (u32) tmp8;
141 break;
142
143 case 2:
144 if (where & 0x01) {
145 printk("pci_read_config_word: misaligned reg [%x]\n",
146 where);
147 return PCIBIOS_SUCCESSFUL;
148 }
149 pci_config_read16((u16 *)addr, &tmp16);
150 *value = (u32) tmp16;
151 break;
152
153 case 4:
154 if (where & 0x03) {
155 printk("pci_read_config_dword: misaligned reg [%x]\n",
156 where);
157 return PCIBIOS_SUCCESSFUL;
158 }
159 pci_config_read32(addr, value);
160 break;
161 }
162 return PCIBIOS_SUCCESSFUL;
163}
164
165static int sun4u_write_pci_cfg_host(struct pci_pbm_info *pbm,
166 unsigned char bus, unsigned int devfn,
167 int where, int size, u32 value)
168{
169 u32 *addr;
170
171 addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
172 if (!addr)
173 return PCIBIOS_SUCCESSFUL;
174
175 switch (size) {
176 case 1:
177 if (where < 8) {
178 unsigned long align = (unsigned long) addr;
179 u16 tmp16;
180
181 align &= ~1;
182 pci_config_read16((u16 *)align, &tmp16);
183 if (where & 1) {
184 tmp16 &= 0x00ff;
185 tmp16 |= value << 8;
186 } else {
187 tmp16 &= 0xff00;
188 tmp16 |= value;
189 }
190 pci_config_write16((u16 *)align, tmp16);
191 } else
192 pci_config_write8((u8 *)addr, value);
193 break;
194 case 2:
195 if (where < 8) {
196 pci_config_write16((u16 *)addr, value);
197 } else {
198 pci_config_write8((u8 *)addr, value & 0xff);
199 pci_config_write8(((u8 *)addr) + 1, value >> 8);
200 }
201 break;
202 case 4:
203 sun4u_write_pci_cfg_host(pbm, bus, devfn,
204 where, 2, value & 0xffff);
205 sun4u_write_pci_cfg_host(pbm, bus, devfn,
206 where + 2, 2, value >> 16);
207 break;
208 }
209 return PCIBIOS_SUCCESSFUL;
210}
211
212static int sun4u_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
213 int where, int size, u32 value)
214{
215 struct pci_pbm_info *pbm = bus_dev->sysdata;
216 unsigned char bus = bus_dev->number;
217 u32 *addr;
218
219 if (!bus_dev->number && !PCI_SLOT(devfn))
220 return sun4u_write_pci_cfg_host(pbm, bus, devfn, where,
221 size, value);
222
223 addr = sun4u_config_mkaddr(pbm, bus, devfn, where);
224 if (!addr)
225 return PCIBIOS_SUCCESSFUL;
226
227 switch (size) {
228 case 1:
229 pci_config_write8((u8 *)addr, value);
230 break;
231
232 case 2:
233 if (where & 0x01) {
234 printk("pci_write_config_word: misaligned reg [%x]\n",
235 where);
236 return PCIBIOS_SUCCESSFUL;
237 }
238 pci_config_write16((u16 *)addr, value);
239 break;
240
241 case 4:
242 if (where & 0x03) {
243 printk("pci_write_config_dword: misaligned reg [%x]\n",
244 where);
245 return PCIBIOS_SUCCESSFUL;
246 }
247 pci_config_write32(addr, value);
248 }
249 return PCIBIOS_SUCCESSFUL;
250}
251
252struct pci_ops sun4u_pci_ops = {
253 .read = sun4u_read_pci_cfg,
254 .write = sun4u_write_pci_cfg,
255};
256
257static int sun4v_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
258 int where, int size, u32 *value)
259{
260 struct pci_pbm_info *pbm = bus_dev->sysdata;
261 u32 devhandle = pbm->devhandle;
262 unsigned int bus = bus_dev->number;
263 unsigned int device = PCI_SLOT(devfn);
264 unsigned int func = PCI_FUNC(devfn);
265 unsigned long ret;
266
267 if (config_out_of_range(pbm, bus, devfn, where)) {
268 ret = ~0UL;
269 } else {
270 ret = pci_sun4v_config_get(devhandle,
271 HV_PCI_DEVICE_BUILD(bus, device, func),
272 where, size);
273 }
274 switch (size) {
275 case 1:
276 *value = ret & 0xff;
277 break;
278 case 2:
279 *value = ret & 0xffff;
280 break;
281 case 4:
282 *value = ret & 0xffffffff;
283 break;
284 }
285
286
287 return PCIBIOS_SUCCESSFUL;
288}
289
290static int sun4v_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
291 int where, int size, u32 value)
292{
293 struct pci_pbm_info *pbm = bus_dev->sysdata;
294 u32 devhandle = pbm->devhandle;
295 unsigned int bus = bus_dev->number;
296 unsigned int device = PCI_SLOT(devfn);
297 unsigned int func = PCI_FUNC(devfn);
298
299 if (config_out_of_range(pbm, bus, devfn, where)) {
300
301 } else {
302
303
304
305
306 pci_sun4v_config_put(devhandle,
307 HV_PCI_DEVICE_BUILD(bus, device, func),
308 where, size, value);
309 }
310 return PCIBIOS_SUCCESSFUL;
311}
312
313struct pci_ops sun4v_pci_ops = {
314 .read = sun4v_read_pci_cfg,
315 .write = sun4v_write_pci_cfg,
316};
317
318void pci_get_pbm_props(struct pci_pbm_info *pbm)
319{
320 const u32 *val = of_get_property(pbm->op->dev.of_node, "bus-range", NULL);
321
322 pbm->pci_first_busno = val[0];
323 pbm->pci_last_busno = val[1];
324
325 val = of_get_property(pbm->op->dev.of_node, "ino-bitmap", NULL);
326 if (val) {
327 pbm->ino_bitmap = (((u64)val[1] << 32UL) |
328 ((u64)val[0] << 0UL));
329 }
330}
331
332static void pci_register_legacy_regions(struct resource *io_res,
333 struct resource *mem_res)
334{
335 struct resource *p;
336
337
338 p = kzalloc(sizeof(*p), GFP_KERNEL);
339 if (!p)
340 return;
341
342 p->name = "Video RAM area";
343 p->start = mem_res->start + 0xa0000UL;
344 p->end = p->start + 0x1ffffUL;
345 p->flags = IORESOURCE_BUSY;
346 request_resource(mem_res, p);
347
348 p = kzalloc(sizeof(*p), GFP_KERNEL);
349 if (!p)
350 return;
351
352 p->name = "System ROM";
353 p->start = mem_res->start + 0xf0000UL;
354 p->end = p->start + 0xffffUL;
355 p->flags = IORESOURCE_BUSY;
356 request_resource(mem_res, p);
357
358 p = kzalloc(sizeof(*p), GFP_KERNEL);
359 if (!p)
360 return;
361
362 p->name = "Video ROM";
363 p->start = mem_res->start + 0xc0000UL;
364 p->end = p->start + 0x7fffUL;
365 p->flags = IORESOURCE_BUSY;
366 request_resource(mem_res, p);
367}
368
369static void pci_register_iommu_region(struct pci_pbm_info *pbm)
370{
371 const u32 *vdma = of_get_property(pbm->op->dev.of_node, "virtual-dma",
372 NULL);
373
374 if (vdma) {
375 struct resource *rp = kzalloc(sizeof(*rp), GFP_KERNEL);
376
377 if (!rp) {
378 pr_info("%s: Cannot allocate IOMMU resource.\n",
379 pbm->name);
380 return;
381 }
382 rp->name = "IOMMU";
383 rp->start = pbm->mem_space.start + (unsigned long) vdma[0];
384 rp->end = rp->start + (unsigned long) vdma[1] - 1UL;
385 rp->flags = IORESOURCE_BUSY;
386 if (request_resource(&pbm->mem_space, rp)) {
387 pr_info("%s: Unable to request IOMMU resource.\n",
388 pbm->name);
389 kfree(rp);
390 }
391 }
392}
393
394void pci_determine_mem_io_space(struct pci_pbm_info *pbm)
395{
396 const struct linux_prom_pci_ranges *pbm_ranges;
397 int i, saw_mem, saw_io;
398 int num_pbm_ranges;
399
400 saw_mem = saw_io = 0;
401 pbm_ranges = of_get_property(pbm->op->dev.of_node, "ranges", &i);
402 if (!pbm_ranges) {
403 prom_printf("PCI: Fatal error, missing PBM ranges property "
404 " for %s\n",
405 pbm->name);
406 prom_halt();
407 }
408
409 num_pbm_ranges = i / sizeof(*pbm_ranges);
410
411 for (i = 0; i < num_pbm_ranges; i++) {
412 const struct linux_prom_pci_ranges *pr = &pbm_ranges[i];
413 unsigned long a, size;
414 u32 parent_phys_hi, parent_phys_lo;
415 u32 size_hi, size_lo;
416 int type;
417
418 parent_phys_hi = pr->parent_phys_hi;
419 parent_phys_lo = pr->parent_phys_lo;
420 if (tlb_type == hypervisor)
421 parent_phys_hi &= 0x0fffffff;
422
423 size_hi = pr->size_hi;
424 size_lo = pr->size_lo;
425
426 type = (pr->child_phys_hi >> 24) & 0x3;
427 a = (((unsigned long)parent_phys_hi << 32UL) |
428 ((unsigned long)parent_phys_lo << 0UL));
429 size = (((unsigned long)size_hi << 32UL) |
430 ((unsigned long)size_lo << 0UL));
431
432 switch (type) {
433 case 0:
434
435 pbm->config_space = a;
436 break;
437
438 case 1:
439
440 pbm->io_space.start = a;
441 pbm->io_space.end = a + size - 1UL;
442 pbm->io_space.flags = IORESOURCE_IO;
443 saw_io = 1;
444 break;
445
446 case 2:
447
448 pbm->mem_space.start = a;
449 pbm->mem_space.end = a + size - 1UL;
450 pbm->mem_space.flags = IORESOURCE_MEM;
451 saw_mem = 1;
452 break;
453
454 case 3:
455
456
457 default:
458 break;
459 }
460 }
461
462 if (!saw_io || !saw_mem) {
463 prom_printf("%s: Fatal error, missing %s PBM range.\n",
464 pbm->name,
465 (!saw_io ? "IO" : "MEM"));
466 prom_halt();
467 }
468
469 printk("%s: PCI IO[%llx] MEM[%llx]\n",
470 pbm->name,
471 pbm->io_space.start,
472 pbm->mem_space.start);
473
474 pbm->io_space.name = pbm->mem_space.name = pbm->name;
475
476 request_resource(&ioport_resource, &pbm->io_space);
477 request_resource(&iomem_resource, &pbm->mem_space);
478
479 pci_register_legacy_regions(&pbm->io_space,
480 &pbm->mem_space);
481 pci_register_iommu_region(pbm);
482}
483
484
485void pci_scan_for_target_abort(struct pci_pbm_info *pbm,
486 struct pci_bus *pbus)
487{
488 struct pci_dev *pdev;
489 struct pci_bus *bus;
490
491 list_for_each_entry(pdev, &pbus->devices, bus_list) {
492 u16 status, error_bits;
493
494 pci_read_config_word(pdev, PCI_STATUS, &status);
495 error_bits =
496 (status & (PCI_STATUS_SIG_TARGET_ABORT |
497 PCI_STATUS_REC_TARGET_ABORT));
498 if (error_bits) {
499 pci_write_config_word(pdev, PCI_STATUS, error_bits);
500 printk("%s: Device %s saw Target Abort [%016x]\n",
501 pbm->name, pci_name(pdev), status);
502 }
503 }
504
505 list_for_each_entry(bus, &pbus->children, node)
506 pci_scan_for_target_abort(pbm, bus);
507}
508
509void pci_scan_for_master_abort(struct pci_pbm_info *pbm,
510 struct pci_bus *pbus)
511{
512 struct pci_dev *pdev;
513 struct pci_bus *bus;
514
515 list_for_each_entry(pdev, &pbus->devices, bus_list) {
516 u16 status, error_bits;
517
518 pci_read_config_word(pdev, PCI_STATUS, &status);
519 error_bits =
520 (status & (PCI_STATUS_REC_MASTER_ABORT));
521 if (error_bits) {
522 pci_write_config_word(pdev, PCI_STATUS, error_bits);
523 printk("%s: Device %s received Master Abort [%016x]\n",
524 pbm->name, pci_name(pdev), status);
525 }
526 }
527
528 list_for_each_entry(bus, &pbus->children, node)
529 pci_scan_for_master_abort(pbm, bus);
530}
531
532void pci_scan_for_parity_error(struct pci_pbm_info *pbm,
533 struct pci_bus *pbus)
534{
535 struct pci_dev *pdev;
536 struct pci_bus *bus;
537
538 list_for_each_entry(pdev, &pbus->devices, bus_list) {
539 u16 status, error_bits;
540
541 pci_read_config_word(pdev, PCI_STATUS, &status);
542 error_bits =
543 (status & (PCI_STATUS_PARITY |
544 PCI_STATUS_DETECTED_PARITY));
545 if (error_bits) {
546 pci_write_config_word(pdev, PCI_STATUS, error_bits);
547 printk("%s: Device %s saw Parity Error [%016x]\n",
548 pbm->name, pci_name(pdev), status);
549 }
550 }
551
552 list_for_each_entry(bus, &pbus->children, node)
553 pci_scan_for_parity_error(pbm, bus);
554}
555
