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35#ifndef _AHCI_H
36#define _AHCI_H
37
38#include <linux/clk.h>
39#include <linux/libata.h>
40
41
42#define EM_CTRL_MSG_TYPE 0x000f0000
43
44
45#define EM_MSG_LED_HBA_PORT 0x0000000f
46#define EM_MSG_LED_PMP_SLOT 0x0000ff00
47#define EM_MSG_LED_VALUE 0xffff0000
48#define EM_MSG_LED_VALUE_ACTIVITY 0x00070000
49#define EM_MSG_LED_VALUE_OFF 0xfff80000
50#define EM_MSG_LED_VALUE_ON 0x00010000
51
52enum {
53 AHCI_MAX_PORTS = 32,
54 AHCI_MAX_SG = 168,
55 AHCI_DMA_BOUNDARY = 0xffffffff,
56 AHCI_MAX_CMDS = 32,
57 AHCI_CMD_SZ = 32,
58 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
59 AHCI_RX_FIS_SZ = 256,
60 AHCI_CMD_TBL_CDB = 0x40,
61 AHCI_CMD_TBL_HDR_SZ = 0x80,
62 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
63 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_PORT_PRIV_FBS_DMA_SZ = AHCI_CMD_SLOT_SZ +
67 AHCI_CMD_TBL_AR_SZ +
68 (AHCI_RX_FIS_SZ * 16),
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
72 AHCI_CMD_PREFETCH = (1 << 7),
73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
75
76 RX_FIS_PIO_SETUP = 0x20,
77 RX_FIS_D2H_REG = 0x40,
78 RX_FIS_SDB = 0x58,
79 RX_FIS_UNK = 0x60,
80
81
82 HOST_CAP = 0x00,
83 HOST_CTL = 0x04,
84 HOST_IRQ_STAT = 0x08,
85 HOST_PORTS_IMPL = 0x0c,
86 HOST_VERSION = 0x10,
87 HOST_EM_LOC = 0x1c,
88 HOST_EM_CTL = 0x20,
89 HOST_CAP2 = 0x24,
90
91
92 HOST_RESET = (1 << 0),
93 HOST_IRQ_EN = (1 << 1),
94 HOST_AHCI_EN = (1 << 31),
95
96
97 HOST_CAP_SXS = (1 << 5),
98 HOST_CAP_EMS = (1 << 6),
99 HOST_CAP_CCC = (1 << 7),
100 HOST_CAP_PART = (1 << 13),
101 HOST_CAP_SSC = (1 << 14),
102 HOST_CAP_PIO_MULTI = (1 << 15),
103 HOST_CAP_FBS = (1 << 16),
104 HOST_CAP_PMP = (1 << 17),
105 HOST_CAP_ONLY = (1 << 18),
106 HOST_CAP_CLO = (1 << 24),
107 HOST_CAP_LED = (1 << 25),
108 HOST_CAP_ALPM = (1 << 26),
109 HOST_CAP_SSS = (1 << 27),
110 HOST_CAP_MPS = (1 << 28),
111 HOST_CAP_SNTF = (1 << 29),
112 HOST_CAP_NCQ = (1 << 30),
113 HOST_CAP_64 = (1 << 31),
114
115
116 HOST_CAP2_BOH = (1 << 0),
117 HOST_CAP2_NVMHCI = (1 << 1),
118 HOST_CAP2_APST = (1 << 2),
119 HOST_CAP2_SDS = (1 << 3),
120 HOST_CAP2_SADM = (1 << 4),
121 HOST_CAP2_DESO = (1 << 5),
122
123
124 PORT_LST_ADDR = 0x00,
125 PORT_LST_ADDR_HI = 0x04,
126 PORT_FIS_ADDR = 0x08,
127 PORT_FIS_ADDR_HI = 0x0c,
128 PORT_IRQ_STAT = 0x10,
129 PORT_IRQ_MASK = 0x14,
130 PORT_CMD = 0x18,
131 PORT_TFDATA = 0x20,
132 PORT_SIG = 0x24,
133 PORT_CMD_ISSUE = 0x38,
134 PORT_SCR_STAT = 0x28,
135 PORT_SCR_CTL = 0x2c,
136 PORT_SCR_ERR = 0x30,
137 PORT_SCR_ACT = 0x34,
138 PORT_SCR_NTF = 0x3c,
139 PORT_FBS = 0x40,
140 PORT_DEVSLP = 0x44,
141
142
143 PORT_IRQ_COLD_PRES = (1 << 31),
144 PORT_IRQ_TF_ERR = (1 << 30),
145 PORT_IRQ_HBUS_ERR = (1 << 29),
146 PORT_IRQ_HBUS_DATA_ERR = (1 << 28),
147 PORT_IRQ_IF_ERR = (1 << 27),
148 PORT_IRQ_IF_NONFATAL = (1 << 26),
149 PORT_IRQ_OVERFLOW = (1 << 24),
150 PORT_IRQ_BAD_PMP = (1 << 23),
151
152 PORT_IRQ_PHYRDY = (1 << 22),
153 PORT_IRQ_DEV_ILCK = (1 << 7),
154 PORT_IRQ_CONNECT = (1 << 6),
155 PORT_IRQ_SG_DONE = (1 << 5),
156 PORT_IRQ_UNK_FIS = (1 << 4),
157 PORT_IRQ_SDB_FIS = (1 << 3),
158 PORT_IRQ_DMAS_FIS = (1 << 2),
159 PORT_IRQ_PIOS_FIS = (1 << 1),
160 PORT_IRQ_D2H_REG_FIS = (1 << 0),
161
162 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
163 PORT_IRQ_IF_ERR |
164 PORT_IRQ_CONNECT |
165 PORT_IRQ_PHYRDY |
166 PORT_IRQ_UNK_FIS |
167 PORT_IRQ_BAD_PMP,
168 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
169 PORT_IRQ_TF_ERR |
170 PORT_IRQ_HBUS_DATA_ERR,
171 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
172 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
173 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
174
175
176 PORT_CMD_ASP = (1 << 27),
177 PORT_CMD_ALPE = (1 << 26),
178 PORT_CMD_ATAPI = (1 << 24),
179 PORT_CMD_FBSCP = (1 << 22),
180 PORT_CMD_PMP = (1 << 17),
181 PORT_CMD_LIST_ON = (1 << 15),
182 PORT_CMD_FIS_ON = (1 << 14),
183 PORT_CMD_FIS_RX = (1 << 4),
184 PORT_CMD_CLO = (1 << 3),
185 PORT_CMD_POWER_ON = (1 << 2),
186 PORT_CMD_SPIN_UP = (1 << 1),
187 PORT_CMD_START = (1 << 0),
188
189 PORT_CMD_ICC_MASK = (0xf << 28),
190 PORT_CMD_ICC_ACTIVE = (0x1 << 28),
191 PORT_CMD_ICC_PARTIAL = (0x2 << 28),
192 PORT_CMD_ICC_SLUMBER = (0x6 << 28),
193
194
195 PORT_FBS_DWE_OFFSET = 16,
196 PORT_FBS_ADO_OFFSET = 12,
197 PORT_FBS_DEV_OFFSET = 8,
198 PORT_FBS_DEV_MASK = (0xf << PORT_FBS_DEV_OFFSET),
199 PORT_FBS_SDE = (1 << 2),
200 PORT_FBS_DEC = (1 << 1),
201 PORT_FBS_EN = (1 << 0),
202
203
204 PORT_DEVSLP_DM_OFFSET = 25,
205 PORT_DEVSLP_DM_MASK = (0xf << 25),
206 PORT_DEVSLP_DITO_OFFSET = 15,
207 PORT_DEVSLP_MDAT_OFFSET = 10,
208 PORT_DEVSLP_DETO_OFFSET = 2,
209 PORT_DEVSLP_DSP = (1 << 1),
210 PORT_DEVSLP_ADSE = (1 << 0),
211
212
213
214#define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
215
216 AHCI_HFLAG_NO_NCQ = (1 << 0),
217 AHCI_HFLAG_IGN_IRQ_IF_ERR = (1 << 1),
218 AHCI_HFLAG_IGN_SERR_INTERNAL = (1 << 2),
219 AHCI_HFLAG_32BIT_ONLY = (1 << 3),
220 AHCI_HFLAG_MV_PATA = (1 << 4),
221 AHCI_HFLAG_NO_MSI = (1 << 5),
222 AHCI_HFLAG_NO_PMP = (1 << 6),
223 AHCI_HFLAG_SECT255 = (1 << 8),
224 AHCI_HFLAG_YES_NCQ = (1 << 9),
225 AHCI_HFLAG_NO_SUSPEND = (1 << 10),
226 AHCI_HFLAG_SRST_TOUT_IS_OFFLINE = (1 << 11),
227
228 AHCI_HFLAG_NO_SNTF = (1 << 12),
229 AHCI_HFLAG_NO_FPDMA_AA = (1 << 13),
230 AHCI_HFLAG_YES_FBS = (1 << 14),
231 AHCI_HFLAG_DELAY_ENGINE = (1 << 15),
232
233
234 AHCI_HFLAG_MULTI_MSI = (1 << 16),
235
236
237
238 AHCI_FLAG_COMMON = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
239 ATA_FLAG_ACPI_SATA | ATA_FLAG_AN,
240
241 ICH_MAP = 0x90,
242
243
244 EM_MAX_SLOTS = 8,
245 EM_MAX_RETRY = 5,
246
247
248 EM_CTL_RST = (1 << 9),
249 EM_CTL_TM = (1 << 8),
250 EM_CTL_MR = (1 << 0),
251 EM_CTL_ALHD = (1 << 26),
252 EM_CTL_XMT = (1 << 25),
253 EM_CTL_SMB = (1 << 24),
254 EM_CTL_SGPIO = (1 << 19),
255 EM_CTL_SES = (1 << 18),
256 EM_CTL_SAFTE = (1 << 17),
257 EM_CTL_LED = (1 << 16),
258
259
260 EM_MSG_TYPE_LED = (1 << 0),
261 EM_MSG_TYPE_SAFTE = (1 << 1),
262 EM_MSG_TYPE_SES2 = (1 << 2),
263 EM_MSG_TYPE_SGPIO = (1 << 3),
264};
265
266struct ahci_cmd_hdr {
267 __le32 opts;
268 __le32 status;
269 __le32 tbl_addr;
270 __le32 tbl_addr_hi;
271 __le32 reserved[4];
272};
273
274struct ahci_sg {
275 __le32 addr;
276 __le32 addr_hi;
277 __le32 reserved;
278 __le32 flags_size;
279};
280
281struct ahci_em_priv {
282 enum sw_activity blink_policy;
283 struct timer_list timer;
284 unsigned long saved_activity;
285 unsigned long activity;
286 unsigned long led_state;
287};
288
289struct ahci_port_priv {
290 struct ata_link *active_link;
291 struct ahci_cmd_hdr *cmd_slot;
292 dma_addr_t cmd_slot_dma;
293 void *cmd_tbl;
294 dma_addr_t cmd_tbl_dma;
295 void *rx_fis;
296 dma_addr_t rx_fis_dma;
297
298 unsigned int ncq_saw_d2h:1;
299 unsigned int ncq_saw_dmas:1;
300 unsigned int ncq_saw_sdb:1;
301 u32 intr_status;
302 spinlock_t lock;
303 u32 intr_mask;
304 bool fbs_supported;
305 bool fbs_enabled;
306 int fbs_last_dev;
307
308 struct ahci_em_priv em_priv[EM_MAX_SLOTS];
309 char *irq_desc;
310};
311
312struct ahci_host_priv {
313 void __iomem * mmio;
314 unsigned int flags;
315 u32 cap;
316 u32 cap2;
317 u32 port_map;
318 u32 saved_cap;
319 u32 saved_cap2;
320 u32 saved_port_map;
321 u32 em_loc;
322 u32 em_buf_sz;
323 u32 em_msg_type;
324 struct clk *clk;
325 void *plat_data;
326};
327
328extern int ahci_ignore_sss;
329
330extern struct device_attribute *ahci_shost_attrs[];
331extern struct device_attribute *ahci_sdev_attrs[];
332
333#define AHCI_SHT(drv_name) \
334 ATA_NCQ_SHT(drv_name), \
335 .can_queue = AHCI_MAX_CMDS - 1, \
336 .sg_tablesize = AHCI_MAX_SG, \
337 .dma_boundary = AHCI_DMA_BOUNDARY, \
338 .shost_attrs = ahci_shost_attrs, \
339 .sdev_attrs = ahci_sdev_attrs
340
341extern struct ata_port_operations ahci_ops;
342extern struct ata_port_operations ahci_pmp_retry_srst_ops;
343
344unsigned int ahci_dev_classify(struct ata_port *ap);
345void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
346 u32 opts);
347void ahci_save_initial_config(struct device *dev,
348 struct ahci_host_priv *hpriv,
349 unsigned int force_port_map,
350 unsigned int mask_port_map);
351void ahci_init_controller(struct ata_host *host);
352int ahci_reset_controller(struct ata_host *host);
353
354int ahci_do_softreset(struct ata_link *link, unsigned int *class,
355 int pmp, unsigned long deadline,
356 int (*check_ready)(struct ata_link *link));
357
358int ahci_stop_engine(struct ata_port *ap);
359void ahci_start_engine(struct ata_port *ap);
360int ahci_check_ready(struct ata_link *link);
361int ahci_kick_engine(struct ata_port *ap);
362int ahci_port_resume(struct ata_port *ap);
363void ahci_set_em_messages(struct ahci_host_priv *hpriv,
364 struct ata_port_info *pi);
365int ahci_reset_em(struct ata_host *host);
366irqreturn_t ahci_interrupt(int irq, void *dev_instance);
367irqreturn_t ahci_hw_interrupt(int irq, void *dev_instance);
368irqreturn_t ahci_thread_fn(int irq, void *dev_instance);
369void ahci_print_info(struct ata_host *host, const char *scc_s);
370int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis);
371
372static inline void __iomem *__ahci_port_base(struct ata_host *host,
373 unsigned int port_no)
374{
375 struct ahci_host_priv *hpriv = host->private_data;
376 void __iomem *mmio = hpriv->mmio;
377
378 return mmio + 0x100 + (port_no * 0x80);
379}
380
381static inline void __iomem *ahci_port_base(struct ata_port *ap)
382{
383 return __ahci_port_base(ap->host, ap->port_no);
384}
385
386static inline int ahci_nr_ports(u32 cap)
387{
388 return (cap & 0x1f) + 1;
389}
390
391#endif
392