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37#include <linux/kernel.h>
38#include <linux/module.h>
39#include <linux/pci.h>
40#include <linux/init.h>
41#include <linux/blkdev.h>
42#include <linux/delay.h>
43#include <scsi/scsi_host.h>
44#include <linux/libata.h>
45
46#define DRV_NAME "pata_ninja32"
47#define DRV_VERSION "0.1.5"
48
49
50
51
52
53
54
55
56
57
58
59static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev)
60{
61 static u16 pio_timing[5] = {
62 0xd6, 0x85, 0x44, 0x33, 0x13
63 };
64 iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0],
65 ap->ioaddr.bmdma_addr + 0x1f);
66 ap->private_data = adev;
67}
68
69
70static void ninja32_dev_select(struct ata_port *ap, unsigned int device)
71{
72 struct ata_device *adev = &ap->link.device[device];
73 if (ap->private_data != adev) {
74 iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f);
75 ata_sff_dev_select(ap, device);
76 ninja32_set_piomode(ap, adev);
77 }
78}
79
80static struct scsi_host_template ninja32_sht = {
81 ATA_BMDMA_SHT(DRV_NAME),
82};
83
84static struct ata_port_operations ninja32_port_ops = {
85 .inherits = &ata_bmdma_port_ops,
86 .sff_dev_select = ninja32_dev_select,
87 .cable_detect = ata_cable_40wire,
88 .set_piomode = ninja32_set_piomode,
89 .sff_data_xfer = ata_sff_data_xfer32
90};
91
92static void ninja32_program(void __iomem *base)
93{
94 iowrite8(0x05, base + 0x01);
95 iowrite8(0xBE, base + 0x02);
96 iowrite8(0x01, base + 0x03);
97 iowrite8(0x20, base + 0x04);
98 iowrite8(0x8f, base + 0x05);
99 iowrite8(0xa4, base + 0x1c);
100 iowrite8(0x83, base + 0x1d);
101}
102
103static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
104{
105 struct ata_host *host;
106 struct ata_port *ap;
107 void __iomem *base;
108 int rc;
109
110 host = ata_host_alloc(&dev->dev, 1);
111 if (!host)
112 return -ENOMEM;
113 ap = host->ports[0];
114
115
116 rc = pcim_enable_device(dev);
117 if (rc)
118 return rc;
119 rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME);
120 if (rc == -EBUSY)
121 pcim_pin_device(dev);
122 if (rc)
123 return rc;
124
125 host->iomap = pcim_iomap_table(dev);
126 rc = pci_set_dma_mask(dev, ATA_DMA_MASK);
127 if (rc)
128 return rc;
129 rc = pci_set_consistent_dma_mask(dev, ATA_DMA_MASK);
130 if (rc)
131 return rc;
132 pci_set_master(dev);
133
134
135
136 base = host->iomap[0];
137 if (!base)
138 return -ENOMEM;
139 ap->ops = &ninja32_port_ops;
140 ap->pio_mask = ATA_PIO4;
141 ap->flags |= ATA_FLAG_SLAVE_POSS;
142
143 ap->ioaddr.cmd_addr = base + 0x10;
144 ap->ioaddr.ctl_addr = base + 0x1E;
145 ap->ioaddr.altstatus_addr = base + 0x1E;
146 ap->ioaddr.bmdma_addr = base;
147 ata_sff_std_ports(&ap->ioaddr);
148 ap->pflags = ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
149
150 ninja32_program(base);
151
152 return ata_host_activate(host, dev->irq, ata_bmdma_interrupt,
153 IRQF_SHARED, &ninja32_sht);
154}
155
156#ifdef CONFIG_PM
157
158static int ninja32_reinit_one(struct pci_dev *pdev)
159{
160 struct ata_host *host = pci_get_drvdata(pdev);
161 int rc;
162
163 rc = ata_pci_device_do_resume(pdev);
164 if (rc)
165 return rc;
166 ninja32_program(host->iomap[0]);
167 ata_host_resume(host);
168 return 0;
169}
170#endif
171
172static const struct pci_device_id ninja32[] = {
173 { 0x10FC, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
174 { 0x1145, 0x8008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
175 { 0x1145, 0xf008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
176 { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
177 { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
178 { 0x1145, 0xf02C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
179 { },
180};
181
182static struct pci_driver ninja32_pci_driver = {
183 .name = DRV_NAME,
184 .id_table = ninja32,
185 .probe = ninja32_init_one,
186 .remove = ata_pci_remove_one,
187#ifdef CONFIG_PM
188 .suspend = ata_pci_device_suspend,
189 .resume = ninja32_reinit_one,
190#endif
191};
192
193module_pci_driver(ninja32_pci_driver);
194
195MODULE_AUTHOR("Alan Cox");
196MODULE_DESCRIPTION("low-level driver for Ninja32 ATA");
197MODULE_LICENSE("GPL");
198MODULE_DEVICE_TABLE(pci, ninja32);
199MODULE_VERSION(DRV_VERSION);
200