/*
 * Copyright © 2006-2007 Intel Corporation
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *      Eric Anholt <eric@anholt.net>
 */

#include <linux/dmi.h>
#include <linux/module.h>
#include <linux/input.h>
#include <linux/i2c.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/vgaarb.h>
#include <drm/drm_edid.h>
#include <drm/drmP.h>
#include "intel_drv.h"
#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "i915_trace.h"
#include <drm/drm_dp_helper.h>
#include <drm/drm_crtc_helper.h>
#include <linux/dma_remapping.h>

bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
static void intel_increase_pllclock(struct drm_crtc *crtc);
static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);

static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
                                struct intel_crtc_config *pipe_config);
static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
                                    struct intel_crtc_config *pipe_config);

static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
                          int x, int y, struct drm_framebuffer *old_fb);


typedef struct {
        int     min, max;
} intel_range_t;

typedef struct {
        int     dot_limit;
        int     p2_slow, p2_fast;
} intel_p2_t;

typedef struct intel_limit intel_limit_t;
struct intel_limit {
        intel_range_t   dot, vco, n, m, m1, m2, p, p1;
        intel_p2_t          p2;
};

/* FDI */
#define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */

int
intel_pch_rawclk(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;

        WARN_ON(!HAS_PCH_SPLIT(dev));

        return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
}

static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device *dev)
{
        if (IS_GEN5(dev)) {
                struct drm_i915_private *dev_priv = dev->dev_private;
                return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
        } else
                return 27;
}

static const intel_limit_t intel_limits_i8xx_dac = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 930000, .max = 1400000 },
        .n = { .min = 3, .max = 16 },
        .m = { .min = 96, .max = 140 },
        .m1 = { .min = 18, .max = 26 },
        .m2 = { .min = 6, .max = 16 },
        .p = { .min = 4, .max = 128 },
        .p1 = { .min = 2, .max = 33 },
        .p2 = { .dot_limit = 165000,
                .p2_slow = 4, .p2_fast = 2 },
};

static const intel_limit_t intel_limits_i8xx_dvo = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 930000, .max = 1400000 },
        .n = { .min = 3, .max = 16 },
        .m = { .min = 96, .max = 140 },
        .m1 = { .min = 18, .max = 26 },
        .m2 = { .min = 6, .max = 16 },
        .p = { .min = 4, .max = 128 },
        .p1 = { .min = 2, .max = 33 },
        .p2 = { .dot_limit = 165000,
                .p2_slow = 4, .p2_fast = 4 },
};

static const intel_limit_t intel_limits_i8xx_lvds = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 930000, .max = 1400000 },
        .n = { .min = 3, .max = 16 },
        .m = { .min = 96, .max = 140 },
        .m1 = { .min = 18, .max = 26 },
        .m2 = { .min = 6, .max = 16 },
        .p = { .min = 4, .max = 128 },
        .p1 = { .min = 1, .max = 6 },
        .p2 = { .dot_limit = 165000,
                .p2_slow = 14, .p2_fast = 7 },
};

static const intel_limit_t intel_limits_i9xx_sdvo = {
        .dot = { .min = 20000, .max = 400000 },
        .vco = { .min = 1400000, .max = 2800000 },
        .n = { .min = 1, .max = 6 },
        .m = { .min = 70, .max = 120 },
        .m1 = { .min = 8, .max = 18 },
        .m2 = { .min = 3, .max = 7 },
        .p = { .min = 5, .max = 80 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 200000,
                .p2_slow = 10, .p2_fast = 5 },
};

static const intel_limit_t intel_limits_i9xx_lvds = {
        .dot = { .min = 20000, .max = 400000 },
        .vco = { .min = 1400000, .max = 2800000 },
        .n = { .min = 1, .max = 6 },
        .m = { .min = 70, .max = 120 },
        .m1 = { .min = 8, .max = 18 },
        .m2 = { .min = 3, .max = 7 },
        .p = { .min = 7, .max = 98 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 112000,
                .p2_slow = 14, .p2_fast = 7 },
};


static const intel_limit_t intel_limits_g4x_sdvo = {
        .dot = { .min = 25000, .max = 270000 },
        .vco = { .min = 1750000, .max = 3500000},
        .n = { .min = 1, .max = 4 },
        .m = { .min = 104, .max = 138 },
        .m1 = { .min = 17, .max = 23 },
        .m2 = { .min = 5, .max = 11 },
        .p = { .min = 10, .max = 30 },
        .p1 = { .min = 1, .max = 3},
        .p2 = { .dot_limit = 270000,
                .p2_slow = 10,
                .p2_fast = 10
        },
};

static const intel_limit_t intel_limits_g4x_hdmi = {
        .dot = { .min = 22000, .max = 400000 },
        .vco = { .min = 1750000, .max = 3500000},
        .n = { .min = 1, .max = 4 },
        .m = { .min = 104, .max = 138 },
        .m1 = { .min = 16, .max = 23 },
        .m2 = { .min = 5, .max = 11 },
        .p = { .min = 5, .max = 80 },
        .p1 = { .min = 1, .max = 8},
        .p2 = { .dot_limit = 165000,
                .p2_slow = 10, .p2_fast = 5 },
};

static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
        .dot = { .min = 20000, .max = 115000 },
        .vco = { .min = 1750000, .max = 3500000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 104, .max = 138 },
        .m1 = { .min = 17, .max = 23 },
        .m2 = { .min = 5, .max = 11 },
        .p = { .min = 28, .max = 112 },
        .p1 = { .min = 2, .max = 8 },
        .p2 = { .dot_limit = 0,
                .p2_slow = 14, .p2_fast = 14
        },
};

static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
        .dot = { .min = 80000, .max = 224000 },
        .vco = { .min = 1750000, .max = 3500000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 104, .max = 138 },
        .m1 = { .min = 17, .max = 23 },
        .m2 = { .min = 5, .max = 11 },
        .p = { .min = 14, .max = 42 },
        .p1 = { .min = 2, .max = 6 },
        .p2 = { .dot_limit = 0,
                .p2_slow = 7, .p2_fast = 7
        },
};

static const intel_limit_t intel_limits_pineview_sdvo = {
        .dot = { .min = 20000, .max = 400000},
        .vco = { .min = 1700000, .max = 3500000 },
        /* Pineview's Ncounter is a ring counter */
        .n = { .min = 3, .max = 6 },
        .m = { .min = 2, .max = 256 },
        /* Pineview only has one combined m divider, which we treat as m2. */
        .m1 = { .min = 0, .max = 0 },
        .m2 = { .min = 0, .max = 254 },
        .p = { .min = 5, .max = 80 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 200000,
                .p2_slow = 10, .p2_fast = 5 },
};

static const intel_limit_t intel_limits_pineview_lvds = {
        .dot = { .min = 20000, .max = 400000 },
        .vco = { .min = 1700000, .max = 3500000 },
        .n = { .min = 3, .max = 6 },
        .m = { .min = 2, .max = 256 },
        .m1 = { .min = 0, .max = 0 },
        .m2 = { .min = 0, .max = 254 },
        .p = { .min = 7, .max = 112 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 112000,
                .p2_slow = 14, .p2_fast = 14 },
};

/* Ironlake / Sandybridge
 *
 * We calculate clock using (register_value + 2) for N/M1/M2, so here
 * the range value for them is (actual_value - 2).
 */
static const intel_limit_t intel_limits_ironlake_dac = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 5 },
        .m = { .min = 79, .max = 127 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 5, .max = 80 },
        .p1 = { .min = 1, .max = 8 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 10, .p2_fast = 5 },
};

static const intel_limit_t intel_limits_ironlake_single_lvds = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 79, .max = 118 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 28, .max = 112 },
        .p1 = { .min = 2, .max = 8 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 14, .p2_fast = 14 },
};

static const intel_limit_t intel_limits_ironlake_dual_lvds = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 79, .max = 127 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 14, .max = 56 },
        .p1 = { .min = 2, .max = 8 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 7, .p2_fast = 7 },
};

/* LVDS 100mhz refclk limits. */
static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 2 },
        .m = { .min = 79, .max = 126 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 28, .max = 112 },
        .p1 = { .min = 2, .max = 8 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 14, .p2_fast = 14 },
};

static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
        .dot = { .min = 25000, .max = 350000 },
        .vco = { .min = 1760000, .max = 3510000 },
        .n = { .min = 1, .max = 3 },
        .m = { .min = 79, .max = 126 },
        .m1 = { .min = 12, .max = 22 },
        .m2 = { .min = 5, .max = 9 },
        .p = { .min = 14, .max = 42 },
        .p1 = { .min = 2, .max = 6 },
        .p2 = { .dot_limit = 225000,
                .p2_slow = 7, .p2_fast = 7 },
};

static const intel_limit_t intel_limits_vlv_dac = {
        .dot = { .min = 25000, .max = 270000 },
        .vco = { .min = 4000000, .max = 6000000 },
        .n = { .min = 1, .max = 7 },
        .m = { .min = 22, .max = 450 }, /* guess */
        .m1 = { .min = 2, .max = 3 },
        .m2 = { .min = 11, .max = 156 },
        .p = { .min = 10, .max = 30 },
        .p1 = { .min = 1, .max = 3 },
        .p2 = { .dot_limit = 270000,
                .p2_slow = 2, .p2_fast = 20 },
};

static const intel_limit_t intel_limits_vlv_hdmi = {
        .dot = { .min = 25000, .max = 270000 },
        .vco = { .min = 4000000, .max = 6000000 },
        .n = { .min = 1, .max = 7 },
        .m = { .min = 60, .max = 300 }, /* guess */
        .m1 = { .min = 2, .max = 3 },
        .m2 = { .min = 11, .max = 156 },
        .p = { .min = 10, .max = 30 },
        .p1 = { .min = 2, .max = 3 },
        .p2 = { .dot_limit = 270000,
                .p2_slow = 2, .p2_fast = 20 },
};

static const intel_limit_t intel_limits_vlv_dp = {
        .dot = { .min = 25000, .max = 270000 },
        .vco = { .min = 4000000, .max = 6000000 },
        .n = { .min = 1, .max = 7 },
        .m = { .min = 22, .max = 450 },
        .m1 = { .min = 2, .max = 3 },
        .m2 = { .min = 11, .max = 156 },
        .p = { .min = 10, .max = 30 },
        .p1 = { .min = 1, .max = 3 },
        .p2 = { .dot_limit = 270000,
                .p2_slow = 2, .p2_fast = 20 },
};

static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
                                                int refclk)
{
        struct drm_device *dev = crtc->dev;
        const intel_limit_t *limit;

        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
                if (intel_is_dual_link_lvds(dev)) {
                        if (refclk == 100000)
                                limit = &intel_limits_ironlake_dual_lvds_100m;
                        else
                                limit = &intel_limits_ironlake_dual_lvds;
                } else {
                        if (refclk == 100000)
                                limit = &intel_limits_ironlake_single_lvds_100m;
                        else
                                limit = &intel_limits_ironlake_single_lvds;
                }
        } else
                limit = &intel_limits_ironlake_dac;

        return limit;
}

static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        const intel_limit_t *limit;

        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
                if (intel_is_dual_link_lvds(dev))
                        limit = &intel_limits_g4x_dual_channel_lvds;
                else
                        limit = &intel_limits_g4x_single_channel_lvds;
        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
                   intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
                limit = &intel_limits_g4x_hdmi;
        } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
                limit = &intel_limits_g4x_sdvo;
        } else /* The option is for other outputs */
                limit = &intel_limits_i9xx_sdvo;

        return limit;
}

static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
{
        struct drm_device *dev = crtc->dev;
        const intel_limit_t *limit;

        if (HAS_PCH_SPLIT(dev))
                limit = intel_ironlake_limit(crtc, refclk);
        else if (IS_G4X(dev)) {
                limit = intel_g4x_limit(crtc);
        } else if (IS_PINEVIEW(dev)) {
                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
                        limit = &intel_limits_pineview_lvds;
                else
                        limit = &intel_limits_pineview_sdvo;
        } else if (IS_VALLEYVIEW(dev)) {
                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
                        limit = &intel_limits_vlv_dac;
                else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
                        limit = &intel_limits_vlv_hdmi;
                else
                        limit = &intel_limits_vlv_dp;
        } else if (!IS_GEN2(dev)) {
                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
                        limit = &intel_limits_i9xx_lvds;
                else
                        limit = &intel_limits_i9xx_sdvo;
        } else {
                if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
                        limit = &intel_limits_i8xx_lvds;
                else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
                        limit = &intel_limits_i8xx_dvo;
                else
                        limit = &intel_limits_i8xx_dac;
        }
        return limit;
}

/* m1 is reserved as 0 in Pineview, n is a ring counter */
static void pineview_clock(int refclk, intel_clock_t *clock)
{
        clock->m = clock->m2 + 2;
        clock->p = clock->p1 * clock->p2;
        clock->vco = refclk * clock->m / clock->n;
        clock->dot = clock->vco / clock->p;
}

static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
{
        return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
}

static void i9xx_clock(int refclk, intel_clock_t *clock)
{
        clock->m = i9xx_dpll_compute_m(clock);
        clock->p = clock->p1 * clock->p2;
        clock->vco = refclk * clock->m / (clock->n + 2);
        clock->dot = clock->vco / clock->p;
}

/**
 * Returns whether any output on the specified pipe is of the specified type
 */
bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
{
        struct drm_device *dev = crtc->dev;
        struct intel_encoder *encoder;

        for_each_encoder_on_crtc(dev, crtc, encoder)
                if (encoder->type == type)
                        return true;

        return false;
}

#define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
/**
 * Returns whether the given set of divisors are valid for a given refclk with
 * the given connectors.
 */

static bool intel_PLL_is_valid(struct drm_device *dev,
                               const intel_limit_t *limit,
                               const intel_clock_t *clock)
{
        if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
                INTELPllInvalid("p1 out of range\n");
        if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
                INTELPllInvalid("p out of range\n");
        if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
                INTELPllInvalid("m2 out of range\n");
        if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
                INTELPllInvalid("m1 out of range\n");
        if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
                INTELPllInvalid("m1 <= m2\n");
        if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
                INTELPllInvalid("m out of range\n");
        if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
                INTELPllInvalid("n out of range\n");
        if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
                INTELPllInvalid("vco out of range\n");
        /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
         * connector, etc., rather than just a single range.
         */
        if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
                INTELPllInvalid("dot out of range\n");

        return true;
}

static bool
i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
                    int target, int refclk, intel_clock_t *match_clock,
                    intel_clock_t *best_clock)
{
        struct drm_device *dev = crtc->dev;
        intel_clock_t clock;
        int err = target;

        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
                /*
                 * For LVDS just rely on its current settings for dual-channel.
                 * We haven't figured out how to reliably set up different
                 * single/dual channel state, if we even can.
                 */
                if (intel_is_dual_link_lvds(dev))
                        clock.p2 = limit->p2.p2_fast;
                else
                        clock.p2 = limit->p2.p2_slow;
        } else {
                if (target < limit->p2.dot_limit)
                        clock.p2 = limit->p2.p2_slow;
                else
                        clock.p2 = limit->p2.p2_fast;
        }

        memset(best_clock, 0, sizeof(*best_clock));

        for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
             clock.m1++) {
                for (clock.m2 = limit->m2.min;
                     clock.m2 <= limit->m2.max; clock.m2++) {
                        if (clock.m2 >= clock.m1)
                                break;
                        for (clock.n = limit->n.min;
                             clock.n <= limit->n.max; clock.n++) {
                                for (clock.p1 = limit->p1.min;
                                        clock.p1 <= limit->p1.max; clock.p1++) {
                                        int this_err;

                                        i9xx_clock(refclk, &clock);
                                        if (!intel_PLL_is_valid(dev, limit,
                                                                &clock))
                                                continue;
                                        if (match_clock &&
                                            clock.p != match_clock->p)
                                                continue;

                                        this_err = abs(clock.dot - target);
                                        if (this_err < err) {
                                                *best_clock = clock;
                                                err = this_err;
                                        }
                                }
                        }
                }
        }

        return (err != target);
}

static bool
pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
                   int target, int refclk, intel_clock_t *match_clock,
                   intel_clock_t *best_clock)
{
        struct drm_device *dev = crtc->dev;
        intel_clock_t clock;
        int err = target;

        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
                /*
                 * For LVDS just rely on its current settings for dual-channel.
                 * We haven't figured out how to reliably set up different
                 * single/dual channel state, if we even can.
                 */
                if (intel_is_dual_link_lvds(dev))
                        clock.p2 = limit->p2.p2_fast;
                else
                        clock.p2 = limit->p2.p2_slow;
        } else {
                if (target < limit->p2.dot_limit)
                        clock.p2 = limit->p2.p2_slow;
                else
                        clock.p2 = limit->p2.p2_fast;
        }

        memset(best_clock, 0, sizeof(*best_clock));

        for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
             clock.m1++) {
                for (clock.m2 = limit->m2.min;
                     clock.m2 <= limit->m2.max; clock.m2++) {
                        for (clock.n = limit->n.min;
                             clock.n <= limit->n.max; clock.n++) {
                                for (clock.p1 = limit->p1.min;
                                        clock.p1 <= limit->p1.max; clock.p1++) {
                                        int this_err;

                                        pineview_clock(refclk, &clock);
                                        if (!intel_PLL_is_valid(dev, limit,
                                                                &clock))
                                                continue;
                                        if (match_clock &&
                                            clock.p != match_clock->p)
                                                continue;

                                        this_err = abs(clock.dot - target);
                                        if (this_err < err) {
                                                *best_clock = clock;
                                                err = this_err;
                                        }
                                }
                        }
                }
        }

        return (err != target);
}

static bool
g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
                   int target, int refclk, intel_clock_t *match_clock,
                   intel_clock_t *best_clock)
{
        struct drm_device *dev = crtc->dev;
        intel_clock_t clock;
        int max_n;
        bool found;
        /* approximately equals target * 0.00585 */
        int err_most = (target >> 8) + (target >> 9);
        found = false;

        if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
                if (intel_is_dual_link_lvds(dev))
                        clock.p2 = limit->p2.p2_fast;
                else
                        clock.p2 = limit->p2.p2_slow;
        } else {
                if (target < limit->p2.dot_limit)
                        clock.p2 = limit->p2.p2_slow;
                else
                        clock.p2 = limit->p2.p2_fast;
        }

        memset(best_clock, 0, sizeof(*best_clock));
        max_n = limit->n.max;
        /* based on hardware requirement, prefer smaller n to precision */
        for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
                /* based on hardware requirement, prefere larger m1,m2 */
                for (clock.m1 = limit->m1.max;
                     clock.m1 >= limit->m1.min; clock.m1--) {
                        for (clock.m2 = limit->m2.max;
                             clock.m2 >= limit->m2.min; clock.m2--) {
                                for (clock.p1 = limit->p1.max;
                                     clock.p1 >= limit->p1.min; clock.p1--) {
                                        int this_err;

                                        i9xx_clock(refclk, &clock);
                                        if (!intel_PLL_is_valid(dev, limit,
                                                                &clock))
                                                continue;

                                        this_err = abs(clock.dot - target);
                                        if (this_err < err_most) {
                                                *best_clock = clock;
                                                err_most = this_err;
                                                max_n = clock.n;
                                                found = true;
                                        }
                                }
                        }
                }
        }
        return found;
}

static bool
vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
                   int target, int refclk, intel_clock_t *match_clock,
                   intel_clock_t *best_clock)
{
        u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
        u32 m, n, fastclk;
        u32 updrate, minupdate, p;
        unsigned long bestppm, ppm, absppm;
        int dotclk, flag;

        flag = 0;
        dotclk = target * 1000;
        bestppm = 1000000;
        ppm = absppm = 0;
        fastclk = dotclk / (2*100);
        updrate = 0;
        minupdate = 19200;
        n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
        bestm1 = bestm2 = bestp1 = bestp2 = 0;

        /* based on hardware requirement, prefer smaller n to precision */
        for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
                updrate = refclk / n;
                for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
                        for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
                                if (p2 > 10)
                                        p2 = p2 - 1;
                                p = p1 * p2;
                                /* based on hardware requirement, prefer bigger m1,m2 values */
                                for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
                                        m2 = (((2*(fastclk * p * n / m1 )) +
                                               refclk) / (2*refclk));
                                        m = m1 * m2;
                                        vco = updrate * m;
                                        if (vco >= limit->vco.min && vco < limit->vco.max) {
                                                ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
                                                absppm = (ppm > 0) ? ppm : (-ppm);
                                                if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
                                                        bestppm = 0;
                                                        flag = 1;
                                                }
                                                if (absppm < bestppm - 10) {
                                                        bestppm = absppm;
                                                        flag = 1;
                                                }
                                                if (flag) {
                                                        bestn = n;
                                                        bestm1 = m1;
                                                        bestm2 = m2;
                                                        bestp1 = p1;
                                                        bestp2 = p2;
                                                        flag = 0;
                                                }
                                        }
                                }
                        }
                }
        }
        best_clock->n = bestn;
        best_clock->m1 = bestm1;
        best_clock->m2 = bestm2;
        best_clock->p1 = bestp1;
        best_clock->p2 = bestp2;

        return true;
}

enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
                                             enum pipe pipe)
{
        struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

        return intel_crtc->config.cpu_transcoder;
}

static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 frame, frame_reg = PIPEFRAME(pipe);

        frame = I915_READ(frame_reg);

        if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
                DRM_DEBUG_KMS("vblank wait timed out\n");
}

/**
 * intel_wait_for_vblank - wait for vblank on a given pipe
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * Wait for vblank to occur on a given pipe.  Needed for various bits of
 * mode setting code.
 */
void intel_wait_for_vblank(struct drm_device *dev, int pipe)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        int pipestat_reg = PIPESTAT(pipe);

        if (INTEL_INFO(dev)->gen >= 5) {
                ironlake_wait_for_vblank(dev, pipe);
                return;
        }

        /* Clear existing vblank status. Note this will clear any other
         * sticky status fields as well.
         *
         * This races with i915_driver_irq_handler() with the result
         * that either function could miss a vblank event.  Here it is not
         * fatal, as we will either wait upon the next vblank interrupt or
         * timeout.  Generally speaking intel_wait_for_vblank() is only
         * called during modeset at which time the GPU should be idle and
         * should *not* be performing page flips and thus not waiting on
         * vblanks...
         * Currently, the result of us stealing a vblank from the irq
         * handler is that a single frame will be skipped during swapbuffers.
         */
        I915_WRITE(pipestat_reg,
                   I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);

        /* Wait for vblank interrupt bit to set */
        if (wait_for(I915_READ(pipestat_reg) &
                     PIPE_VBLANK_INTERRUPT_STATUS,
                     50))
                DRM_DEBUG_KMS("vblank wait timed out\n");
}

/*
 * intel_wait_for_pipe_off - wait for pipe to turn off
 * @dev: drm device
 * @pipe: pipe to wait for
 *
 * After disabling a pipe, we can't wait for vblank in the usual way,
 * spinning on the vblank interrupt status bit, since we won't actually
 * see an interrupt when the pipe is disabled.
 *
 * On Gen4 and above:
 *   wait for the pipe register state bit to turn off
 *
 * Otherwise:
 *   wait for the display line value to settle (it usually
 *   ends up stopping at the start of the next frame).
 *
 */
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
                                                                      pipe);

        if (INTEL_INFO(dev)->gen >= 4) {
                int reg = PIPECONF(cpu_transcoder);

                /* Wait for the Pipe State to go off */
                if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
                             100))
                        WARN(1, "pipe_off wait timed out\n");
        } else {
                u32 last_line, line_mask;
                int reg = PIPEDSL(pipe);
                unsigned long timeout = jiffies + msecs_to_jiffies(100);

                if (IS_GEN2(dev))
                        line_mask = DSL_LINEMASK_GEN2;
                else
                        line_mask = DSL_LINEMASK_GEN3;

                /* Wait for the display line to settle */
                do {
                        last_line = I915_READ(reg) & line_mask;
                        mdelay(5);
                } while (((I915_READ(reg) & line_mask) != last_line) &&
                         time_after(timeout, jiffies));
                if (time_after(jiffies, timeout))
                        WARN(1, "pipe_off wait timed out\n");
        }
}

/*
 * ibx_digital_port_connected - is the specified port connected?
 * @dev_priv: i915 private structure
 * @port: the port to test
 *
 * Returns true if @port is connected, false otherwise.
 */
bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
                                struct intel_digital_port *port)
{
        u32 bit;

        if (HAS_PCH_IBX(dev_priv->dev)) {
                switch(port->port) {
                case PORT_B:
                        bit = SDE_PORTB_HOTPLUG;
                        break;
                case PORT_C:
                        bit = SDE_PORTC_HOTPLUG;
                        break;
                case PORT_D:
                        bit = SDE_PORTD_HOTPLUG;
                        break;
                default:
                        return true;
                }
        } else {
                switch(port->port) {
                case PORT_B:
                        bit = SDE_PORTB_HOTPLUG_CPT;
                        break;
                case PORT_C:
                        bit = SDE_PORTC_HOTPLUG_CPT;
                        break;
                case PORT_D:
                        bit = SDE_PORTD_HOTPLUG_CPT;
                        break;
                default:
                        return true;
                }
        }

        return I915_READ(SDEISR) & bit;
}

static const char *state_string(bool enabled)
{
        return enabled ? "on" : "off";
}

/* Only for pre-ILK configs */
void assert_pll(struct drm_i915_private *dev_priv,
                enum pipe pipe, bool state)
{
        int reg;
        u32 val;
        bool cur_state;

        reg = DPLL(pipe);
        val = I915_READ(reg);
        cur_state = !!(val & DPLL_VCO_ENABLE);
        WARN(cur_state != state,
             "PLL state assertion failure (expected %s, current %s)\n",
             state_string(state), state_string(cur_state));
}

struct intel_shared_dpll *
intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;

        if (crtc->config.shared_dpll < 0)
                return NULL;

        return &dev_priv->shared_dplls[crtc->config.shared_dpll];
}

/* For ILK+ */
void assert_shared_dpll(struct drm_i915_private *dev_priv,
                        struct intel_shared_dpll *pll,
                        bool state)
{
        bool cur_state;
        struct intel_dpll_hw_state hw_state;

        if (HAS_PCH_LPT(dev_priv->dev)) {
                DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
                return;
        }

        if (WARN (!pll,
                  "asserting DPLL %s with no DPLL\n", state_string(state)))
                return;

        cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
        WARN(cur_state != state,
             "%s assertion failure (expected %s, current %s)\n",
             pll->name, state_string(state), state_string(cur_state));
}

static void assert_fdi_tx(struct drm_i915_private *dev_priv,
                          enum pipe pipe, bool state)
{
        int reg;
        u32 val;
        bool cur_state;
        enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
                                                                      pipe);

        if (HAS_DDI(dev_priv->dev)) {
                /* DDI does not have a specific FDI_TX register */
                reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
                val = I915_READ(reg);
                cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
        } else {
                reg = FDI_TX_CTL(pipe);
                val = I915_READ(reg);
                cur_state = !!(val & FDI_TX_ENABLE);
        }
        WARN(cur_state != state,
             "FDI TX state assertion failure (expected %s, current %s)\n",
             state_string(state), state_string(cur_state));
}
#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)

static void assert_fdi_rx(struct drm_i915_private *dev_priv,
                          enum pipe pipe, bool state)
{
        int reg;
        u32 val;
        bool cur_state;

        reg = FDI_RX_CTL(pipe);
        val = I915_READ(reg);

        cur_state = !!(val & FDI_RX_ENABLE);
        WARN(cur_state != state,
             "FDI RX state assertion failure (expected %s, current %s)\n",
             state_string(state), state_string(cur_state));
}
#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)

static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
                                      enum pipe pipe)
{
        int reg;
        u32 val;

        /* ILK FDI PLL is always enabled */
        if (dev_priv->info->gen == 5)
                return;

        /* On Haswell, DDI ports are responsible for the FDI PLL setup */
        if (HAS_DDI(dev_priv->dev))
                return;

        reg = FDI_TX_CTL(pipe);
        val = I915_READ(reg);
        WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
}

void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
                       enum pipe pipe, bool state)
{
        int reg;
        u32 val;
        bool cur_state;

        reg = FDI_RX_CTL(pipe);
        val = I915_READ(reg);
        cur_state = !!(val & FDI_RX_PLL_ENABLE);
        WARN(cur_state != state,
             "FDI RX PLL assertion failure (expected %s, current %s)\n",
             state_string(state), state_string(cur_state));
}

static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
                                  enum pipe pipe)
{
        int pp_reg, lvds_reg;
        u32 val;
        enum pipe panel_pipe = PIPE_A;
        bool locked = true;

        if (HAS_PCH_SPLIT(dev_priv->dev)) {
                pp_reg = PCH_PP_CONTROL;
                lvds_reg = PCH_LVDS;
        } else {
                pp_reg = PP_CONTROL;
                lvds_reg = LVDS;
        }

        val = I915_READ(pp_reg);
        if (!(val & PANEL_POWER_ON) ||
            ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
                locked = false;

        if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
                panel_pipe = PIPE_B;

        WARN(panel_pipe == pipe && locked,
             "panel assertion failure, pipe %c regs locked\n",
             pipe_name(pipe));
}

void assert_pipe(struct drm_i915_private *dev_priv,
                 enum pipe pipe, bool state)
{
        int reg;
        u32 val;
        bool cur_state;
        enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
                                                                      pipe);

        /* if we need the pipe A quirk it must be always on */
        if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
                state = true;

        if (!intel_display_power_enabled(dev_priv->dev,
                                POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
                cur_state = false;
        } else {
                reg = PIPECONF(cpu_transcoder);
                val = I915_READ(reg);
                cur_state = !!(val & PIPECONF_ENABLE);
        }

        WARN(cur_state != state,
             "pipe %c assertion failure (expected %s, current %s)\n",
             pipe_name(pipe), state_string(state), state_string(cur_state));
}

static void assert_plane(struct drm_i915_private *dev_priv,
                         enum plane plane, bool state)
{
        int reg;
        u32 val;
        bool cur_state;

        reg = DSPCNTR(plane);
        val = I915_READ(reg);
        cur_state = !!(val & DISPLAY_PLANE_ENABLE);
        WARN(cur_state != state,
             "plane %c assertion failure (expected %s, current %s)\n",
             plane_name(plane), state_string(state), state_string(cur_state));
}

#define assert_plane_enabled(d, p) assert_plane(d, p, true)
#define assert_plane_disabled(d, p) assert_plane(d, p, false)

static void assert_planes_disabled(struct drm_i915_private *dev_priv,
                                   enum pipe pipe)
{
        struct drm_device *dev = dev_priv->dev;
        int reg, i;
        u32 val;
        int cur_pipe;

        /* Primary planes are fixed to pipes on gen4+ */
        if (INTEL_INFO(dev)->gen >= 4) {
                reg = DSPCNTR(pipe);
                val = I915_READ(reg);
                WARN((val & DISPLAY_PLANE_ENABLE),
                     "plane %c assertion failure, should be disabled but not\n",
                     plane_name(pipe));
                return;
        }

        /* Need to check both planes against the pipe */
        for_each_pipe(i) {
                reg = DSPCNTR(i);
                val = I915_READ(reg);
                cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
                        DISPPLANE_SEL_PIPE_SHIFT;
                WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
                     "plane %c assertion failure, should be off on pipe %c but is still active\n",
                     plane_name(i), pipe_name(pipe));
        }
}

static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
                                    enum pipe pipe)
{
        struct drm_device *dev = dev_priv->dev;
        int reg, i;
        u32 val;

        if (IS_VALLEYVIEW(dev)) {
                for (i = 0; i < dev_priv->num_plane; i++) {
                        reg = SPCNTR(pipe, i);
                        val = I915_READ(reg);
                        WARN((val & SP_ENABLE),
                             "sprite %c assertion failure, should be off on pipe %c but is still active\n",
                             sprite_name(pipe, i), pipe_name(pipe));
                }
        } else if (INTEL_INFO(dev)->gen >= 7) {
                reg = SPRCTL(pipe);
                val = I915_READ(reg);
                WARN((val & SPRITE_ENABLE),
                     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
                     plane_name(pipe), pipe_name(pipe));
        } else if (INTEL_INFO(dev)->gen >= 5) {
                reg = DVSCNTR(pipe);
                val = I915_READ(reg);
                WARN((val & DVS_ENABLE),
                     "sprite %c assertion failure, should be off on pipe %c but is still active\n",
                     plane_name(pipe), pipe_name(pipe));
        }
}

static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
{
        u32 val;
        bool enabled;

        if (HAS_PCH_LPT(dev_priv->dev)) {
                DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
                return;
        }

        val = I915_READ(PCH_DREF_CONTROL);
        enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
                            DREF_SUPERSPREAD_SOURCE_MASK));
        WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
}

static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
                                           enum pipe pipe)
{
        int reg;
        u32 val;
        bool enabled;

        reg = PCH_TRANSCONF(pipe);
        val = I915_READ(reg);
        enabled = !!(val & TRANS_ENABLE);
        WARN(enabled,
             "transcoder assertion failed, should be off on pipe %c but is still active\n",
             pipe_name(pipe));
}

static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
                            enum pipe pipe, u32 port_sel, u32 val)
{
        if ((val & DP_PORT_EN) == 0)
                return false;

        if (HAS_PCH_CPT(dev_priv->dev)) {
                u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
                u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
                if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
                        return false;
        } else {
                if ((val & DP_PIPE_MASK) != (pipe << 30))
                        return false;
        }
        return true;
}

static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
                              enum pipe pipe, u32 val)
{
        if ((val & SDVO_ENABLE) == 0)
                return false;

        if (HAS_PCH_CPT(dev_priv->dev)) {
                if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
                        return false;
        } else {
                if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
                        return false;
        }
        return true;
}

static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
                              enum pipe pipe, u32 val)
{
        if ((val & LVDS_PORT_EN) == 0)
                return false;

        if (HAS_PCH_CPT(dev_priv->dev)) {
                if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
                        return false;
        } else {
                if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
                        return false;
        }
        return true;
}

static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
                              enum pipe pipe, u32 val)
{
        if ((val & ADPA_DAC_ENABLE) == 0)
                return false;
        if (HAS_PCH_CPT(dev_priv->dev)) {
                if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
                        return false;
        } else {
                if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
                        return false;
        }
        return true;
}

static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
                                   enum pipe pipe, int reg, u32 port_sel)
{
        u32 val = I915_READ(reg);
        WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
             "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
             reg, pipe_name(pipe));

        WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
             && (val & DP_PIPEB_SELECT),
             "IBX PCH dp port still using transcoder B\n");
}

static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
                                     enum pipe pipe, int reg)
{
        u32 val = I915_READ(reg);
        WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
             "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
             reg, pipe_name(pipe));

        WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
             && (val & SDVO_PIPE_B_SELECT),
             "IBX PCH hdmi port still using transcoder B\n");
}

static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
                                      enum pipe pipe)
{
        int reg;
        u32 val;

        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
        assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);

        reg = PCH_ADPA;
        val = I915_READ(reg);
        WARN(adpa_pipe_enabled(dev_priv, pipe, val),
             "PCH VGA enabled on transcoder %c, should be disabled\n",
             pipe_name(pipe));

        reg = PCH_LVDS;
        val = I915_READ(reg);
        WARN(lvds_pipe_enabled(dev_priv, pipe, val),
             "PCH LVDS enabled on transcoder %c, should be disabled\n",
             pipe_name(pipe));

        assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
        assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
        assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
}

static void vlv_enable_pll(struct intel_crtc *crtc)
{
        struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        int reg = DPLL(crtc->pipe);
        u32 dpll = crtc->config.dpll_hw_state.dpll;

        assert_pipe_disabled(dev_priv, crtc->pipe);

        /* No really, not for ILK+ */
        BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));

        /* PLL is protected by panel, make sure we can write it */
        if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
                assert_panel_unlocked(dev_priv, crtc->pipe);

        I915_WRITE(reg, dpll);
        POSTING_READ(reg);
        udelay(150);

        if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
                DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);

        I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
        POSTING_READ(DPLL_MD(crtc->pipe));

        /* We do this three times for luck */
        I915_WRITE(reg, dpll);
        POSTING_READ(reg);
        udelay(150); /* wait for warmup */
        I915_WRITE(reg, dpll);
        POSTING_READ(reg);
        udelay(150); /* wait for warmup */
        I915_WRITE(reg, dpll);
        POSTING_READ(reg);
        udelay(150); /* wait for warmup */
}

static void i9xx_enable_pll(struct intel_crtc *crtc)
{
        struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        int reg = DPLL(crtc->pipe);
        u32 dpll = crtc->config.dpll_hw_state.dpll;

        assert_pipe_disabled(dev_priv, crtc->pipe);

        /* No really, not for ILK+ */
        BUG_ON(dev_priv->info->gen >= 5);

        /* PLL is protected by panel, make sure we can write it */
        if (IS_MOBILE(dev) && !IS_I830(dev))
                assert_panel_unlocked(dev_priv, crtc->pipe);

        I915_WRITE(reg, dpll);

        /* Wait for the clocks to stabilize. */
        POSTING_READ(reg);
        udelay(150);

        if (INTEL_INFO(dev)->gen >= 4) {
                I915_WRITE(DPLL_MD(crtc->pipe),
                           crtc->config.dpll_hw_state.dpll_md);
        } else {
                /* The pixel multiplier can only be updated once the
                 * DPLL is enabled and the clocks are stable.
                 *
                 * So write it again.
                 */
                I915_WRITE(reg, dpll);
        }

        /* We do this three times for luck */
        I915_WRITE(reg, dpll);
        POSTING_READ(reg);
        udelay(150); /* wait for warmup */
        I915_WRITE(reg, dpll);
        POSTING_READ(reg);
        udelay(150); /* wait for warmup */
        I915_WRITE(reg, dpll);
        POSTING_READ(reg);
        udelay(150); /* wait for warmup */
}

/**
 * i9xx_disable_pll - disable a PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to disable
 *
 * Disable the PLL for @pipe, making sure the pipe is off first.
 *
 * Note!  This is for pre-ILK only.
 */
static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
{
        /* Don't disable pipe A or pipe A PLLs if needed */
        if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
                return;

        /* Make sure the pipe isn't still relying on us */
        assert_pipe_disabled(dev_priv, pipe);

        I915_WRITE(DPLL(pipe), 0);
        POSTING_READ(DPLL(pipe));
}

void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
{
        u32 port_mask;

        if (!port)
                port_mask = DPLL_PORTB_READY_MASK;
        else
                port_mask = DPLL_PORTC_READY_MASK;

        if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
                WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
                     'B' + port, I915_READ(DPLL(0)));
}

/**
 * ironlake_enable_shared_dpll - enable PCH PLL
 * @dev_priv: i915 private structure
 * @pipe: pipe PLL to enable
 *
 * The PCH PLL needs to be enabled before the PCH transcoder, since it
 * drives the transcoder clock.
 */
static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
        struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);

        /* PCH PLLs only available on ILK, SNB and IVB */
        BUG_ON(dev_priv->info->gen < 5);
        if (WARN_ON(pll == NULL))
                return;

        if (WARN_ON(pll->refcount == 0))
                return;

        DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
                      pll->name, pll->active, pll->on,
                      crtc->base.base.id);

        if (pll->active++) {
                WARN_ON(!pll->on);
                assert_shared_dpll_enabled(dev_priv, pll);
                return;
        }
        WARN_ON(pll->on);

        DRM_DEBUG_KMS("enabling %s\n", pll->name);
        pll->enable(dev_priv, pll);
        pll->on = true;
}

static void intel_disable_shared_dpll(struct intel_crtc *crtc)
{
        struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
        struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);

        /* PCH only available on ILK+ */
        BUG_ON(dev_priv->info->gen < 5);
        if (WARN_ON(pll == NULL))
               return;

        if (WARN_ON(pll->refcount == 0))
                return;

        DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
                      pll->name, pll->active, pll->on,
                      crtc->base.base.id);

        if (WARN_ON(pll->active == 0)) {
                assert_shared_dpll_disabled(dev_priv, pll);
                return;
        }

        assert_shared_dpll_enabled(dev_priv, pll);
        WARN_ON(!pll->on);
        if (--pll->active)
                return;

        DRM_DEBUG_KMS("disabling %s\n", pll->name);
        pll->disable(dev_priv, pll);
        pll->on = false;
}

static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
                                           enum pipe pipe)
{
        struct drm_device *dev = dev_priv->dev;
        struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        uint32_t reg, val, pipeconf_val;

        /* PCH only available on ILK+ */
        BUG_ON(dev_priv->info->gen < 5);

        /* Make sure PCH DPLL is enabled */
        assert_shared_dpll_enabled(dev_priv,
                                   intel_crtc_to_shared_dpll(intel_crtc));

        /* FDI must be feeding us bits for PCH ports */
        assert_fdi_tx_enabled(dev_priv, pipe);
        assert_fdi_rx_enabled(dev_priv, pipe);

        if (HAS_PCH_CPT(dev)) {
                /* Workaround: Set the timing override bit before enabling the
                 * pch transcoder. */
                reg = TRANS_CHICKEN2(pipe);
                val = I915_READ(reg);
                val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
                I915_WRITE(reg, val);
        }

        reg = PCH_TRANSCONF(pipe);
        val = I915_READ(reg);
        pipeconf_val = I915_READ(PIPECONF(pipe));

        if (HAS_PCH_IBX(dev_priv->dev)) {
                /*
                 * make the BPC in transcoder be consistent with
                 * that in pipeconf reg.
                 */
                val &= ~PIPECONF_BPC_MASK;
                val |= pipeconf_val & PIPECONF_BPC_MASK;
        }

        val &= ~TRANS_INTERLACE_MASK;
        if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
                if (HAS_PCH_IBX(dev_priv->dev) &&
                    intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
                        val |= TRANS_LEGACY_INTERLACED_ILK;
                else
                        val |= TRANS_INTERLACED;
        else
                val |= TRANS_PROGRESSIVE;

        I915_WRITE(reg, val | TRANS_ENABLE);
        if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
                DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
}

static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
                                      enum transcoder cpu_transcoder)
{
        u32 val, pipeconf_val;

        /* PCH only available on ILK+ */
        BUG_ON(dev_priv->info->gen < 5);

        /* FDI must be feeding us bits for PCH ports */
        assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
        assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);

        /* Workaround: set timing override bit. */
        val = I915_READ(_TRANSA_CHICKEN2);
        val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
        I915_WRITE(_TRANSA_CHICKEN2, val);

        val = TRANS_ENABLE;
        pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));

        if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
            PIPECONF_INTERLACED_ILK)
                val |= TRANS_INTERLACED;
        else
                val |= TRANS_PROGRESSIVE;

        I915_WRITE(LPT_TRANSCONF, val);
        if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
                DRM_ERROR("Failed to enable PCH transcoder\n");
}

static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
                                            enum pipe pipe)
{
        struct drm_device *dev = dev_priv->dev;
        uint32_t reg, val;

        /* FDI relies on the transcoder */
        assert_fdi_tx_disabled(dev_priv, pipe);
        assert_fdi_rx_disabled(dev_priv, pipe);

        /* Ports must be off as well */
        assert_pch_ports_disabled(dev_priv, pipe);

        reg = PCH_TRANSCONF(pipe);
        val = I915_READ(reg);
        val &= ~TRANS_ENABLE;
        I915_WRITE(reg, val);
        /* wait for PCH transcoder off, transcoder state */
        if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
                DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));

        if (!HAS_PCH_IBX(dev)) {
                /* Workaround: Clear the timing override chicken bit again. */
                reg = TRANS_CHICKEN2(pipe);
                val = I915_READ(reg);
                val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
                I915_WRITE(reg, val);
        }
}

static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
{
        u32 val;

        val = I915_READ(LPT_TRANSCONF);
        val &= ~TRANS_ENABLE;
        I915_WRITE(LPT_TRANSCONF, val);
        /* wait for PCH transcoder off, transcoder state */
        if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
                DRM_ERROR("Failed to disable PCH transcoder\n");

        /* Workaround: clear timing override bit. */
        val = I915_READ(_TRANSA_CHICKEN2);
        val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
        I915_WRITE(_TRANSA_CHICKEN2, val);
}

/**
 * intel_enable_pipe - enable a pipe, asserting requirements
 * @dev_priv: i915 private structure
 * @pipe: pipe to enable
 * @pch_port: on ILK+, is this pipe driving a PCH port or not
 *
 * Enable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe is actually running (i.e. first vblank) before
 * returning.
 */
static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
                              bool pch_port)
{
        enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
                                                                      pipe);
        enum pipe pch_transcoder;
        int reg;
        u32 val;

        assert_planes_disabled(dev_priv, pipe);
        assert_sprites_disabled(dev_priv, pipe);

        if (HAS_PCH_LPT(dev_priv->dev))
                pch_transcoder = TRANSCODER_A;
        else
                pch_transcoder = pipe;

        /*
         * A pipe without a PLL won't actually be able to drive bits from
         * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
         * need the check.
         */
        if (!HAS_PCH_SPLIT(dev_priv->dev))
                assert_pll_enabled(dev_priv, pipe);
        else {
                if (pch_port) {
                        /* if driving the PCH, we need FDI enabled */
                        assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
                        assert_fdi_tx_pll_enabled(dev_priv,
                                                  (enum pipe) cpu_transcoder);
                }
                /* FIXME: assert CPU port conditions for SNB+ */
        }

        reg = PIPECONF(cpu_transcoder);
        val = I915_READ(reg);
        if (val & PIPECONF_ENABLE)
                return;

        I915_WRITE(reg, val | PIPECONF_ENABLE);
        intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
 * intel_disable_pipe - disable a pipe, asserting requirements
 * @dev_priv: i915 private structure
 * @pipe: pipe to disable
 *
 * Disable @pipe, making sure that various hardware specific requirements
 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
 *
 * @pipe should be %PIPE_A or %PIPE_B.
 *
 * Will wait until the pipe has shut down before returning.
 */
static void intel_disable_pipe(struct drm_i915_private *dev_priv,
                               enum pipe pipe)
{
        enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
                                                                      pipe);
        int reg;
        u32 val;

        /*
         * Make sure planes won't keep trying to pump pixels to us,
         * or we might hang the display.
         */
        assert_planes_disabled(dev_priv, pipe);
        assert_sprites_disabled(dev_priv, pipe);

        /* Don't disable pipe A or pipe A PLLs if needed */
        if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
                return;

        reg = PIPECONF(cpu_transcoder);
        val = I915_READ(reg);
        if ((val & PIPECONF_ENABLE) == 0)
                return;

        I915_WRITE(reg, val & ~PIPECONF_ENABLE);
        intel_wait_for_pipe_off(dev_priv->dev, pipe);
}

/*
 * Plane regs are double buffered, going from enabled->disabled needs a
 * trigger in order to latch.  The display address reg provides this.
 */
void intel_flush_display_plane(struct drm_i915_private *dev_priv,
                                      enum plane plane)
{
        if (dev_priv->info->gen >= 4)
                I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
        else
                I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
}

/**
 * intel_enable_plane - enable a display plane on a given pipe
 * @dev_priv: i915 private structure
 * @plane: plane to enable
 * @pipe: pipe being fed
 *
 * Enable @plane on @pipe, making sure that @pipe is running first.
 */
static void intel_enable_plane(struct drm_i915_private *dev_priv,
                               enum plane plane, enum pipe pipe)
{
        int reg;
        u32 val;

        /* If the pipe isn't enabled, we can't pump pixels and may hang */
        assert_pipe_enabled(dev_priv, pipe);

        reg = DSPCNTR(plane);
        val = I915_READ(reg);
        if (val & DISPLAY_PLANE_ENABLE)
                return;

        I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
        intel_flush_display_plane(dev_priv, plane);
        intel_wait_for_vblank(dev_priv->dev, pipe);
}

/**
 * intel_disable_plane - disable a display plane
 * @dev_priv: i915 private structure
 * @plane: plane to disable
 * @pipe: pipe consuming the data
 *
 * Disable @plane; should be an independent operation.
 */
static void intel_disable_plane(struct drm_i915_private *dev_priv,
                                enum plane plane, enum pipe pipe)
{
        int reg;
        u32 val;

        reg = DSPCNTR(plane);
        val = I915_READ(reg);
        if ((val & DISPLAY_PLANE_ENABLE) == 0)
                return;

        I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
        intel_flush_display_plane(dev_priv, plane);
        intel_wait_for_vblank(dev_priv->dev, pipe);
}

static bool need_vtd_wa(struct drm_device *dev)
{
#ifdef CONFIG_INTEL_IOMMU
        if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
                return true;
#endif
        return false;
}

int
intel_pin_and_fence_fb_obj(struct drm_device *dev,
                           struct drm_i915_gem_object *obj,
                           struct intel_ring_buffer *pipelined)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 alignment;
        int ret;

        switch (obj->tiling_mode) {
        case I915_TILING_NONE:
                if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
                        alignment = 128 * 1024;
                else if (INTEL_INFO(dev)->gen >= 4)
                        alignment = 4 * 1024;
                else
                        alignment = 64 * 1024;
                break;
        case I915_TILING_X:
                /* pin() will align the object as required by fence */
                alignment = 0;
                break;
        case I915_TILING_Y:
                /* Despite that we check this in framebuffer_init userspace can
                 * screw us over and change the tiling after the fact. Only
                 * pinned buffers can't change their tiling. */
                DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
                return -EINVAL;
        default:
                BUG();
        }

        /* Note that the w/a also requires 64 PTE of padding following the
         * bo. We currently fill all unused PTE with the shadow page and so
         * we should always have valid PTE following the scanout preventing
         * the VT-d warning.
         */
        if (need_vtd_wa(dev) && alignment < 256 * 1024)
                alignment = 256 * 1024;

        dev_priv->mm.interruptible = false;
        ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
        if (ret)
                goto err_interruptible;

        /* Install a fence for tiled scan-out. Pre-i965 always needs a
         * fence, whereas 965+ only requires a fence if using
         * framebuffer compression.  For simplicity, we always install
         * a fence as the cost is not that onerous.
         */
        ret = i915_gem_object_get_fence(obj);
        if (ret)
                goto err_unpin;

        i915_gem_object_pin_fence(obj);

        dev_priv->mm.interruptible = true;
        return 0;

err_unpin:
        i915_gem_object_unpin_from_display_plane(obj);
err_interruptible:
        dev_priv->mm.interruptible = true;
        return ret;
}

void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
{
        i915_gem_object_unpin_fence(obj);
        i915_gem_object_unpin_from_display_plane(obj);
}

/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
 * is assumed to be a power-of-two. */
unsigned long intel_gen4_compute_page_offset(int *x, int *y,
                                             unsigned int tiling_mode,
                                             unsigned int cpp,
                                             unsigned int pitch)
{
        if (tiling_mode != I915_TILING_NONE) {
                unsigned int tile_rows, tiles;

                tile_rows = *y / 8;
                *y %= 8;

                tiles = *x / (512/cpp);
                *x %= 512/cpp;

                return tile_rows * pitch * 8 + tiles * 4096;
        } else {
                unsigned int offset;

                offset = *y * pitch + *x * cpp;
                *y = 0;
                *x = (offset & 4095) / cpp;
                return offset & -4096;
        }
}

static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
                             int x, int y)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        struct intel_framebuffer *intel_fb;
        struct drm_i915_gem_object *obj;
        int plane = intel_crtc->plane;
        unsigned long linear_offset;
        u32 dspcntr;
        u32 reg;

        switch (plane) {
        case 0:
        case 1:
                break;
        default:
                DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
                return -EINVAL;
        }

        intel_fb = to_intel_framebuffer(fb);
        obj = intel_fb->obj;

        reg = DSPCNTR(plane);
        dspcntr = I915_READ(reg);
        /* Mask out pixel format bits in case we change it */
        dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
        switch (fb->pixel_format) {
        case DRM_FORMAT_C8:
                dspcntr |= DISPPLANE_8BPP;
                break;
        case DRM_FORMAT_XRGB1555:
        case DRM_FORMAT_ARGB1555:
                dspcntr |= DISPPLANE_BGRX555;
                break;
        case DRM_FORMAT_RGB565:
                dspcntr |= DISPPLANE_BGRX565;
                break;
        case DRM_FORMAT_XRGB8888:
        case DRM_FORMAT_ARGB8888:
                dspcntr |= DISPPLANE_BGRX888;
                break;
        case DRM_FORMAT_XBGR8888:
        case DRM_FORMAT_ABGR8888:
                dspcntr |= DISPPLANE_RGBX888;
                break;
        case DRM_FORMAT_XRGB2101010:
        case DRM_FORMAT_ARGB2101010:
                dspcntr |= DISPPLANE_BGRX101010;
                break;
        case DRM_FORMAT_XBGR2101010:
        case DRM_FORMAT_ABGR2101010:
                dspcntr |= DISPPLANE_RGBX101010;
                break;
        default:
                BUG();
        }

        if (INTEL_INFO(dev)->gen >= 4) {
                if (obj->tiling_mode != I915_TILING_NONE)
                        dspcntr |= DISPPLANE_TILED;
                else
                        dspcntr &= ~DISPPLANE_TILED;
        }

        if (IS_G4X(dev))
                dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;

        I915_WRITE(reg, dspcntr);

        linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);

        if (INTEL_INFO(dev)->gen >= 4) {
                intel_crtc->dspaddr_offset =
                        intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
                                                       fb->bits_per_pixel / 8,
                                                       fb->pitches[0]);
                linear_offset -= intel_crtc->dspaddr_offset;
        } else {
                intel_crtc->dspaddr_offset = linear_offset;
        }

        DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
                      i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
                      fb->pitches[0]);
        I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
        if (INTEL_INFO(dev)->gen >= 4) {
                I915_MODIFY_DISPBASE(DSPSURF(plane),
                                     i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
                I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
                I915_WRITE(DSPLINOFF(plane), linear_offset);
        } else
                I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
        POSTING_READ(reg);

        return 0;
}

static int ironlake_update_plane(struct drm_crtc *crtc,
                                 struct drm_framebuffer *fb, int x, int y)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        struct intel_framebuffer *intel_fb;
        struct drm_i915_gem_object *obj;
        int plane = intel_crtc->plane;
        unsigned long linear_offset;
        u32 dspcntr;
        u32 reg;

        switch (plane) {
        case 0:
        case 1:
        case 2:
                break;
        default:
                DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
                return -EINVAL;
        }

        intel_fb = to_intel_framebuffer(fb);
        obj = intel_fb->obj;

        reg = DSPCNTR(plane);
        dspcntr = I915_READ(reg);
        /* Mask out pixel format bits in case we change it */
        dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
        switch (fb->pixel_format) {
        case DRM_FORMAT_C8:
                dspcntr |= DISPPLANE_8BPP;
                break;
        case DRM_FORMAT_RGB565:
                dspcntr |= DISPPLANE_BGRX565;
                break;
        case DRM_FORMAT_XRGB8888:
        case DRM_FORMAT_ARGB8888:
                dspcntr |= DISPPLANE_BGRX888;
                break;
        case DRM_FORMAT_XBGR8888:
        case DRM_FORMAT_ABGR8888:
                dspcntr |= DISPPLANE_RGBX888;
                break;
        case DRM_FORMAT_XRGB2101010:
        case DRM_FORMAT_ARGB2101010:
                dspcntr |= DISPPLANE_BGRX101010;
                break;
        case DRM_FORMAT_XBGR2101010:
        case DRM_FORMAT_ABGR2101010:
                dspcntr |= DISPPLANE_RGBX101010;
                break;
        default:
                BUG();
        }

        if (obj->tiling_mode != I915_TILING_NONE)
                dspcntr |= DISPPLANE_TILED;
        else
                dspcntr &= ~DISPPLANE_TILED;

        if (IS_HASWELL(dev))
                dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
        else
                dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;

        I915_WRITE(reg, dspcntr);

        linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
        intel_crtc->dspaddr_offset =
                intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
                                               fb->bits_per_pixel / 8,
                                               fb->pitches[0]);
        linear_offset -= intel_crtc->dspaddr_offset;

        DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
                      i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
                      fb->pitches[0]);
        I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
        I915_MODIFY_DISPBASE(DSPSURF(plane),
                             i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
        if (IS_HASWELL(dev)) {
                I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
        } else {
                I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
                I915_WRITE(DSPLINOFF(plane), linear_offset);
        }
        POSTING_READ(reg);

        return 0;
}

/* Assume fb object is pinned & idle & fenced and just update base pointers */
static int
intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
                           int x, int y, enum mode_set_atomic state)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;

        if (dev_priv->display.disable_fbc)
                dev_priv->display.disable_fbc(dev);
        intel_increase_pllclock(crtc);

        return dev_priv->display.update_plane(crtc, fb, x, y);
}

void intel_display_handle_reset(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct drm_crtc *crtc;

        /*
         * Flips in the rings have been nuked by the reset,
         * so complete all pending flips so that user space
         * will get its events and not get stuck.
         *
         * Also update the base address of all primary
         * planes to the the last fb to make sure we're
         * showing the correct fb after a reset.
         *
         * Need to make two loops over the crtcs so that we
         * don't try to grab a crtc mutex before the
         * pending_flip_queue really got woken up.
         */

        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
                enum plane plane = intel_crtc->plane;

                intel_prepare_page_flip(dev, plane);
                intel_finish_page_flip_plane(dev, plane);
        }

        list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
                struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

                mutex_lock(&crtc->mutex);
                if (intel_crtc->active)
                        dev_priv->display.update_plane(crtc, crtc->fb,
                                                       crtc->x, crtc->y);
                mutex_unlock(&crtc->mutex);
        }
}

static int
intel_finish_fb(struct drm_framebuffer *old_fb)
{
        struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
        struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
        bool was_interruptible = dev_priv->mm.interruptible;
        int ret;

        /* Big Hammer, we also need to ensure that any pending
         * MI_WAIT_FOR_EVENT inside a user batch buffer on the
         * current scanout is retired before unpinning the old
         * framebuffer.
         *
         * This should only fail upon a hung GPU, in which case we
         * can safely continue.
         */
        dev_priv->mm.interruptible = false;
        ret = i915_gem_object_finish_gpu(obj);
        dev_priv->mm.interruptible = was_interruptible;

        return ret;
}

static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_master_private *master_priv;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);

        if (!dev->primary->master)
                return;

        master_priv = dev->primary->master->driver_priv;
        if (!master_priv->sarea_priv)
                return;

        switch (intel_crtc->pipe) {
        case 0:
                master_priv->sarea_priv->pipeA_x = x;
                master_priv->sarea_priv->pipeA_y = y;
                break;
        case 1:
                master_priv->sarea_priv->pipeB_x = x;
                master_priv->sarea_priv->pipeB_y = y;
                break;
        default:
                break;
        }
}

static int
intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
                    struct drm_framebuffer *fb)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        struct drm_framebuffer *old_fb;
        int ret;

        /* no fb bound */
        if (!fb) {
                DRM_ERROR("No FB bound\n");
                return 0;
        }

        if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
                DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
                          plane_name(intel_crtc->plane),
                          INTEL_INFO(dev)->num_pipes);
                return -EINVAL;
        }

        mutex_lock(&dev->struct_mutex);
        ret = intel_pin_and_fence_fb_obj(dev,
                                         to_intel_framebuffer(fb)->obj,
                                         NULL);
        if (ret != 0) {
                mutex_unlock(&dev->struct_mutex);
                DRM_ERROR("pin & fence failed\n");
                return ret;
        }

        /* Update pipe size and adjust fitter if needed */
        if (i915_fastboot) {
                I915_WRITE(PIPESRC(intel_crtc->pipe),
                           ((crtc->mode.hdisplay - 1) << 16) |
                           (crtc->mode.vdisplay - 1));
                if (!intel_crtc->config.pch_pfit.enabled &&
                    (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
                     intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
                        I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
                        I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
                        I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
                }
        }

        ret = dev_priv->display.update_plane(crtc, fb, x, y);
        if (ret) {
                intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
                mutex_unlock(&dev->struct_mutex);
                DRM_ERROR("failed to update base address\n");
                return ret;
        }

        old_fb = crtc->fb;
        crtc->fb = fb;
        crtc->x = x;
        crtc->y = y;

        if (old_fb) {
                if (intel_crtc->active && old_fb != fb)
                        intel_wait_for_vblank(dev, intel_crtc->pipe);
                intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
        }

        intel_update_fbc(dev);
        intel_edp_psr_update(dev);
        mutex_unlock(&dev->struct_mutex);

        intel_crtc_update_sarea_pos(crtc, x, y);

        return 0;
}

static void intel_fdi_normal_train(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
        u32 reg, temp;

        /* enable normal train */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        if (IS_IVYBRIDGE(dev)) {
                temp &= ~FDI_LINK_TRAIN_NONE_IVB;
                temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
        } else {
                temp &= ~FDI_LINK_TRAIN_NONE;
                temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
        }
        I915_WRITE(reg, temp);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        if (HAS_PCH_CPT(dev)) {
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp |= FDI_LINK_TRAIN_NORMAL_CPT;
        } else {
                temp &= ~FDI_LINK_TRAIN_NONE;
                temp |= FDI_LINK_TRAIN_NONE;
        }
        I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);

        /* wait one idle pattern time */
        POSTING_READ(reg);
        udelay(1000);

        /* IVB wants error correction enabled */
        if (IS_IVYBRIDGE(dev))
                I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
                           FDI_FE_ERRC_ENABLE);
}

static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
{
        return crtc->base.enabled && crtc->active &&
                crtc->config.has_pch_encoder;
}

static void ivb_modeset_global_resources(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *pipe_B_crtc =
                to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
        struct intel_crtc *pipe_C_crtc =
                to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
        uint32_t temp;

        /*
         * When everything is off disable fdi C so that we could enable fdi B
         * with all lanes. Note that we don't care about enabled pipes without
         * an enabled pch encoder.
         */
        if (!pipe_has_enabled_pch(pipe_B_crtc) &&
            !pipe_has_enabled_pch(pipe_C_crtc)) {
                WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
                WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);

                temp = I915_READ(SOUTH_CHICKEN1);
                temp &= ~FDI_BC_BIFURCATION_SELECT;
                DRM_DEBUG_KMS("disabling fdi C rx\n");
                I915_WRITE(SOUTH_CHICKEN1, temp);
        }
}

/* The FDI link training functions for ILK/Ibexpeak. */
static void ironlake_fdi_link_train(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
        int plane = intel_crtc->plane;
        u32 reg, temp, tries;

        /* FDI needs bits from pipe & plane first */
        assert_pipe_enabled(dev_priv, pipe);
        assert_plane_enabled(dev_priv, plane);

        /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
           for train result */
        reg = FDI_RX_IMR(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_RX_SYMBOL_LOCK;
        temp &= ~FDI_RX_BIT_LOCK;
        I915_WRITE(reg, temp);
        I915_READ(reg);
        udelay(150);

        /* enable CPU FDI TX and PCH FDI RX */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_DP_PORT_WIDTH_MASK;
        temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_1;
        I915_WRITE(reg, temp | FDI_TX_ENABLE);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_1;
        I915_WRITE(reg, temp | FDI_RX_ENABLE);

        POSTING_READ(reg);
        udelay(150);

        /* Ironlake workaround, enable clock pointer after FDI enable*/
        I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
        I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
                   FDI_RX_PHASE_SYNC_POINTER_EN);

        reg = FDI_RX_IIR(pipe);
        for (tries = 0; tries < 5; tries++) {
                temp = I915_READ(reg);
                DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

                if ((temp & FDI_RX_BIT_LOCK)) {
                        DRM_DEBUG_KMS("FDI train 1 done.\n");
                        I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
                        break;
                }
        }
        if (tries == 5)
                DRM_ERROR("FDI train 1 fail!\n");

        /* Train 2 */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_2;
        I915_WRITE(reg, temp);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_2;
        I915_WRITE(reg, temp);

        POSTING_READ(reg);
        udelay(150);

        reg = FDI_RX_IIR(pipe);
        for (tries = 0; tries < 5; tries++) {
                temp = I915_READ(reg);
                DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

                if (temp & FDI_RX_SYMBOL_LOCK) {
                        I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
                        DRM_DEBUG_KMS("FDI train 2 done.\n");
                        break;
                }
        }
        if (tries == 5)
                DRM_ERROR("FDI train 2 fail!\n");

        DRM_DEBUG_KMS("FDI train done\n");

}

static const int snb_b_fdi_train_param[] = {
        FDI_LINK_TRAIN_400MV_0DB_SNB_B,
        FDI_LINK_TRAIN_400MV_6DB_SNB_B,
        FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
        FDI_LINK_TRAIN_800MV_0DB_SNB_B,
};

/* The FDI link training functions for SNB/Cougarpoint. */
static void gen6_fdi_link_train(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
        u32 reg, temp, i, retry;

        /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
           for train result */
        reg = FDI_RX_IMR(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_RX_SYMBOL_LOCK;
        temp &= ~FDI_RX_BIT_LOCK;
        I915_WRITE(reg, temp);

        POSTING_READ(reg);
        udelay(150);

        /* enable CPU FDI TX and PCH FDI RX */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_DP_PORT_WIDTH_MASK;
        temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_1;
        temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
        /* SNB-B */
        temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
        I915_WRITE(reg, temp | FDI_TX_ENABLE);

        I915_WRITE(FDI_RX_MISC(pipe),
                   FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        if (HAS_PCH_CPT(dev)) {
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
        } else {
                temp &= ~FDI_LINK_TRAIN_NONE;
                temp |= FDI_LINK_TRAIN_PATTERN_1;
        }
        I915_WRITE(reg, temp | FDI_RX_ENABLE);

        POSTING_READ(reg);
        udelay(150);

        for (i = 0; i < 4; i++) {
                reg = FDI_TX_CTL(pipe);
                temp = I915_READ(reg);
                temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
                temp |= snb_b_fdi_train_param[i];
                I915_WRITE(reg, temp);

                POSTING_READ(reg);
                udelay(500);

                for (retry = 0; retry < 5; retry++) {
                        reg = FDI_RX_IIR(pipe);
                        temp = I915_READ(reg);
                        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
                        if (temp & FDI_RX_BIT_LOCK) {
                                I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
                                DRM_DEBUG_KMS("FDI train 1 done.\n");
                                break;
                        }
                        udelay(50);
                }
                if (retry < 5)
                        break;
        }
        if (i == 4)
                DRM_ERROR("FDI train 1 fail!\n");

        /* Train 2 */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_2;
        if (IS_GEN6(dev)) {
                temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
                /* SNB-B */
                temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
        }
        I915_WRITE(reg, temp);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        if (HAS_PCH_CPT(dev)) {
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
        } else {
                temp &= ~FDI_LINK_TRAIN_NONE;
                temp |= FDI_LINK_TRAIN_PATTERN_2;
        }
        I915_WRITE(reg, temp);

        POSTING_READ(reg);
        udelay(150);

        for (i = 0; i < 4; i++) {
                reg = FDI_TX_CTL(pipe);
                temp = I915_READ(reg);
                temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
                temp |= snb_b_fdi_train_param[i];
                I915_WRITE(reg, temp);

                POSTING_READ(reg);
                udelay(500);

                for (retry = 0; retry < 5; retry++) {
                        reg = FDI_RX_IIR(pipe);
                        temp = I915_READ(reg);
                        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
                        if (temp & FDI_RX_SYMBOL_LOCK) {
                                I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
                                DRM_DEBUG_KMS("FDI train 2 done.\n");
                                break;
                        }
                        udelay(50);
                }
                if (retry < 5)
                        break;
        }
        if (i == 4)
                DRM_ERROR("FDI train 2 fail!\n");

        DRM_DEBUG_KMS("FDI train done.\n");
}

/* Manual link training for Ivy Bridge A0 parts */
static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
        u32 reg, temp, i, j;

        /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
           for train result */
        reg = FDI_RX_IMR(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_RX_SYMBOL_LOCK;
        temp &= ~FDI_RX_BIT_LOCK;
        I915_WRITE(reg, temp);

        POSTING_READ(reg);
        udelay(150);

        DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
                      I915_READ(FDI_RX_IIR(pipe)));

        /* Try each vswing and preemphasis setting twice before moving on */
        for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
                /* disable first in case we need to retry */
                reg = FDI_TX_CTL(pipe);
                temp = I915_READ(reg);
                temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
                temp &= ~FDI_TX_ENABLE;
                I915_WRITE(reg, temp);

                reg = FDI_RX_CTL(pipe);
                temp = I915_READ(reg);
                temp &= ~FDI_LINK_TRAIN_AUTO;
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp &= ~FDI_RX_ENABLE;
                I915_WRITE(reg, temp);

                /* enable CPU FDI TX and PCH FDI RX */
                reg = FDI_TX_CTL(pipe);
                temp = I915_READ(reg);
                temp &= ~FDI_DP_PORT_WIDTH_MASK;
                temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
                temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
                temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
                temp |= snb_b_fdi_train_param[j/2];
                temp |= FDI_COMPOSITE_SYNC;
                I915_WRITE(reg, temp | FDI_TX_ENABLE);

                I915_WRITE(FDI_RX_MISC(pipe),
                           FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);

                reg = FDI_RX_CTL(pipe);
                temp = I915_READ(reg);
                temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
                temp |= FDI_COMPOSITE_SYNC;
                I915_WRITE(reg, temp | FDI_RX_ENABLE);

                POSTING_READ(reg);
                udelay(1); /* should be 0.5us */

                for (i = 0; i < 4; i++) {
                        reg = FDI_RX_IIR(pipe);
                        temp = I915_READ(reg);
                        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

                        if (temp & FDI_RX_BIT_LOCK ||
                            (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
                                I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
                                DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
                                              i);
                                break;
                        }
                        udelay(1); /* should be 0.5us */
                }
                if (i == 4) {
                        DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
                        continue;
                }

                /* Train 2 */
                reg = FDI_TX_CTL(pipe);
                temp = I915_READ(reg);
                temp &= ~FDI_LINK_TRAIN_NONE_IVB;
                temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
                I915_WRITE(reg, temp);

                reg = FDI_RX_CTL(pipe);
                temp = I915_READ(reg);
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
                I915_WRITE(reg, temp);

                POSTING_READ(reg);
                udelay(2); /* should be 1.5us */

                for (i = 0; i < 4; i++) {
                        reg = FDI_RX_IIR(pipe);
                        temp = I915_READ(reg);
                        DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);

                        if (temp & FDI_RX_SYMBOL_LOCK ||
                            (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
                                I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
                                DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
                                              i);
                                goto train_done;
                        }
                        udelay(2); /* should be 1.5us */
                }
                if (i == 4)
                        DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
        }

train_done:
        DRM_DEBUG_KMS("FDI train done.\n");
}

static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
{
        struct drm_device *dev = intel_crtc->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        int pipe = intel_crtc->pipe;
        u32 reg, temp;


        /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
        temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
        temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
        I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);

        POSTING_READ(reg);
        udelay(200);

        /* Switch from Rawclk to PCDclk */
        temp = I915_READ(reg);
        I915_WRITE(reg, temp | FDI_PCDCLK);

        POSTING_READ(reg);
        udelay(200);

        /* Enable CPU FDI TX PLL, always on for Ironlake */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        if ((temp & FDI_TX_PLL_ENABLE) == 0) {
                I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);

                POSTING_READ(reg);
                udelay(100);
        }
}

static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
{
        struct drm_device *dev = intel_crtc->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        int pipe = intel_crtc->pipe;
        u32 reg, temp;

        /* Switch from PCDclk to Rawclk */
        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        I915_WRITE(reg, temp & ~FDI_PCDCLK);

        /* Disable CPU FDI TX PLL */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);

        POSTING_READ(reg);
        udelay(100);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);

        /* Wait for the clocks to turn off. */
        POSTING_READ(reg);
        udelay(100);
}

static void ironlake_fdi_disable(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        int pipe = intel_crtc->pipe;
        u32 reg, temp;

        /* disable CPU FDI tx and PCH FDI rx */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
        POSTING_READ(reg);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~(0x7 << 16);
        temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
        I915_WRITE(reg, temp & ~FDI_RX_ENABLE);

        POSTING_READ(reg);
        udelay(100);

        /* Ironlake workaround, disable clock pointer after downing FDI */
        if (HAS_PCH_IBX(dev)) {
                I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
        }

        /* still set train pattern 1 */
        reg = FDI_TX_CTL(pipe);
        temp = I915_READ(reg);
        temp &= ~FDI_LINK_TRAIN_NONE;
        temp |= FDI_LINK_TRAIN_PATTERN_1;
        I915_WRITE(reg, temp);

        reg = FDI_RX_CTL(pipe);
        temp = I915_READ(reg);
        if (HAS_PCH_CPT(dev)) {
                temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
                temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
        } else {
                temp &= ~FDI_LINK_TRAIN_NONE;
                temp |= FDI_LINK_TRAIN_PATTERN_1;
        }
        /* BPC in FDI rx is consistent with that in PIPECONF */
        temp &= ~(0x07 << 16);
        temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
        I915_WRITE(reg, temp);

        POSTING_READ(reg);
        udelay(100);
}

static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
        unsigned long flags;
        bool pending;

        if (i915_reset_in_progress(&dev_priv->gpu_error) ||
            intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
                return false;

        spin_lock_irqsave(&dev->event_lock, flags);
        pending = to_intel_crtc(crtc)->unpin_work != NULL;
        spin_unlock_irqrestore(&dev->event_lock, flags);

        return pending;
}

static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;

        if (crtc->fb == NULL)
                return;

        WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));

        wait_event(dev_priv->pending_flip_queue,
                   !intel_crtc_has_pending_flip(crtc));

        mutex_lock(&dev->struct_mutex);
        intel_finish_fb(crtc->fb);
        mutex_unlock(&dev->struct_mutex);
}

/* Program iCLKIP clock to the desired frequency */
static void lpt_program_iclkip(struct drm_crtc *crtc)
{
        struct drm_device *dev = crtc->dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        u32 divsel, phaseinc, auxdiv, phasedir = 0;
        u32 temp;

        mutex_lock(&dev_priv->dpio_lock);

        /* It is necessary to ungate the pixclk gate prior to programming
         * the divisors, and gate it back when it is done.
         */
        I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);

        /* Disable SSCCTL */
        intel_sbi_write(dev_priv, SBI_SSCCTL6,
                        intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
                                SBI_SSCCTL_DISABLE,
                        SBI_ICLK);

        /* 20MHz is a corner case which is out of range for the 7-bit divisor */
        if (crtc->mode.clock == 20000) {
                auxdiv = 1;
                divsel = 0x41;
                phaseinc = 0x20;
        } else {
                /* The iCLK virtual clock root frequency is in MHz,
                 * but the crtc->mode.clock in in KHz. To get the divisors,
                 * it is necessary to divide one by another, so we
                 * convert the virtual clock precision to KHz here for higher
                 * precision.
                 */
                u32 iclk_virtual_root_freq = 172800 * 1000;
                u32 iclk_pi_range = 64;
                u32 desired_divisor, msb_divisor_value, pi_value;

                desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
                msb_divisor_value = desired_divisor / iclk_pi_range;
                pi_value = desired_divisor % iclk_pi_range;

                auxdiv = 0;
                divsel = msb_divisor_value - 2;
                phaseinc = pi_value;
        }

        /* This should not happen with any sane values */
        WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
                ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
        WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
                ~SBI_SSCDIVINTPHASE_INCVAL_MASK);

        DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
                        crtc->mode.clock,
                        auxdiv,
                        divsel,
                        phasedir,
                        phaseinc);

        /* Program SSCDIVINTPHASE6 */
        temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
        temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
        temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
        temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
        temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
        temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
        temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
        intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);

        /* Program SSCAUXDIV */
        temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
        temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
        temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
        intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);

        /* Enable modulator and associated divider */
        temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
        temp &= ~SBI_SSCCTL_DISABLE;
        intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);

        /* Wait for initialization time */
        udelay(24);

        I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);

        mutex_unlock(&dev_priv->dpio_lock);
}

static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
                                                enum pipe pch_transcoder)
{
        struct drm_device *dev = crtc->base.dev;
        struct drm_i915_private *dev_priv = dev->dev_private;
        enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;

        I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
                   I915_READ(HTOTAL(cpu_transcoder)));
        I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
                   I915_READ(HBLANK(cpu_transcoder)));
        I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
                   I915_READ(HSYNC(cpu_transcoder)));

        I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
                   I915_READ(VTOTAL(cpu_transcoder)));
        I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
                   I915_READ(VBLANK(cpu_transcoder)));
        I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
                   I915_READ(VSYNC(cpu_transcoder)));
        I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
                   I915_READ(VSYNCSHIFT(cpu_transcoder)));
}

static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
{
        struct drm_i915_private *dev_priv = dev->dev_private;
        uint32_t temp;

        temp = I915_READ(SOUTH_CHICKEN1);
        if (temp & FDI_BC_BIFURCATION_SELECT)
                return;

        WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
        WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);

        temp |= FDI_BC_BIFURCATION_SELECT;
        DRM_DEBUG_KMS("enabling fdi C rx\n");
        I915_WRITE(SOUTH_CHICKEN1, temp);
        POSTING_READ(SOUTH_CHICKEN1);
}